UPD8874CY-A [NEC]
CCD Sensor, 5400 Horiz pixels, 5400 Vert pixels, 2-2.50V, Rectangular, Through Hole Mount, 10.16 MM, PLASTIC, DIP-22;
| 型号： | UPD8874CY-A |
| 厂家： | 
NEC |
| 描述： | CCD Sensor, 5400 Horiz pixels, 5400 Vert pixels, 2-2.50V, Rectangular, Through Hole Mount, 10.16 MM, PLASTIC, DIP-22 CD ISM频段 传感器 换能器 |
| 文件： | 总32页 (文件大小：323K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
μPD8874
(5400 + 5400) PIXELS × 3 + COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The μPD8874 is a color CCD (Charge Coupled Device) linear image sensor that changes optical images to
electrical signal and has the function of color separation.
The μPD8874 has 3 rows of (5400 + 5400) staggered pixels, and each row has dual-sided readout type of charge
transfer register. This product is high speed and High response version of the existing product μPD8873.
And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 1200 dpi/A4
color image scanners, color MFP and so on.
FEATURES
• Valid photocell
• Photocell’s size
• Line spacing
: (5400 + 5400) staggered pixels × 3
: 5.25 × 5.25 μm
: 63 μm (12 lines) Red line - Green line, Green line - Blue line
10.5 μm (2 lines) Odd line - Even line (for each color)
: High transmittance new color filter
• Color filter
• Resolution
Primary colors (red, green and blue), pigment filter
Light resistance 107 lx•hour with standard sunlight and ultraviolet cut filter (L40).
: 48 dot/mm A4 (210 × 297 mm) size (shorter side) for color
1200 dpi US letter (8.5” × 11”) size (shorter side) for color
: CMOS output under 5 V operation
• Drive clock level
• Data rate
: 20 MHz Max.
• Power supply
• On-chip circuit
: +12 V
: Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
μPD8874CY-A
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
Remark The μPD8874CY-A is a lead-free product.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S18773EJ1V0DS00 (1st edition)
Date Published June 2007 NS CP (K)
Printed in Japan
2007
μ PD8874
BLOCK DIAGRAM
φ2L
φSEL
φ2
φ1
17
14
16
15
CCD analog shift register
Transfer gate
GND 19
Photocell
(Blue)
···
···
V
OUT
1
20
(Blue)
Photocell
(Blue)
φTG1
Transfer gate
13
CCD analog shift register
V
OD
1
2
21
22
CCD analog shift register
Transfer gate
Photocell
(Green)
···
···
V
OUT
(Green)
Photocell
(Green)
φTG2
Transfer gate
12
CCD analog shift register
CCD analog shift register
Transfer gate
11 GND
Photocell
(Red)
···
···
V
(Red)
OUT
3
1
2
Photocell
(Red)
φTG3
Transfer gate
10
CCD analog shift register
V 2
OD
4
3
5
8
9
φCLB
φR
φ1L
φ1
φ2
2
Data Sheet S18773EJ1V0DS
μ PD8874
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
μPD8874CY-A
Output signal 3 (Red)
Output unit drain voltage 2
Reset gate clock
1
2
3
4
5
6
7
8
9
V
V
OUT
3
V
V
OUT
2
1
1
22 Output signal 2 (Green)
OD
2
V
OD
21 Output unit drain voltage 1
20 Output signal 1 (Blue)
OUT
φR
Reset feed through level clamp clock
Last stage shift register clock 1L
No connection
GND 19 Ground
φCLB
φ1L
NC
NC 18 No connection
17 Last stage shift register clock 2L
φ2L
φ2
No connection
NC
16 Shift register clock 2
15 Shift register clock 1
14 dpi selecter
Shift register clock 1
φ1
φ1
Shift register clock 2
φ2
φSEL
φTG1
φTG2
Transfer gate clock 3 (Red) 10
13 Transfer gate clock 1 (Blue)
12 Transfer gate clock 2 (Green)
φTG3
Ground 11 GND
Caution Connect the no connection pins (NC) to GND.
3
Data Sheet S18773EJ1V0DS
μ PD8874
PHOTOCELL STRUCTURE DIAGRAM
2.75 μ m
2.5 μ m
μ
Channel stopper
Aluminum
shield
PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
5.25 μ m
5.25 μ m
5.25 μ m
Blue photocell array
Blue photocell array
2 lines
(10.5 μ m)
12 lines
10 lines
(52.5 μ m)
(63 μ m)
5.25 μ m
5.25 μ m
5.25 μ m
Green photocell array
Green photocell array
2 lines
(10.5 μ m)
12 lines
(63 μ m)
10 lines
(52.5 μ m)
5.25 μ m
5.25 μ m
5.25 μ m
Red photocell array
Red photocell array
2 lines
(10.5 μ m)
4
Data Sheet S18773EJ1V0DS
μ PD8874
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Parameter
Output drain voltage
Symbol
Ratings
–0.3 to +15
–0.3 to +8
–0.3 to +8
–0.3 to +8
–0.3 to +8
–0.3 to +8
–0.3 to +8
0 to +55
Unit
V
VOD1, VOD2
Vφ 1, Vφ 2
Vφ 1L, Vφ 2L
Vφ R
Shift register clock voltage
V
Last stage shift register clock voltage
Reset gate clock voltage
V
V
Reset feed-through level clamp clock voltage
Dpi select signal voltage
Vφ CLB
V
Vφ SEL
V
Transfer gate clock voltage
Vφ TG1 to Vφ TG3
TA
V
Operating ambient temperature Note
˚C
˚C
Storage temperature
Tstg
–40 to +70
Note The operating ambient temperature TA is defined as an atmosphere temperature in a point 10 mm away on the
substrate, and 10 mm away from the short side of package (pin 1 side). Use at the condition without dewy
condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25°C)
Parameter
Output drain voltage
Symbol
MIN.
11.4
4.75
0
TYP.
12.0
5.0
0
MAX.
12.6
5.5
Unit
V
VOD1, VOD2
Shift register clock high level
Shift register clock low level
Last stage shift register clock high level
Last stage shift register clock low level
Reset gate clock high level
Vφ 1H, Vφ 2H
Vφ 1L, Vφ 2L
Vφ 1LH, Vφ 2LH
Vφ 1LL, Vφ 2LL
Vφ RH
V
0.15
5.5
V
4.75
0
5.0
0
V
0.15
5.5
V
4.75
0
5.0
0
V
Reset gate clock low level
Vφ RL
0.15
5.5
V
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
Dpi select signal high level
Vφ CLBH
4.75
0
5.0
0
V
Vφ CLBL
0.15
5.5
V
Vφ SELH
4.75
0
5.0
0
V
Dpi select signal low level
Vφ SELL
0.15
V
Note
Note
Transfer gate clock high level
Transfer gate clock low level
Data rate
Vφ TG1H to Vφ TG3H
Vφ TG1L to Vφ TG3L
fφ R
4.75
0
Vφ 1H
Vφ 1H
V
0
2
2
0.15
V
–
20
20
MHz
MHz
Clock pulse frequency
fφ 1, fφ 2
–
Note When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than Shift register clock high level (Vφ 1H),
Image lag increases.
5
Data Sheet S18773EJ1V0DS
μ PD8874
ELECTRICAL CHARACTERISTICS
TA = +25°C, VOD = 12 V, data rate (fφ R) = 2 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p
light source: 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm)+ HA-50 (heat absorbing filter, t = 3 mm)
Parameter
Saturation voltage
Saturation exposure
Symbol
Test Conditions
MIN.
TYP.
2.5
MAX.
–
Unit
V
Vsat
2.0
Red
SER
–
–
0.25
0.27
0.5
–
lx•s
lx•s
lx•s
%
Green SEG
–
Blue
SEB
PRNU
ADS
DSNU
PW
–
–
Photo response non-uniformity
Average dark signal
VOUT = 1.0 V
–
6
20
2.0
5.0
540
0.4
13.0
11.7
6.5
7.0
8.5
–
Light shielding
Light shielding
Light shielding
–
0.2
mV
mV
mW
kΩ
Dark signal non-uniformity
Total power consumption
Output impedance
–
1.5
–
360
0.2
ZO
–
Response
Red
RR
7.0
6.3
3.5
–
10.0
9.0
V/lx•s
V/lx•s
V/lx•s
%
Green RG
Blue
RB
IL
5.0
Image lag
VOUT = 1.0 V
3.0
Offset level
VOS
td
6.5
–
7.5
V
Output fall delay time Note
VOUT = 1.0 V
15
ns
Total transfer efficiency Note
TTE
RI
VOUT = 1.0 V, data rate = 20 MHz
VOUT = 1.0 V
92
–
98
–
%
Register imbalance
1.0
4.0
–
%
Response peak
Red
–
610
535
460
1666
1041
–100
500
2.4
nm
Green
Blue
–
–
nm
–
–
nm
Dynamic range
DR1
Vsat / DSNU
–
–
times
times
mV
mV
mV
DR2
Vsat / σ dark
–
–
Reset feed-through noise
Random noise
RFTN
PRFTN
σ dark
Light shielding
–2000
–
+500
800
–
Light shielding, t4 and t5 = 2 ns
Light shielding, Bit clamp (t11 > 10 ns)
–
Note When the fall time of φ1L and φ2L (t1L and t2L) is the typical value (refer to TIMING CHART 2-1 to 2-3).
6
Data Sheet S18773EJ1V0DS
μ PD8874
INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V)
Parameter
Symbol
Pin name
Pin No.
MIN.
–
TYP.
550
550
1100
550
550
1100
10
MAX.
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Shift register clock pin capacitance 1
Cφ 1
φ1
8
–
–
–
–
–
–
–
–
–
–
15
–
Cφ 1 total capacitance
φ2
–
Shift register clock pin capacitance 2
Cφ 2
9
–
16
–
Cφ 2 total capacitance
–
Last stage shift register clock pin capacitance 1 Cφ 1L
Last stage shift register clock pin capacitance 2 Cφ 2L
φ1L
φ2L
φR
5
17
3
–
–
10
Reset gate clock pin capacitance
Cφ R
–
10
Reset feed-through level clamp clock pin
capacitance
Cφ CLB
φCLB
4
–
10
Dpi select signal pin capacitance
Transfer gate clock pin capacitance
Cφ SEL
Cφ TG
φSEL
φTG1
φTG2
φTG3
14
13
12
10
–
–
–
–
10
–
–
–
–
pF
pF
pF
pF
100
100
100
Remarks 1. Pin 8, 15 (φ1) and pin 9, 16 (φ2) are each connected inside of the device.
2. Cφ 1 and Cφ 2 show the equivalent capacity of the real drive including the capacity of between φ1 and φ2.
7
Data Sheet S18773EJ1V0DS
μ PD8874
0 8 1 6 8
0 8 1 6 5
0 8 1 6 4
6 5
6 4
6 1
6 0
1 4
1 3
1 2
1 1
φ
5
4
3
2
1
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
8
Data Sheet S18773EJ1V0DS
μ PD8874
1 0 8 6 8
1 0 8 6 5
1 0 8 6 4
6 5
6 4
6 1
6 0
1 4
1 3
1 2
1 1
φ
5
4
3
2
1
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
9
Data Sheet S18773EJ1V0DS
μ PD8874
8 6 1 8 0
8 6 1 6 0
8 6 1 4 0
6 6
6 4
6 2
6 0
1 4
1 2
1 0
8
φ
6
4
2
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
10
Data Sheet S18773EJ1V0DS
μ PD8874
1 0 8 6 8
1 0 8 6 6
1 0 8 6 4
6 6
6 4
6 2
6 0
1 4
1 2
1 0
8
φ
6
4
2
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
11
Data Sheet S18773EJ1V0DS
μ PD8874
8
4
+ 1 0 8 6 1 0 8 6 6
1 0 8 6
6
+ 1 0 8 6 1 0 8 6 2
2
1 0 8 6
6 6 + 6 8
6 6
6 2 + 6 4
6 2
5 8 + 6 0
5 8
1 4 + 1 6
1 4
1 0 + 1 2
1 0
6 + 8
6
φ
2 + 4
2
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
12
Data Sheet S18773EJ1V0DS
μ PD8874
8
4
+ 1 0 8 6 1 0 8 6 6
1 0 8 6
6
+ 1 0 8 6 1 0 8 6 2
2
8
1 0 8 6
6 6 + 6
6 6
4
0
6 2 + 6
6 2
5 8 + 6
5 8
6
1 4 + 1
1 4
1 0 + 1 2
1 0
6 + 8
6
φ
2 + 4
2
φ
φ
φ
φ
φ
φ
φ
φ
φ
φ
13
Data Sheet S18773EJ1V0DS
μ PD8874
TIMING CHART 2-1 (1200 dpi, for each color)
t1
t2
90%
φ1
10%
90%
φ2
10%
t1L
t2L
90%
φ1L
10%
90%
10%
φ2L
90%
φR
10%
t3
t3
t11
t11
t8
t4
t5
t6
t4
t5
t6
t8
t9
t9
t7
t7
t10
t10
90%
10%
φCLB
(Bit clamp mode)
"H"
φCLB
(Line clamp mode)
t
d
td
V
OUT
10%
Symbol
MIN.
0
TYP. Note
MAX.
Unit
t1, t2
15
5
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
t1L, t2L
t3
0
5
50
5
t4, t5
t6
0
0
70
50
5
t7
10
0
t8, t9
t10
0
45
50
t11
10
Note TYP. is the case of φR = 2 MHz
14
Data Sheet S18773EJ1V0DS
μ PD8874
TIMING CHART 2-2 (600 dpi, for each color)
t2
t1
90%
10%
φ1
φ2
90%
10%
t2L
t1L
90%
10%
φ1L
φ2L
90%
10%
90%
10%
φR
t3
t11
t8
t4
t5
t6
t9
t7
t10
90%
φCLB
(Bit clamp mode)
10%
"H"
φCLB
(Line clamp mode)
t
d
V
OUT
10%
Symbol
MIN.
0
TYP. Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t1, t2
15
5
–
–
–
–
–
–
–
–
–
t1L, t2L
t3
0
5
50
5
t4, t5
t6
0
0
70
50
5
t7
10
0
t8, t9
t10
0
45
50
t11
10
Note TYP. is the case of φR = 2 MHz
15
Data Sheet S18773EJ1V0DS
μ PD8874
TIMING CHART 2-3 (300 dpi, for each color)
t2
t1
90%
10%
φ1
φ2
90%
10%
t2L
t1L
90%
10%
φ1L
φ2L
90%
10%
90%
10%
t4
φR
t3
t5
t11
t8
t9
t7
t6
t10
90%
φCLB
(Bit clamp mode)
10%
"H"
φCLB
(Line clamp mode)
t
d
V
OUT
10%
Symbol
MIN.
0
TYP. Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
t1, t2
15
5
–
–
–
–
–
–
–
–
–
t1L, t2L
t3
0
5
50
5
t4, t5
t6
0
0
70
50
5
t7
10
0
t8, t9
t10
0
45
50
t11
10
Note TYP. is the case of φR = 1 MHz
16
Data Sheet S18773EJ1V0DS
μ PD8874
φTG1 to φTG3, φ1, φ2 TIMING CHART
t13
t14
t12
90%
10%
φTG1 to φTG3
t15
t16
90%
φ1, φ1L
φ2, φ2L
φR
t11
t17
t18
Note
10%
φCLB
(Bit clamp mode)
φCLB
(Line clamp mode)
t7
Symbol
t7
MIN.
10
TYP.
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
–
t11
10
50
–
t12
5000
0
10000
50
50000
t13, t14
t15, t16
t17, t18
–
–
–
900
200
1000
400
Note Set the φR to low level and φCLB to high level during this period.
17
Data Sheet S18773EJ1V0DS
μ PD8874
φ1, φ2 cross points
φ1
1.5 V or more
1.5 V or more
φ2
φ1, φ2L cross points, φ2, φ1L cross points
φ1
φ2
3 V or more
3 V or more
0.2 V or more
0.2 V or more
φ2L
φ1L
Remark Adjust cross points (φ1, φ2), (φ1L, φ2) and (φ1, φ2L) with input resistance of each pin.
φ1, φ2, φ1L, φ2L clock width
Min. 7 ns
Min. 15 ns
4.75 V
4.75 V
φ1, φ2
φ1, φ2
φ1L, φ2L
φ1L, φ2L
0.25 V
0.25 V
Min. 7 ns
Min. 15 ns
φTG, φSEL TIMING CHART
90%
φTG1 to φTG3
10%
t19
t20
φSEL (High to Low)
φSEL (Low to High)
90%
10%
Symbol
MIN.
0
TYP.
0
MAX.
Unit
ns
t19
t20
–
–
4500
9500
ns
18
Data Sheet S18773EJ1V0DS
μ PD8874
SELECTION OF RESOLUTION MODE
The μPD8874 has function of two readout modes, High Resolution Mode and Low Resolution Mode. These two
modes can be selected by φSEL switch.
Read Mode
High Resolution Mode
Low Resolution Mode
Description
φSEL
1200 dpi (Max.)
600 dpi (Max.) (even line readout mode)
High level
Low level
(1) High Resolution Mode
In this mode, both signals in even lines and odd lines can be read out. This mode enables 1200 dpi (Max.)
resolution with A4 size (210 × 297 mm, shorter side).
Please refer to TIMING CHART 1-1, 1-2 and 2-1.
(2) Low Resolution Mode
In this mode, only signal in even lines can be read out.
This mode enables 600 dpi (Max.) resolution with A4 size.
To use intermittent reset drive enable signal charges of adjacent pixels in even line to add at the charge to voltage
conversion area. Then it can achieve low resolution with A4 size such as 300, 200 or 150 dpi.
Please refer to TIMING CHART 1-3 to 1-6, 2-2 and 2-3.
19
Data Sheet S18773EJ1V0DS
μ PD8874
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of
uniform illumination. This is calculated by the following formula.
Δ x
× 100
PRNU (%) =
x
Δx : maximum of | x − x |
j
10800
x
j
Σ
j=1
x =
10800
xj
: Output voltage of valid pixel number j
V
OUT
x
Register Dark
DC level
Δ x
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
10800
dj
Σ
j=1
ADS (mV) =
10800
dj
: Dark signal of valid pixel number j
20
Data Sheet S18773EJ1V0DS
μ PD8874
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid
pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of | dj − ADS | j = 1 to 10800
dj : Dark signal of valid pixel number j
V
OUT
ADS
Register Dark
DC level
DSNU
6. Output impedance : ZO
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lx•s).
Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
φTG
Light
ON
OFF
V
OUT
V
1
V
OUT
V
1
× 100
IL (%) =
V
OUT
21
Data Sheet S18773EJ1V0DS
μ PD8874
9. Register imbalance : RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the
average output voltage of all the valid pixels.
n
2
2
n
(V2j–1 – V2j
)
Σ
j=1
× 100
RI (%) =
n
1
n
V
j
Σ
j=1
n
: Number of valid pixels
V
j
: Output voltage of each pixel
10. Offset level : VOS
DC level of output signal is defined as follows.
11. Reset feed-through noise : RFTN, PRFTN
Reset feed-through noise (RFTN) and peak of RFTN (PRFTN) are defined as follows.
+
PRFTN
PRFTN
RFTN
–
V
OUT
V
OS
22
Data Sheet S18773EJ1V0DS
μ PD8874
12. Light shielding random noise: σ dark
Light shielding random noise σ dark is defined as the standard deviation of a valid pixel output signal with 100
times (= 100 lines) data sampling at dark (light shielding).
100
(Vi – V)2
Σ
100
i=1
1
100
,
V =
Vi
Σ
σ (mV) =
100
i=1
Vi : A valid pixel output signal among all of the valid pixels for each
V
OUT
line1
line2
V
V
1
2
line100
V
100
Remark This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double
Sampling)
23
Data Sheet S18773EJ1V0DS
μ PD8874
STANDARD CHARACTERISTIC CURVES (Reference Value)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T = +25°C)
A
2
8
4
1
2
1
0.5
0.2
0.1
0.25
0.1
0
10
20
30
40 50
1
5
10
Storage Time (ms)
Operating Ambient Temperature T (°C)
A
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter and heat absorbing filter) (TA = +25°C)
110%
100%
90%
R
G
80%
B
70%
60%
50%
40%
30%
20%
10%
0%
400
450
500
550
600
650
700
Wavelength (nm)
24
Data Sheet S18773EJ1V0DS
μ PD8874
APPLICATION CIRCUIT EXAMPLE
+12 V
A equivalent circuit
+12 V
+
+
47 μ F
+5 V
0.1 μ F 47 μ F
+
B3
1
2
V
V
OUT
3
V
OUT
2
1
1
22
21
20
B2
A
47 μ F 0.1 μ F
OD
2
A
V
OD
+5 V
φR
47 Ω
φCLB
47 Ω
φ1L
φR
3
V
OUT
B1
+
φCLB
φ1L
4
GND 19
NC 18
0.1 μ F 47 μ F
5
47 Ω
φ2L
φ2
φ2L
6
NC
17
16
15
14
13
12
47 Ω
φ2
7
NC
3
3
4.7 Ω
φ1
φ2
φ1
φ1
φ1
3
3
8
4.7 Ω
4.7 Ω
4.7 Ω
φ2
φSEL
φTG1
φTG2
φSEL
φTG1
φTG2
9
150 Ω
φTG3
φTG3
10
10 Ω
10 Ω
10 Ω
11 GND
Caution Connect the no connection pins (NC) to GND.
Remark The inverters are the 74AC04, and pins 8, 9, 15 and 16 (φ1, φ2) connect three inverters in parallel.
B1 to B3 EQUIVALENT CIRCUIT
+12 V
+
1.5 kΩ
47 μ F/25 V
110 Ω
CCD
2SA1206
V
OUT
25
Data Sheet S18773EJ1V0DS
μ PD8874
PACKAGE DRAWING
μ
PD8874CY-A
CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400))
(Unit : mm)
44.0 0.3
9.25 0.3
12
11
22
1
1
4
0.4 0.3
1st valid pixel
2.0
4
37.5
2
10.16 0.2
(1.72)
1.02 0.15
4.39 0.4
3
2.62 0.2
(5.42)
4.21 0.5
0.25 0.05
0.46 0.1
2.54 0.25
+
0.7
0.2
10.16
Name
Dimensions
42.7×8.35×0.8(0.7
Refractive index
5
Plastic cap
)
1.5
1 Distance between the 1st valid pixel and the center of the pin1
2 Distance between the top of the cap and the surface of the CCD chip
3
4
Distance between the bottom of the package and the surface of the CCD chip
Transparent window
5 Thickness of the transparent window
22C-1CCD-PKG19
NEC Electronics Corporation 2007
26
Data Sheet S18773EJ1V0DS
μ PD8874
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
Type of Through-hole Device
μPD8874CY-A: CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
Process
Conditions
Partial heating method
Pin temperature: 380°C or below, Heat time: 3 seconds or less (per pin).
Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the plastic cap.
The optical characteristics could be degraded by such contact.
2. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap
soiling and heat resistance. So the method cannot be guaranteed.
27
Data Sheet S18773EJ1V0DS
μ PD8874
NOTES ON HANDLING THE PACKAGES
1
DUST AND DIRT PROTECTING
The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either
touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt
stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is
recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents.
CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below.
Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is
recommended that a clean surface or cloth be used.
RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap.
Use of solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
Solvents
Ethyl Alcohol
Symbol
EtOH
MeOH
IPA
Methyl Alcohol
Isopropyl Alcohol
N-methyl Pyrrolidone
NMP
2
MOUNTING OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips
to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't
have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to
use a IC-inserter when you assemble to PCB.
Also, be care that the any of the following can cause the package to crack or dust to be generated.
1. Applying heat to the external leads for an extended period of time with soldering iron.
2. Applying repetitive bending stress to the external leads.
3. Rapid cooling or heating
3
4
OPERATE AND STORAGE ENVIRONMENTS
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject
to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid
storage or usage in such conditions.
Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the
devices are transported from a low-temperature environment to a high-temperature environment. Avoid such
rapid temperature changes.
For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes
detected. Before handling be sure to take the following protective measures.
1. Ground the tools such as soldering iron, radio cutting pliers of or pincer.
2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity.
3. Either handle bare handed or use non-chargeable gloves, clothes or material.
4. Ionized air is recommended for discharge when handling CCD image sensor.
5. For the shipment of mounted substrates, use box treated for prevention of static charges.
6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on
which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle
straps which are grounded via a series resistance connection of about 1 MΩ.
28
Data Sheet S18773EJ1V0DS
μ PD8874
[MEMO]
29
Data Sheet S18773EJ1V0DS
μ PD8874
[MEMO]
30
Data Sheet S18773EJ1V0DS
μ PD8874
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
31
Data Sheet S18773EJ1V0DS
μ PD8874
•
The information in this document is current as of June 2007. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
相关型号：
UPD8894CY-A
CCD Sensor, 5340 Horiz pixels, 5340 Vert pixels, 2.50-2.80V, Rectangular, Through Hole Mount, PLASTIC, DIP-32
NEC
©2020 ICPDF网 联系我们和版权申明