74AVC4T774PW [NEXPERIA]
4-bit dual supply translating transceiver; 3-stateProduction;型号: | 74AVC4T774PW |
厂家: | Nexperia |
描述: | 4-bit dual supply translating transceiver; 3-stateProduction |
文件: | 总20页 (文件大小:290K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
Rev. 2 — 20 October 2021
Product data sheet
1. General description
The 74AVC4T774PW is a 4-bit, dual supply transceiver that enables bidirectional level translation.
It features eight 1-bit input-output ports (An and Bn), four direction control inputs (DIR1, DIR2, DIR3
and DIR4), an output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and
VCC(B) can be supplied at any voltage between 0.8 V and 1.95 V for translating between the 0.8 V,
1.2 V, 1.5 V and 1.8 V supply voltage nodes or 1.1 V to 3.6 V for translating between the 1.2 V,
1.5 V, 1.8 V, 2.5 V and 3.3 V supply voltage nodes. Pins An, OE and DIRn are referenced to VCC(A)
and pins Bn are referenced to VCC(B). A HIGH on DIRn allows transmission from An to Bn and a
LOW on DIRn allows transmission from Bn to An. The output enable input (OE) can be used to
disable the outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing any damaging backflow current through the device when it is
powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both An and Bn
are in the high-impedance OFF-state.
2. Features and benefits
•
Wide supply voltage range:
VCC(A) and VCC(B): 0.8 V to 1.95 V or 1.1 V to 3.6 V
Complies with JEDEC standards:
•
•
•
•
•
•
•
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
•
•
ESD protection:
•
•
HBM JESD22-A114E Class 3B exceeds 8000 V
CDM JESD22-C101C exceeds 1500 V
Maximum data rates:
•
•
•
•
•
•
380 Mbit/s (≥ 1.8 V to 3.3 V translation)
200 Mbit/s (≥ 1.1 V to 3.3 V translation)
200 Mbit/s (≥ 1.1 V to 2.5 V translation)
200 Mbit/s (≥ 1.1 V to 1.8 V translation)
150 Mbit/s (≥ 1.1 V to 1.5 V translation)
100 Mbit/s (≥ 1.1 V to 1.2 V translation)
•
•
•
•
•
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
IOFF circuitry provides partial Power-down mode operation
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74AVC4T774PW -40 °C to +125 °C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
4. Marking
Table 2. Marking codes
Type number
Marking code
74AVC4T774PW
VC4T774
5. Functional diagram
B1
B2
B3
B4
V
CC(B)
V
CC(A)
A1 DIR1
A2 DIR2
A3 DIR3
A4 DIR4
OE
001aao069
Fig. 1. Logic symbol
OE
An
DIRn
Bn
V
V
CC(B)
CC(A)
to next transceiver
001aao070
Fig. 2. Logic diagram (one 1-bit transceiver)
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
2 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
6. Pinning information
6.1. Pinning
74AVC4T774
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DIR1
V
V
CC(A)
CC(B)
DIR2
A1
B1
A2
B2
A3
B3
A4
B4
DIR3
DIR4
GND
OE
aaa-027528
Fig. 3. Pin configuration SOT403-1 (TSSOP16)
6.2. Pin description
Table 3. Pin description
Symbol
Pin
Description
VCC(A)
16
supply voltage A (An, OE and DIRn inputs are referenced to VCC(A)
)
DIR1, DIR2, DIR3, DIR4 1, 2, 7, 8
direction control input
A1, A2, A3, A4
GND
3, 4, 5, 6
data input or output
10
ground (0 V)
B1, B2, B3, B4
OE
14, 13, 12, 11
data input or output
9
output enable input (active LOW)
VCC(B)
15
supply voltage B (Bn pins are referenced to VCC(B))
7. Functional description
Table 4. Function table [1] [2]
Supply voltage
VCC(A), VCC(B)
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
GND [3]
Input
Input/output
An
OE
L
DIR1
L
DIR2
X
DIR3
X
DIR4
X
Bn
A1 = B1
input A1
A2 = B2
input A2
A3 = B3
input A3
A4 = B4
input A4
Z
input B1
B1 = A1
input B2
B2 = A2
input B3
B3 = A3
input B4
B4 = A4
Z
L
H
X
X
X
L
X
L
X
X
L
X
H
X
X
L
X
X
L
X
L
X
X
H
X
L
X
X
X
L
L
X
X
X
H
H
X
X
X
X
X
X
X
X
X
Z
Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2] The An, DIRn and OE input circuit is referenced to VCC(A); The Bn input circuit is referenced to VCC(B)
[3] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
.
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
3 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-0.5
-50
-0.5
-50
-0.5
-0.5
-
Max
+4.6
+4.6
-
Unit
V
VCC(A) supply voltage A
VCC(B) supply voltage B
V
IIK
input clamping current
VI < 0 V
mA
V
VI
input voltage
[1]
+4.6
-
IOK
VO
output clamping current
output voltage
VO < 0 V
mA
V
Active mode
[1] [2] [3]
[1]
VCCO + 0.5
+4.6
±50
Suspend or 3-state mode
VO = 0 V to VCCO
ICC(A) or ICC(B)
V
IO
output current
[2]
mA
mA
mA
°C
mW
ICC
IGND
Tstg
Ptot
supply current
-
100
ground current
-100
-65
-
-
storage temperature
total power dissipation
+150
500
Tamb = -40 °C to +125 °C
[4]
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 4.6 V.
[4] For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
9. Recommended operating conditions
Table 6. Recommended operating conditions
Symbol Parameter
Conditions
Min
0.8
0.8
0
Max
3.6
Unit
V
VCC(A) supply voltage A
VCC(B) supply voltage B
3.6
V
VI
input voltage
3.6
V
VO
output voltage
Active mode
[1]
[2]
0
VCCO
3.6
V
Suspend or 3-state mode
0
V
Tamb
ambient temperature
-40
-
+125
10
°C
ns/V
Δt/ΔV
input transition rise and fall rate
VCCI =0.8 V to 3.6 V
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the input port.
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
4 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
10. Static characteristics
Table 7. Typical static characteristics at Tamb = 25 °C [1] [2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
0.69
0.07
Max Unit
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = -1.5 mA; VCC(A) = VCC(B) = 0.8 V
VI = VIH or VIL
-
-
-
V
V
VOL
LOW-level
output voltage
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V
-
-
II
input leakage DIRn, OE input; VI = 0 V or 3.6 V;
±0.025 ±0.25 μA
current
VCC(A) = VCC(B) = 0.8 V to 3.6 V
IOZ
OFF-state
output current
A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 3.6 V
[3]
[3]
-
-
±0.5
±0.5
±2.5 μA
±2.5 μA
suspend mode A port; VO = 0 V or VCCO
;
VCC(A) = 3.6 V; VCC(B) = 0 V
suspend mode B port; VO = 0 V or VCCO
VCC(A) = 0 V; VCC(B) = 3.6 V
;
[3]
-
-
-
-
-
±0.5
±0.1
±0.1
2.0
±2.5 μA
IOFF
power-off
leakage
current
A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V;
VCC(B) = 0.8 V to 3.6 V
±1
±1
-
μA
μA
pF
pF
B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V;
VCC(A) = 0.8 V to 3.6 V
CI
input
DIRn, OE input; VI = 0 V or 3.3 V; VCC(A) = VCC(B) = 3.3 V
capacitance
CI/O
input/output
capacitance
A and B port; VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V
4.0
-
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] For I/O ports, the parameter IOZ includes the input leakage current.
Table 8. Static characteristics [1] [2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C
Unit
Min
Max
Min
Max
VIH
HIGH-level
data input
input voltage
VCCI = 0.8 V
0.70VCCI
0.65VCCI
1.6
-
-
-
-
0.70VCCI
0.65VCCI
1.6
-
-
-
-
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIRn, OE input
2
2
VCC(A) = 0.8 V
0.70VCC(A)
-
-
-
-
0.70VCC(A)
-
-
-
-
V
V
V
V
VCC(A) = 1.1 V to 1.95 V
VCC(A) = 2.3 V to 2.7 V
VCC(A) = 3.0 V to 3.6 V
0.65VCC(A)
0.65VCC(A)
1.6
2
1.6
2
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
5 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C
Unit
Min
Max
Min
Max
VIL
LOW-level
data input
input voltage
VCCI = 0.8 V
-
-
-
-
0.30VCCI
0.35VCCI
0.7
-
-
-
-
0.30VCCI
0.35VCCI
0.7
V
V
V
V
VCCI = 1.1 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
DIRn, OE input
0.8
0.8
VCC(A) = 0.8 V
-
-
-
-
0.30VCC(A)
0.35VCC(A)
0.7
-
-
-
-
0.30VCC(A)
0.35VCC(A)
0.7
V
V
V
V
VCC(A) = 1.1 V to 1.95 V
VCC(A) = 2.3 V to 2.7 V
VCC(A) = 3.0 V to 3.6 V
VI = VIH or VIL
0.8
0.8
VOH
HIGH-level
output voltage
IO = -100 μA;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
VCCO - 0.1
0.85
-
-
-
-
-
-
VCCO - 0.1
0.85
-
-
-
-
-
-
V
V
V
V
V
V
IO = -3 mA;
VCC(A) = VCC(B) = 1.1 V
IO = -6 mA;
VCC(A) = VCC(B) = 1.4 V
1.05
1.05
IO = -8 mA;
VCC(A) = VCC(B) = 1.65 V
1.2
1.2
IO = -9 mA;
VCC(A) = VCC(B) = 2.3 V
1.75
1.75
IO = -12 mA;
2.3
2.3
VCC(A) = VCC(B) = 3.0 V
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 100 μA;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
-
-
-
-
-
-
-
-
-
0.1
0.25
0.35
0.45
0.55
0.7
-
-
-
-
-
-
-
-
-
0.1
0.25
0.35
0.45
0.55
0.7
V
IO = 3 mA;
VCC(A) = VCC(B) = 1.1 V
V
IO = 6 mA;
VCC(A) = VCC(B) = 1.4 V
V
IO = 8 mA;
VCC(A) = VCC(B) = 1.65 V
V
IO = 9 mA;
VCC(A) = VCC(B) = 2.3 V
V
IO = 12 mA;
VCC(A) = VCC(B) = 3.0 V
V
II
input leakage DIRn, OE input; VI = 0 V or 3.6 V;
current
±1
±5
μA
μA
μA
VCC(A) = VCC(B) = 0.8 V to 3.6 V
IOZ
OFF-state
output current VCC(A) = VCC(B) = 3.6 V
A or B port; VO = 0 V or VCCO
;
[3]
[3]
±5
±30
±30
suspend mode A port;
±5
VO = 0 V or VCCO; VCC(A) = 3.6 V;
VCC(B) = 0 V
suspend mode B port;
VO = 0 V or VCCO; VCC(A) = 0 V;
VCC(B) = 3.6 V
[3]
-
±5
-
±30
μA
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
6 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C
Unit
Min
Max
Min
Max
IOFF
power-off
leakage
current
A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
-
±5
-
±30
μA
μA
B port; VI or VO = 0 V to 3.6 V;
-
±5
-
±30
VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
ICC
supply current A port; VI = 0 V or VCCI; IO = 0 A
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
-
-
10
8
-
-
55
50
μA
μA
VCC(A) = 1.1 V to 3.6 V;
VCC(B) = 1.1 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
VCC(A) = 0 V; VCC(B) = 3.6 V
B port; VI = 0 V or VCCI; IO = 0 A
-
8
-
-
50
-
μA
μA
-2
-12
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
-
-
10
8
-
-
55
50
μA
μA
VCC(A) = 1.1 V to 3.6 V;
VCC(B) = 1.1 V to 3.6 V
VCC(A) = 3.6 V; VCC(B) = 0 V
VCC(A) = 0 V; VCC(B) = 3.6 V
A plus B port (ICC(A) + ICC(B));
-2
-
-
-12
-
μA
μA
μA
8
-
-
50
70
-
20
IO = 0 A; VI = 0 V or VCCI
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
;
A plus B port (ICC(A) + ICC(B));
-
-
16
-
-
65
μA
μA
IO = 0 A; VI = 0 V or VCCI
VCC(A) = 1.1 V to 3.6 V;
VCC(B) = 1.1 V to 3.6 V
;
ΔICC
additional
VI = 3.0 V; VCC(A) = VCC(B) = 3.6 V
500
650
supply current
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the data input port.
[3] For I/O ports, the parameter IOZ includes the input leakage current.
Table 9. Typical total supply current (ICC(A) + ICC(B)
)
VCC(A)
VCC(B)
0 V
0
Unit
0.8 V
0.1
0.1
0.1
0.1
0.1
0.3
1.6
1.2 V
0.1
0.1
0.1
0.1
0.1
0.1
0.8
1.5 V
0.1
0.1
0.1
0.1
0.1
0.1
0.4
1.8 V
2.5 V
3.3 V
0.1
1.6
0.8
0.4
0.2
0.1
0.1
0 V
0.1
0.1
0.1
0.1
0.1
0.1
0.2
0.1
0.3
0.1
0.1
0.1
0.1
0.1
μA
μA
μA
μA
μA
μA
μA
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.1
0.1
0.1
0.1
0.1
0.1
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
7 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
11. Dynamic characteristics
Table 10. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C [1] [2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VCC(A) = VCC(B)
Unit
0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V
CPD
power
dissipation
capacitance
A port: (direction An to Bn); output enabled
0.2
0.2
0.2
9.7
0.6
9.7
0.6
0.2
0.2
0.2
0.2
9.8
0.6
9.8
0.6
0.2
0.2
0.2
0.2
9.9
0.6
9.9
0.6
0.2
0.2
0.3
0.3
0.4 pF
A port: (direction An to Bn); output disabled 0.2
A port: (direction Bn to An); output enabled 9.5
A port: (direction Bn to An); output disabled 0.6
B port: (direction An to Bn); output enabled 9.5
B port: (direction An to Bn); output disabled 0.6
B port: (direction Bn to An); output enabled 0.2
B port: (direction Bn to An); output disabled 0.2
0.4 pF
11.9 pF
0.7 pF
11.9 pF
0.7 pF
0.4 pF
0.4 pF
10.7
0.7
10.7
0.7
0.3
0.3
[1] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD x VCC 2 × fi x N + Σ(CL x VCC 2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL x VCC 2 x fo) = sum of the outputs.
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω.
Table 11. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 6; for waveforms see Fig. 4 and Fig. 5
Symbol Parameter
Conditions
VCC(B)
Unit
0.8 V
14.5
14.5
14.3
17.0
18.2
19.2
1.2 V
7.3
1.5 V
6.5
1.8 V
tpd
tdis
ten
propagation delay An to Bn
6.2
12.3
14.3
9.4
ns
ns
ns
ns
ns
ns
Bn to An
OE to An
OE to Bn
OE to An
OE to Bn
12.7
14.3
9.9
12.4
14.3
9.0
disable time
enable time
18.2
10.7
18.2
9.8
18.2
9.6
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
Table 12. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 6; for waveforms see Fig. 4 and Fig. 5
Symbol Parameter
Conditions
VCC(A)
Unit
0.8 V
14.5
14.5
14.3
17.0
18.2
19.2
1.2 V
12.7
7.3
1.5 V
12.4
6.5
1.8 V
12.3
6.2
tpd
tdis
ten
propagation delay An to Bn
ns
ns
ns
ns
ns
ns
Bn to An
OE to An
OE to Bn
OE to An
OE to Bn
disable time
enable time
5.5
4.1
4.0
13.8
5.6
13.4
4.0
13.1
3.2
14.6
14.1
13.9
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
8 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
Table 13. Dynamic characteristics for temperature range -40 °C to +85 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 6; for waveforms see Fig. 4 and Fig. 5
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V ±0.1 V 1.5 V ±0.1 V 1.8 V ±0.15 V 2.5 V ±0.2 V 3.3 V ±0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
VCC(A) = 1.1 V to 1.3 V
tpd
tdis
ten
propagation An to Bn
2.0
2.0
2.0
2.0
2.0
2.0
10.5
10.5
10.0
11.1
13.5
15.0
1.3
1.5
2.0
2.0
2.0
2.0
7.8
9.9
1.2
1.5
2.0
1.0
2.0
2.0
6.9
9.7
1.0
1.4
2.0
0.7
2.0
1.0
5.9
9.4
0.8
1.4
2.0
1.0
2.0
1.0
5.7 ns
9.3 ns
10.0 ns
8.0 ns
13.5 ns
7.4 ns
delay
Bn to An
disable time OE to An
OE to Bn
10.0
8.6
10.0
8.0
10.0
7.0
enable time OE to An
OE to Bn
13.5
11.0
13.5
9.4
13.5
7.8
VCC(A) = 1.4 V to 1.6 V
tpd
tdis
ten
propagation An to Bn
delay
1.5
1.3
1.0
2.0
1.0
2.0
9.9
7.8
1.0
1.0
1.0
1.5
1.0
1.4
7.1
7.1
6.0
7.5
7.5
7.9
1.0
0.9
1.0
0.9
1.0
1.3
6.0
6.9
6.0
7.2
7.5
7.7
0.5
0.8
1.0
0.4
1.0
1.1
4.8
6.6
6.0
6.2
7.5
6.4
0.5
0.6
1.0
0.4
1.0
1.1
4.3 ns
6.5 ns
6.0 ns
6.1 ns
7.5 ns
5.6 ns
Bn to An
disable time OE to An
OE to Bn
6.0
10.2
7.5
enable time OE to An
OE to Bn
14.4
VCC(A) = 1.65 V to 1.95 V
tpd
tdis
ten
propagation An to Bn
delay
1.5
1.2
0.5
2.0
1.0
1.5
9.7
6.9
0.9
1.0
0.5
1.5
1.0
1.2
6.9
6.0
5.7
7.0
6.7
7.2
0.8
0.8
0.5
0.8
1.0
1.2
5.7
5.7
5.7
6.9
6.7
6.9
0.5
0.5
0.5
0.2
1.0
0.8
4.5
5.5
5.7
5.8
6.7
5.4
0.3
0.5
0.5
0.2
1.0
0.6
4.0 ns
5.3 ns
5.7 ns
5.9 ns
6.7 ns
5.0 ns
Bn to An
disable time OE to An
OE to Bn
5.7
9.9
enable time OE to An
OE to Bn
6.7
13.9
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
ten
propagation An to Bn
delay
1.4
1.0
0.2
2.0
0.6
1.5
9.4
5.9
0.8
0.5
0.2
1.5
0.6
1.0
6.6
4.8
4.0
6.7
4.5
6.8
0.5
0.5
0.2
0.7
0.6
1.0
5.5
4.5
4.0
6.3
4.5
6.0
0.4
0.4
0.2
0.2
0.6
0.8
4.2
4.2
4.0
5.0
4.5
4.6
0.2
0.3
0.2
0.2
0.6
0.6
3.7 ns
3.9 ns
4.0 ns
5.7 ns
4.5 ns
4.2 ns
Bn to An
disable time OE to An
OE to Bn
4.0
9.3
enable time OE to An
OE to Bn
4.5
13.6
VCC(A) = 3.0 V to 3.6 V
tpd
tdis
ten
propagation An to Bn
delay
1.4
0.8
0.2
2.0
0.5
1.5
9.3
5.7
0.6
0.5
0.2
1.5
0.5
1.0
6.5
4.3
4.5
6.4
4.0
6.7
0.5
0.3
0.2
0.7
0.5
1.0
5.3
4.0
4.5
6.1
4.0
5.9
0.3
0.2
0.2
0.2
0.5
0.7
3.9
3.7
4.5
4.8
4.0
4.4
0.2
0.2
0.2
0.2
0.5
0.5
3.5 ns
3.5 ns
4.5 ns
5.6 ns
4.0 ns
4.0 ns
Bn to An
disable time OE to An
OE to Bn
4.5
9.0
enable time OE to An
OE to Bn
4.0
13.4
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
9 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
Table 14. Dynamic characteristics for temperature range -40 °C to +125 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 6; for waveforms see Fig. 4 and Fig. 5
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V ±0.1 V 1.5 V ±0.1 V 1.8 V ±0.15 V 2.5 V ±0.2 V 3.3 V ±0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
VCC(A) = 1.1 V to 1.3 V
tpd
tdis
ten
propagation An to Bn
2.0
2.0
2.0
2.0
2.0
2.0
12.1
12.1
11.5
12.8
15.6
17.3
1.3
1.5
2.0
2.0
2.0
2.0
9.0
11.4
11.5
9.9
1.2
1.5
2.0
1.0
2.0
2.0
8.0
11.2
11.5
9.2
1.0
1.4
2.0
0.7
2.0
1.0
6.8
10.9
11.5
8.1
0.8
1.4
2.0
1.0
2.0
1.0
6.6 ns
10.7 ns
11.5 ns
9.2 ns
15.6 ns
8.6 ns
delay
Bn to An
disable time OE to An
OE to Bn
enable time OE to An
OE to Bn
15.6
12.7
15.6
10.9
15.6
9.0
VCC(A) = 1.4 V to 1.6 V
tpd
tdis
ten
propagation An to Bn
delay
1.5
1.3
1.0
2.0
1.0
2.0
11.4
9.0
1.0
1.0
1.0
1.5
1.0
1.4
8.2
8.2
6.9
8.7
8.7
9.1
1.0
0.9
1.0
0.9
1.0
1.3
6.9
8.0
6.9
8.3
8.7
8.9
0.5
0.8
1.0
0.4
1.0
1.1
5.6
7.6
6.9
7.2
8.7
7.4
0.5
0.6
1.0
0.4
1.0
1.1
5.0 ns
7.5 ns
6.9 ns
7.1 ns
8.7 ns
6.5 ns
Bn to An
disable time OE to An
OE to Bn
6.9
11.8
8.7
enable time OE to An
OE to Bn
16.6
VCC(A) = 1.65 V to 1.95 V
tpd
tdis
ten
propagation An to Bn
delay
1.5
1.2
0.5
2.0
1.0
1.5
11.2
8.0
0.9
1.0
0.5
1.5
1.0
1.2
8.0
6.9
6.6
8.1
7.8
8.3
0.8
0.8
0.5
0.8
1.0
1.2
6.6
6.6
6.6
8.0
7.8
8.0
0.5
0.5
0.5
0.2
1.0
0.8
5.2
6.4
6.6
6.7
7.8
6.3
0.3
0.5
0.5
0.2
1.0
0.6
4.6 ns
6.1 ns
6.6 ns
6.8 ns
7.8 ns
5.8 ns
Bn to An
disable time OE to An
OE to Bn
6.6
11.4
7.8
enable time OE to An
OE to Bn
16.0
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
ten
propagation An to Bn
delay
1.4
1.0
0.2
2.0
0.6
1.5
10.9
6.8
0.8
0.5
0.2
1.5
0.6
1.0
7.6
5.6
4.6
7.8
5.2
7.9
0.5
0.5
0.2
0.7
0.6
1.0
6.4
5.2
4.6
7.3
5.2
6.9
0.4
0.4
0.2
0.2
0.6
0.8
4.9
4.9
4.6
5.8
5.2
5.3
0.2
0.3
0.2
0.2
0.6
0.6
4.3 ns
4.5 ns
4.6 ns
6.6 ns
5.2 ns
4.9 ns
Bn to An
disable time OE to An
OE to Bn
4.6
10.7
5.2
enable time OE to An
OE to Bn
15.7
VCC(A) = 3.0 V to 3.6 V
tpd
tdis
ten
propagation An to Bn
delay
1.4
0.8
0.2
2.0
0.5
1.5
10.7
6.6
0.6
0.5
0.2
1.5
0.5
1.0
7.5
5.0
5.2
7.4
4.6
7.8
0.5
0.3
0.2
0.7
0.5
1.0
6.1
4.6
5.2
7.1
4.6
6.8
0.3
0.2
0.2
0.2
0.5
0.7
4.5
4.3
5.2
5.6
4.6
5.1
0.2
0.2
0.2
0.2
0.5
0.5
4.1 ns
4.1 ns
5.2 ns
6.5 ns
4.6 ns
4.6 ns
Bn to An
disable time OE to An
OE to Bn
5.2
10.4
4.6
enable time OE to An
OE to Bn
15.5
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
10 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
11.1. Waveforms and test circuit
V
I
V
An, Bn input
GND
M
t
t
PLH
PHL
V
OH
V
Bn, An output
M
V
OL
001aao074
Measurement points are given in Table 15.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 4. The data input (An, Bn) to output (Bn, An) propagation delay times
V
I
V
OE input
M
GND
t
t
PZL
PLZ
V
CCO
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aao075
Measurement points are given in Table 15.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 5. Enable and disable times
Table 15. Measurement points
Supply voltage
VCC(A), VCC(B)
0.8 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input [1]
Output [2]
VM
VM
VX
VY
0.5VCCI
0.5VCCI
0.5VCCI
0.5VCCO
0.5VCCO
0.5VCCO
VOL + 0.1 V
VOL + 0.15 V
VOL + 0.3 V
VOH - 0.1 V
VOH - 0.15 V
VOH - 0.3 V
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
11 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 16.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 6. Test circuit for measuring switching times
Table 16. Test data
Supply voltage
VCC(A), VCC(B)
0.8 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Input
VI [1]
VCCI
VCCI
VCCI
Load
CL
VEXT
Δt/ΔV [2]
≤ 1.0 ns/V
≤ 1.0 ns/V
≤ 1.0 ns/V
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ [3]
2VCCO
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
open
GND
2VCCO
open
GND
2VCCO
[1] VCCI is the supply voltage associated with the data input port.
[2] dV/dt ≥ 1.0 V/ns
[3] VCCO is the supply voltage associated with the output port.
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
12 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
11.2. Typical propagation delay characteristics
aaa-026797
aaa-026798
24
21
(1)
(2)
(3)
(4)
t
pd
(ns)
t
pd
(ns)
(1)
20
17
16
12
8
13
(2)
(3)
(4)
4
9
0
20
40
60
0
20
40
60
C
L
(pF)
C (pF)
L
a. Propagation delay (A to B); VCC(A) = 0.8 V
b. Propagation delay (A to B); VCC(B) = 0.8 V
(1) VCC(B) = 0.8 V
(2) VCC(B) = 1.2 V
(3) VCC(B) = 1.5 V
(4) VCC(B) = 1.8 V
(1) VCC(A) = 0.8 V
(2) VCC(A) = 1.2 V
(3) VCC(A) = 1.5 V
(4) VCC(A) = 1.8 V
Fig. 7. Typical propagation delay versus load capacitance; Tamb = 25 °C
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
13 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
001aai478
001aai491
7
7
(1)
t
t
PLH
(ns)
PHL
(ns)
(1)
(2)
(3)
5
3
1
5
3
1
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
a. LOW to HIGH propagation delay (A to B); VCC(A) = 1.2 V
b. HIGH to LOW propagation delay (A to B); VCC(A) = 1.2 V
001aai479
001aai480
7
7
(1)
t
t
PLH
(ns)
PHL
(ns)
(1)
5
3
1
5
3
1
(2)
(3)
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
c. LOW to HIGH propagation delay (A to B); VCC(A) = 1.5 V
d. HIGH to LOW propagation delay (A to B); VCC(A) = 1.5 V
(1) VCC(B) = 1.2 V
(2) VCC(B) = 1.5 V
(3) VCC(B) = 1.8 V
(4) VCC(B) = 2.5 V
(5) VCC(B) = 3.3 V
Fig. 8. Typical propagation delay versus load capacitance; Tamb = 25 °C
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
14 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
001aai481
001aai482
7
7
(1)
t
t
PLH
(ns)
PHL
(ns)
(1)
5
3
1
5
3
1
(2)
(3)
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
a. LOW to HIGH propagation delay (A to B); VCC(A) = 1.8 V
b. HIGH to LOW propagation delay (A to B); VCC(A) = 1.8 V
001aai483
001aai486
7
7
t
t
PLH
(ns)
PHL
(ns)
(1)
(1)
5
3
1
5
3
1
(2)
(3)
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
c. LOW to HIGH propagation delay (A to B); VCC(A) = 2.5 V
d. HIGH to LOW propagation delay (A to B); VCC(A) = 2.5 V
(1) VCC(B) = 1.2 V
(2) VCC(B) = 1.5 V
(3) VCC(B) = 1.8 V
(4) VCC(B) = 2.5 V
(5) VCC(B) = 3.3 V
Fig. 9. Typical propagation delay versus load capacitance; Tamb = 25 °C
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
15 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
001aai485
001aai484
7
7
t
t
PLH
(ns)
PHL
(ns)
(1)
(1)
5
3
1
5
3
1
(2)
(3)
(2)
(3)
(4)
(5)
(4)
(5)
0
20
40
60
0
20
40
60
C
L
(pF)
C
L
(pF)
a. LOW to HIGH propagation delay (A to B); VCC(A) = 3.3 V
b. HIGH to LOW propagation delay (A to B); VCC(A) = 3.3 V
(1) VCC(B) = 1.2 V
(2) VCC(B) = 1.5 V
(3) VCC(B) = 1.8 V
(4) VCC(B) = 2.5 V
(5) VCC(B) = 3.3 V
Fig. 10. Typical propagation delay versus load capacitance; Tamb = 25 °C
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
16 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
12. Package outline
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
1
0.2
0.13
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig. 11. Package outline SOT403-1 (TSSOP16)
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
17 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
13. Abbreviations
Table 17. Abbreviations
Acronym
Description
CDM
DUT
ESD
HBM
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
14. Revision history
Table 18. Revision history
Document ID
Release date Data sheet status
20211020 Product data sheet
Section 8: Derating values for Ptot total power dissipation updated.
20170925 Product data sheet
Change notice Supersedes
74AVC4T774PW v.2
Modifications:
-
74AVC4T774PW v.1
•
74AVC4T774PW v.1
-
-
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
18 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
injury, death or severe property or environmental damage. Nexperia and its
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15. Legal information
Quick reference data — The Quick reference data is an extract of the
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Definition
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or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
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Preliminary [short]
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Production
This document contains data from
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This document contains the product
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[1] Please consult the most recently issued document before initiating or
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©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
19 / 20
Nexperia
74AVC4T774PW
4-bit dual supply translating transceiver; 3-state
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Marking..........................................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................3
6.1. Pinning.........................................................................3
6.2. Pin description.............................................................3
7. Functional description................................................. 3
8. Limiting values............................................................. 4
9. Recommended operating conditions..........................4
10. Static characteristics..................................................5
11. Dynamic characteristics.............................................8
11.1. Waveforms and test circuit.......................................11
11.2. Typical propagation delay characteristics.................13
12. Package outline........................................................ 17
13. Abbreviations............................................................18
14. Revision history........................................................18
15. Legal information......................................................19
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 20 October 2021
©
74AVC4T774PW
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 2 — 20 October 2021
20 / 20
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