DP7113 [NIDEC]
100-Tap Digital Potentiometer;
| 型号： | DP7113 |
| 厂家： | 
NIDEC COMPONENTS |
| 描述： | 100-Tap Digital Potentiometer |
| 文件： | 总12页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DP7113
100-Tap Digital Potentiometer (DP)
Description
The DP7113 is
a
single digital potentiometer (DP)
designed as an electronic replacement for mechanical
potentiometers. Ideal for automated adjustments on high volume
production lines, they are also well suited for applications where
equipment requiring periodic adjustment is either difficult to access or
located in a hazardous or remote environment.
The DP7113 contains a ꢀꢁꢁïWDS series resistor array connected
between two terminals R and R . An up/down counter and decoder
SOICï8
H
L
MSOPï8
that are controlled by three input pins, determines which tap is
connected to the wiper, R . The wiper setting, stored in nonvolatile
W
memory, is not lost when the device is powered down and is
automatically reinstated when power is returned. The wiper can be
adjusted to test new system values without affecting the stored setting.
Wiperïcontrol of the DP7113 is accomplished with three input
control pins, CS, U/D, and INC. The INC input increments the wiper
in the direction which is determined by the logic state of the U/D input.
The CS input is used to select the device and also store the wiper
position prior to power down.
TSSOPï8
The digital potentiometer can be used as a three-terminal
resistive divider or as a two-terminal variable resistor.
PIN CONFIGURATIONS
1
V
INC
U/D
H
GND
CC
CS
L
W
Features
R
R
R
v 100ïposition Linear Taper Potentiometer
v Nonïvolatile EEPROM Wiper Storage
v 10 nA Ultraïlow Standby Current
v Single Supply Operation: 2.5 V ï 6.0 V
v Increment Up/Down Serial Interface
v Resistance Values: 1 k , 10 k , 50 k and 100 k
v Available in SOIC, TSSOP and MSOP Packages
v These Devices are PbïFree, Halogen Free/BFR Free and are RoHS
Compliant
SOIC (V),
MSOP (Z)
1
R
R
CS
L
V
CC
W
INC
GND
R
H
U/D
TSSOP (Y)
(Top Views)
PIN FUNCTION
Applications
Pin Name
INC
Function
v Automated Product Calibration
v Remote Control Adjustments
Increment Control
Up/Down Control
v Offset, Gain and Zero Control
v Tamperïproof Calibrations
U/D
R
H
Potentiometer High Terminal
Ground
v Contrast, Brightness and Volume Controls
v Motor Controls and Feedback Systems
v Programmable Analog Functions
GND
R
W
Wiper Terminal
R
L
Potentiometer Low Terminal
Chip Select
CS
V
CC
Supply Voltage
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
¢
NIDEC COPAL ELECTRONICS CORP.
1
Publication Order Number:
August, 2010 ï Rev. 24
DP7113/D
DP7113
DEVICE MARKING INFORMATION
MSOP
SOIC
TSSOP
RL4A
CAT5113VI
YMXXXX
AARR
YMP
A3RL
4YMXXX
R = Resistance:
A3 = Device Code
R = Resistance:
ABCN = DP7113ZIï01ïT3
AARR = DP7113ZIï10ïT3
AARC = DP7113ZIï50ïT3
AARG = DP7113ZIï00ïT3
Y = Production Year (Last Digit)
M = Production Month
0 = 1 k
0 = 1 k
2 = 10 k
2 = 10 k
4 = 50 k
4 = 50 k
5 = 100 k
5 = 100 k
L = Assembly Location
4 = Lead Finish ï NiPdAu
A = Product Revision (Fixed as “A”)
L = Assembly Location
4 = Lead Finish ï NiPdAu
Y = Production Year (Last Digit)
M = Production Month
(ꢀï9, A, B, C or O, N, D)
XXX = Last Three Digits of
XXX = Assembly Lot Number
(ꢀï9, A, B, C or O, N, D)
P = Product Revision
CAT5113V = Device Code
I = Temperature Range (Industrial)
Y = Production Year (Last Digit)
M = Production Month
(ꢀï9, A, B, C or O, N, D)
XXXX = Last Four Digits of Assembly Lot Number
2
DP7113
Functional Diagram
R
7ïBit
H
99
98
U/D
INC
CS
R
R
R
H
Up/Down
Counter
V
CC
R
R
R
97
96
H
U/D
7ïBit
Nonvolatile
Memory
Control
Transfer Resistor
Gates Array
INC
CS
and
1 of 100
W
Memory
W
Decoder
Power On
Recall
2
Store and
Recall
L
1
0
V
Control
Circuitry
CC
GND
GND
R
R
L
L
W
Figure 1. General
Figure 2. Detailed
Device Operation
Figure 3. Electronic
Potentiometer
Implementation
Pin Description
INC: Increment Control Input
The INC input moves the wiper in the up or down direction
determined by the condition of the U/D input.
The DP7113 operates like a digital potentiometer
with R and R equivalent to the high and low
H
L
W
terminals and
R
equivalent to the mechanical
potentiometer·s wiper. There are 100 available tap positions
U/D: Up/Down Control Input
including the resistor end points, R and R . There are 99
H
L
The U/D input controls the direction of the wiper movement.
When in a high state and CS is low, any highïtoïlow
transition on INC will cause the wiper to move one
resistor elements connected in series between the R and R
H
L
terminals. The wiper terminal is connected to one of the 100
taps and controlled by three inputs, INC, U/D and CS. These
inputs control a sevenïbit up/down counter whose output is
decoded to select the wiper position. The selected wiper
position can be stored in nonvolatile memory using the INC
and CS inputs.
increment toward the R terminal. When in a low state and
H
CS is low, any highïtoïlow transition on INC will cause the
wiper to move one increment towards the R terminal.
L
R : High End Potentiometer Terminal
H
With CS set LOW the DP7113 is selected and will
respond to the U/D and INC inputs. HIGH to LOW
transitions on INC will increment or decrement the wiper
(depending on the state of the U/D input and sevenïbit
counter). The wiper, when at either fixed terminal, acts like
its mechanical equivalent and does not move beyond the last
position. The value of the counter is stored in nonvolatile
memory whenever CS transitions HIGH while the INC input
is also HIGH. When the DP7113 is powereGïdown, the last
stored wiper counter position is maintained in the
nonvolatile memory. When power is restored, the contents
of the memory are recalled and the counter is set to the value
stored.
R
is the high end terminal of the potentiometer. It is not
H
required that this terminal be connected to a potential greater
than the R terminal. Voltage applied to the R terminal
L
H
cannot exceed the supply voltage, V or go below ground,
CC
GND.
R : Wiper Potentiometer Terminal
W
R
is the wiper terminal of the potentiometer. Its position on
W
the resistor array is controlled by the control inputs, INC,
U/D and CS. Voltage applied to the R terminal cannot
W
exceed the supply voltage, V or go below ground, GND.
CC
R : Low End Potentiometer Terminal
L
R is the low end terminal of the potentiometer. It is not
L
With INC set low, the DP7113 may be dHïselected and
powered down without storing the current wiper position in
nonvolatile memory. This allows the system to always
power up to a preset value stored in nonvolatile memory.
required that this terminal be connected to a potential less
than the R terminal. Voltage applied to the R terminal
H
L
cannot exceed the supply voltage, V or go below ground,
CC
GND. R and R are electrically interchangeable.
L
H
CS: Chip Select
The chip select input is used to activate the control input of
the DP7113 and is active low. When in a high state, activity
on the INC and U/D inputs will not affect or change the
position of the wiper.
3
DP7113
Table 1. OPERATION MODES
INC
High to Low
High to Low
High
CS
U/D
High
Low
X
Operation
Wiper toward H
Low
Low
Wiper toward L
Low to High
Low to High
High
Store Wiper Position
No Store, Return to Standby
Standby
Low
X
X
X
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Supply Voltage
V
V
to GND
ï0.5 to +7
CC
Inputs
V
CS to GND
INC to GND
U/D to GND
ï0.5 to V +0.5
CC
ï0.5 to V +0.5
V
V
V
V
V
CC
ï0.5 to V +0.5
CC
R
to GND
ï0.5 to V +0.5
CC
H
R to GND
ï0.5 to V +0.5
CC
L
R
to GND
ï0.5 to V +0.5
CC
W
Operating Ambient Temperature
Industrial ꢁ¶,· suffix)
ï40 to +85
+150
oC
oC
oC
oC
Junction Temperature
Storage Temperature
Lead Soldering (10 s max)
ï65 to 150
+300
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. RELIABILITY CHARACTERISTICS
Symbol
Parameter
ESD Susceptibility
LatchïUp
Test Method
Min
2000
Typ
Max
Units
V
V
(Note 1)
MILïSTDï883, Test Method 3015
JEDEC Standard 17
ZAP
I
(Notes 1, 2)
100
mA
LTH
T
Data Retention
Endurance
MILïSTDï883, Test Method 1008
MILïSTDï883, Test Method 1003
100
Years
Stores
DR
N
END
1,000,000
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latchïup protection is provided for stresses up to 100 mA on address and data pins from ï1 V to V + 1 V
CC
4
DP7113
Table 4. DC ELECTRICAL CHARACTERISTICS (V = +2.5 V to +6 V unless otherwise specified)
CC
Symbol
Parameter
Conditions
Min
Typ
Max
Units
POWER SUPPLY
V
I
Operating Voltage Range
Supply Current (Increment)
2.5
–
–
–
6.0
100
50
V
A
A
A
A
A
CC
V
V
= 6 V, f = 1 MHz, I = 0
CC1
CC2
CC
W
= 6 V, f = 250 kHz, I = 0
–
–
CC
W
I
Supply Current (Write)
Programming, V = 6 V
–
–
1000
500
1
CC
V
CC
= 3 V
–
–
I
(Note 3)
Supply Current (Standby)
CS = V ï 0.3 V
–
0.01
SB1
CC
U/D, INC = V ï 0.3 V or GND
CC
LOGIC INPUTS
I
Input Leakage Current
V
V
= V
CC
–
–
–
–
–
–
10
A
A
IH
IN
I
Input Leakage Current
= 0 V
ï10
IL
IN
V
IH2
CMOS High Level Input Voltage
CMOS Low Level Input Voltage
2.5 V b V b 6 V
V
CC
x 0.7
V + 0.3
CC
V
CC
V
ï0.3
V
x 0.2
V
IL2
CC
POTENTIOMETER CHARACTERISTICS
R
POT
Potentiometer Resistance
ï01 Device
ï10 Device
ï50 Device
ï00 Device
1
k
10
50
100
Pot. Resistance Tolerance
p20
%
V
V
RH
Voltage on R pin
0
0
V
CC
V
CC
H
V
RL
Voltage on R pin
V
L
Resolution
1
%
INL
Integral Linearity Error
Differential Linearity Error
Wiper Resistance
I
I
b 2
b 2
A
A
0.5
0.25
1
LSB
LSB
W
DNL
0.5
400
1000
4.4
W
R
WI
V
V
= 5 V, I = 1 mA
W
CC
CC
= 2.5 V, I = 1 mA
W
I
W
Wiper Current
(Note 4)
ï4.4
mA
ppm/oC
ppm/oC
nV/Hz
pF
TC
TC of Pot Resistance
Ratiometric TC
300
RPOT
RATIO
TC
20
V
N
Noise
100 kHz / 1 kHz
8/24
8/8/25
1.7
C /C /C
Potentiometer Capacitances
Frequency Response
H
L
W
fc
Passive Attenuator, 10 k
MHz
3. Latchïup protection is provided for stresses up to 100 mA on address and data pins from ï1 V to V + 1 V
CC
4. This parameter is not 100% tested.
5
DP7113
Table 5. AC TEST CONDITIONS
V
CC
Range
2.5 V b V b 6 V
CC
Input Pulse Levels
0.2 V to 0.7 V
CC
CC
Input Rise and Fall Times
Input Reference Levels
10 ns
0.5 V
CC
Table 6. AC OPERATING CHARACTERISTICS (V = +2.5 V to +6.0 V, V = V , V = 0 V, unless otherwise specified)
CC
H
CC
L
Symbol
Parameter
Min
100
50
100
250
250
1
Typ (Note 5)
Max
Units
ns
ns
ns
ns
ns
s
t
CI
t
DI
t
ID
CS to INC Setup
U/D to INC Setup
U/D to INC Hold
INC LOW Period
INC HIGH Period
ï
ï
ï
ï
ï
ï
ï
ï
1
ï
ï
–
5
ï
ï
ï
t
ï
IL
IH
IC
t
t
ï
INC Inactive to CS Inactive
CS Deselect Time (NO STORE)
CS Deselect Time (STORE)
ï
t
t
100
10
ï
ï
ns
ms
s
CPH
CPH
ï
t
IW
INC to V
Change
5
OUT
t
INC Cycle Time
1
ï
s
CYC
t , t (Note 6) INC Input Rise and Fall Time
ï
500
1
s
R
F
t
(Note 6)
Powerïup to Wiper Stable
–
ms
ms
PU
t
Store Cycle
–
10
WR
5. Typical values are for T = 25oC and nominal supply voltage.
A
6. This parameter is periodically sampled and not 100% tested.
CS
(store)
CPH
t
CYC
t
t
IC
t
CI
t
IL
t
IH
90%
90%
INC
U/D
10%
t
DI
t
ID
t
F
t
R
(Note 7)
t
IW
MI
R
W
Figure 4. A.C. Timing
7. MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position.
6
DP7113
Applications Information
(a) resistive divider
(b) variable resistance
(c) twoïport
Figure 5. Potentiometer Configuration
Applications
3
2
V (ï)
+
–
1
R
R
4
3
+5 V
1
+5 V
8
R
1
2
1
7
R
R
A
6
+5 V
+5 V
4
8
1
DP
pR
POT
8
7
4
R
–
+
A
2
9
2
1
3
5
3
5
4
R
(1ïp)R
V
1
10
POT
O
3
DP
8
R
2
11
7
4
B
555
R
2
R
4
–
+
R
3
6
DP7113/7114
6
5
+2.5 V
7
V (+)
2
2
0.01
0.003
F
1
C
0.01
F
A = A = A = / LM6064
1
2
3
3
4
F
R = R = R = 5 k
2
POT
4
R
= 10 k
Figure 6. Programmable Instrumentation
Amplifier
Figure 7. Programmable Sq. Wave Oscillator (555)
IC3A
6
–
+
V
= 1 V
1
REF
/ 74HC132
7
4
OSC
CS
+5 V
8
5
+200 mV
20 k
IC1B
2
1
7
DP
10 k
+
–
499 k
V
CORR
4
0.01
F
499 k
+5 V
4
2
3
–
DP7111/7112
IC2
1
V
= 1 V ( 1 mV
OUT
+
IC1A
11
ï5 V
499 k
499 k
= 1 V ( 50 mV
V
SENSOR
Figure 8. Sensor Auto Referencing Circuit
7
DP7113
+5 V
8
100 k
V
2
1
7
DP7113/7114
DP
V
(REG)
OUT
O
4
R
V
(UNREG)
1
IN
2952
11 k
6.8 F
0.1
F
(1ïp)R
pR
SHUTDOWN
1.23 V
1 M
330
330
SD
FB
GND
6
3
R
820
2
5
1
F
+5 V
7
+5 V
7
+5 V
2
3
2
3
8
2
10 k
–
+
–
+
A
6
A
1
2
3
V
O
1
7
6
DP
R
10 k
3
I
4
5
4
S
DP7113/7114
6
4
LT1097
+2.5 V
Figure 9. Programmable Voltage Regulator
Figure 10. Programmable I to V Converter
+5 V
IC1
393
2
IC2
74HC132
R
R
V
1
LL
–
+
1
CLO
OSC
C
1
3
6
R3
0.001
R1
F
R
2
100 k
C
1
F
2
–
+
+5 V
2
CHI
7
10 k
V
7
S
3
–
0.1
F
50 k
0.001
F
V
O
+5 V
5
+5 V
V
6
+
UL
R2
4
8
3
A
2
1
10 k
+5 V
IC3
1
DP
DP7111/7112
+2.5 V
7
+5 V
6
3
DP7113/7114
4
8
5
2
–
+
10 k
1
V
O
DP
Figure 12. Programmable Bandpass Filter
0 ) V ) 2.5 V
7
4
O
AI
IC4
+2.5 V
0 ) V ) 2.5 V
V
S
S
Figure 11. Automatic Gain Control
R
1
100 k
+5 V
+5 V
R
1
–
+
Serial
Bus
+5 V
100 k
V
S
2
3
R
4
–
+
2.5 k
I
S
1
+2.5 V
11
R
100 k
1
DP7111/7112
R
1
100 k
+
5
6
7
+2.5 V
A = A = LMC6064A
–
A
2
1
2
Figure 13. Programmable Current Source/Sink
8
DP7113
PACKAGE DIMENSIONS
SOIC 8, 150 mils
SYMBOL
MIN
NOM
MAX
1.35
A
1.75
A1
b
0.10
0.33
0.19
0.25
0.51
0.25
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
Q
TOP VIEW
D
h
A1
Q
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
9
DP7113
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
L
L1
0.50
0.60
0.75
0º
8º
Q
e
TOP VIEW
D
c
A2
A
1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
10
DP7113
PACKAGE DIMENSIONS
MSOP 8, 3x3
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.10
0.15
0.95
0.38
0.23
3.10
5.00
3.10
0.05
0.75
0.22
0.13
2.90
4.80
2.90
0.10
0.85
c
D
3.00
4.90
E
E1
E
E1
e
3.00
0.65 BSC
0.60
L
0.40
0.80
L1
L2
Q
0.95 REF
0.25 BSC
0º
6º
TOP VIEW
D
A2
A
DETAIL A
A1
e
b
c
SIDE VIEW
END VIEW
L2
Notes:
L
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L1
DETAIL A
11
DP7113
Example of Ordering Information (Note 11)
Prefix
Device #
Suffix
DP
7113
V
I
ï10
ï G
T3
Temperature Range
I = Industrial (ï40oC to +85oC)
Lead Finish (Note 9)
G: NiPdAu
Blank: MatteïTin
Product Number
7113
Package
Resistance
Company ID
(Optional)
ï01: 1 k
V: SOIC
Y: TSSOP
Z: MSOP
Tape & Reel
T: Tape & Reel
3: 3,000 Units / Reel
ï10: 10 k
ï50: 50 k
ï00: 100 k
Table 7. ORDERING INFORMATION
Orderable Part Number
DP7113VIï01ïGT3
DP7113VIï10ïGT3
DP7113VIï50ïGT3
DP7113VIï00ïGT3
DP7113YIï01ïGT3
DP7113YIï10ïGT3
DP7113YIï50ïGT3
DP7113YIï00ïGT3
DP7113ZIï01ïT3
Resistance (k )
PackageïPins
Lead Finish
1
10
50
100
1
SOICï8
TSSOPï8
MSOPï8
NiPdAu
NiPdAu
10
50
100
1
MatteïTin
DP7113ZIï10ïT3
10
50
100
DP7113ZIï50ïT3
DP7113ZIï00ïT3
8. All packages are RoHSïcompliant (Leadïfree, Halogenïfree).
9. The standard lead finish is NiPdAu, except MSOP package is MatteïTin.
10. The device used in the above example is a DP7113VIï10ïGT3 (SOIC, Industrial Temperature, 10 k , NiPdAu, Tape & Reel, 3,000/Reel).
NIDEC COPAL reserves the right to make changes without further notice to any products herein.
NIDEC COPAL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does NIDEC COPAL assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in NIDEC COPAL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.
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NIDEC COPAL does not convey any license under its patent rights nor the rights of others.
NIDEC COPAL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the NIDEC COPAL product could create a situation where personal injury or death may occur.
Should Buyer purchase or use NIDEC COPAL products for any such unintended or unauthorized application, Buyer shall indemnify and hold NIDEC COPAL and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that NIDEC COPAL was negligent regarding the design or
manufacture of the part.
DP7113/D
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