DP7114 [NIDEC]
32-Tap Digital Potentiometer;
| 型号： | DP7114 |
| 厂家： | 
NIDEC COMPONENTS |
| 描述： | 32-Tap Digital Potentiometer |
| 文件： | 总14页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DP7114
32-Tap Digital Potentiometer (DP)
Description
The DP7114 is
a
single digital potentiometer (DP)
designed as an electronic replacement for mechanical
potentiometers and trim pots. Ideal for automated adjustments on high
volume production lines, they are also well suited for applications
where equipment requiring periodic adjustment is either difficult to
access or located in a hazardous or remote environment.
The DP7114 contains a ꢀꢁïWDS series resistor array connected
between two terminals R and R . An up/down counter and decoder
SOICï8
H
L
MSOPï8
TDFNï8
that are controlled by three input pins, determines which tap is
connected to the wiper, R . The wiper setting, stored in nonvolatile
W
memory, is not lost when the device is powered down and is
automatically reinstated when power is returned. The wiper can be
adjusted to test new system values without affecting the stored setting.
Wiperïcontrol of the DP7114 is accomplished with three input
control pins, CS, U/D, and INC. The INC input increments the wiper
in the direction which is determined by the logic state of the U/D input.
The CS input is used to select the device and also store the wiper
position prior to power down.
TSSOPï8
The digital potentiometer can be used as a WKUHHïterminal
resistive divider or as
a
WZRïWHUPLQDO variable resistor.
PIN CONFIGURATIONS
DPs bring variability and programmability to a wide variety of
applications including control, parameter adjustments, and signal
processing.
1
V
INC
U/D
CC
CS
L
W
R
R
R
H
GND
Features
SOIC (V),
MSOP (Z)
v 32ïposition Linear Taper Potentiometer
v Nonïvolatile EEPROM Wiper Storage
v Low Standby Current
v Single Supply Operation: 2.5 V ï 6.0 V
v Increment Up/Down Serial Interface
v Resistance Values: 10 k , 50 k and 100 k
v Available in SOIC, TSSOP, MSOP and Space Saving
2 x 3 mm TDFN Packages
1
R
R
CS
L
W
V
CC
INC
GND
R
U/D
H
TSSOP (Y)
1
INC
U/D
V
CC
CS
v These Devices are PbïFree, Halogen Free/BFR Free and are RoHS
R
R
H
L
Compliant
GND
R
W
Applications
TDFN (VP2)
(Top Views)
v Automated Product Calibration
v Remote Control Adjustments
v Offset, Gain and Zero Control
v Tamperïproof Calibrations
v Contrast, Brightness and Volume Controls
v Motor Controls and Feedback Systems
v Programmable Analog Functions
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
¢ NIDEC COPAL ELECTRONICS CORP.
June, 2011 ï Rev. 20
1
Publication Order Number:
DP7114/D
DP7114
DEVICE MARKING INFORMATION
MSOP
SOIC
TSSOP
YMBR
5114GI
RL4B
CAT5114VI
YMXXXX
ABMS
YMP
ABMS = DP7114ZIï10ïGT3
ABMT = DP7114ZIï50ïGT3
ABTH = DP7114ZI ï00ïGT3
Y = Production Year (Last Digit)
M = Production Month
Y = Production Year (Last Digit)
M = Production Month
R = Resistance:
2 = 10 k
(ꢀï9, A, B, C or O, N, D)
B = Product Revision (Fixed as “B”)
R = Resistance:
4 = 50 k
5 = 100 k
2 = 10 k
L = Assembly Location
(ꢀï9, A, B, C or O, N, D)
P = Product Revision
4 = 50 k
4 = Lead Finish ï NiPdAu
5 = 100 k
B = Product Revision (Fixed as “B”)
5114G = Device Code
I = Temperature Range (Industrial)
CAT5114V = Device Code
I = Temperature Range (Industrial)
Y = Production Year (Last Digit)
M = Production Month
TDFN
(ꢀï9, A, B, C or O, N, D)
XXXX = Last Four Digits of Assembly Lot Number
EF = DP7114VP2I-10-GT3
HF = DP7114VP2I-50-GT3
GW = DP7114VP2I-00-GT3
L = Assembly Location
EFL
XXX
YM
XXX = Last Three Digits of Assembly Lot Number
Y = Production Year (Last Digit)
M = Production Month (ꢀï9, A, B, C or O, N, D)
Functional Diagram
R /V
R /V
H
H
H
H
5ïBit
31
30
U/D
Up/Down
Counter
INC
V
CC
CS
R /V
29
28
H
H
U/D
5ïBit
Nonvolatile
Memory
Control
and
32ï
R /V
W W
Transfer Resistor
Gates Array
INC
CS
R /V
W
W
Position
Decoder
Memory
Power On
Recall
2
R /V
Store and
Recall
L
L
1
0
V
CC
Control
Circuitry
GND
GND
R /V
L L
R /V
R /V
L
L
W
W
Figure 1. General
Figure 2. Detailed
Figure 3. Electronic
Potentiometer
Implementation
2
DP7114
than the R terminal. Voltage applied to the R terminal
H
L
Table 1. PIN DESCRIPTIONS
Name
cannot exceed the supply voltage, V or go below ground,
CC
Function
GND. R and R are electrically interchangeable.
L
H
INC
U/D
Increment Control
Up/Down Control
CS: Chip Select
The chip select input is used to activate the control input of
the DP7114 and is active low. When in a high state, activity
on the INC and U/D inputs will not affect or change the
position of the wiper.
R
Potentiometer High Terminal
Ground
H
GND
R
W
Wiper Terminal
R
Potentiometer Low Terminal
Chip Select
Device Operation
L
The DP7114 operates like a digital potentiometer
CS
with R and R equivalent to the high and low
H
L
W
V
CC
Supply Voltage
terminals and
R
equivalent to the mechanical
potentiometer·s wiper. There are 32 available tap positions
Pin Function
INC: Increment Control Input
The INC input moves the wiper in the up or down direction
determined by the condition of the U/D input.
including the resistor end points, R and R . There are 31
H
L
resistor elements connected in series between the R and R
H
L
terminals. The wiper terminal is connected to one of the 32
taps and controlled by three inputs, INC, U/D and CS. These
inputs control a fiveïbit up/down counter whose output is
decoded to select the wiper position. The selected wiper
position can be stored in nonvolatile memory using the INC
and CS inputs.
U/D: Up/Down Control Input
The U/D input controls the direction of the wiper movement.
When in a high state and CS is low, any highïtoïlow
transition on INC will cause the wiper to move one
With CS set LOW the DP7114 is selected and will
respond to the U/D and INC inputs. HIGH to LOW
transitions on INC will increment or decrement the wiper
(depending on the state of the U/D input and ILYHïELW
counter). The wiper, when at either fixed terminal, acts like
its mechanical equivalent and does not move beyond the last
position. The value of the counter is stored in nonvolatile
memory whenever CS transitions HIGH while the INC input
is also HIGH. When the DP7114 is poweredïdown, the last
stored wiper counter position is maintained in the
nonvolatile memory. When power is restored, the contents
of the memory are recalled and the counter is set to the value
stored.
increment toward the R terminal. When in a low state and
H
CS is low, any highïtoïlow transition on INC will cause the
wiper to move one increment towards the R terminal.
L
R : High End Potentiometer Terminal
H
R
is the high end terminal of the potentiometer. It is not
H
required that this terminal be connected to a potential greater
than the R terminal. Voltage applied to the R terminal
L
H
cannot exceed the supply voltage, V or go below ground,
CC
GND.
R : Wiper Potentiometer Terminal
W
R
is the wiper terminal of the potentiometer. Its position on
W
the resistor array is controlled by the control inputs, INC,
With INC set low, the DP7114 may be deïselected and
powered down without storing the current wiper position in
nonvolatile memory. This allows the system to always
power up to a preset value stored in nonvolatile memory.
U/D and CS. Voltage applied to the R terminal cannot
W
exceed the supply voltage, V or go below ground, GND.
CC
R : Low End Potentiometer Terminal
L
R is the low end terminal of the potentiometer. It is not
L
required that this terminal be connected to a potential less
3
DP7114
Table 2. OPERATION MODES
INC
High to Low
High to Low
High
CS
U/D
High
Low
X
Operation
Wiper toward H
Low
Low
Wiper toward L
Low to High
Low to High
High
Store Wiper Position
No Store, Return to Standby
Standby
Low
X
X
X
R
H
C
H
R
WI
R
W
C
W
C
L
R
L
Figure 4. Potentiometer Equivalent Circuit
Table 3. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Supply Voltage
V
V
to GND
ï0.5 to +7
CC
Inputs
V
CS to GND
INC to GND
U/D to GND
ï0.5 to V +0.5
CC
ï0.5 to V +0.5
V
V
CC
ï0.5 to V +0.5
CC
R
to GND
ï0.5 to V +0.5
V
CC
H
R to GND
ï0.5 to V +0.5
V
CC
L
R
to GND
ï0.5 to V +0.5
V
CC
W
Operating Ambient Temperature
oC
,QGXVWULDOꢁꢂ¶,·ꢁVXffix)
ï40 to +85
+150
Junction Temperature
Storage Temperature
Lead Soldering (10 s max)
oC
oC
oC
ï65 to 150
+300
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. RELIABILITY CHARACTERISTICS
Symbol
Parameter
ESD Susceptibility
LatchïUp
Test Method
Min
2000
Typ
Max
Units
V
V
(Note 1)
MILïSTDï883, Test Method 3015
JEDEC Standard 17
ZAP
I
(Notes 1, 2)
100
mA
LTH
T
Data Retention
Endurance
MILïSTDï883, Test Method 1008
MILïSTDï883, Test Method 1003
100
Years
Stores
DR
N
1,000,000
END
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latchïup protection is provided for stresses up to 100 mA on address and data pins from ï1 V to V + 1 V.
CC
4
DP7114
Table 5. DC ELECTRICAL CHARACTERISTICS (V = +2.5 V to +6 V unless otherwise specified)
CC
Symbol
Parameter
Conditions
Min
Typ
Max
Units
POWER SUPPLY
V
I
Operating Voltage Range
Supply Current (Increment)
2.5
–
–
–
–
–
–
ï
6.0
100
50
V
A
A
A
A
A
CC
V
V
= 6 V, f = 1 MHz, I = 0
CC1
CC2
CC
W
= 6 V, f = 250 kHz, I = 0
–
CC
W
I
Supply Current (Write)
Programming, V = 6 V
–
1000
500
1
CC
V
CC
= 3 V
–
I
(Note 4)
Supply Current (Standby)
CS = V ï 0.3 V
–
SB1
CC
U/D, INC = V ï 0.3 V or GND
CC
LOGIC INPUTS
I
Input Leakage Current
V
V
= V
CC
–
–
–
–
–
–
10
A
A
IH
IN
I
Input Leakage Current
= 0 V
ï10
IL
IN
V
IH2
CMOS High Level Input Voltage
CMOS Low Level Input Voltage
2.5 V b V b 6 V
V
CC
x 0.7
V + 0.3
CC
V
CC
V
ï0.3
V
x 0.2
V
IL2
CC
POTENTIOMETER CHARACTERISTICS
R
Potentiometer Resistance
ï10 Device
ï50 Device
ï00 Device
10
50
k
POT
100
R
Pot. Resistance Tolerance
p20
%
V
TOL
V
Voltage on R pin
0
0
V
CC
V
CC
RH
H
V
Voltage on R pin
V
RL
L
RES
INL
Resolution
3.2
0.5
%
Integral Linearity Error
Differential Linearity Error
Wiper Resistance
I
I
b 2
b 2
A
A
1
LSB
LSB
W
DNL
0.25
70
0.5
200
400
4.4
W
R
WI
V
V
= 5 V, I = 1 mA
W
CC
CC
= 2.5 V, I = 1 mA
150
W
I
W
Wiper Current
ï4.4
mA
ppm/oC
ppm/oC
nV/Hz
pF
TC
TC of Pot Resistance
Ratiometric TC
300
RPOT
RATIO
TC
20
V
N
Noise
100 kHz / 1 kHz
8/24
8/8/25
1.7
C /C /C
Potentiometer Capacitances
Frequency Response
H
L
W
fc
Passive Attenuator, 10 k
MHz
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Latchïup protection is provided for stresses up to 100 mA on address and data pins from ï1 V to V + 1 V.
CC
5. I = source or sink.
W
6. These parameters are periodically sampled and are not 100% tested.
5
DP7114
Table 6. AC TEST CONDITIONS
V
CC
Range
2.5 V b V b 6 V
CC
Input Pulse Levels
0.2 x V to 0.7 x V
CC
CC
Input Rise and Fall Times
Input Reference Levels
10 ns
0.5 x V
CC
Table 7. AC OPERATING CHARACTERISTICS (V = +2.5 V to +6.0 V, V = V , V = 0 V, unless otherwise specified)
CC
H
CC
L
Symbol
Parameter
Min
100
50
100
250
250
1
Typ (Note 7)
Max
Units
ns
ns
ns
ns
ns
s
t
CI
t
DI
t
ID
CS to INC Setup
U/D to INC Setup
U/D to INC Hold
INC LOW Period
INC HIGH Period
ï
ï
ï
ï
ï
ï
ï
ï
1
ï
ï
–
5
ï
ï
ï
t
ï
IL
IH
IC
t
t
ï
INC Inactive to CS Inactive
CS Deselect Time (NO STORE)
CS Deselect Time (STORE)
ï
t
t
100
10
ï
ï
ns
ms
s
CPH
CPH
ï
t
IW
INC to V
Change
5
OUT
t
INC Cycle Time
1
ï
s
CYC
t , t (Note 8) INC Input Rise and Fall Time
ï
500
1
s
R
F
t
(Note 8)
Powerïup to Wiper Stable
–
ms
ms
PU
t
Store Cycle
–
10
WR
7. Typical values are for T = 25oC and nominal supply voltage.
A
8. This parameter is periodically sampled and not 100% tested.
CS
(store)
CPH
t
CYC
t
t
IC
t
CI
t
IL
t
IH
90%
90%
INC
U/D
10%
t
DI
t
ID
t
F
t
R
(Note 9)
t
IW
MI
R
W
Figure 5. A.C. Timing
9. MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position.
6
DP7114
Applications Information
(a) resistive divider
(b) variable resistance
(c) twoïport
Figure 6. Potentiometer Configuration
Applications
3
2
A
1
V (ï)
+
–
1
R
R
4
3
+5 V
1
+5 V
8
R
1
2
1
7
R
R
A
6
+5 V
+5 V
4
8
1
DP
pR
POT
8
7
4
R
–
+
A
9
2
2
1
3
5
3
5
4
R
(1ïp)R
V
1
10
POT
O
3
DP
8
R
2
11
7
4
B
555
DP7114
R
2
A
2
R
–
+
R
4
3
6
DP7113/7114
6
5
+2.5 V
7
V (+)
2
2
0.01
0.003
F
1
C
0.01
F
A = A = A = / LM6064
1
2
3
3
4
F
R = R = R = 5 k
2
POT
4
R
= 10 k
Figure 7. Programmable Instrumentation
Amplifier
Figure 8. Programmable Sq. Wave Oscillator (555)
+5 V
100 k
8
2
DP7113/7114
1
7
DP
V
OUT
V
(REG)
O
4
R
V
(UNREG)
1
IN
2952
6.8
0.1 F
F
11 k
(1ïp)R
pR
SHUTDOWN
1.23 V
1 M
330
330
SD
FB
GND
6
3
R
820
2
5
+5 V
7
+5 V
7
1
F
+5 V
2
3
2
3
10 k
8
2
–
+
–
+
A
6
A
6
2
1
3
V
O
1
7
DP
R
10 k
I
S
3
4
4
5
DP7113/7114
6
4
LT1097
+2.5 V
Figure 9. Programmable Voltage Regulator
Figure 10. Programmable I to V Convertor
7
DP7114
C
F
1
R3
0.001
R1
100 k
C
1
F
2
+5 V
2
V
S
7
–
50 k
0.001
F
V
O
+5 V
8
6
+
R2
4
3
A
1
2
10 k
1
7
DP
+2.5 V
DP7113/7114
4
Figure 11. Programmable Bandpass Filter
+5 V
IC1
393
2
IC2
R
R
V
1
3
LL
–
+
74HC132
1
7
OSC
CLO
3
6
R
2
–
+
CHI
10 k
0.1
F
+5 V
5
V
UL
+5 V
IC3
DP7114
+5 V
6
8
5
2
1
–
+
10 k
3
V
O
DP
2.5 ) V ) 5 V
7
4
O
AI
IC4
+2.5 V
0 ) V ) 2.5 V
V
S
S
Figure 12. Automatic Gain Control
8
DP7114
PACKAGE DIMENSIONS
SOIC 8, 150 mils
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
Q
TOP VIEW
D
h
A1
Q
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
9
DP7114
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
Q
e
TOP VIEW
D
c
A2
A
1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
10
DP7114
PACKAGE DIMENSIONS
MSOP 8, 3x3
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.10
0.15
0.95
0.38
0.23
3.10
5.00
3.10
0.05
0.75
0.22
0.13
2.90
4.80
2.90
0.10
0.85
c
D
3.00
4.90
E
E1
E
E1
e
3.00
0.65 BSC
0.60
L
0.40
0.80
L1
L2
Q
0.95 REF
0.25 BSC
0º
6º
TOP VIEW
D
A2
A
DETAIL A
A1
e
b
c
SIDE VIEW
END VIEW
L2
Notes:
L
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L1
DETAIL A
11
DP7114
PACKAGE DIMENSIONS
TDFN8, 2x3
D
A
e
b
E2
E
PIN#1
IDENTIFICATION
A1
PIN#1 INDEX AREA
D2
L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.70
0.00
0.45
NOM
MAX
0.80
0.05
0.65
A
A1
A2
A3
b
0.75
0.02
A2
0.55
0.20 REF
0.25
A3
0.20
1.90
1.30
2.90
1.20
0.30
2.10
1.50
3.10
1.40
D
2.00
FRONT VIEW
D2
E
1.40
3.00
E2
e
1.30
0.50 TYP
0.30
L
0.20
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
12
DP7114
Table 8. ORDERING INFORMATION
Orderable Part Numbers
Reset Threshold Voltage
PackageïPin
SOICï8
Lead Finish
DP7114VIï10ïGT3
DP7114VIï50ïGT3
10
50
NiPdAu
DP7114VIï00ïGT3
100
10
DP7114VP2I-10-GT3 (Note 10)
DP7114VP2I-50-GT3 (Note 10)
DP7114VP2I-00-GT3 (Note 10)
DP7114YIï10ïGT3
TDFNï8
50
NiPdAu
NiPdAu
NiPdAu
2 x 3 mm
100
10
DP7114YIï50ïG
50
TSSOPï8
MSOPï8
DP7114YIï00ïGT3
100
10
DP7114ZIï10ïGT3
DP7114ZIï50ïGT3
50
DP7114ZIï00ïGT3
100
10.Contact factory for package availability.
13
DP7114
Example of Ordering Information (Note 14)
Prefix
Device #
Suffix
DP
7114
V
I
ï10
ï G
T3
Temperature Range
I = Industrial (ï40oC to +85oC)
Lead Finish
G: NiPdAu
Tape & Reel
T: Tape & Reel
3: 3,000 Units / Reel
Company ID
(Optional)
Product Number
7114
Resistance
ï10: 10 k
ï50: 50 k
ï00: 100 k
Package
V: SOIC
Y: TSSOP
Z: MSOP
VP2: TDFN (Note 13)
11.All packages are RoHSïcompliant (Leadïfree, Halogenïfree).
12.The standard lead finish is NiPdAu.
13.Contact factory for package availability.
14.The device used in the above example is a DP7114VIï10ïGT3 (SOIC, Industrial Temperature, 10 k , NiPdAu, Tape & Reel, 3,000/Reel).
NIDEC COPAL reserves the right to make changes without further notice to any products herein.
NIDEC COPAL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does NIDEC COPAL assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in NIDEC COPAL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.
$OOꢁRSHUDWLQJꢁSDUDPHWHUVꢃꢁLQFOXGLQJꢁ´7\SLFDOVµꢁPXVWꢁEHꢁYDOLGDWHGꢁIRUꢁHDFKꢁFXVWRPHUꢁDSSOLFDWLRQꢁE\ꢁFXVWRPHU·VꢁWHFKQLFDOꢁH[SHUWVꢄꢁ
NIDEC COPAL does not convey any license under its patent rights nor the rights of others.
NIDEC COPAL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the NIDEC COPAL product could create a situation where personal injury or death may occur.
Should Buyer purchase or use NIDEC COPAL products for any such unintended or unauthorized application, Buyer shall indemnify and hold NIDEC COPAL and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that NIDEC COPAL was negligent regarding the design or
manufacture of the part.
DP7114/D
相关型号：
©2020 ICPDF网 联系我们和版权申明