NJU6824H_技术文档

NJU6824

128COMMON x 128RGB LCD DRIVER

FOR 4,096-COLOR STN DISPLAY

ꢀ GENERAL DESCRIPTION

PACKAGE

The NJU6824 is a 128COMMON x 128RGB LCD driver for

4,096-color STN display. It contains common drivers, RGB drivers,

2RGB icon-drivers, a serial and a parallel MPU interface circuit, an

internal LCD power supply, grayscale palettes and 196,608-bit display

data RAM. The segment drivers for RGB (Red, Green, Blue)

independently produce optimum 16 grayscales from a built-in

32-grayscale palette, and the LSI achieves 4,096 colors (16x16x16). And

the LSI features the display-rotation function which rotates an on-screen

image in the unit of 90 degrees.

In addition, the NJU6824 operates with a low voltage of 1.7V and a

low operating current, therefore it is ideally suited for battery-powered

handheld applications.

BUMP CHIP

ꢀ FEATURES

ꢁ

4,096-color STN LCD driver

Built-in LCD Drivers

: 128-common Drivers

: 2RGB Icon-drivers

x 128RGB Drivers (384-segment Drivers in B&W)

ꢁ

Built-in Display Data RAM (DDRAM) : 196,608 bits for Graphic Display

Programmable Display Mode

- Variable 16-grayscale Mode

- Variable 8-grayscale Mode

- Fixed 8-grayscale Mode

- B&W Mode

: 4,096 Colors

: 256 Colors

: Black & White

ꢁ

8-/16-bit Parallel Interface Selectable

8-/16-bit Bus Length for Display Data Selectable

3-/4-line Serial Interface Selectable

Programmable Duty Ratio and Bias Ratio

Programmable Internal Voltage Booster : Maximum 6 times

Programmable Contrast Control

: 128-step Electrical Variable Resistor (EVR)

LCD Bias Adjustment Circuit

Various Useful Instructions

Display-rotation Function / Mirror-inversion Function

Low Operating Current

Low Logic Voltage

Wide LCD Voltage Range

C-MOS Technology

Slim Chip for COG

Package

: 450uA Typical at V_DD=3V, 4-time Boost, Checker Flag Display

: 1.7V to 3.3V

: 5.0V to 18.0V

: Bump Chip / TCP

Ver.2004-01-06

- 1 -

NJU6824

TABLE OF CONTENTS

ꢀGENERAL DESCRIPTION

PACKAGE ........................................................................................1

ꢀFEATURES .............................................................................................................................................1

ꢀPAD LOCATION......................................................................................................................................5

ꢀPAD COORDINATES 1...........................................................................................................................8

ꢀPAD COORDINATES 2...........................................................................................................................9

ꢀPAD COORDINATES 3.........................................................................................................................10

ꢀPAD COORDINATES 4.........................................................................................................................11

ꢀPAD COORDINATES 5.........................................................................................................................12

ꢀPAD COORDINATES 6.........................................................................................................................13

ꢀBLOCK DIAGRAM ...............................................................................................................................14

ꢀLCD POWER SUPPLY BLOCK DIAGRAM.........................................................................................15

ꢀTERMINAL DESCRIPTION 1...............................................................................................................16

ꢀTERMINAL DESCRIPTION 2...............................................................................................................17

ꢀTERMINAL DESCRIPTION 3...............................................................................................................18

ꢀFUNCTIONAL DESCRIPTION .............................................................................................................19

(1) MPU INTERFACE..........................................................................................................................19

(1-1) Selection of Parallel/Serial Interface Mode.....................................................................................19

(1-2) Selection of MPU Mode ..................................................................................................................19

(1-3) Data Recognition.............................................................................................................................19

(1-4) Selection of 3-/4-line Serial Interface Mode....................................................................................19

(1-5) 4-line Serial Interface Mode............................................................................................................19

(1-6) 3-line Serial Interface Mode............................................................................................................20

(1-7) Accessing DDRAM..........................................................................................................................21

(1-8) Accessing Instruction Register........................................................................................................22

(1-9) Selection of 8-/16-bit Bus Length (Parallel Interface Mode)...........................................................22

(2) INITIAL DISPLAY LINE REGISTER ..............................................................................................22

(3) COLUMN AND ROW ADDRESS COUNTERS .............................................................................22

(4) DDRAM...........................................................................................................................................23

(4-1) DDRAM Address Range.................................................................................................................23

(4-2) Window Area for DDRAM Access...................................................................................................24

(4-3) DDRAM Access Direction (Display-rotation and Mirror-inversion Functions).................................25

(4-4) Bit Assignment of Display Data.......................................................................................................26

(4-4-1) Bit Assignment Overview ........................................................................................................................26

(4-4-2) Bit Assignment in Variable 16-grayscale Mode (DDRAM).......................................................................27

(4-4-3) Bit Assignment in variable 8-grayscale Mode (DDRAM) .........................................................................29

(4-4-4) Bit Assignment in Fixed 8-grayscale Mode (DDRAM).............................................................................30

(4-4-5) Bit Assignment in B&W Mode (DDRAM).................................................................................................32

(4-4-6) Write Data and Read Data......................................................................................................................34

(5) GRAYSCALE CONTROL CIRCUIT...............................................................................................35

(5-1) Display Mode Selection ..................................................................................................................35

(5-1-1) Variable 16-grayscale Mode....................................................................................................................35

(5-1-2) Variable 8-grayscale Mode......................................................................................................................35

(5-1-3) Fixed 8-grayscale Mode..........................................................................................................................35

(5-1-4) B&W Mode..............................................................................................................................................35

(6) GRAYSCALE PALETTE ................................................................................................................36

(6-1) Grayscale Selection in Variable 16-grayscale Mode ......................................................................36

(6-2) Grayscale Selection in Variable 8-grayscale Mode ........................................................................37

(6-3) Grayscale Selection in Fixed 8-grayscale Mode.............................................................................38

Ver.2004-01-06

- 2 -

NJU6824

(6-4) Grayscale Selection in B&W Mode.................................................................................................38

(7) DISPLAY TIMING GENERATOR...................................................................................................39

(8) DATA LATCH CIRCUIT .................................................................................................................39

(9) COMMON DRIVERS AND SEGMENT DRIVERS.........................................................................39

(10) ICON SEGMENT..........................................................................................................................40

(10-1) Icon Segment Driver .....................................................................................................................40

(10-2) Bit Assignment of Icon Segment Register Data............................................................................41

(10-2-1) Bit Assignment Overview ........................................................................................................................41

(10-2-2) Bit Assignment in Variable 16-grayscale Mode (Icon Segment Register)................................................42

(10-2-3) Bit Assignment in variable 8-grayscale Mode (Icon Segment Register)..................................................44

(10-2-4) Bit Assignment in Fixed 8-grayscale Mode (Icon Segment Register)......................................................45

(10-2-5) Bit Assignment in B&W Mode (Icon Segment Register)..........................................................................47

(11) OSCILLATOR...............................................................................................................................49

(11-1) Using Internal Resistor (CKS=0)...................................................................................................49

(11-2) Using External Resistor (CKS=1)..................................................................................................49

(11-3) Using External Clock (CKS=1)......................................................................................................49

(12) LCD POWER SUPPLY ................................................................................................................49

(12-1) Voltage Booster.............................................................................................................................50

(12-2) Voltage Converter .........................................................................................................................51

(12-2-1) Reference Voltage Generator .................................................................................................................51

(12-2-2) Voltage Regulator....................................................................................................................................51

(12-2-3) Electrical Variable Resistor (EVR)...........................................................................................................51

(12-2-4) LCD Bias Voltage Generator...................................................................................................................51

(12-3) External Components for LCD Power Supply...............................................................................52

(12-4) Discharge Circuit...........................................................................................................................55

(12-5) Power ON/OFF..............................................................................................................................55

(12-5-1) Power ON/OFF in Using Internal LCD Power Supply .............................................................................55

(12-5-2) Power ON/OFF in Using External LCD Power Supply............................................................................55

(12-6) LCD Bias Adjustment Circuit.........................................................................................................55

(13) RESET FUNCTION......................................................................................................................56

(14) INSTRUCTION TABLES..............................................................................................................57

(14-1) Instruction Table and Register Address........................................................................................57

(14-2) Instruction Table 0 (RE2, RE1, RE0)=(0, 0, 0)...........................................................................58

(14-3) Instruction Table 1 (RE2, RE1, RE0)=(0, 0, 1)...........................................................................59

(14-4) Instruction Table 2 (RE2, RE1, RE0)=(0, 1, 0)...........................................................................60

(14-5) Instruction Table 3 (RE2, RE1, RE0)=(0, 1, 1)...........................................................................61

(14-6) Instruction Table 4 (RE2, RE1, RE0)=(1, 0, 0)...........................................................................62

(14-7) Instruction Table 5 (RE2, RE1, RE0)=(1, 0, 1)...........................................................................63

(15) INSTRUCTION DESCRIPTIONS.................................................................................................64

(15-1) Display Data Write.........................................................................................................................64

(15-2) Display Data Read ........................................................................................................................64

(15-3) Window Start Column Address .....................................................................................................64

(15-4) Window Start Row Address ..........................................................................................................64

(15-5) Initial Display Line .........................................................................................................................64

(15-6) N-line Inversion .............................................................................................................................65

(15-7) Display Control (1).........................................................................................................................66

(15-8) Display Control (2).........................................................................................................................67

(15-9) Increment/Decrement Control.......................................................................................................68

(15-10) Power Control..............................................................................................................................69

(15-11) Duty Cycle Ratio..........................................................................................................................70

(15-12) Boost Level..................................................................................................................................70

(15-13) LCD Bias Ratio............................................................................................................................71

(15-14) Instruction Table Select...............................................................................................................71

(15-15) Palette A / B / C...........................................................................................................................72

(15-16) Initial COM...................................................................................................................................78

(15-17) Duty-1 /Display Clock ON/OFF ...................................................................................................78

(15-18) Display Mode Control /Boost Clock Control................................................................................78

(15-19) Bus Length ..................................................................................................................................79

(15-20) EVR Control.................................................................................................................................79

Ver.2004-01-06

- 3 -

NJU6824

(15-21) Frequency Control.......................................................................................................................80

(15-22) Discharge ON/OFF......................................................................................................................80

(15-23) Register Address.........................................................................................................................81

(15-24) Register Read..............................................................................................................................81

(15-25) Window End Column Address.....................................................................................................81

(15-26) Window End Row Address..........................................................................................................81

(15-27) Initial Line-reverse Address.........................................................................................................81

(15-28) Last Line-reverse Address ..........................................................................................................82

(15-29) Line Reverse ON/OFF.................................................................................................................82

(15-30) Upper/Lower Palette Select /Icon Segment Access ON/OFF.....................................................83

(15-31) PWM Control ...............................................................................................................................83

(16) PARTIAL DISPLAY FUNCTION ..................................................................................................84

(17) SWAP FUNCTION .......................................................................................................................84

(17-1) Swap Function in Variable 16-grayscale Mode.............................................................................85

(17-2) Swap Function in Variable 8-Grayscale Mode..............................................................................87

(17-3) Swap Function in Fixed 8-grayscale Mode...................................................................................88

(17-4) Swap Function in B&W Mode .......................................................................................................90

(18) RELATION BETWEEN ROW ADDRESS AND COMMON DRIVER...........................................91

(18-1) SHIFT=0, Initial Display Line “0”, Duty Cycle Ratio “1/129”..........................................................92

(18-2) SHIFT=0, Initial Display Line “0”, Duty Cycle Ratio “1/17”............................................................93

(18-3) SHIFT=1, Initial Display Line “0”, Duty Cycle Ratio “1/129”..........................................................94

(18-4) SHIFT=0, Initial Display Line “5”, Duty Cycle Ratio “1/129”..........................................................95

(18-5) SHIFT=0, Initial Display Line “0”, Duty Cycle Ratio “1/128” (Dity-1 ON) ......................................96

(19) TYPICAL INSTRUCTION SEQUENCES.....................................................................................97

(19-1) Initialization Sequence in Using Internal LCD Power Supply .......................................................97

(19-2) Initialization Sequence in Using External LCD Power Supply ......................................................98

(19-3) Display Data Write Sequence .......................................................................................................99

(19-4) Partial Display Sequence............................................................................................................100

(19-5) Power OFF Sequence.................................................................................................................101

ꢀABSOLUTE MAXIMUM RATINGS.....................................................................................................102

ꢀRECOMMENDED OPERATING CONDITIONS .................................................................................102

ꢀDC CHARACTERISTICS....................................................................................................................103

ꢀOSCILLATION FREQUENCY AND FRAME FREQUENCY..............................................................104

ꢀAC CHARACTERISTICS....................................................................................................................106

(1) Write Operation (Parallel Interface / 80-series MPU) ..................................................................106

(2) Read Operation (Parallel Interface / 80-series MPU) ..................................................................107

(3) Write Operation (Parallel Interface / 68-series MPU) ..................................................................108

(4) Read Operation (Parallel Interface / 68-series MPU) ..................................................................109

(5) Serial Interface .............................................................................................................................110

(6) Display Control Timing .................................................................................................................111

(7) Input Clock Timing........................................................................................................................112

(8) Reset Input Timing .......................................................................................................................112

(9) Delay Time of Gate ......................................................................................................................112

ꢀINPUT/OUTPUT BLOCK DIAGRAMS...............................................................................................113

ꢀMPU CONNECTIONS.........................................................................................................................114

Ver.2004-01-06

- 4 -

NJU6824

ꢀ PAD LOCATION

DMY₄₄

DMY₄₅

DMY₄₆

COM₁₁₄

COM₁₂₇

DMY₄₇

DMY₇₁

1

Chip Center

Chip Size

:X=0um, Y=0um

:X=22.07mm, Y= 2.55mm

:625um + 25um

Chip Thickness

Bump Pitch

Bump Space

Bump Size

:43um (Min)

:15um

:28um x 110um (COM/SEG, DMY₁₀-DMY₇₁)

:60um x 100um (MPU I/F)

:28um x 100um (DMY₀-DMY₉)

:14.0um–22.5um (18um Typical)

:Au

Bump Height

Bump Material

NOTE1) Multiple PADs with successive numbers are internally connected.

NOTE2) Dummy PADs, symbolized with DUMMY, are electrically open.

NOTE3) The purpose of this drawing is to show the order of PADs. Use "PAD CORDINATE TABLE 1 to 6" for design.

Ver.2004-01-06

- 5 -

NJU6824

Y

X

a

Alignment Mark

d

a: 30um

b: 6um

c: 120um

d: 27um

d

b

c

Coordinates

a

X=10,866um, Y=1,106um

X=10,866um, Y=-1,106um

b

c

Ver.2004-01-06

- 6 -

NJU6824

DMY₃₇

DMY₃₆

DMY₃₅

COM₅₀

Y

X

COM₆₃

DMY₃₄

DMY₁₀

Ver.2004-01-06

- 7 -

NJU6824

ꢀ PAD COORDINATES 1

Chip Size : 22,070µm x 2,550µm (Center 0µm x 0µm )

No.

PAD NAME

X(um)

Y(um)

No.

PAD NAME

X(um)

Y(um)

No.

PAD NAME

X(um)

Y(um)

1

DMY₀

DMY₁

DMY₂

V_SSA

-10642.5

-10599.5

-10556.5

-10475.5

-10402.5

-10293.0

-10220.0

-10110.5

-10037.5

-9928.0

-9855.0

-9745.5

-9672.5

-9563.0

-9490.0

-9380.5

-9271.0

-9198.0

-9088.5

-8979.0

-8906.0

-8796.5

-8687.0

-8614.0

-8504.5

-8395.0

-8322.0

-8212.5

-8139.5

-7993.5

-7920.5

-7774.5

-7701.5

-7555.5

-7482.5

-7336.5

-7263.5

-7117.5

-7044.5

-6898.5

-6825.5

-6679.5

-6606.5

-6460.5

-6387.5

-6241.5

-6168.5

-6022.5

-5949.5

-5803.5

-5730.5

-1090.0

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

D₁₀

-5584.5

-5511.5

-5365.5

-5292.5

-5146.5

-5073.5

-4927.5

-4854.5

-4708.5

-4635.5

-4489.5

-4416.5

-4197.5

-4124.5

-4051.5

-3978.5

-3905.5

-3832.5

-3759.5

-3613.5

-3540.5

-3394.5

-3321.5

-3175.5

-3102.5

-2956.5

-2883.5

-2701.0

-2628.0

-2409.0

-2336.0

-2044.0

-1971.0

-1898.0

-1825.0

-1752.0

-1679.0

-1606.0

-1460.0

-1387.0

-1277.5

-1204.5

-1095.0

-1022.0

-912.5

-1090.0

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

V₄A₂

V_SSA

V_LCD

V₁

-292.0

-182.5

-109.5

0.0

-1090.0

2

3

D₁₁

4

D₁₁

5

V_SSA

D₁₂

73.0

6

SEL68

V_DDA

D₁₂

146.0

7

D₁₃

219.0

8

D₁₃

292.0

9

V_DDA

D₁₄

365.0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

P/S

D₁₄

511.0

P/S

D₁₅

V₁

584.0

V_SSA

D₁₅

V₁

657.0

V_SSA

V_DD

CL

V₁

730.0

RESb

DMY₃

CSb

V₁

803.0

V₁

876.0

V₂

1022.0

1095.0

1168.0

1241.0

1314.0

1387.0

1533.0

1606.0

1679.0

1752.0

1825.0

1898.0

2044.0

2117.0

2190.0

2263.0

2336.0

2409.0

2555.0

2628.0

2701.0

2774.0

2847.0

2920.0

3029.5

3102.5

3175.5

3248.5

3321.5

3394.5

3504.0

3577.0

3650.0

3723.0

3796.0

3869.0

V₂

CSb

V₂

DMY₄

RS

V₂

RS

CL

V₂

DMY₅

WRb

DMY₆

RDb

FLM

FR

V₃

FR

V₃

CLK

OSC₁

OSC₂

V_SS

V₃

RDb

V₃

V_DDA

V₄

V_DDA

V₄

D₀/SCL

D₁/SDA

D₂

V₄

V_SS

V₄

V_SS

V_REG

V_REF

V_BA

D₂

V_SS

D₃/SMODE

D₄/SPOL

D₅

V_SS

V₁A₁

V_DDA

V₁A₂

V_SSA

V₄A₁

V_DDA

V₄A₂

D₅

D₆

D₇

V_SSA

-839.5

V_SSA

-730.0

D₈

-657.0

D₈

-547.5

D₉

-474.5

D₉

-365.0

Ver.2004-01-06

- 8 -

NJU6824

ꢀ PAD COORDINATES 2

Chip Size : 22,070µm x 2,550µm (Center 0µm x 0µm )

No.

PAD NAME

X(um)

Y(um)

No.

PAD NAME

X(um)

Y(um)

No.

PAD NAME

X(um)

Y(um)

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

V_SSH

V_OUT

V_EE

C₁+

C₁-

4051.5

4124.5

4197.5

4270.5

4343.5

4416.5

4489.5

4672.0

4745.0

4818.0

4891.0

4964.0

5037.0

5110.0

5292.5

5365.5

5438.5

5511.5

5584.5

5657.5

5730.5

5840.0

5913.0

5986.0

6059.0

6132.0

6205.0

6314.5

6387.5

6460.5

6533.5

6606.5

6679.5

6789.0

6862.0

6935.0

7008.0

7081.0

7154.0

7263.5

7336.5

7409.5

7482.5

7555.5

7628.5

7738.0

7811.0

7884.0

7957.0

8030.0

8103.0

-1090.0

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

C₃-

8212.5

8285.5

-1090.0

-881.5

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

DMY₂₈

DMY₂₉

DMY₃₀

DMY₃₁

DMY₃₂

DMY₃₃

DMY₃₄

COM₆₃

COM₆₂

COM₆₁

COM₆₀

COM₅₉

COM₅₈

COM₅₇

COM₅₆

COM₅₅

COM₅₄

COM₅₃

COM₅₂

COM₅₁

COM₅₀

DMY₃₅

DMY₃₆

DMY₃₇

DMY₃₈

DMY₃₉

DMY₄₀

COM₄₉

COM₄₈

COM₄₇

COM₄₆

COM₄₅

COM₄₄

COM₄₃

COM₄₂

COM₄₁

COM₄₀

COM₃₉

COM₃₈

COM₃₇

COM₃₆

COM₃₅

COM₃₄

COM₃₃

COM₃₂

COM₃₁

COM₃₀

COM₂₉

COM₂₈

COM₂₇

COM₂₆

10845.0

10642.5

10599.5

10556.5

10513.5

10470.5

10427.5

10384.5

10341.5

10298.5

10255.5

10212.5

10169.5

10126.5

10083.5

10040.5

9997.5

-107.5

-64.5

C₃-

8358.5

-21.5

C₃-

8431.5

21.5

C₃-

8504.5

64.5

C₃-

8577.5

107.5

C₄+

8687.0

150.5

C₄+

8760.0

193.5

C₄+

8833.0

236.5

C₄+

8906.0

279.5

C₄+

8979.0

322.5

C₄+

9052.0

365.5

C₄-

9161.5

408.5

C₄-

9234.5

451.5

C₄-

9307.5

494.5

C₄-

9380.5

537.5

C₄-

9453.5

580.5

C₄-

9526.5

623.5

C₅+

9636.0

666.5

C₅+

9709.0

709.5

C₅+

9782.0

752.5

C₅+

9855.0

795.5

C₅+

9928.0

838.5

C₅+

10001.0

10110.5

10183.5

10256.5

10329.5

10402.5

10475.5

10556.5

10599.5

10642.5

10845.0

881.5

C₅-

1085.0

C₅-

C₁-

C₅-

C₁-

C₅-

C₁-

DMY₇

DMY₈

DMY₉

DMY₁₀

DMY₁₁

DMY₁₂

DMY₁₃

DMY₁₄

DMY₁₅

DMY₁₆

DMY₁₇

DMY₁₈

DMY₁₉

DMY₂₀

DMY₂₁

DMY₂₂

DMY₂₃

DMY₂₄

DMY₂₅

DMY₂₆

DMY₂₇

C₁-

C₂+

C₂-

-838.5

-795.5

-752.5

-709.5

-666.5

-623.5

C₂-

-580.5

9954.5

C₂-

-537.5

9911.5

C₂-

-494.5

9868.5

C₂-

-451.5

9825.5

C₂-

-408.5

9782.5

C₃+

-365.5

9739.5

-322.5

9696.5

-279.5

9653.5

-236.5

9610.5

-193.5

9567.5

-150.5

9524.5

Ver.2004-01-06

- 9 -

NJU6824

ꢀ PAD COORDINATES 3

Chip Size : 22,070µm x 2,550µm (Center 0µm x 0µm )

No.

PAD NAME

X(um)

Y(um)

No.

PAD NAME

X(um)

Y(um)

No.

PAD NAME

X(um)

Y(um)

307

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

352

353

354

355

356

357

COM₂₅

COM₂₄

COM₂₃

COM₂₂

COM₂₁

COM₂₀

COM₁₉

COM₁₈

COM₁₇

COM₁₆

COM₁₅

COM₁₄

COM₁₃

COM₁₂

COM₁₁

COM₁₀

COM₉

9481.5

9438.5

9395.5

9352.5

9309.5

9266.5

9223.5

9180.5

9137.5

9094.5

9051.5

9008.5

8965.5

8922.5

8879.5

8836.5

8793.5

8750.5

8707.5

8664.5

8621.5

8578.5

8535.5

8492.5

8449.5

8406.5

8363.5

8320.5

8277.5

8234.5

8191.5

8148.5

8105.5

8062.5

8019.5

7976.5

7933.5

7890.5

7847.5

7804.5

7761.5

7718.5

7675.5

7632.5

7589.5

7546.5

7503.5

7460.5

7417.5

7374.5

7331.5

1085.0

358

359

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

385

386

387

388

389

390

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

408

SEGB₇

SEGC₇

SEGA₈

SEGB₈

SEGC₈

SEGA₉

SEGB₉

SEGC₉

SEGA₁₀

SEGB₁₀

SEGC₁₀

SEGA₁₁

SEGB₁₁

SEGC₁₁

SEGA₁₂

SEGB₁₂

SEGC₁₂

SEGA₁₃

SEGB₁₃

SEGC₁₃

SEGA₁₄

SEGB₁₄

SEGC₁₄

SEGA₁₅

SEGB₁₅

SEGC₁₅

SEGA₁₆

SEGB₁₆

SEGC₁₆

SEGA₁₇

SEGB₁₇

SEGC₁₇

SEGA₁₈

SEGB₁₈

SEGC₁₈

SEGA₁₉

SEGB₁₉

SEGC₁₉

SEGA₂₀

SEGB₂₀

SEGC₂₀

SEGA₂₁

SEGB₂₁

SEGC₂₁

SEGA₂₂

SEGB₂₂

SEGC₂₂

SEGA₂₃

SEGB₂₃

SEGC₂₃

SEGA₂₄

7288.5

7245.5

7202.5

7159.5

7116.5

7073.5

7030.5

6987.5

6944.5

6901.5

6858.5

6815.5

6772.5

6729.5

6686.5

6643.5

6600.5

6557.5

6514.5

6471.5

6428.5

6385.5

6342.5

6299.5

6256.5

6213.5

6170.5

6127.5

6084.5

6041.5

5998.5

5955.5

5912.5

5869.5

5826.5

5783.5

5740.5

5697.5

5654.5

5611.5

5568.5

5525.5

5482.5

5439.5

5396.5

5353.5

5310.5

5267.5

5224.5

5181.5

5138.5

1085.0

409

410

411

412

413

414

415

416

417

418

419

420

421

422

423

424

425

426

427

428

429

430

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

449

450

451

452

453

454

455

456

457

458

459

SEGB₂₄

SEGC₂₄

SEGA₂₅

SEGB₂₅

SEGC₂₅

SEGA₂₆

SEGB₂₆

SEGC₂₆

SEGA₂₇

SEGB₂₇

SEGC₂₇

SEGA₂₈

SEGB₂₈

SEGC₂₈

SEGA₂₉

SEGB₂₉

SEGC₂₉

SEGA₃₀

SEGB₃₀

SEGC₃₀

SEGA₃₁

SEGB₃₁

SEGC₃₁

SEGA₃₂

SEGB₃₂

SEGC₃₂

SEGA₃₃

SEGB₃₃

SEGC₃₃

SEGA₃₄

SEGB₃₄

SEGC₃₄

SEGA₃₅

SEGB₃₅

SEGC₃₅

SEGA₃₆

SEGB₃₆

SEGC₃₆

SEGA₃₇

SEGB₃₇

SEGC₃₇

SEGA₃₈

SEGB₃₈

SEGC₃₈

SEGA₃₉

SEGB₃₉

SEGC₃₉

SEGA₄₀

SEGB₄₀

SEGC₄₀

SEGA₄₁

5095.5

5052.5

5009.5

4966.5

4923.5

4880.5

4837.5

4794.5

4751.5

4708.5

4665.5

4622.5

4579.5

4536.5

4493.5

4450.5

4407.5

4364.5

4321.5

4278.5

4235.5

4192.5

4149.5

4106.5

4063.5

4020.5

3977.5

3934.5

3891.5

3848.5

3805.5

3762.5

3719.5

3676.5

3633.5

3590.5

3547.5

3504.5

3461.5

3418.5

3375.5

3332.5

3289.5

3246.5

3203.5

3160.5

3117.5

3074.5

3031.5

2988.5

2945.5

1085.0

COM₈

COM₇

COM₆

COM₅

COM₄

COM₃

COM₂

COM₁

COM₀

SEGSA₀

SEGSB₀

SEGSC₀

SEGA₀

SEGB₀

SEGC₀

SEGA₁

SEGB₁

SEGC₁

SEGA₂

SEGB₂

SEGC₂

SEGA₂

SEGB₃

SEGC₃

SEGA₄

SEGB₄

SEGC₄

SEGA₅

SEGB₅

SEGC₅

SEGA₆

SEGB₆

SEGC₆

SEGA₇

Ver.2004-01-06

- 10 -

NJU6824

ꢀ PAD COORDINATES 4

Chip Size : 22,070µm x 2,550µm (Center 0µm x 0µm )

No.

PAD NAME

X(um)

Y(um)

No.

PAD NAME

X(um)

Y(um)

No.

PAD NAME

X(um)

Y(um)

460

461

462

463

464

465

466

467

468

469

470

471

472

473

474

475

476

477

478

479

480

481

482

483

484

485

486

487

488

489

490

491

492

493

494

495

496

497

498

499

500

501

502

503

504

505

506

507

508

509

510

SEGB₄₁

SEGC₄₁

SEGA₄₂

SEGB₄₂

SEGC₄₂

SEGA₄₃

SEGB₄₃

SEGC₄₃

SEGA₄₄

SEGB₄₄

SEGC₄₄

SEGA₄₅

SEGB₄₅

SEGC₄₅

SEGA₄₆

SEGB₄₆

SEGC₄₆

SEGA₄₇

SEGB₄₇

SEGC₄₇

SEGA₄₈

SEGB₄₈

SEGC₄₈

SEGA₄₉

SEGB₄₉

SEGC₄₉

SEGA₅₀

SEGB₅₀

SEGC₅₀

SEGA₅₁

SEGB₅₁

SEGC₅₁

SEGA₅₂

SEGB₅₂

SEGC₅₂

SEGA₅₃

SEGB₅₃

SEGC₅₃

SEGA₅₄

SEGB₅₄

SEGC₅₄

SEGA₅₅

SEGB₅₅

SEGC₅₅

SEGA₅₆

SEGB₅₆

SEGC₅₆

SEGA₅₇

SEGB₅₇

SEGC₅₇

SEGA₅₈

2902.5

2859.5

2816.5

2773.5

2730.5

2687.5

2644.5

2601.5

2558.5

2515.5

2472.5

2429.5

2386.5

2343.5

2300.5

2257.5

2214.5

2171.5

2128.5

2085.5

2042.5

1999.5

1956.5

1913.5

1870.5

1827.5

1784.5

1741.5

1698.5

1655.5

1612.5

1569.5

1526.5

1483.5

1440.5

1397.5

1354.5

1311.5

1268.5

1225.5

1182.5

1139.5

1096.5

1053.5

1010.5

967.5

1085.0

511

512

513

514

515

516

517

518

519

520

521

522

523

524

525

526

527

528

529

530

531

532

533

534

535

536

537

538

539

540

541

542

543

544

545

546

547

548

549

550

551

552

553

554

555

556

557

558

559

560

561

SEGB₅₈

SEGC₅₈

SEGA₅₉

SEGB₅₉

SEGC₅₉

SEGA₆₀

SEGB₆₀

SEGC₆₀

SEGA₆₁

SEGB₆₁

SEGC₆₁

SEGA₆₂

SEGB₆₂

SEGC₆₂

SEGA₆₃

SEGB₆₃

SEGC₆₃

SEGA₆₄

SEGB₆₄

SEGC₆₄

SEGA₆₅

SEGB₆₅

SEGC₆₅

SEGA₆₆

SEGB₆₆

SEGC₆₆

SEGA₆₇

SEGB₆₇

SEGC₆₇

SEGA₆₈

SEGB₆₈

SEGC₆₈

SEGA₆₉

SEGB₆₉

SEGC₆₉

SEGA₇₀

SEGB₇₀

SEGC₇₀

SEGA₇₁

SEGB₇₁

SEGC₇₁

SEGA₇₂

SEGB₇₂

SEGC₇₂

SEGA₇₃

SEGB₇₃

SEGC₇₃

SEGA₇₄

SEGB₇₄

SEGC₇₄

SEGA₇₅

709.5

666.5

1085.0

562

563

564

565

566

567

568

569

570

571

572

573

574

575

576

577

578

579

580

581

582

583

584

585

586

587

588

589

590

591

592

593

594

595

596

597

598

599

600

601

602

603

604

605

606

607

608

609

610

611

612

SEGB₇₅

SEGC₇₅

SEGA₇₆

SEGB₇₆

SEGC₇₆

SEGA₇₇

SEGB₇₇

SEGC₇₇

SEGA₇₈

SEGB₇₈

SEGC₇₈

SEGA₇₉

SEGB₇₉

SEGC₇₉

SEGA₈₀

SEGB₈₀

SEGC₈₀

SEGA₈₁

SEGB₈₁

SEGC₈₁

SEGA₈₂

SEGB₈₂

SEGC₈₂

SEGA₈₃

SEGB₈₃

SEGC₈₃

SEGA₈₄

SEGB₈₄

SEGC₈₄

SEGA₈₅

SEGB₈₅

SEGC₈₅

SEGA₈₆

SEGB₈₆

SEGC₈₆

SEGA₈₇

SEGB₈₇

SEGC₈₇

SEGA₈₈

SEGB₈₈

SEGC₈₈

SEGA₈₉

SEGB₈₉

SEGC₈₉

SEGA₉₀

SEGB₉₀

SEGC₉₀

SEGA₉₁

SEGB₉₁

SEGC₉₁

SEGA₉₂

-1483.5

-1526.5

-1569.5

-1612.5

-1655.5

-1698.5

-1741.5

-1784.5

-1827.5

-1870.5

-1913.5

-1956.5

-1999.5

-2042.5

-2085.5

-2128.5

-2171.5

-2214.5

-2257.5

-2300.5

-2343.5

-2386.5

-2429.5

-2472.5

-2515.5

-2558.5

-2601.5

-2644.5

-2687.5

-2730.5

-2773.5

-2816.5

-2859.5

-2902.5

-2945.5

-2988.5

-3031.5

-3074.5

-3117.5

-3160.5

-3203.5

-3246.5

-3289.5

-3332.5

-3375.5

-3418.5

-3461.5

-3504.5

-3547.5

-3590.5

-3633.5

1085.0

623.5

580.5

537.5

494.5

451.5

408.5

365.5

322.5

279.5

236.5

193.5

150.5

107.5

64.5

21.5

-21.5

-64.5

-107.5

-150.5

-193.5

-236.5

-279.5

-322.5

-365.5

-408.5

-451.5

-494.5

-537.5

-580.5

-623.5

-666.5

-709.5

-752.5

-795.5

-838.5

-881.5

-924.5

-967.5

-1010.5

-1053.5

-1096.5

-1139.5

-1182.5

-1225.5

-1268.5

-1311.5

-1354.5

-1397.5

-1440.5

924.5

881.5

838.5

795.5

752.5

Ver.2004-01-06

- 11 -

NJU6824

ꢀ PAD COORDINATES 5

Chip Size : 22,070µm x 2,550µm (Center 0µm x 0µm )

No.

PAD NAME

X(um)

Y(um)

No.

PAD NAME

X(um)

Y(um)

No.

PAD NAME

X(um)

Y(um)

613

614

615

616

617

618

619

620

621

622

623

624

625

626

627

628

629

630

631

632

633

634

635

636

637

638

639

640

641

642

643

644

645

646

647

648

649

650

651

652

653

654

655

656

657

658

659

660

661

662

663

SEGB₉₂

SEGC₉₂

SEGA₉₃

SEGB₉₃

SEGC₉₃

SEGA₉₄

SEGB₉₄

SEGC₉₄

SEGA₉₅

SEGB₉₅

SEGC₉₅

SEGA₉₆

SEGB₉₆

SEGC₉₆

SEGA₉₇

SEGB₉₇

SEGC₉₇

SEGA₉₈

SEGB₉₈

SEGC₉₈

SEGA₉₉

SEGB₉₉

SEGC₉₉

SEGA₁₀₀

SEGB₁₀₀

SEGC₁₀₀

SEGA₁₀₁

SEGB₁₀₁

SEGC₁₀₁

SEGA₁₀₂

SEGB₁₀₂

SEGC₁₀₂

SEGA₁₀₃

SEGB₁₀₃

SEGC₁₀₃

SEGA₁₀₄

SEGB₁₀₄

SEGC₁₀₄

SEGA₁₀₅

SEGB₁₀₅

SEGC₁₀₅

SEGA₁₀₆

SEGB₁₀₆

SEGC₁₀₆

SEGA₁₀₇

SEGB₁₀₇

SEGC₁₀₇

SEGA₁₀₈

SEGB₁₀₈

SEGC₁₀₈

SEGA₁₀₉

-3676.5

-3719.5

-3762.5

-3805.5

-3848.5

-3891.5

-3934.5

-3977.5

-4020.5

-4063.5

-4106.5

-4149.5

-4192.5

-4235.5

-4278.5

-4321.5

-4364.5

-4407.5

-4450.5

-4493.5

-4536.5

-4579.5

-4622.5

-4665.5

-4708.5

-4751.5

-4794.5

-4837.5

-4880.5

-4923.5

-4966.5

-5009.5

-5052.5

-5095.5

-5138.5

-5181.5

-5224.5

-5267.5

-5310.5

-5353.5

-5396.5

-5439.5

-5482.5

-5525.5

-5568.5

-5611.5

-5654.5

-5697.5

-5740.5

-5783.5

-5826.5

1085.0

664

665

666

667

668

669

670

671

672

673

674

675

676

677

678

679

680

681

682

683

684

685

686

687

688

689

690

691

692

693

694

695

696

697

698

699

700

701

702

703

704

705

706

707

708

709

710

711

712

713

714

SEGB₁₀₉

SEGC₁₀₉

SEGA₁₁₀

SEGB₁₁₀

SEGC₁₁₀

SEGA₁₁₁

SEGB₁₁₁

SEGC₁₁₁

SEGA₁₁₂

SEGB₁₁₂

SEGC₁₁₂

SEGA₁₁₃

SEGB₁₁₃

SEGC₁₁₃

SEGA₁₁₄

SEGB₁₁₄

SEGC₁₁₄

SEGA₁₁₅

SEGB₁₁₅

SEGC₁₁₅

SEGA₁₁₆

SEGB₁₁₆

SEGC₁₁₆

SEGA₁₁₇

SEGB₁₁₇

SEGC₁₁₇

SEGA₁₁₈

SEGB₁₁₈

SEGC₁₁₈

SEGA₁₁₉

SEGB₁₁₉

SEGC₁₁₉

SEGA₁₂₀

SEGB₁₂₀

SEGC₁₂₀

SEGA₁₂₁

SEGB₁₂₁

SEGC₁₂₁

SEGA₁₂₂

SEGB₁₂₂

SEGC₁₂₂

SEGA₁₂₃

SEGB₁₂₃

SEGC₁₂₃

SEGA₁₂₄

SEGB₁₂₄

SEGC₁₂₄

SEGA₁₂₅

SEGB₁₂₅

SEGC₁₂₅

SEGA₁₂₆

-5869.5

-5912.5

-5955.5

-5998.5

-6041.5

-6084.5

-6127.5

-6170.5

-6213.5

-6256.5

-6299.5

-6342.5

-6385.5

-6428.5

-6471.5

-6514.5

-6557.5

-6600.5

-6643.5

-6686.5

-6729.5

-6772.5

-6815.5

-6858.5

-6901.5

-6944.5

-6987.5

-7030.5

-7073.5

-7116.5

-7159.5

-7202.5

-7245.5

-7288.5

-7331.5

-7374.5

-7417.5

-7460.5

-7503.5

-7546.5

-7589.5

-7632.5

-7675.5

-7718.5

-7761.5

-7804.5

-7847.5

-7890.5

-7933.5

-7976.5

-8019.5

1085.0

715

716

717

718

719

720

721

722

723

724

725

726

727

728

729

730

731

732

733

734

735

736

737

738

739

740

741

742

743

744

745

746

747

748

749

750

751

752

753

754

755

756

757

758

759

760

761

762

763

764

765

SEGB₁₂₆

SEGC₁₂₆

SEGA₁₂₇

SEGB₁₂₇

SEGC₁₂₇

SEGSA₁

SEGSB₁

SEGSC₁

COM₆₄

COM₆₅

COM₆₆

COM₆₇

COM₆₈

COM₆₉

COM₇₀

COM₇₁

COM₇₂

COM₇₃

COM₇₄

COM₇₅

COM₇₆

COM₇₇

COM₇₈

COM₇₉

COM₈₀

COM₈₁

COM₈₂

COM₈₃

COM₈₄

COM₈₅

COM₈₆

COM₈₇

COM₈₈

COM₈₉

COM₉₀

COM₉₁

COM₉₂

COM₉₃

COM₉₄

COM₉₅

COM₉₆

COM₉₇

COM₉₈

COM₉₉

COM₁₀₀

COM₁₀₁

COM₁₀₂

COM₁₀₃

COM₁₀₄

COM₁₀₅

COM₁₀₆

-8062.5

-8105.5

-8148.5

-8191.5

-8234.5

-8277.5

-8320.5

-8363.5

-8406.5

-8449.5

-8492.5

-8535.5

-8578.5

-8621.5

-8664.5

-8707.5

-8750.5

-8793.5

-8836.5

-8879.5

-8922.5

-8965.5

-9008.5

-9051.5

-9094.5

-9137.5

-9180.5

-9223.5

-9266.5

-9309.5

-9352.5

-9395.5

-9438.5

-9481.5

-9524.5

-9567.5

-9610.5

-9653.5

-9696.5

-9739.5

-9782.5

-9825.5

-9868.5

-9911.5

-9954.5

-9997.5

-10040.5

-10083.5

-10126.5

-10169.5

-10212.5

1085.0

Ver.2004-01-06

- 12 -

NJU6824

ꢀ PAD COORDINATES 6

Chip Size : 22,070µm x 2,550µm (Center 0µm x 0µm )

No.

PAD NAME

X(um)

Y(um)

No.

817

PAD NAME

DMY₇₁

X(um)

Y(um)

No.

PAD NAME

X(um)

Y(um)

766

767

768

769

770

771

772

773

774

775

776

777

778

779

780

781

782

783

784

785

786

787

788

789

790

791

792

793

794

795

796

797

798

799

800

801

802

803

804

805

806

807

808

809

810

811

812

813

814

815

816

COM₁₀₇

COM₁₀₈

COM₁₀₉

COM₁₁₀

COM₁₁₁

COM₁₁₂

COM₁₁₃

DMY₄₁

DMY₄₂

DMY₄₃

DMY₄₄

DMY₄₅

DMY₄₆

COM₁₁₄

COM₁₁₅

COM₁₁₆

COM₁₁₇

COM₁₁₈

COM₁₁₉

COM₁₂₀

COM₁₂₁

COM₁₂₂

COM₁₂₃

COM₁₂₄

COM₁₂₅

COM₁₂₆

COM₁₂₇

DMY₄₇

DMY₄₈

DMY₄₉

DMY₅₀

DMY₅₁

DMY₅₂

DMY₅₃

DMY₅₄

DMY₅₅

DMY₅₆

DMY₅₇

DMY₅₈

DMY₅₉

DMY₆₀

DMY₆₁

DMY₆₂

DMY₆₃

DMY₆₄

DMY₆₅

DMY₆₆

DMY₆₇

DMY₆₈

DMY₆₉

DMY₇₀

-10255.5

-10298.5

-10341.5

-10384.5

-10427.5

-10470.5

-10513.5

-10556.5

-10599.5

-10642.5

-10845.0

1085.0

881.5

838.5

795.5

752.5

709.5

666.5

623.5

580.5

537.5

494.5

451.5

408.5

365.5

322.5

279.5

236.5

193.5

150.5

107.5

64.5

-10845.0

-881.5

21.5

-21.5

-64.5

-107.5

-150.5

-193.5

-236.5

-279.5

-322.5

-365.5

-408.5

-451.5

-494.5

-537.5

-580.5

-623.5

-666.5

-709.5

-752.5

-795.5

-838.5

Ver.2004-01-06

- 13 -

NJU6824

ꢀ BLOCK DIAGRAM

V_SSH

V_S

V_SSA

V_DDA

V_DD

Segment Driver

Common Driver

Shift Register

5

V_LCD, V₁-V₄

V_REF

Grayscale Control Circuit

Data Latch Circuit

Grayscale

Palette

(A/B/C)

V_BA

V_REG

Voltage

Converter

V₁A₁/V₁A₂

V₄A₁/V₄A₂

V_EE

C₁₊/C₁

C₂₊/C₂

C₃₊/C₃

C₄₊/C₄

C₅₊/C₅

Voltage

Booster

Display Data RAM

(DD RAM)

128x128x(4+4+4)bits

V_OUT

D₁₅

Column Address Decoder

Column Address Counter

Column Address Register

D₁₄

FR

D₁₃

RAM

Interface

Display

Timing

Generator

FLM

CL

D₁₂

D₁₁

D₁₀

D₉

CLK

OSC2

OSC1

D₈

Oscillator

D₇

D₆

D₅

D₄/SPOL

D₃/SMODE

D₂

Instruction

Decoder

Register Read

Control

Bus Holder

Internal Bus

N-line Control

D₁/SDA

D₀/SCL

MPU

CSb RS

RDb WR

P/S

SEL68 RESb

Ver.2004-01-06

- 14 -

NJU6824

ꢀ LCD POWER SUPPLY BLOCK DIAGRAM

Voltage Converter

LCD Bias Voltage Generator

+

V_BA

Reference Voltage Generator

Voltage Regulator

+

-

V_LCD

+

-

V₁

V_REG

V_REF

+

-

+

-

V₂

+

-

Gain

V₃

V₄

EVR

1/2 VREG

Control

(1x - 6x)

+

-

EVR Register

Boost Level Register

LCD Bias Adjustment

C₁₊

C_1-

C₂₊

C_2-

C₃₊

C_3-

C₄₊

C_4-

C₅₊

C_5-

Voltage Booster

V_EE

V_OUT

Ver.2004-01-06

- 15 -

NJU6824

ꢀ TERMINAL DESCRIPTION 1

No.

64~70

83~39

Terminal

V_DD

I/O

Function

Power Supply for Logic Circuits

GND for Logic Circuits

Power

V_SS

154~160

8,9

GND for High Voltage Circuits

V_SSH

V_DDAis internally connected to V_DDto fix SEL68 or P/S to “H” if necessary, and

cannot be used as main power supply.

28,29

92,93

100,101

4,5,

V_DDA

Power

• V_DDAshould be open if not used.

V_SSAis internally connected to V_SSto fix SEL68 or P/S to “L” if necessary, and

cannot be used as main GND.

12,13

46,47

96,97

104,105

V_SSA

Power

• V_SSAshould be open if not used.

LCD Bias Voltages

V_LCD

V₁

106~111

112~117

118~123

124~129

130~135

• When the internal LCD power supply is used, internal LCD bias voltages (V_LCD

and V₁-V₄) are activated by the “Power Control” instruction. Stabilizing capacitors

Power

are required between each bias voltage and V_SS.

V₂

• When the external LCD power supply is used, LCD bias voltages are externally

supplied on V_LCD, V₁, V₂, V₃and V₄individually, with the following relation

maintained: V_SSH<V₄<V₃<V₂<V₁<V_LCD

V₃

V₄

C₁₊

C₁-

C₂₊

C₂-

C₃₊

C₃-

C₄₊

C₄-

C₅₊

C₅-

V_BA

V_REF

175~180

181~186

Capacitor Connection for Voltage Booster

Power

187~192

193~198

199~204

205~210

211~216

217~222

223~228

229~234

148~153

142~147

Reference-Voltage Generator Output

Voltage Regulator Input

Voltage Booster Input

Power

168~174

V_EE

Power

•

V_EEis normally connected to V_DD.

Voltage Booster Output

161~167

136~141

V_OUT

Power

I

• Input if an external LCD power supply is used.

Voltage Regulator Output

V_REG

V₁A₁

V₁A₂

V₄A₁

V₄A₂

90,91

V₁Bias Voltage Adjustment

94,95

98,99

I

V₄Bias Voltage Adjustment

102,103

Reset

• Active “L”

MPU Mode Select

14,15

RESb

SEL86

MPU

H

L

6,7

SEL68

I

68-series

80-series

Ver.2004-01-06

- 16 -

NJU6824

ꢀ TERMINAL DESCRIPTION 2

No.

Terminal

I/O

Function

Parallel Interface

D₀

D₇to D₀: 8-bit Bi-directional Bus

I/O

30,31

/SCL

•

In the parallel interface mode (P/S=“H”), D₇-D₀are connected to 8-bit

bi-directional MPU bus.

D₁

32,33

36,37

38,39

I/O

/SDA

Serial Interface

SDA : Serial Data

SCL : Serial Clock

D₃

SMODE : 3-/4-line Serial Mode Select

SPOL : RS Polarity Select (3-line Serial Interface Mode)

/SMODE

• In the 3 or 4-line serial interface mode (P/S=“L”), D₀is assigned to SCL, and D₁

to SDA.

D₄

/SPOL

• In the 3-line serial interface mode, D₄is assigned to SPOL.

• Serial data on SDA is latched at the rising edge of SCL signal in order of D₇,

D₆,… and D₀, and then converted into 8-bit parallel data at the timing of the internal

signal produced from the 8^thSCL.

34,35

40,41

42,43

44,45

48,49

50,51

52,53

54,55

56,57

58,59

60,61

62,63

D₂

D₅

D₆

D₇

• SCL should be set to “L” right after data transmission or during non-access.

D₈

D₉

8-bit Bi-directional Bus

D₁₀

D₁₁

D₁₂

D₁₃

D₁₄

D₁₅

• In the 16-bit bus length mode, D₁₅-D₈are assigned to upper 8-bit data bus.

• In the serial interface mode or the 8-bit parallel interface mode, D₁₅-D₈should be

fixed to “H” or “L”.

I/O

Chip Select

17,18

CSb

I

• Active “L”

Register Select

• This signal interprets transferred data as display data or instruction.

20,21

RS

H

L

Data

Instruction

Display Data

80-series MPU Interface (P/S=“H”, SEL68=“L”)

Data Read (RDb) Signal

• Active “L”

26,27

23,24

RDb (E)

I

68-series MPU Interface (P/S=“H”, SEL68=“H”)

Enable Signal

• Active “H”

80-series MPU Interface (P/S=“H”, SEL68=“L”)

Data Write (WRb) Signal

• Active “L”

68-series MPU Interface (P/S=“H”, SEL68=“H”)

Data Read or Write (R/W) Signal

WRb (R/W)

R/W

Status

H

Read

L

Write

Ver.2004-01-06

- 17 -

NJU6824

ꢀ TERMINAL DESCRIPTION 3

No.

Terminal

I/O

Function

Parallel/Serial Interface Mode Select

Chip

Select

CSb

Display /

Instruction

RS

Read

/Write

RDb, WRb

Write Only

Serial

Clock

-

P/S

Data

10,11

P/S

I

H

L

D₀~ D₇

SDA (D₁)

CSb

RS

SCL (D₀)

• In the serial interface mode (P/S=“L”), RDb, WRb, D₂and D₅-D₁₅should be fixed

to “H” or “L”,.

Line Clock

71,72

73,74

75,76

77,78

CL

FLM

FR

O

• CL is normally open.

First Line Maker

• FLM is normally open.

Frame Rate

• FR is normally open.

Clock Output

CLK

• CLK is normally open.

OSC

• When the internal oscillator is used, fix OSC1 to “H” or “L” and leave OSC2 open.

79,80

81,82

OSC1

OSC2

I

To attain more accurate frequency, connect OSC1 and OSC2 with an external

O

resistor.

• When the internal oscillator is not used, input external clock to OSC1 and leave

OSC2 open.

Segment Drivers

REV Register

Normal

OFF

0

1

ON

1

0

Reverse

SEGA₀

• Segment drivers output the following voltage levels.

B/W Mode (Example)

~SEGA₁₂₇

SEGB₀

336~719

~SEGB₁₂₇

O

FR Signal

SEGB₀

~SEGB₁₂₇

Display Data

Reverse Display OFF

V₂

V_LCD

V₂

V₃

V_SSH

V₃

(Normal)

Reverse Display ON

V_LCD

333

720

334

721

335

722

SEGSA₀

SEGSA₁

SEGSB₀

SEGSB₁

SEGSC₀

SEGSC₁

Icon Segment Drivers

O

• SEGSA₀~SEGSC₁are used for icon display.

Common Drivers

• Common drivers output the following voltage levels.

263~276

283~332

723~772

779~792

Data

H

L

H

L

FR

H

L

Output Levels

COM₀~

COM₁₂₇

V_SSH

V₁

V_LCD

V₄

L

NOTE) DUMMY PADs: No. 1~3, 16, 19, 22, 25, 235~262, 277~282, 773~778, 793~817

Ver.2004-01-06

- 18 -

NJU6824

ꢀ FUNCTIONAL DESCRIPTION

(1) MPU INTERFACE

(1-1) Selection of Parallel/Serial Interface Mode

The P/S selects a parallel or a serial interface mode, as shown in Table 1. In the serial interface mode, neither

display data in the DDRAM nor instruction data in the registers can be read out.

Table 1 Selection of Parallel/Serial Interface Mode

P/S

H

I/F Mode

Parallel I/F

Serial I/F

CSb

RS

RDb

-

WRb

-

SEL68

-

SDA

SCL

Data

D₇-D₀(D₁₅-D₀)

-

L

NOTE) “ -” : Fix to “H” or “L”.

(1-2) Selection of MPU Mode

In the parallel interface mode, the SEL68 selects 68 or 80-series MPU mode, as shown in Table 2.

Table 2 Selection of MPU Mode

SEL68

MPU Mode

68-series MPU

80-series MPU

CSb

RS

RDb

E

WRb

R/W

Data

D₇-D₀(D₁₅-D₀)

H

L

RDb

WRb

(1-3) Data Recognition

In the parallel interface mode, the data from MPU is interpreted as display data or instruction according to the

combination of the RS, RDb and WRb (R/W) signals, as shown in Table 3.

Table 3 Data Recognition (Parallel Interface Mode)

68-series

80-series

RS

Function

R/W

H

RDb

L

WRb

H

L

H

Read Instruction

L

H

L

Write Instruction

Read Display Data

Write Display Data

H

L

H

L

H

(1-4) Selection of 3-/4-line Serial Interface Mode

In the serial interface mode, the SMODE selects 3- or 4-line serial interface mode, as shown in Table 4.

Table 4 Selection of 3-/4-line Serial Interface Mode

SMODE

Serial Interface Mode

H

L

3-line

4-line

(1-5) 4-line Serial Interface Mode

While the chip select is active (CSb=“L”), the SDA and SCL are enabled. While the chip select is inactive

(CSb=“H”), the SDA and SCL are disabled, and the internal shift register and the internal counter are being initialized.

8-bit serial data on the SDA is latched at the rising edge of the SCL signal in order of D₇, D₆,…, and D₀, and converted

into 8-bit parallel data at the timing of the internal signal produced from the 8^thSCL signal. The data on the SDA is

interpreted as display data or instruction according to the RS.

Ver.2004-01-06

- 19 -

NJU6824

Table 5 Data Recognition (4-line Serial Interface)

RS

H

Data Recognition

Instruction

L

Display Data

Note that the SCL should be set to “L” right after data transmission or during non-access because the serial interface

is susceptible to external noises which may cause malfunctions. For added safety, inactivate the chip-select (CSb=“H”)

temporary whenever 8-bit data transmission is completed. Fig 1 illustrates the interface timing of the 4-line serial

interface mode.

CSb

RS

VALID

D₀

SDA

D₇

D₆

D₅

D₄

D₃

D₂

D₁

SCL

1

2

3

4

5

6

7

8

Fig 1 4-line Serial Interface Timing

(1-6) 3-line Serial Interface Mode

While the chip select is active (CSb=“L”), the SDA and SCL are enabled. While the chip select is not active

(CSb=“H”), the SDA and SCL are disabled, and the internal shift register and the internal counter are being initialized.

9-bit serial data on the SDA is latched at the rising edge of the SCL signal in order of RS, D₇, D₆,…, and D₀, and then

converted into 9-bit parallel data at the timing of the internal signal produced from the 9^thSCL signal. The data on the

SDA is interpreted as display data or instruction according to the combination of the RS bit and the SPOL status, as

follows.

Table 6 Data Recognition (3-line Serial Interface)

SPOL=L

SPOL=H

Data Recognition

Instruction

RS

0

Data Recognition

Display Data

Instruction

RS

0

1

Display Data

Note that the SCL should be set to “L” right after data transmission or during non-access because the serial interface

is susceptible to external noises which may cause malfunctions. For added safety, inactivate the chip-select (CSb=“H”)

temporary whenever 9-bit data transmission is completed. Fig 2 illustrates the interface timing of the 3-line serial

interface mode.

CSb

SDA

SCL

RS

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

1

2

3

4

5

6

7

8

9

Fig 2 3-line Serial Interface Timing

Ver.2004-01-06

- 20 -

NJU6824

(1-7) Accessing DDRAM

While the chip select is active (CSb=“L”), the data from MPU can be written into the DDRAM or the instruction

register. When the RS is “L”, the data is interpreted as display data which is stored in the DDRAM. The display data is

latched at the rising edge of the WRb signal in the 80-series MPU mode, or at the falling edge of the E signal in the

68-series MPU mode.

Table 7 Data Recognition

RS

L

Data Recognition

Display Data

Instruction

H

In the DDRAM read sequence, be sure to execute a dummy read right after setting an address or right after writing

display data or instruction. The data from MPU is temporarily held in the internal bus-holder, then released on the

internal data-bus, therefore a dummy data is read out by the 1^st“Display Data Read” instruction. After that, the display

data is read out from a specified address by the 2^ndinstruction. Note that the “Display Data Read” instruction cannot be

used in the serial interface mode.

Display Data Write Operation

n

n+1

n+2

n+3

n+4

D₀to D₁₅

WRb

Bus Holder

WRb

n

n+1

n+2

n+3

n+4

Display Data Read Operation

WRb

D₀to D₇(D₀to D₁₅)

n

n+1

n+2

Address Set

n

Dummy

Read

Data Read

n Address

Data Read

n+1 Address

n+2 Address

RDb

Fig 3 Internal-signal Timing of Display Data Read/Write Operations

NOTE) In 16-bit bus length mode, instruction is transmitted to/from instruction register in 16 bits, as well as display data.

Ver.2004-01-06

- 21 -

NJU6824

(1-8) Accessing Instruction Register

Each instruction register has a specific address in between (0H) and (FH), and instruction data is read out from the

register by the “Register Address” and ”Register Read” instructions. For more information, refer to “(15-23) Register

Address” and “(15-24) Register Read”.

WRb

M

m

N

n

D₀to D₇

Register Address

Register Read

Register Address

Register Read

RDb

Fig 4 Access Timing of Instruction Register

(1-9) Selection of 8-/16-bit Bus Length (Parallel Interface Mode)

Either 8- or 16-bit bus length is selected by the D₀(WLS) bit of the “Bus Length” instruction. In the 16-bit bus

length mode, instruction as well as display data is transmitted to/from the instruction registers in 16 bits (D₁₅to D₀).

However, only lower 8 bits (D₇to D₀) are valid for instruction register access. And only 12 bits are actually stored in the

DDRAM, even though entire 16 bits (D₁₅to D₀) are transmitted for DDRAM access. For more information, refer to

“(4-4) Bit Assignment of Display Data”.

Table 8 Selection of 8-/16-bit Bus Length Mode

WLS

L

Bus Length Mode

8-bit Bus Length

16-bit Bus Length

H

(2) INITIAL DISPLAY LINE REGISTER

The address data in the initial display line register specifies the row address, which corresponds to an initial COM

and is normally positioned on top of a screen in full display. The initial COM is the start position of common scanning,

which is specified by the “Initial COM” instruction.

The row address, which is established in the initial display line register, is preset into the line counter whenever the

FLM becomes “H”. At the rising edge of the CL signal, the line counter is counted-up, then 384-bit display data is

latched into the data latch circuit. At the falling edge of the CL signal, the latch data is released to the grayscale control

circuit to decide a grayscale level, then the segment drivers Ai, Bi and Ci (i=0 to 127) generate LCD waveforms.

(3) COLUMN AND ROW ADDRESS COUNTERS

The column and row address counters designate a column address and a row address respectively for DDRAM

access, but they are completely independent from the line counter. The line counter provides a line address which is

synchronized with display control timings such as the FLM and the CL.

Ver.2004-01-06

- 22 -

NJU6824

(4) DDRAM

(4-1) DDRAM Address Range

The DDRAM is capable of 128 bits for row address and 1,536 bits (12-bit

x

128-segment) for column address. The

range of the column address is from (00H) to (7FH), and the row address is from (00H) to (7FH). Setting outside these

ranges is not allowed, otherwise it may cause malfunctions. For DDRAM access, two data transmissions are needed for 1

RGB-pixel in the 8-bit bus length mode, and one transmission in the 16-bit bus length mode.

8-bit Bus Length

Column Address

00H

7FH

00H

7bit

5bit

7bit

5bit

Row Address

7FH

00H

7bit

4bit

5bit

8bit

7bit

4bit

5bit

8bit

Column Address

ABS=’1’

Row Address

7FH

00H

4bit

8bit

4bit

8bit

C256=’1’

00H

8bit

1H

7EH

8bit

7FH

8bit

Row Address

7FH

8bit

Fig 5 Range of Column Address in 8-bit Bus Length

16-bit Bus Length

Column Address

00H

7FH

00H

7FH

12bit

Row Address

12bit

Fig 6 Range of Column Address in 16-bit Bus Length

Ver.2004-01-06

- 23 -

NJU6824

(4-2) Window Area for DDRAM Access

Be sure to set up window area prior to DDRAM access. This area is set by the “Increment/Decrement Control”

instruction and the designation of the start point and the end point.

By the “Increment/Decrement Control”, either auto-increment or -decrement is set for column address and row

address individually. Once this mode is set up, the column address, row address or both are automatically counted up or

down, whenever the DDRAM is accessed. And, the start point is specified by the “Window Start Column Address” and

“Window Start Row Address” instructions, and the end point by the “Window End Column Address” and ”Window End

Row Address” instructions. For more information, refer to “(15-9) Increment/Decrement Control”, “(15-25) Window

End Column Address” and “(15-26)Window End Row Address”. The typical sequence of the window area setting is

listed below.

1. Set D₂(HV), D₁(XD) and D₀(YD) of “Increment/Decrement Control” instruction.

2. Set start point by “Window Start Column Address” and “Window Start Row Address” instructions.

3. Set end point by “Window End Column Address” and “Window End Row Address” instructions.

4. Window area is set up, and DDRAM can be accessed.

NOTE) The order of address setting is column address first, then row address.

Column Address

Start Point

(AX, AY)

Window Area

End Point

(EX, EY)

Whole DDRAM Area

Fig 7 Window Area

NOTE1) The following relation should be maintained to avoid malfunctions.

- AX (Window Start Column Address) < EX (Window End Column Address) < Maximum Column Address

- AY (Window Start Row Address) < EY (Window End Row Address) < Maximum Row Address

NOTE2) The display-rotation function or the mirror-inversion function is enabled by this setting. Refer to “(4-3) DDRAM Access

Direction”.

NOTE3)A read-modify-write operation is enabled by setting “1” at the D3 (AIM) of the “Increment/Decrement Control” instruction.

Refer to the description about “AIM” bit in “(15-9) Increment/Decrement Control”.

Ver.2004-01-06

- 24 -

NJU6824

(4-3) DDRAM Access Direction (Display-rotation and Mirror-inversion Functions)

The access direction of the DDRAM is selected out of eight options by setting the D₂(HV), D₁(XD) and D₀(YD)

bits of the “Increment/Decrement Control” instruction. This function allows the display data to be rotated 90, 180 or 270

degrees or mirror-inversed while being written onto the DDRAM. The following table shows the correspondences

between instruction setting and on-screen image.

DDRAM Access Direction

(AX, AY)

On-screen Image

Valid Address

AX < EX

No. HV XD YD

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

AY < EY

AX < EX

AY > EY

AX > EX

AY < EY

AX > EX

AY > EY

AX < EX

AY < EY

AX < EX

AY > EY

AX > EX

AY < EY

AX >EX

AY > EY

(EX, EY)

(AX, AY)

(EX, EY)

(AX, AY)

(EX, EY)

(AX, AY)

(EX, EY)

(AX, AY)

Fig 8 Display-rotation Function and Mirror-inverse Function

NOTE1) The same display data is used for each option’s on-screen image. Only difference is “HV”, “XD” and “YD” bits setting.

NOTE2) The following relation must be maintained to avoid malfunctions.

AX (Window Start Column Address) < EX (Window End Column Address) < Maximum Column Address

AY (Window Start Row Address) < EY (Window End Row Address) < Maximum Row Address

Ver.2004-01-06

- 25 -

NJU6824

(4-4) Bit Assignment of Display Data

(4-4-1) Bit Assignment Overview

These maps is used for grasping general outlines of the variations in the bit assignment of display data.

C256

ABS

C256

ABS

WLS

Mode

WLS

Mode

SWAP

8bit

16bit

8bit

Ver.2004-01-06

- 26 -

NJU6824

(4-4-2) Bit Assignment in Variable 16-grayscale Mode (DDRAM)

16-bit Bus Length (MON=0, PWM=0, C256=0, WLS=1)

ABS

0

SWAP

0

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGA₀

Palette B

SEGB₀

Palette C

SEGC₀

Palette A

SEGA₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGC₁₂₇

←→

ABS

0

SWAP

1

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGC₀

Palette B

SEGB₀

Palette C

SEGA₀

Palette A

SEGC₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGA₁₂₇

←→

ABS

1

SWAP

0

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGA₀

Palette B

SEGB₀

Palette C

SEGC₀

Palette A

SEGA₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGC₁₂₇

←→

ABS

1

SWAP

1

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGC₀

Palette B

SEGB₀

Palette C

SEGA₀

Palette A

SEGC₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGA₁₂₇

←→

Ver.2004-01-06

- 27 -

NJU6824

8-bit Bus Length

(MON=0, PWM=0, C256=0, WLS=0)

ABS

0

SWAP

0

Column Address / Display Data / Segment Driver

X=00H(Upper)

X=00H(Lower)

X=7FH(Upper)

X=7FH(Lower)

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGA₀

Palette B

SEGB₀

Palette C

SEGC₀

Palette A

SEGA₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGC₁₂₇

←→

ABS

0

SWAP

1

Column Address / Display Data / Segment Driver

X=00H(Upper)

X=00H(Lower)

X=7FH(Upper)

X=7FH(Lower)

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGC₀

Palette B

SEGB₀

Palette C

SEGA₀

Palette A

SEGC₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGA₁₂₇

←→

ABS

1

SWAP

0

Column Address / Display Data / Segment Driver

X=7FH

X=00H

X=00H(Lower)

X=7FH(Lower)

←→

(Upper)

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGA₀

Palette B

SEGB₀

Palette C

SEGC₀

Palette A

SEGA₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGC₁₂₇

←→

ABS

1

SWAP

1

Column Address / Display Data / Segment Driver

X=7FH

X=00H

X=00H(Lower)

X=7FH(Lower)

←→

(Upper)

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGC₀

Palette B

SEGB₀

Palette C

SEGA₀

Palette A

SEGC₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGA₁₂₇

←→

Ver.2004-01-06

- 28 -

NJU6824

(4-4-3) Bit Assignment in variable 8-grayscale Mode (DDRAM)

8-bit Bus Length

(MON=0, PWM=0, C256=1, WLS=0)

ABS

*

SWAP

0

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGA₀

Palette B

SEGB₀

Palette C

SEGC₀

Palette A

SEGA₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGC₁₂₇

←→

ABS

*

SWAP

1

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGC₀

Palette B

SEGB₀

Palette C

SEGA₀

Palette A

SEGC₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGA₁₂₇

←→

Ver.2004-01-06

- 29 -

NJU6824

(4-4-4) Bit Assignment in Fixed 8-grayscale Mode (DDRAM)

16-bit Bus Length (MON=0, PWM=1, C256=0, WLS=1)

ABS

0

SWAP

0

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGA₀

Palette B

SEGB₀

Palette C

SEGC₀

Palette A

SEGA₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGC₁₂₇

←→

ABS

0

SWAP

1

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGC₀

Palette B

SEGB₀

Palette C

SEGA₀

Palette A

SEGC₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGA₁₂₇

←→

NOTE) The data indicated with a slash mark ( / ) are invalid.

ABS

1

SWAP

0

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGA₀

Palette B

SEGB₀

Palette C

SEGC₀

Palette A

SEGA₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGC₁₂₇

←→

ABS

1

SWAP

1

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGC₀

Palette B

SEGB₀

Palette C

SEGA₀

Palette A

SEGC₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGA₁₂₇

←→

NOTE) The data indicated with a slash mark ( / ) is invalid.

Ver.2004-01-06

- 30 -

NJU6824

8-bit Bus Length

(MON=0, PWM=1, C256=0, WLS=0)

ABS

0

SWAP

0

Column Address / Display Data / Segment Driver

X=00H(Upper)

X=00H(Lower)

X=7FH Upper)

X=7FH(Lower)

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGA₀

Palette B

SEGB₀

Palette C

SEGC₀

Palette A

SEGA₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGC₁₂₇

←→

ABS

0

SWAP

1

Column Address / Display Data / Segment Driver

X=00H(Upper)

X=00H(Lower)

X=7FH(Upper)

X=7FH(Lower)

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGC₀

Palette B

SEGB₀

Palette C

SEGA₀

Palette A

SEGC₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGA₁₂₇

←→

NOTE) The data indicated with a slash mark ( / ) is invalid.

ABS

1

SWAP

0

Column Address / Display Data / Segment Driver

X=7FH

X=00H

X=00H(Lower)

X=7FH(Lower)

←→

(Upper)

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGA₀

Palette B

SEGB₀

Palette C

SEGC₀

Palette A

SEGA₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGC₁₂₇

←→

ABS

1

SWAP

1

Column Address / Display Data / Segment Driver

X=7FH

X=00H

X=00H(Lower)

X=7FH(Lower)

←→

(Upper)

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGC₀

Palette B

SEGB₀

Palette C

SEGA₀

Palette A

SEGC₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGA₁₂₇

←→

NOTE) The data indicated with a slash mark ( / ) is invalid.

8-bit Bus Length

(MON=0, PWM=1, C256=1, WLS=0)

ABS

*

SWAP

0

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGA₀

Palette B

SEGB₀

Palette C

SEGC₀

Palette A

SEGA₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGC₁₂₇

←→

ABS

*

SWAP

1

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGC₀

Palette B

SEGB₀

Palette C

SEGA₀

Palette A

SEGC₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGA₁₂₇

←→

Ver.2004-01-06

- 31 -

NJU6824

(4-4-5) Bit Assignment in B&W Mode (DDRAM)

16-bit Bus Length (MON=1, PWM=*, C256=0, WLS=1)

ABS

0

SWAP

0

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGA₀

Palette B

SEGB₀

Palette C

SEGC₀

Palette A

SEGA₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGC₁₂₇

←→

ABS

0

SWAP

1

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGC₀

Palette B

SEGB₀

Palette C

SEGA₀

Palette A

SEGC₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGA₁₂₇

←→

ABS

1

SWAP

0

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGA₀

Palette B

SEGB₀

Palette C

SEGC₀

Palette A

SEGA₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGC₁₂₇

←→

ABS

1

SWAP

1

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGC₀

Palette B

SEGB₀

Palette C

SEGA₀

Palette A

SEGC₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGA₁₂₇

←→

NOTE) The data indicated with a slash mark ( / ) is invalid, and only MSB bits are effective.

Ver.2004-01-06

- 32 -

NJU6824

8-bit Bus Length

(MON=1, PWM=*, C256=0, WLS=0)

ABS

0

SWAP

0

Column Address / Display Data / Segment Driver

X=00H(Upper)

X=00H(Lower)

X=7FH(Upper)

X=7FH(Lower)

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGA₀

Palette B

SEGB₀

Palette C

SEGC₀

Palette A

SEGA₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGC₁₂₇

←→

ABS

0

SWAP

1

Column Address / Display Data / Segment Driver

X=00H(Upper)

X=00H(Lower)

X=7FH(Upper)

X=7FH(Lower)

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGC₀

Palette B

SEGB₀

Palette C

SEGA₀

Palette A

SEGC₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGA₁₂₇

←→

ABS

1

SWAP

0

Column Address / Display Data / Segment Driver

X=7FH

X=00H

X=00H(Lower)

X=7FH(Lower)

←→

(Upper)

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGA₀

Palette B

SEGB₀

Palette C

SEGC₀

Palette A

SEGA₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGC₁₂₇

←→

ABS

1

SWAP

1

Column Address / Display Data / Segment Driver

X=7FH

X=00H

X=00H(Lower)

X=7FH(Lower)

←→

(Upper)

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGC₀

Palette B

SEGB₀

Palette C

SEGA₀

Palette A

SEGC₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGA₁₂₇

←→

NOTE) The data indicated with a slash mark ( / ) is invalid, and only MSB bits are effective.

8-bit Bus Length

(MON=1, PWM=*, C256=1, WLS=0)

ABS

*

SWAP

0

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGA₀

Palette B

SEGB₀

Palette C

SEGC₀

Palette A

SEGA₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGC₁₂₇

←→

ABS

*

SWAP

1

Column Address / Display Data / Segment Driver

X=00H

X=7FH

←→

Display Data in DDRAM

←→

Grayscale Palette

Segment Driver

Palette A

SEGC₀

Palette B

SEGB₀

Palette C

SEGA₀

Palette A

SEGC₁₂₇

Palette B

SEGB₁₂₇

Palette C

SEGA₁₂₇

←→

NOTE) The data indicated with a slash mark ( / ) is invalid, and only MSB bits are effective.

Ver.2004-01-06

- 33 -

NJU6824

(4-4-6) Write Data and Read Data

16-bit Bus Length

ABS=0

Write Data

D₁₅

↓

D₁₄

D₁₃

D₁₂

D₁₁

*

D₁₀

D₉

D₈

D₇

D₆

*

D₅

*

D₄

D₃

D₂

D₁

D₀

↓

Read Data

D₁₅

*

ABS=1

Write Data

Read Data

D₁₅

↓

D₁₄

*

D₁₃

*

D₁₂

*

D₁₁

D₁₀

D₉

D₈

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

↓

*

D₀

8-bit Bus Length

ABS=0, C256=0 (Upper byte)

Write Data

Read Data

D₇

↓

D₆

D₅

D₄

D₃

D₂

D₁

D₀

↓

D₇

D₆

D₅

D₄

*

D₀

ABS=0, C256=0 (Lower byte)

Write Data

Read Data

D₇

↓

D₆

D₅

D₄

D₃

D₂

D₁

D₀

↓

D₇

*

D₄

D₃

*

ABS=1, C256=0 (Upper byte)

Write Data

Read Data

D₇

↓

D₆

D₅

D₄

D₃

D₂

D₁

D₀

↓

*

D₃

D₀

ABS=1, C256=0 (Lower byte)

Write Data

Read Data

D₇

↓

D₆

D₅

D₄

D₃

D₂

D₁

D₀

↓

D₇

D₆

D₅

D₄

D₃

D₀

ABS=0, C256=1

Write Data

Read Data

D₇

↓

D₆

D₅

D₄

D₃

D₂

D₁

D₀

↓

D₇

D₆

D₅

D₀

NOTE) * : Invalid Data

Ver.2004-01-06

- 34 -

NJU6824

(5) GRAYSCALE CONTROL CIRCUIT

(5-1) Display Mode Selection

A display mode is selected by the combination of the D₂(MON) bit of the “Display Control (1)” instruction and the

D₃(PWM) and D₂(C256) bits of the “Display Mode Control” instruction, as shown below.

Table 11 Display Mode Selection

C256

Oscillation

(NOTE2)

MON

PWM

Display Mode

Bus Length

(WLS=0/1)

(NOTE1)

0

1

0

1

0

1

Variable 16-grayscale Mode

Variable 8-grayscale Mode

4096 Colors

256 Colors

8-/16-bit

8-bit

0

1

*

f_OSC1

f_OSC2

f_OSC3

(WLS=0)

(WLS=0/1)

(WLS=0)

(WLS=0/1)

(WLS=0)

0

1

8-/16-bit

8-bit

Fixed 8-grayscale Mode

256 Colors

8-/16-bit

8-bit

B&W Mode

Black & White

NOTE1) In the variable grayscale mode, “C256” bit selects either 16-grayscale (4K colors) or 8-grayscale (256 colors). When

C256=”0” (16-grayscale), all 12 bits are assigned to 1 RGB-pixel. When C256=”1” (8-grayscale), only 8 bits are

assigned and the 8-bit bus length should be used. In the fixed 8-grayscale mode or the B&W mode, the “C256” bit is

usually “1”. For more information how the display data is assigned, refer to “(4-4) Bit Assignment of Display Data”.

NOTE2)Oscillation frequency is decided according to the display mode, and is fine-tuned by the “Frequency Control” Instruction.

Refer to “(11) OSCILLATOR” and “OSCILLATION FREQUENCY AND FRAME FREQUENCY”.

(5-1-1) Variable 16-grayscale Mode

In this mode, each of the palettes Aj, Bj and Cj (j=0-15) is capable of selecting 16 from 32 grayscales (0/31-31/31)

by setting palette data in the grayscale palette. Then, each of the segment drivers SEGAi, SEGBi and SEGCi (i=0 to 127)

generates 16 grayscales to achieve 4,096 colors. Refer to Table 12-1 and Table 12-2.

(5-1-2) Variable 8-grayscale Mode

Each of the palettes Aj, Bj and Cj (j=0-15) is capable of selecting 8 from 32 grayscales (0/31-31/31). 2 segment

drivers of 1 RGB-group (SEGAi, SEGBi and SEGCi (i=0 to 127)) generate 8 grayscales, and the other driver does 4

grayscales to achieve 256 colors. Refer to Table 13-1 through Table 13-4. The 8-bit bus length is usually used in this

mode.

(5-1-3) Fixed 8-grayscale Mode

The palette setting is not necessary, because the palettes Aj, Bj and Cj (j=0-15) are always fixed at 4 or 8 grayscales

between 0/7 and 7/7. 2 segment drivers of 1 RGB-group (SEGAi, SEGBi and SEGCi (i=0 to 127)) are fixed at 8

grayscales, and the other driver is 4 grayscales, then results in 256 colors. Refer to Table 14-1 and Table 14-2.

(5-1-4) B&W Mode

The palette setting is not necessary, where the only MSB bits of display data are valid. Refer to Table 15.

Ver.2004-01-06

- 35 -

NJU6824

(6) GRAYSCALE PALETTE

(6-1) Grayscale Selection in Variable 16-grayscale Mode

Table 12-1 Grayscale selection

Table 12-2 Grayscale Palette

( Palette Aj, Bj, and Cj )

Display Data

Palette Name

MSB----LSB

Palette Data

MSB---LSB

Grayscale

Default Setting

Grayscale

Default Setting

MSB---LSB

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Palette A0/B0/C0

Palette A1/B1/C1

Palette A2/B2/C2

Palette A3/B3/C3

Palette A4/B4/C4

Palette A5/B5/C5

Palette A6/B6/C6

Palette A7/B7/C7

Palette A8/B8/C8

Palette A9/B9/C9

Palette A10/B10/C10

Palette A11/B11/C11

Palette A12/B12/C12

Palette A13/B13/C13

Palette A14/B14/C14

Palette A15/B15/C15

0 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 0

0 0 1 0 1

0 0 1 1 0

0 0 1 1 1

0 1 0 0 0

0 1 0 0 1

0 1 0 1 0

0 1 0 1 1

0 1 1 0 0

0 1 1 0 1

0 1 1 1 0

0 1 1 1 1

0

Palette A0/B0/C0

1 0 0 0 0

1 0 0 0 1

1 0 0 1 0

1 0 0 1 1

1 0 1 0 0

1 0 1 0 1

1 0 1 1 0

1 0 1 1 1

1 1 0 0 0

1 1 0 0 1

1 1 0 1 0

1 1 0 1 1

1 1 1 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

16/31

17/31

18/31

19/31

20/31

21/31

22/31

23/31

24/31

25/31

26/31

27/31

28/31

29/31

30/31

31/31

1/31

2/31

3/31

4/31

5/31

6/31

7/31

8/31

9/31

10/31

11/31

12/31

13/31

14/31

15/31

Palette A8/B8/C8

Palette A1/B1/C1

Palette A2/B2/C2

Palette A3/B3/C3

Palette A4/B4/C4

Palette A5/B5/C5

Palette A6/B6/C6

Palette A7/B7/C7

Palette A9/B9/C9

Palette A10/B10/C10

Palette A11/B11/C11

Palette A12/B12/C12

Palette A13/B13/C13

Palette A14/B14/C14

Palette A15/B15/C15

NOTE1) “MON=0”, “PWM=0”, “C256=0”

NOTE2) Applied to palette Aj, Bj and Cj (j=0 to 15)

Ver.2004-01-06

- 36 -

NJU6824

(6-2) Grayscale Selection in Variable 8-grayscale Mode

Table 13-1 Grayscale selection

Table 13-2 Grayscale Palette

( Palette Aj and Bj )

Display Data

Palette Name

MSB----LSB

Palette Data

MSB---LSB

Grayscale

Default Setting

Grayscale

Default Setting

MSB---LSB

0 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 0

0 0 1 0 1

0 0 1 1 0

0 0 1 1 1

0 1 0 0 0

0 1 0 0 1

0 1 0 1 0

0 1 0 1 1

0 1 1 0 0

0 1 1 0 1

0 1 1 1 0

0 1 1 1 1

0

1 0 0 0 0

1 0 0 0 1

1 0 0 1 0

1 0 0 1 1

1 0 1 0 0

1 0 1 0 1

1 0 1 1 0

1 0 1 1 1

1 1 0 0 0

1 1 0 0 1

1 1 0 1 0

1 1 0 1 1

1 1 1 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

16/31

17/31

18/31

19/31

20/31

21/31

22/31

23/31

24/31

25/31

26/31

27/31

28/31

29/31

30/31

31/31

0 0 0 *

0 0 1 *

0 1 0 *

0 1 1 *

1 0 0 *

1 0 1 *

1 1 0 *

1 1 1 *

Palette A1/B1/C1

Palette A3/B3/C3

Palette A5/B5/C5

Palette A7/B7/C7

Palette A9/B9/C9

Palette A11/B11/C11

Palette A13/B13/C13

Palette A15/B15/C15

1/31

2/31

3/31

4/31

5/31

6/31

7/31

8/31

9/31

10/31

11/31

12/31

13/31

14/31

15/31

Palette A1/B1/C1

Palette A3/B3/C3

Palette A5/B5/C5

Palette A7/B7/C7

Palette A9/B9/C9

Palette A11/B11/C11

Palette A13/B13/C13

Palette A15/B15/C15

NOTE1) “MON=0”, “PWM=0”, “C256=1”.

NOTE2) Applied to palette Aj and Bj (j=0 to 15)

NOTE3) Palette 0, 2, 4, 6, 8, 10, 12 and 14 are disabled.

Table 13-3 Grayscale selection

Table 13-4 Grayscale Palette

( Palette Cj )

Display Data

Palette Name

MSB----LSB

Palette Data

MSB---LSB

Grayscale

Default Setting

Grayscale

Default Setting

MSB---LSB

0 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 0

0 0 1 0 1

0 0 1 1 0

0 0 1 1 1

0 1 0 0 0

0 1 0 0 1

0 1 0 1 0

0 1 0 1 1

0 1 1 0 0

0 1 1 0 1

0 1 1 1 0

0 1 1 1 1

0

1 0 0 0 0

1 0 0 0 1

1 0 0 1 0

1 0 0 1 1

1 0 1 0 0

1 0 1 0 1

1 0 1 1 0

1 0 1 1 1

1 1 0 0 0

1 1 0 0 1

1 1 0 1 0

1 1 0 1 1

1 1 1 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

16/31

17/31

18/31

19/31

20/31

21/31

22/31

23/31

24/31

25/31

26/31

27/31

28/31

29/31

30/31

31/31

1/31

2/31

3/31

4/31

5/31

6/31

7/31

8/31

9/31

10/31

11/31

12/31

13/31

14/31

15/31

0 0 * *

0 1 * *

1 0 * *

1 1 * *

Palette A3/B3/C3

Palette A7/B7/C7

Palette A3/B3/C3

Palette A7/B7/C7

Palette A11/B11/C11

Palette A15/B15/C15

Palette A11/B11/C11

Palette A15/B15/C15

NOTE1) “MON=0”, “PWM=0”, “C256=1”

NOTE2) Applied to palette Cj (j=0 to 15)

NOTE3) Palette 0, 1, 2, 4, 5, 6, 8, 9, 10, 12, 13 and 14 are disabled.

Ver.2004-01-06

- 37 -

NJU6824

(6-3) Grayscale Selection in Fixed 8-grayscale Mode

Table 14-1 Grayscale Selection

Table 14-2 Grayscale Palette

( Palette Aj and Bj )

( Palette Cj )

Display Data

Grayscale

0/7

MSB- - - -LSB

0 0 0 *

0 0 1 *

0 1 0 *

0 1 1 *

1 0 0 *

1 0 1 *

1 1 0 *

1 1 1 *

0/7

1/7

2/7

3/7

4/7

5/7

6/7

7/7

0 0 * *

0 1 * *

1 0 * *

1 1 * *

3/7

5/7

7/7

NOTE1) “MON=0”, “PWM=1”, “C256=0 or 1”

(6-4) Grayscale Selection in B&W Mode

Table 15 Grayscale Selection

Display Data

Grayscale

MSB- - - -LSB

0 * * *

1 * * *

0

1

NOTE1) “MON=1”, “PWM=0 or 1” and “C256=0 or 1”

Ver.2004-01-06

- 38 -

NJU6824

(7) DISPLAY TIMING GENERATOR

The display timing generator generates timing clocks such as the CL (Line Clock), FR (Frame Rate) and FLM (First

Line Maker) by dividing an oscillation frequency. These clocks are used inside the LSI, and are activated by setting “1”

at the D₀(SON) bit of the “Duty-1 /Display Clock ON/OFF” instruction.

The CL is used for the line counter and the data latch circuit. At the rising edge of the CL signal, the line counter is

counted up, then 384-bit display data is latched into the data latch circuit. At the falling edge of the CL signal, the latch

data is released to the grayscale control circuit, then segment drivers Ai, Bi and Ci (i=0 to 127) produce LCD driving

waveforms. The internal data-transmission timing between the DDRAM and segment drivers is completely independent

from external data-transmission timing, so that MPU makes access to the LSI without concern for the LSI’s internal

operation.

The FR and FLM are generated by the CL. The FR toggles once every frame in the default status, and is

programmed to toggle once every N lines. And the FLM is used to specify an initial display line, which is preset

whenever the FLM becomes “H”.

(8) DATA LATCH CIRCUIT

The data latch circuit is used to temporarily store display data which is released to the grayscale control circuit. The

display data in this circuit is updated in synchronization with the CL. The “All Pixels ON/OFF”, “Display ON/OFF” and

“Reverse Display ON/OFF” instructions control the data in this circuit, but does not change the data in the DDRAM.

(9) COMMON DRIVERS AND SEGMENT DRIVERS

The LSI includes 128-common drivers, 384-segment drivers and 6-icon segment drivers. The common drivers

generate LCD driving waveforms formed on the V_LCD, V₁, V₄and V_SSHlevels. The segment drivers generate waveforms

formed on the V_LCD, V₂, V₃and V_SSHlevels.

COM₀

1

2

3

4

5

1

2

3

4

5

1

129

COM₁

CL

SEG₂

SEG

⁰SEG₁

FLM

FR

V_LCD

V₁

V₂

COM₀

V₃

V₄

V_SSH

V_LCD

V₁

V₂

COM₁

SEG₀

V₃

V₄

V_SSH

V_LCD

V₁

V₂

V₃

V₄

V_SSH

V_LCD

V₁

SEG₁

V₂

V₃

V₄

V_SSH

Fig 9 LCD Driving Waveforms (B&W Mode, Color Reverse OFF, 1/129 Duty)

Ver.2004-01-06

- 39 -

NJU6824

(10) ICON SEGMENT

(10-1) Icon Segment Driver

The IC incorporates 6 icon segment drivers, such as the SEGSA₀, SEGSB₀, SEGSC₀, SEGSA₁, SEGSB₁and

SEGSC₁, and 2 icon segment registers. These drivers are used for the icon display in the periphery of an LCD screen.

The palettes Aj, Bj and Cj (j=0-15) are applied to the SEGSA₀/SEGSA₁, SEGSB₀/SEGSB₁and SEGSC₀/SEGSC₁

respectively, and each register has 12 bits to individually control the grayscale of 1 RGB-group (SEGSA₀, SEGSB₀,

SEGSC₀or SEGSA₁, SEGSB₁, SEGSC₁). This function is enabled by setting “1” at the D₁(ICON) bit of the

“Upper/Lower Palette Select and Icon Segment Access ON/OFF” instruction, and then either address (00H) or (01H) is

specified by the “Window Start Column Address” instruction.

The D₁(ALLON) bit of the “Display Control (1)” and the D₃(REV) bit of the “Display Control (2)” instruction are

effective in this function, and the D₀(LREV) bit of the “Line Reverse ON/OFF” is ineffective.

Column Address (00H) : SEGSA₀, SEGSB₀, SEGSC₀

Column Address (01H) : SEGSA₁, SEGSB₁, SEGSC₁

Table 16 Selection of DDRAM Access or Icon Segment Register Access

68-series

80-series

RS

ICON

Function

R/W

H

RDb

L

WRb

L

0

1

H

L

Read Data (DDRAM)

Write Data (DDRAM)

Read Data (Icon Segment Register)

Write Data (Icon Segment Register)

L

H

L

H

L

H

NOTE1) Right after setting an address or right after writing data, a dummy read is necessary for accessing the icon segment

registers as well as the DDRAM. The dummy data is read out by the 1^stread instruction, and then correct data is read

out from the specified address by the 2^ndinstruction.

NOTE2) The icon segment registers and the DDRAM use the same address counter. For this reason, whenever changing the

“ICON” bit, the column address should be reset by the “Window Start Column Address” instruction.

NOTE3) The “HV” bit of the “Increment/Decrement Control” instruction should be “0” while accessing the icon segment register.

Ver.2004-01-06

- 40 -

NJU6824

(10-2) Bit Assignment of Icon Segment Register Data

(10-2-1) Bit Assignment Overview

These maps is used for grasping general outlines of the variations in the bit assignment of the icon segment register

data.

C256

ABS

C256

ABS

WLS

Mode

WLS

Mode

SWAP

16bit

8bit

Ver.2004-01-06

- 41 -

NJU6824

(10-2-2) Bit Assignment in Variable 16-grayscale Mode (Icon Segment Register)

16-bit Bus Length (MON=0, PWM=0, C256=0, WLS=1)

ABS

0

SWAP

0

Column Address / Register Data / Icon Segment Driver

X=00H X=01H

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

ABS

0

SWAP

1

Column Address / Register Data / Icon Segment Driver

X=00H X=01H

Register Data

Grayscale Palette

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

Icon Segment Driver

ABS

1

SWAP

0

Column Address / Register Data / Icon Segment Driver

X=00H X=01H

Register Data

Grayscale Palette

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

Icon Segment Driver

ABS

1

SWAP

1

Column Address / Register Data / Icon Segment Driver

X=00H X=01H

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

Ver.2004-01-06

- 42 -

NJU6824

8-bit Bus Length

(MON=0, PWM=0, C256=0, WLS=0)

ABS

0

SWAP

0

Column Address / Register Data / Icon Segment Driver

X=00H(Upper)

X=00H(Lower)

X=01H(Upper)

X=01H(Lower)

Register Data

Grayscale Palette

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

Icon Segment Driver

ABS

0

SWAP

1

Column Address / Register Data / Icon Segment Driver

X=00H(Upper)

X=00H(Lower)

X=01H(Upper)

X=01H(Lower)

Register Data

Grayscale Palette

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

Icon Segment Driver

ABS

1

SWAP

0

Column Address / Register Data / Icon Segment Driver

X=01H

X=00H

X=00H(Lower)

X=01H(Lower)

(Upper)

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

ABS

SWAP

1

Column Address / Register Data / Icon Segment Driver

X=01H

X=00H

1

X=00H(Lower)

X=01H(Lower)

(Upper)

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

Ver.2004-01-06

- 43 -

NJU6824

(10-2-3) Bit Assignment in variable 8-grayscale Mode (Icon Segment Register)

8-bit Bus Length

(MON=0, PWM=0, C256=1, WLS=0)

ABS

*

SWAP

0

Column Address / Register Data / Icon Segment Driver

X=00H

X=01H

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

ABS

*

SWAP

1

Column Address / Register Data / Icon Segment Driver

X=00H X=01H

Register Data

Grayscale Palette

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

Icon Segment Driver

Ver.2004-01-06

- 44 -

NJU6824

(10-2-4) Bit Assignment in Fixed 8-grayscale Mode (Icon Segment Register)

16-bit Bus Length (MON=0, PWM=1, C256=0, WLS=1)

ABS

0

SWAP

0

Column Address / Register Data / Icon Segment Driver

X=00H X=01H

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

ABS

0

SWAP

1

Column Address / Register Data / Icon Segment Driver

X=00H X=01H

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

NOTE) The data indicated with a slash mark ( / ) are invalid.

ABS

1

SWAP

0

Column Address / Register Data / Icon Segment Driver

X=00H X=01H

Register Data

Grayscale Palette

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

Icon Segment Driver

ABS

1

SWAP

1

Column Address / Register Data / Icon Segment Driver

X=00H X=01H

Register Data

Grayscale Palette

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

Icon Segment Driver

NOTE) The data indicated with a slash mark ( / ) is invalid.

Ver.2004-01-06

- 45 -

NJU6824

8-bit Bus Length

(MON=0, PWM=1, C256=0, WLS=0)

ABS

0

SWAP

0

Column Address / Register Data / Icon Segment Driver

X=00H(Upper)

X=00H(Lower)

X=01H Upper)

X=01H(Lower)

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

ABS

0

SWAP

1

Column Address / Register Data / Icon Segment Driver

X=00H(Upper)

X=00H(Lower)

X=01H Upper)

X=01H(Lower)

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

NOTE) The data indicated with a slash mark ( / ) is invalid.

ABS

1

SWAP

0

Column Address / Register Data / Icon Segment Driver

X=01H

X=00H

X=00H(Lower)

X=01H(Lower)

(Upper)

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

ABS

SWAP

1

Column Address / Register Data / Icon Segment Driver

X=01H

X=00H

1

X=00H(Lower)

X=01H(Lower)

(Upper)

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

NOTE) The data indicated with a slash mark ( / ) is invalid.

8-bit Bus Length

(MON=0, PWM=1, C256=1, WLS=0)

ABS

*

SWAP

0

Column Address / Register Data / Icon Segment Driver

X=00H X=01H

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

ABS

*

SWAP

1

Column Address / Register Data / Icon Segment Driver

X=00H X=01H

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

Ver.2004-01-06

- 46 -

NJU6824

(10-2-5) Bit Assignment in B&W Mode (Icon Segment Register)

16-bit Bus Length (MON=1, PWM=*, C256=0, WLS=1)

ABS

0

SWAP

0

Column Address / Register Data / Icon Segment Driver

X=00H X=01H

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

ABS

0

SWAP

1

Column Address / Register Data / Icon Segment Driver

X=00H X=01H

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

ABS

1

SWAP

0

Column Address / Register Data / Icon Segment Driver

X=00H X=01H

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

ABS

1

SWAP

1

Column Address / Register Data / Icon Segment Driver

X=00H X=01H

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

NOTE) The data indicated with a slash mark ( / ) is invalid, and only MSB bits are effective.

Ver.2004-01-06

- 47 -

NJU6824

8-bit Bus Length

(MON=1, PWM=*, C256=0, WLS=0)

ABS

0

SWAP

0

Column Address / Register Data / Icon Segment Driver

X=00H(Upper)

X=00H(Lower)

X=01H(Upper)

X=01H(Lower)

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

ABS

0

SWAP

1

Column Address / Register Data / Icon Segment Driver

X=00H(Upper)

X=00H(Lower)

X=01H(Upper)

X=01H(Lower)

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

ABS

SWAP

0

Column Address / Register Data / Icon Segment Driver

X=01H

X=00H

1

X=00H(Lower)

X=01H(Lower)

(Upper)

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

ABS

1

SWAP

1

Column Address / Register Data / Icon Segment Driver

X=01H

X=00H

X=00H(Lower)

X=01H(Lower)

(Upper)

Register Data

Grayscale Palette

Icon Segment Driver

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

NOTE) The data indicated with a slash mark ( / ) is invalid, and only MSB bits are effective.

8-bit Bus Length

(MON=1, PWM=*, C256=1, WLS=0)

ABS

*

SWAP

0

Column Address / Register Data / Icon Segment Driver

X=00H

X=01H

Register Data

Grayscale Palette

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

Icon Segment Driver

ABS

*

SWAP

1

Column Address / Register Data / Icon Segment Driver

X=00H X=01H

Register Data

Grayscale Palette

Palette A

SEGSA₀

Palette B

SEGSB₀

Palette C

SEGSC₀

Palette A

SEGSA₁

Palette B

SEGSB₁

Palette C

SEGSC₁

Icon Segment Driver

NOTE) The data indicated with a slash mark ( / ) is invalid, and only MSB bits are effective.

Ver.2004-01-06

- 48 -

NJU6824

(11) OSCILLATOR

The oscillator is equipped with a resistor and a capacitor, and generates internal clocks used for the display timing

generator and the voltage booster. The internal resistor is enabled by setting “0” at the D₁(CKS) bit of the “Bus Length”

instruction. For more accurate frequency, using an external resistor or external clock is recommended.

When using the internal resistor, the resistance is controlled to optimize frame frequency for different LCD panels,

by setting the D₂-D₀(RF2-RF0) bits of the “Frequency Control” instruction. For more safety, make sure what is the best

frequency in the particular application.

(11-1) Using Internal Resistor (CKS=0)

In this case, the OSC1 should be fixed at “H” or “L” and the OSC2 is open. The oscillation frequency is varied

according to the display mode, as follows.

Table 18 Oscillation Frequency vs. Display Mode

Symbol

f_OSC1

MON

PWM

Display Mode

Variable 8-/16-grayscale Mode

Fixed 8-grayscale Mode

B&W Mode

0

1

0

1

*

f_OSC2

f_OSC3

*: Don’t care

(11-2) Using External Resistor (CKS=1)

Be sure to connect the OSC1 and OSC2 with an external resistor. The frequency of the oscillator should be adjusted

to the same value generated by the internal resistor.

(11-3) Using External Clock (CKS=1)

Input external clock to the OSC1 and leave the OSC2 open. The external clock with 50% duty is recommended. The

frequency of the external clock should be the same value generated by the internal resistor.

(12) LCD POWER SUPPLY

The internal LCD power supply is organized into the voltage converter and the voltage booster. The voltage

converter consists of the reference voltage generator, the voltage regulator with EVR and the LCD bias voltage generator.

The configuration of the LCD power supply is arranged by setting the D₃(AMPON) and D₁(DCON) bits of the “Power

Control” instruction. For this configuration, the internal LCD power supply can be partially used in combination with an

external supply voltage, as shown in Table 19.

Table 19 Configuration of LCD Power Supply

DCON

AMPON

Voltage Booster

Voltage Converter

External Supply Voltage

NOTE

0

1

0

1

Inactive

Active

Inactive

Active

V_OUT, V_LCD, V₁, V₂, V₃, V₄

1, 3, 4

2, 3, 4

-

V_OUT

−

NOTE1) No internal LCD power supply is used. The LCD bias voltages are externally supplied, and the C₁₊, C₁-, C₂₊, C₂-, C₃₊,

C₃-, C₄₊, C₄-, C₅₊, C₅-, V_REF, V_REGand V_EEare open.

NOTE2) Only the voltage converter is used. The V_OUTis externally supplied, and the C₁₊, C₁-, C₂₊, C₂-, C₃₊, C₃-, C₄₊, C₄-, C₅₊,

C₅- and V_EEare open. The reference voltage is supplied on the V_REF

.

NOTE3) The following relation among each LCD bias voltages must be maintained.

_OUT≥ V_LCD≥ V₁≥ V₂≥ V₃≥ V₄≥ V_SSH

V

NOTE4) If the internal LCD power supply doesn’t have enough capability to drive the particular LCD panel, use the external

LCD power supply. Otherwise, it may affect display quality.

Ver.2004-01-06

- 49 -

NJU6824

(12-1) Voltage Booster

The internal voltage booster generates up to 6xV_EEvoltage. The boost level is selected from 2x, 3x, 4x, 5x or 6x by

setting the D₂-D₀(VU2-VU0) bits of the “Boost Level” instruction. The boost voltage V_OUTmust not exceed 18.0V,

otherwise the voltage stress may cause a permanent damage to the LSI.

V_OUT=18V

V_OUT=9V

V_EE=3V

V_SSH=0V

3-time Boost

6-time Boost

Fig 10 Boost Voltage

5-time Boost

6-time Boost

C₁₊

C₁-

C₁₊

C₁-

+

C₂₊

C₂-

C₂₊

C₂-

C₃₊

C₃-

C₃₊

C₃-

C₄₊

C₄-

C₄₊

C₄-

C₅₊

C₅-

C₅₊

C₅-

V_OUT

V_SSH

V_OUT

V_SSH

+

4-time Boost

3-time Boost

2-time Boost

C₁₊

C₁-

C₁₊

C₁-

C₁₊

C₁-

+

C₂₊

C₂-

C₂₊

C₂-

C₂₊

C₂-

+

C₃₊

C₃-

C₃₊

C₃-

C₃₊

C₃-

C₄₊

C₄-

C₄₊

C₄-

C₄₊

C₄-

C₅₊

C₅-

C₅₊

C₅-

C₅₊

C₅-

V_OUT

V_SSH

V_OUT

V_SSH

V_OUT

V_SSH

+

Fig 11 External Capacitor Connection of Voltage Booster

Ver.2004-01-06

- 50 -

NJU6824

(12-2) Voltage Converter

(12-2-1) Reference Voltage Generator

The reference voltage generator produces the reference voltage (V_BA=0.9xV_EE). When using the internal LCD

power supply, connect the V_BAand the V_REF, or supply 0.9xV_EEor lower voltage on the V_REF. When using an external

LCD power supply, the V_BAshould be open. Refer to Fig 12, 14 and 15.

(12-2-2) Voltage Regulator

The voltage regulator consists of an operational amplifier with gain control and EVR. The V_REFvoltage is

multiplied to obtain the V_REGvoltage, and its multiple (boost level) is set by the D₂-D₀(VU2-VU0) bits of the “Boost

Level” instruction. The formula is shown below.

V_REG= V_REF

x

N

(N: Boost Level)

(12-2-3) Electrical Variable Resistor (EVR)

The EVR is used to fine-tune the V_LCDvoltage to optimize display contrast. The EVR value is controlled in 128

steps by setting the D₃-D₀(DV₆-DV₀) bits of the “EVR Control” instruction. The formula is shown below.

V_LCD= 0.5

x

V_REG+ M (V_REG- 0.5

x

V_REG) / 127

(M: EVR Value)

(12-2-4) LCD Bias Voltage Generator

The LCD bias voltage generator consists of buffer amplifiers and bleeder resistors to generate the LCD bias

voltages such as the V_LCD, V₁, V₂, V₃and V₄, and its bias ratio is selected from 1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11 and

1/12.

As shown in Fig 12, when using only the internal LCD power supply, the capacitors CA2 are connected to the V_LCD

V₁, V₂, V₃and V₄respectively.

,

As shown in Fig 13, when using no internal LCD power supply, the LCD bias voltages are externally supplied on

the V_LCD, V₁, V₂, V₃and V₄, and the internal LCD power supply should be turned off by setting “0” at the “DCON” and

“AMPON” bits. And the C₁₊, C₁-, C₂₊, C_2-, C₃₊, C₃-, C₄₊, C₄-, C₅₊, C₅-, V_EE, V_REFand V_REGare open.

Fig 14 and 15 show typical peripheral circuits when partially using the LCD power supply without the reference

voltage generator.

Fig 16 shows the circuit when partially using the LCD power supply without the voltage booster.

Ver.2004-01-06

- 51 -

NJU6824

(12-3) External Components for LCD Power Supply

Using Only Internal LCD Power Supply (6x boost)

Using Only External LCD Power Supply

V_DD

V_EE

CA1

V_EE

CA1

V_BA

V_REF

V_REG

CA3

V_REG

CA3

C_1-

C₁₊

C_2-

C₂₊

C_3-

C₃₊

C_4-

C₄₊

C_5-

C₅₊

CA1

C₁₊

C_2-

CA1

C₂₊

C_3-

CA1

C₃₊

C_4-

CA1

C₄₊

C_5-

CA1

C₅₊

V_OUT

CA1

V_LCD

V₁

V_LCD

V₁

CA2

V_LCD

External V₁

Power V₂

Circuit V₃

V₄

V₂

V₃

V₄

CA2 CA2 CA2 CA2

Fig 12

Fig 13

Reference Values

CA1

CA2

CA3

1.0 to 4.7µF

1.0 to 2.2µF

0.1µF

NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular

application.

NOTE2) Parasitic resistance on the power supply lines (V_DD, V_SS, V_EE, V_SSH, V_OUT, V_LCD, V₁, V₂, V₃and V₄) reduces step-up

efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality. To minimize this

impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible.

Ver.2004-01-06

- 52 -

NJU6824

Using Internal LCD Power Supply

Without Reference Voltage generator (1)

(6x boost)

Using Internal LCD Power Supply

Without Reference Voltage generator (2)

(6x boost)

V_DD

V_EE

V_DD

V_EE

CA1

V_BA

V_REF

V_REG

V_REF

V_REG

CA3

C_1-

C₁₊

C_2-

C₂₊

C_3-

C₃₊

C_4-

C₄₊

C_5-

C₅₊

C_1-

C₁₊

C_2-

C₂₊

C_3-

C₃₊

C_4-

C₄₊

C_5-

C₅₊

CA1

V_OUT

CA1

V_LCD

V₁

V_LCD

V₁

CA2

V₂

V₃

V₄

Fig 14

Fig 15

Reference Values

CA1

CA2

CA3

1.0 to 4.7µF

1.0 to 2.2µF

0.1µF

NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular

application.

NOTE2) Parasitic resistance on the power supply lines (V_DD, V_SS, V_EE, V_SSH, V_OUT, V_LCD, V₁, V₂, V₃and V₄) reduces step-up

efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality. To minimize this

impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible.

Ver.2004-01-06

- 53 -

NJU6824

Using Internal LCD Power Supply

Without Voltage Booster

V_DD

V_EE

CA1

V_BA

V_REF

V_REG

CA3

C_1-

C₁₊

C_2-

C₂₊

C_3-

C₃₊

C_4-

C₄₊

C_5-

C₅₊

External

Power

Circuit

V_OUT

CA1

V_LCD

V₁

CA2

V₂

V₃

V₄

Fig 16

Reference Values

CA1

CA2

CA3

1.0 to 4.7µF

1.0 to 2.2µF

0.1µF

NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular

application.

NOTE2) Parasitic resistance on the power supply lines (V_DD, V_SS, V_EE, V_SSH, V_OUT, V_LCD, V₁, V₂, V₃and V₄) reduces step-up

efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality. To minimize this

impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible.

Ver.2004-01-06

- 54 -

NJU6824

(12-4) Discharge Circuit

The LSI incorporates two discharge circuits which are independently controlled for the V_LCDand V₁-V₄and for the

V

_OUT. The V_LCDand V₁-V₄are discharged by setting "1" at the D₀(DIS) bit of the "Discharge ON/OFF" instruction or

the reset by the RESb. And the V_OUT(100KΩ internal resistor between V_OUTand V_EE) is discharged by setting "1" at the

D₁(DIS2) bit of this instruction. Be sure to turned off the internal or external LCD power supply when this instruction is

executed, otherwise it may function as a current load and affect an operating current. Refer to “(15-22) Discharge

ON/OFF”.

(12-5) Power ON/OFF

To protect the LSI from overcurrent, the following sequences must be maintained to turn on and off the power

supply. In addition to the following discussions, refer to “(19) TYPICAL INSTRUCTION SEQUENCES”.

(12-5-1) Power ON/OFF in Using Internal LCD Power Supply

Power ON

First “V_DDand V_EEON”, next “Reset by RESb”, then “Internal LCD power supply ON”. Be sure to execute the

“Display ON” instruction later than the completion of this power ON sequence. Otherwise, unexpected pixels may be

turned on instantly.

Power OFF

First “Reset by RESb or “HALT” instruction”, next “V_DDand V_EEOFF”. If using different power sources for the

V

_DDand the V_EEindividually, the V_EEmust be turned off after the reset or the “HALT”. After that, the V_DDcan be turned

off, waiting until the LCD bias voltages (V_LCD, V₁, V₂, V₃and V₄) drop below the threshold level of LCD pixels.

(12-5-2) Power ON/OFF in Using External LCD Power Supply

Power ON

First “V_DDand V_EEON”, next “Reset by RESb”, then “External LCD power supply ON”. When using only external

V_OUT, first “V_DDON”, next “Reset by RESb”, then “External V_OUTON”, as well.

Power OFF

First “Reset by RESb or “HALT” instruction” to isolate external LCD bias voltages, next “V_DDOFF”. For more

safety, placing a resistor in series on the V_LCDline (or the V_OUTline in using only the external V_OUT) is recommended.

That resistance is usually between 50Ω and 100Ω.

(12-6) LCD Bias Adjustment Circuit

The LCD bias voltages V₁and V₄can be fine-tuned for different LCD panels by setting the V₁A₁&V₁A₂and

V₄A₁&V₄A₂terminals, as follows.

Table 20-1 LCD Bias Adjustment (V₁A₁, V₁A₂)

Table 20-2 LCD Bias Adjustment (V₄A₁, V₄A₂)

V₄A₁

L

V₄A₂

L

Voltage Variation [mV] (NOTE1)

V₁A₁

L

V₁A₂

L

Voltage Variation [mV] (NOTE1)

0

+5

-5

0

+5

-5

L

H

L

H

L

H

L

+10

H

+10

NOTE1) The variation is defined as the voltage shifted from 0mV at (V₁A₁, V₁A₂)=(0,0) and (V₄A₁, V₄A₂)=(0,0). And “+” means

shifting toward the V_LCD, and “-“ means shifting toward the V_SS

.

NOTE2) The voltage variations as mentioned above are theoretical values, and therefore may have a certain amount of error.

NOTE3) The voltage variations as mentioned above are the theoretical values at V_LCD=13.5V.

Ver.2004-01-06

- 55 -

NJU6824

(13) RESET FUNCTION

The reset function initializes the LSI to the following default status by setting the RESb to “L”. Connecting the

RESb with MPU’s reset is recommended so that the LSI and MPU is initialized at a time.

Default Status

1. Display Data in DDRAM

2. Window Start Column Address

3. Window Start Row Address

4. Initial Display Line

5. Display ON/OFF

6. Reverse Display ON/OFF

7. Duty Cycle Ratio

8. N-line Inversion ON/OFF

9. COM Scan Direction

10. Increment/Decrement Control

11. Read-modify-write

12. Swap

:Undefined

:(00)H

:(0)H (1st line)

:OFF

:OFF (Normal)

:1/129 Duty (DSE=0)

:OFF

:COM₀→ COM₁₂₇

:(HV, XD, YD)=(0, 0, 0)

:OFF (AIM=0)

:OFF (Normal)

:(0, 0, 0, 0, 0, 0, 0)

:OFF

13. EVR Value

14. Internal LCD Power Supply

15. Display Mode

16. LCD Bias Ratio

17. Palette 0

:Grayscale Mode

:1/9 Bias

:(0, 0, 0, 0, 0)

:(0, 0, 0, 1, 1)

:(0, 0, 1, 0, 1)

:(0, 0, 1, 1, 1)

:(0, 1, 0, 0, 1)

:(0, 1, 0, 1, 1)

:(0, 1, 1, 0, 1)

:(0, 1, 1, 1, 1)

:(1, 0, 0, 0, 1)

:(1, 0, 0, 1, 1)

:(1, 0, 1, 0, 1)

:(1, 0, 1, 1, 1)

:(1, 1, 0, 0, 1)

:(1, 1, 0, 1, 1)

:(1, 1, 1, 0, 1)

:(1, 1, 1, 1, 1)

:Variable 16-grayscale Mode (4,096 Colors)

:8-bit Bus Length

:OFF (DIS,DIS2)=(0,0)

18. Palette 1

19. Palette 2

20. Palette 3

21. Palette 4

22. Palette 5

23. Palette 6

24. Palette 7

25. Palette 8

26. Palette 9

27. Palette 10

28. Palette 11

29. Palette 12

30. Palette 13

31. Palette 14

32. Palette 15

33. Display Mode Control

34. Bus Length

35. Discharge ON/OFF

Ver.2004-01-06

- 56 -

NJU6824

(14) INSTRUCTION TABLES

(14-1) Instruction Table and Register Address

The LSI incorporates 6 instruction tables as shown in Fig 17, and each instruction table has a specific address in

between “0” and “5”. And each instruction register has a specific address in between (0H) and (FH), and instruction is

read out from the register by the “Register Address” and “Register Read” instructions.

Fig 18 shows part of the instruction sequence, where the instruction table should be specified prior to other

instructions. However, when some instructions of the same table are sequentially executed, the table selection may be

omitted. In addition, the “Display Data Write”, “Display Data Read” and “Register Read” instructions can be performed

in any table.

Table “0”

Table “1”

Table “2”

Table “3”

Table “4”

Table “5”

(RE2,RE1,RE0)=(0,0,0) (RE2,RE1,RE0)=(0,0,1) (RE2,RE1,RE0)=(0,1,0) (RE2,RE1,RE0)=(0,1,1) (RE2,RE1,RE0)=(1,0,0) (RE2,RE1,RE0)=(1,0,1)

Instruction (0H)

Instruction (FH)

NOTE) Address (FH) is assigned to “Instruction Table Select” in any table.

Fig 17 Instruction Table Overview

Optional Status

[RE2:RE0]=[0,0,0]

Instruction Table “0” Select

Instruction 1

Instructions in Table “0”

Instruction 2

Instruction 3

[RE2:RE0]=[1,0,0]

Instruction Table “4” Select

Instruction 4

Instructions in Table “4”

Instruction 5

[RE2:RE0]=[1,0,1]

Instruction in Table “5”

Instruction Table “5” Select

Instruction 6

Optional Status

Fig 18 Outline of Instruction Sequence

Ver.2004-01-06

- 57 -

NJU6824

(14-2) Instruction Table 0 (RE2, RE1, RE0)=(0, 0, 0)

Code (80 Series MPU I/F)

Code

D₄D₃

Instructions/

Functions

Writing Display Data

Register Address [NH]

CSb RS RDb WRb RE2 RE1 RE0

D₇

D₆

D₅

D₂

D₁

D₀

1

2

Display Data Write

Display Data Read

0

1

0

1

0/1

Write Data

Read Data

Reading Display Data

Window Start Column Address

(Lower) [0H]

Setting Column Address

for start point

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

AX3 AX2 AX1 AX0

AX7 AX6 AX5 AX4

AY3 AY2 AY1 AY0

3

4

5

6

Window Start Column Address

(Upper) [1H]

Setting Column Address

for start point

Window Start Row Address

(Lower) [2H]

Setting Row Address

for start point

Window Start Row Address

(Upper) [3H]

Setting Row Address

for start point

*

LA3

*

AY6 AY5 AY4

LA2 LA1 LA0

LA6 LA5 LA4

Initial Display Line

(Lower) [4H]

Setting Row Address

for Initial COM

Initial Display Line

(Upper) [5H]

Setting Row Address

for Initial COM

N-line Inversion

(Lower) [6H]

Setting the Number of

N-line Inversion

N3

*

N2

N6

N1

N5

N0

N4

N-line Inversion

(Upper) [7H]

Setting the Number of

N-line Inversion

SHIFT

: Common Scan Direction

Display Control (1)

[8H]

ALL ON/ MON

: Grayscale/B/W Mode

7

8

9

0

1

0

1

0

1

0

1

0

SHIFT MON

ON OFF ALLON : All Pixels ON/OFF

ON/OFF : Display ON/OFF

REV

: Reverse Display ON/OFF

Display Control (2)

[9H]

REV NLIN SWAP

*

NLIN

SWAP

: N-line Inversion ON/OFF

: SWAP ON/OFF

AIM

HV

XD

YD

: Read-Modify-Write ON/OFF

:Horizontal/ Vertical Direction

: X Increment / Decrement

: Y Increment / Decrement

Increment/Decrement Control

[AH]

AIM

HV

XD

YD

AMPON : Voltage Converter ON/OFF

Power Control

[BH]

AMP

ON

DC

ON

HALT

DCON

ACL

: Power Save ON/OFF

: Voltage Booster ON/OFF

: Reset

10

0

1

0

1

0

1

HALT

ACL

Duty Cycle Ratio

[CH]

11

12

13

14

0

1

0

1

0

1

0

1

0

1

DS3 DS2 DS1 DS0 Setting LCD Duty Cycle Ratio

Boost Level

[DH]

*

VU2 VU1 VU0 Setting Boost Level

LCD Bias Ratio

[EH]

0

B2

B1

B0 Setting LCD Bias Ratio

Instruction Table Select

[FH]

0/1

TST0 RE2 RE1 RE0 Setting Instruction Table

NOTE1) * : Don’t care.

NOTE2) [NH] (N=0-F) : Register Address

NOTE3) Any nonexistent instruction code is prohibited.

NOTE4) Dual instructions except for “EVR Control” are already effective when either upper byte or lower byte is set.

NOTE5) “EVR Control” instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower

byte.

Ver.2004-01-06

- 58 -

NJU6824

(14-3) Instruction Table 1 (RE2, RE1, RE0)=(0, 0, 1)

Code (80 series MPU I/F)

Code

Instructions/

Functions

Register Address [NH]

CSb RS RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

0

D₄

D₃

D₂

D₁

D₀

Palette A0/A8

Setting Palette Data :

PA03/ PA02/ PA01/ PA00/

0

1

0

1

0

PA83 PA82

PA81 PA80

(Lower) [0H]

A0(PS=0) /A8(PS=1)

Palette A0/A8

Palette A1/A9

Palette A2/A10

Palette A3/A11

Palette A4/A12

Palette A5/A13

Palette A6/A14

Setting Palette Data :

A0(PS=0) /A8(PS=1)

PA04/

*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PA84

(Upper) [1H]

(Lower) [2H]

(Upper) [3H]

(Lower) [4H]

(Upper) [5H]

(Lower) [6H]

(Upper) [7H]

(Lower) [8H]

(Upper) [9H]

(Lower) [AH]

(Upper) [BH]

(Lower) [CH]

(Upper) [DH]

Setting Palette Data :

A1(PS=0) /A9(PS=1)

PA13/ PA12/ PA11/ PA10/

0

1

PA93 PA92

PA91 PA90

Setting Palette Data :

A1(PS=0) /A9(PS=1)

PA14/

*

0

1

PA94

Setting Palette Data :

A2(PS=0) /A10(PS=1)

PA23/ PA22/ PA21/ PA20/

PA103 PA102 PA101 PA100

0

1

Setting Palette Data :

A2(PS=0) /A10(PS=1)

PA24/

*

0

1

PA104

Setting Palette Data :

A3(PS=0) /A11(PS=1)

PA33/ PA32/P PA31/ PA30/

PA113 A112 PA111 PA110

0

1

15

Setting Palette Data :

A3(PS=0) /A11(PS=1)

PA34/

*

0

1

PA114

Setting Palette Data :

A4(PS=0) /A12(PS=1)

PA43/ PA42/P PA41/ PA40/

PA123 A122 PA121 PA120

0

1

Setting Palette Data :

A4(PS=0) /A12(PS=1)

PA44/

*

0

1

PA124

Setting Palette Data :

A5(PS=0) /A13(PS=1)

PA53/ PA52/P PA51/ PA50/

PA133 A132 PA131 PA130

0

1

Setting Palette Data :

A5(PS=0) /A13(PS=1)

PA54/

*

0

1

PA134

Setting Palette Data :

A6(PS=0) /A14(PS=1)

PA63/ PA62/P PA61/ PA60/

PA143 A142 PA141 PA140

0

1

Setting Palette Data :

A6(PS=0) /A14(PS=1)

PA64/

*

0

1

PA144

Instruction Table Select

TST0

RE2

RE1

RE0

14

0/1

Setting Instruction Table

[FH]

NOTE1) * : Don’t care.

NOTE2) [NH] (N=0-F) : Register Address

NOTE3) Any nonexistent instruction code is prohibited.

NOTE4) Dual instructions except for “EVR Control” are already effective when either upper byte or lower byte is set.

NOTE5) “EVR Control” instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower

byte.

Ver.2004-01-06

- 59 -

NJU6824

(14-4) Instruction Table 2 (RE2, RE1, RE0)=(0, 1, 0)

Code (80 series MPU I/F)

Code

D₃

Instructions/

Functions

Register Address [NH]

CSb RS RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

0

D₄

0

D₂

D₁

D₀

Palette A7/A15

Setting Palette Data :

A7(PS=0) /A15(PS=1)

PA73/ PA72/P PA71/ PA70/

PA153 A152 PA151 PA150

0

1

0

1

0

(Lower) [0H]

Palette A7/A15

Palette B0/B8

Palette B1/B9

Palette B2/B10

Palette B3/B11

Palette B4/B12

Palette B5/B13

Setting Palette Data :

A7(PS=0) /A15(PS=1)

PA74/

*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PA154

(Upper) [1H]

(Lower) [2H]

(Upper) [3H]

(Lower) [4H]

(Upper) [5H]

(Lower) [6H]

(Upper) [7H]

(Lower) [8H]

(Upper) [9H]

(Lower) [AH]

(Upper) [BH]

(Lower) [CH]

(Upper) [DH]

Setting Palette Data :

B0(PS=0) /B8(PS=1)

PB03/ PB02/ PB01/ PB00/

PB83 PB82 PB81 PB80

0

1

0

Setting Palette Data :

B0(PS=0) /B8(PS=1)

PB04/

*

0

1

0

PG84

Setting Palette Data :

B1(PS=0) /B9(PS=1)

PB13/ PB12/ PB11/ PB10/

PB93 PB92 PB91 PB90

0

1

0

Setting Palette Data :

B1(PS=0) /B9(PS=1)

PB14/

*

0

1

0

PB94

Setting Palette Data :

B2(PS=0) /B10(PS=1)

PB23/ PB22/ PB21/ PB20/

PB103 PB102 PB101 PB100

0

1

0

15

Setting Palette Data :

B2(PS=0) /B10(PS=1)

PB24/

*

0

1

0

PB104

Setting Palette Data :

B3(PS=0) /B11(PS=1)

PB33/ PB32/ PB31/ PB30/

PB113 PB112 PB111 PB110

0

1

0

Setting Palette Data :

B3(PS=0) /B11(PS=1)

PB34/

*

0

1

0

PB114

Setting Palette Data :

B4(PS=0) /B12(PS=1)

PB43/ PB42/ PB41/ PB40/

PB123 PB122 PB121 PB120

0

1

0

Setting Palette Data :

B4(PS=0) /B12(PS=1)

PB44/

*

0

1

0

PB124

Setting Palette Data :

B5(PS=0) /B13(PS=1)

PB53/ PB52/ PB51/ PB50/

PB133 PB132 PB131 PB130

0

1

0

Setting Palette Data :

B5(PS=0) /B13(PS=1)

PB54/

*

0

1

0

PB134

Instruction Table Select

TST0

RE2

RE1

RE0

14

0/1

Setting Instruction Tablet

[FH]

NOTE1) * : Don’t care.

NOTE2) [NH] (N=0-F) : Register Address

NOTE3) Any nonexistent instruction code is prohibited.

NOTE4) Dual instructions except for “EVR Control” are already effective when either upper byte or lower byte is set.

NOTE5) “EVR Control” instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower

byte.

Ver.2004-01-06

- 60 -

NJU6824

(14-5) Instruction Table 3 (RE2, RE1, RE0)=(0, 1, 1)

Code (80 series MPU I/F)

Code

D₃

Instructions/

Functions

Register Address [NH]

CSb RS RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

0

D₄

0

D₂

D₁

D₀

Palette B6/B14

Setting Palette Data :

B6(PS=0) /B14(PS=1)

PB63/ PB62/ PB61/ PB60/

PB143 PB142 PB141 PB140

0

1

0

1

(Lower) [0H]

Palette B6/B14

Palette B7/B15

Palette C0/C8

Palette C1/C9

Palette C2/C10

Palette C3/C11

Palette C4/C12

Setting Palette Data :

B6(PS=0) /B14(PS=1)

PB64/

*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PB144

(Upper) [1H]

(Lower) [2H]

(Upper) [3H]

(Lower) [4H]

(Upper) [5H]

(Lower) [6H]

(Upper) [7H]

(Lower) [8H]

(Upper) [9H]

(Lower) [AH]

(Upper) [BH]

Setting Palette Data :

B7(PS=0) /B15(PS=1)

PB73/ PB72/ PB71/ PB70/

PB153 PB152 PB151 PB150

0

1

Setting Palette Data :

B7(PS=0) /B15(PS=1)

PB74/

*

0

1

PB154

Setting Palette Data :

C0(PS=0) /C8(PS=1)

PC03/ PC02/ PC01/ PC00/

PC83 PC82 PC81 PC80

0

1

Setting Palette Data :

C0(PS=0) /C8(PS=1)

PC04/

*

0

1

PC84

Setting Palette Data :

C1(PS=0) /C9(PS=1)

PC13/ PC12/ PC11/ PC10/

PC93 PC92 PC91 PC90

0

1

15

Setting Palette Data :

C1(PS=0) /C9(PS=1)

PC14/

*

0

1

PC94

Setting Palette Data :

C2(PS=0) /C10(PS=1)

PC23/ PC22/ PC21/ PC20/

PC103 PC102 PC101 PC100

0

1

Setting Palette Data :

C2(PS=0) /C10(PS=1)

PC24/

*

0

1

PC104

Setting Palette Data :

C3(PS=0) /C11(PS=1)

PC33P PC32/ PC31/ PC30/

C113 PC112 PC111 PC110

0

1

Setting Palette Data :

C3(PS=0) /C11(PS=1)

PC34/

*

0

1

PC114

Setting Palette Data :

C4(PS=0) /C12(PS=1)

PC43/ PC42/ PC41/ PC40/

PC123 PC122 PC121 PC120

0

1

(Lower) [CH]

Palette C4/C12

(Upper) [DH]

Setting Palette Data :

C4(PS=0) /C12(PS=1)

PC44/

*

0

1

PC124

Instruction Table Select

TST0

RE2

RE1

RE0

14

0/1

Setting Instruction Table

[FH]

NOTE1) * : Don’t care.

NOTE2) [NH] (N=0-F) : Register Address

NOTE3) Any nonexistent instruction code is prohibited.

NOTE4) Dual instructions except for “EVR Control” are already effective when either upper byte or lower byte is set.

NOTE5) “EVR Control” instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower

byte.

Ver.2004-01-06

- 61 -

NJU6824

(14-6) Instruction Table 4 (RE2, RE1, RE0)=(1, 0, 0)

Code (80 series MPU I/F)

Code

D₃

Instructions/

Functions

Register Address [NH]

CSb RS RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

0

D₄

0

D₂

D₁

D₀

Palette C5/C13

Setting Palette Data :

C5(PS=0) /C13(PS=1)

PC53/ PC52/ PC51/ PC50/

PC133 PC132 PC131 PC130

0

1

0

1

0

1

0

1

0

(Lower) [0H]

Palette C5/C13

Palette C6/C14

Palette C7/C15

Initial COM

Setting Palette Data :

C5(PS=0) /C13(PS=1)

PC54/

*

0

1

*

0

1

0

1

*

0

1

0

1

0

1

0

1

0

*

1

0

1

0

1

0

1

0

1

0

1

0

*

PC134

(Upper) [1H]

(Lower) [2H]

(Upper) [3H]

(Lower) [4H]

(Upper) [5H]

[6H]

Setting Palette Data :

C6(PS=0) /C14(PS=1)

PC63/P PC62/ PC61/ PC60/

C143 PC142 PC141 PC140

1

0

15

Setting Palette Data :

C6(PS=0) /C14(PS=1)

PC64/

*

1

0

PC144

Setting Palette Data :

C7(PS=0) /C15(PS=1)

PC73/ PC72/ PC71/ PC70/

PC153 PC152 PC151 PC150

1

0

Setting Palette Data :

C7(PS=0) /C15(PS=1)

PC74/

*

SC3

*

SC2

*

1

0

PC154

SC1

DSE

SC0

16

17

1

0

Setting start COM for scanning

Duty-1 /Display Clock ON/OFF

[7H]

SON

DSE

: Display Clock ON/OFF

: Duty-1 ON/OFF

SON

1

0

Display Mode Control

PWM

C256

:

Variable/Fixed Grayscale

PWM C256 FDC1 FDC2

18 /Boost Clock Control

1

0

: 256-color Mode ON/OFF

[8H]

[9H]

FDC1,2 : Boost Clock Control

ABS

: Bit Assignment

Bus Length

19

*

ABS CKS

WLS CKS

WLS

: Oscillator Set

1

0

: 8-/16-bit Bus Length

EVR Control

DV3

DV2

DV6

RF2

*

DV1

DV5

RF1

DIS2

DV0

DV4

RF0

DIS

1

0

Setting EVR Value (Lower Bit)

Setting EVR Value (Upper Bit)

Adjusting Oscillation Frequency

Discharge ON/OFF

(Lower) [AH]

(Upper) [BH]

20

EVR Control

*

1

0

Frequency Control

Discharge ON/OFF

Register Address

21

22

23

1

0

[DH]

[EH]

[CH]

1

0

Setting

Register Address

Read Data

1

0

Register Address

24 Register Read

0/1

Reading Instruction

Instruction Table Select

14

TST0

RE2

RE1

RE0

1

Setting Instruction Table Select

[FH]

NOTE1) * : Don’t care.

NOTE2) [NH] (N=0-F) : Register Address

NOTE3) Any nonexistent instruction code is prohibited.

NOTE4) Dual instructions except for “EVR Control” are already effective when either upper byte or lower byte is set.

NOTE5) “EVR Control” instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower

byte.

Ver.2004-01-06

- 62 -

NJU6824

(14-7) Instruction Table 5 (RE2, RE1, RE0)=(1, 0, 1)

Code (80 series MPU I/F)

Code

D₄D₃

Instructions/

Functions

Register Address [NH]

CSb RS RDb WRb RE2 RE1 RE0 D₇

D₆

0

D₅

0

D₂

D₁

D₀

Window End Column Address

Setting Column Address

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

EX3 EX2 EX1 EX0

EX7 EX6 EX5 EX4

EY3 EY2 EY1 EY0

(Lower) [0H]

for end point

25

26

27

Window End Column Address

(Upper) [1H]

Setting Column Address

for end point

0

1

0

1

0

1

0

1

0

1

Window End Row Address

(Lower) [2H]

Setting Row Address

for end point

1

0

1

Window End Row Address

(Upper) [3H]

Setting Row Address

for end point

1

0

1

*

EY6 EY5 EY4

Initial Line-reverse Address

(Lower) [4H]

Setting Start Line

1

0

1

LS3 LS2 LS1 LS0

for Line-reverse Display

Initial Line-reverse Address

(Upper) [5H]

Setting Start Line

1

0

1

*

LS6 LS5 LS4

for Line-reverse Display

Last Line-reverse Address

(Lower) [6H]

Setting End Line

1

0

1

LE3 LE2 LE1 LE0

for Line-reverse Display

28

29

Last Line-reverse Address

(Upper) [7H]

Setting End Line

1

0

1

*

LE6 LE5 LE4

for Line-reverse Display

Line Reverse ON/OFF

BT

: Blink Set

1

0

1

*

BT LREV

ICON PS

[8H]

LREV : Line-reverse ON/OFF

Upper/Lower Palette Select

PS

: Upper/Lower Palette

30 /Icon Segment Access ON/OFF

1

0

1

ICON : Icon Segment ON/OFF

[9H]

[AH]

PWM Control

31

PWM PWM PWM PWM

1

0

1

Setting PWM Mode

S

A

B

C

Instruction Table Select

14

0/1

TST0 RE2 RE1 RE0 Setting Instruction Table

[FH]

NOTE1) * : Don’t care.

NOTE2) [NH] (N=0-F) : Register Address

NOTE3) Any nonexistent instruction code is prohibited.

NOTE4) Dual instructions except for “EVR Control” are already effective when either upper byte or lower byte is set.

NOTE5) “EVR Control” instruction is finally effective when both upper and lower bytes are set. Send upper byte first, next lower

byte.

Ver.2004-01-06

- 63 -

NJU6824

(15) INSTRUCTION DESCRIPTIONS

This chapter provides detailed descriptions about each instruction. These descriptions are written with the

assumption that 80-series MPU is used. When using 68-series MPU, the polarities of the E and R/W signals differ from

those of the RDb and WRb signals.

(15-1) Display Data Write

The “Display Data Write” instruction writes display data on a specified DDRAM address.

CSb

0

RS

0

RDb WRb RE2 RE1 RE0

0/1 0/1 0/1

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

1

0

Display Data

(15-2) Display Data Read

The “Display Data Read” instruction reads out display data from a specified DDRAM address. One dummy read is

necessary right after DDRAM address setting.

CSb

0

RS

0

RDb WRb RE2 RE1 RE0

0/1 0/1 0/1

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

0

1

Display Data

(15-3) Window Start Column Address

The “Window Start Column Address” instruction specifies the column address of the start point. The setting order is

lower byte first, then upper byte.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

1

0

AX3

AX2

AX1 AX0

(Default: AX3-AX0=0H / Register Address: 0H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

0

D₄

1

D₃

D₂

D₁

D₀

1

0

AX7

AX6

AX5 AX4

(Default: AX7-AX4=0H / Register Address: 1H)

(15-4) Window Start Row Address

The “Window Start Row Address” instruction specifies the row address of the start point. Available setting range is

from (00H) to (7FH), and outside this range is not allowed. The setting order is lower byte first, then upper byte.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

1

0

AY3

AY2

AY1 AY0

(Default: AY3-AY0=0H / Register Address: 2H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

1

D₄

1

D₃

*

D₂

D₁

D₀

1

0

AY6

AY5 AY4

(Default: AY6-AY4=0H / Register Address: 3H)

(15-5) Initial Display Line

This instruction sets the row address, which corresponds to an initial COM and is normally positioned on top of a

screen in full display. For more information, refer to “(15-16) Initial COM”. The setting order is lower byte first, then

upper byte.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

1

0

LA3

LA2

LA1

LA0

(Default: LA3-LA0=0H / Register Address: 4H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

0

D₄

1

D₃

*

D₂

D₁

D₀

1

0

LA6

LA5

LA4

(Default: LA6-LA4=0H / Register Address: 5H)

Ver.2004-01-06

- 64 -

NJU6824

Table 21 Initial Display Line Address

LA6

0

LA5

0

LA4

0

LA3

0

LA2

0

LA1

0

LA0

0

1

Row Address

0

1

:

1

127

(15-6) N-line Inversion

The number of N line is selected in between “2” and “128”. When the N-line inversion is enabled by setting “1” at

the D₂(NLIN) bit of the “Display Control (2)” instruction, the FR toggles once every N lines. When the N-line inversion

is disabled by setting “0” at this bit, the FR toggles by the frame.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

1

D₄

0

D₃

D₂

D₁

D₀

1

0

N3

N2

N1

N0

(Default: N3-N0=0H / Register Address: 6H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

1

D₄

1

D₃

*

D₂

D₁

D₀

1

0

N6

N5

N4

(Default: N6-N4=0H / Register Address: 7H)

Table 22 N-line Inversion

N6

0

N5

0

N4

0

N3

N2

0

N1

N0

0

N Line

0

:

0

Inhibited

0

1

2

:

1

128

NOTE1) N Line=(N Value)+1

N-line inversion OFF

1^stline

3^rdline

128^thline

1^stline

129^thline

2^ndline

CL

FLM

FR

N-line inversion ON

N-line Inversion

1^stline

3^rdline

N line

2^ndline

1^stline

CL

FR

Fig 19 N-line Inversion Timing (1/129 Duty)

Ver.2004-01-06

- 65 -

NJU6824

(15-7) Display Control (1)

The “Display Control (1)” instruction controls display conditions.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

ALL

ON

1

0

SHIFT MON

ON /OFF

(Default: [SHIFT,MON,ALLON,ON/OFF]=0H / Register Address: 8H)

D₀(ON/OFF)

ON/OFF=0 : Display OFF (All COM/SEG fixed at V_SSHlevel)

ON/OFF=1 : Display ON

D₁(ALLON)

This bit forcibly turns on all pixels regardless of display data. This bit has a priority over the “REV” bit of the

“Display Control (2)” instruction.

ALLON=0

ALLON=1

: Normal

: All pixels ON

D₂(MON)

MON=0

MON=1

: Grayscale Mode (Variable 16-grayscale, Variable 8-grayscale or Fixed 8-grayscale Mode)

: B&W Mode

D₃(SHIFT)

SHIFT=0

SHIFT=1

: COM₀→ COM₁₂₇

: COM₀← COM₁₂₇

Ver.2004-01-06

- 66 -

NJU6824

(15-8) Display Control (2)

The “Display Control (2)” instruction controls display conditions.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

0

D₄

1

D₃

D₂

D₁

D₀

*

1

0

REV NLIN SWAP

(Default: [REV,NLIN,SWAP]=0H / Register Address: 9H)

D₁(SWAP)

This bit swaps palettes Aj and palettes Cj (j=0-15). This function reduces the restrictions on the IC position of an

LCD module. For more information, refer to “(17) SWAP FUNCTION”.

SWAP=0

SWAP=1

: SWAP OFF

: SWAP ON

D₂(NLIN)

This bit enables the N-line inversion.

NLIN=0

NLIN=1

: N-line Inversion OFF

: N-line Inversion ON

(FR toggles by the frame.)

(FR toggles once every N lines.)

D₃(REV)

This bit enables the reverse display function that reverses the polarities of all display data without changing the

DDRAM.

REV=0

REV=1

: Reverse Display OFF

: Reverse Display ON

(Normal)

Table 23 Reverse Display ON/OFF

REV

Display

DDRAM Data → Display Data

0

1

0

1

0

1

0

Normal

1

Reverse

Ver.2004-01-06

- 67 -

NJU6824

(15-9) Increment/Decrement Control

The “HV”, “XD” and “YD” bits set either auto-increment or auto-decrement mode to the column address and row

address individually. Once this mode is set up, the column address, row address or both are automatically counted up or

down, whenever the DDRAM is accessed. This instruction is used for the window area setting as well as the “Window

Start Column/Row Address” and “Window End Column/Row Address” instructions. The display-rotation function or the

mirror-inversion function is also enabled by this setting. For more information, refer to “(4-3) DDRAM Access

Direction”.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

1

0

AIM

HV

XD

YD

(Default: [AIM,HV,XD,YD]=0H / Register Address: AH)

D₀(YD), D₁(XD), D₂(HV)

Table 24 Horizontal/Vertical & Increment/Decrement

HV

0

XD

0

YD

0

X

Y

Direction

Increment

Decrement

Increment

Decrement

Increment

Decrement

Increment

Decrement

Increment

Decrement

Increment

Decrement

0

1

Horizontal

0

1

0

1

0

1

0

1

Vertical

1

0

1

D₃(AIM)

Table 25 Read-modify-write ON/OFF

AIM

Increment Mode

NOTE

0

1

Read-modify-write OFF

Read-modify-write ON

1

2

NOTE1) Increment or decrement in writing and reading display data

NOTE2) Increment or decrement in writing display data only

Ver.2004-01-06

- 68 -

NJU6824

(15-10) Power Control

CSb RS RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

1

D₄

1

D₃

D₂

D₁

DCON

D₀

ACL

0

1

0

AMPON HALT

(Default: [AMPON,HALT,DCON,ACL]=0H / Register Address: BH)

D₀(ACL)

This bit initializes the internal LCD power supply.

ACL=0

ACL=1

: Initialization OFF (Normal)

: Initialization ON

NOTE) During the initialization, “1” is read out as the status of the “ACL” bit by the “Register Read” instruction. After the

initialization, it is “0”. As the CLK triggers the initialization, the “wait time” at least equivalent to 2 cycles of the CLK is

required for the next instruction.

D₁(DCON)

The “DCON” bit activates the voltage booster.

DCON=0

DCON=1

: Voltage Booster OFF

: Voltage Booster ON

D₂(HALT)

The “HALT” bit enables the power save mode. During the power save, operating current is down to the stand-by

level. The internal state of the LSI in the power save mode is listed below.

HALT=0

HALT=1

: Power Save OFF (Normal)

: Power Save ON

Internal State in Power Save Mode (HALT=”1”)

- Internal oscillator and internal LCD power supply are halted.

- All segment and common drivers are fixed at V_SSHlevel.

- External clock to the OSC1 cannot be accepted.

- Display data in the DDRAM is being maintained.

- Data in the instruction registers are being maintained.

- V_LCD, V₁, V₂, V₃and V₄are in high impedance.

NOTE) In the power save ON sequence, execute the “Display OFF” prior to the “Power Save ON”. In the power save OFF

sequence, execute the “Power save OFF” prior to the “Display ON”. If the “Power Save ON/OFF” instruction is

executed during the “Display ON”, unexpected pixels may be turned on instantly.

D₃(AMPON)

The “AMPON” bit activates the voltage converter which includes the reference voltage generator, the voltage

regulator and the LCD bias generator.

AMPON=0 : Voltage Converter OFF

AMPON=1 : Voltage Converter ON

Ver.2004-01-06

- 69 -

NJU6824

(15-11) Duty Cycle Ratio

The “Duty Cycle Ratio” instruction selects LCD duty cycle ratio, and is used to carry out the partial display in

combination with other instructions such as the “Boost Level”, the “LCD Bias Ratio” and the “EVR Control”.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

1

0

DS3 DS2 DS1 DS0

(Default: DS3-DS0=0H / Register Address: CH)

Table 26 Duty Cycle Ratio

Duty Cycle Ratio

DS3

DS2

DS1

DS0

# of Commons

DSE=0

DES=1

1/128

1/120

1/112

1/104

1/96

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1/129

1/121

1/113

1/105

1/97

1/89

1/81

1/73

1/65

1/57

1/49

1/41

1/33

1/25

1/17

128 commons

120 commons

112 commons

104 commons

96 commons

88 commons

80 commons

72 commons

64 commons

56 commons

48 commons

40 commons

32 commons

24 commons

16 commons

1/88

1/80

1/72

1/64

1/56

1/48

1/40

1/32

1/24

1/16

Inhibited

NOTE) Duty cycle ratio is subtracted by 1 (Duty-1) from the original duty cycle ratio by setting “1” at the D₁(DSE) bit of the

“Duty-1 ON/OFF” instruction. Refer to “(15-17) Duty-1 /Display Clock ON/OFF”.

(15-12) Boost Level

The “Boost level” selects the multiple of the voltage booster.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

1

D₅

0

D₄

1

D₃

*

D₂

D₁

D₀

1

0

VU2 VU1 VU0

(Default: VU2-VU0=0H / Register Address: DH)

Table 27 Boost Level

VU2

0

VU1

0

VU0

0

Boost Level

1 time (No boost)

2 times

0

1

0

1

0

3 times

0

1

4 times

1

0

5 times

1

0

1

6 times

1

0

Inhibited

1

Inhibited

Ver.2004-01-06

- 70 -

NJU6824

(15-13) LCD Bias Ratio

The “LCD bias ratio” selects LCD bias ratio.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

1

D₅

1

D₄

0

D₃

*

D₂

D₁

D₀

1

0

B2

B1

B0

(Default: B2-B0=0H / Register Address: EH)

Table 28 LCD Bias Ratio

B2

0

B1

0

B0

0

LCD Bias Ratio

1/9

1/8

0

1

0

1

0

1/7

0

1

1/6

1

0

1/5

1

0

1

1/10

1/11

1/12

1

0

1

(15-14) Instruction Table Select

This instruction specifies an instruction table, and should be executed prior to other instructions.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

0/1 0/1 0/1

D₇

1

D₆

1

D₅

1

D₄

1

D₃

D₂

D₁

D₀

1

0

TST0 RE2 RE1 RE0

(Default: TST0, RE2-RE0=0H / Register Address: FH)

Table 29 Instruction Table Select

RE2

0

RE1

0

RE0

0

Instructions

Instruction Table (0)

Instruction Table (1)

Instruction Table (2)

Instruction Table (3)

Instruction Table (4)

Instruction Table (5)

0

1

0

1

0

1

0

1

0

1

NOTE) “TST0” bit must be “0”. This is used for maker tests only.

Ver.2004-01-06

- 71 -

NJU6824

(15-15) Palette A / B / C

Palette A0 (PS=0) / Palette A8 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PA03/ PA02/ PA01/ PA00/

1

0

1

PA83 PA82 PA81 PA80

(Register Address: 0H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PA04/

1

0

1

PA84

(Register Address: 1H)

Palette A1 (PS=0) / Palette A9 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PA13/ PA12/ PA11/ PA10/

1

0

1

PA93 PA92 PA91 PA90

(Register Address: 2H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PA14/

1

0

1

PA94

(Register Address: 3H)

Palette A2 (PS=0) / Palette A10 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PA23/ PA22/ PA21/ PA20/

1

0

1

PA103 PA102 PA101 PA100

(Register Address: 4H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PA24/

1

0

1

PA104

(Register Address: 5H)

Palette A3 (PS=0) / Palette A11 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PA33/ PA32/ PA31/ PA30/

1

0

1

PA113 PA112 PA111 PA110

(Register Address: 6H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PA34/

1

0

1

PA114

(Register Address: 7H)

Palette A4 (PS=0) / Palette A12 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PA43/ PA42/ PA41/ PA40/

1

0

1

PA123 PA122 PA121 PA120

(Register Address: 8H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PA44/

1

0

1

PA124

(Register Address: 9H)

NOTE) Refer to the tables in “(6) GRAYSCALE PALETTE” for default setting.

Ver.2004-01-06

- 72 -

NJU6824

Palette A5 (PS=0) / Palette A13 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PA53/ PA52/ PA51/ PA50/

1

0

1

PA133 PA132 PA131 PA130

(Register Address: AH)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PA54/

1

0

1

PA134

(Register Address: BH)

Palette A6 (PS=0) / Palette A14 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PA63/ PA62/ PA61/ PA60/

1

0

1

PA143 PA142 PA141 PA140

(Register Address: CH)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

1

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PA64/

1

0

1

PA144

(Register Address: DH)

Palette A7 (PS=0) / Palette A15 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PA73/ PA72/ PA71/ PA70/

1

0

1

0

PA153 PA152 PA151 PA150

(Register Address: 0H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PA74/

1

0

1

0

PA154

(Register Address: 1H)

NOTE) Refer to the tables in “(6) GRAYSCALE PALETTE” for default setting.

Ver.2004-01-06

- 73 -

NJU6824

Palette B0 (PS=0) / Palette B8 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PB03/ PB02/ PB01/ PB00/

1

0

1

0

PB83 PB82 PB81 PB80

(Register Address: 2H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PB04/

1

0

1

0

PB84

(Register Address: 3H)

Palette B1 (PS=0) / Palette B9 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PB13/ PB12/ PB11/ PB10/

1

0

1

0

PB93 PB92 PB91 PB90

(Register Address: 4H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PB14/

1

0

1

0

PB94

(Register Address: 5H)

Palette B2 (PS=0) / Palette B10 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PB23/ PB22/ PB21/ PB20/

1

0

1

0

PB103 PB102 PB101 PB100

(Register Address: 6H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PB24/

1

0

1

0

PB104

(Register Address: 7H)

Palette B3 (PS=0) / Palette B11 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PB33/ PB32/ PB31/ PB30/

1

0

1

0

PB113 PB112 PB111 PB110

(Register Address: 8H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PB34/

1

0

1

0

PB114

(Register Address: 9H)

Palette B4 (PS=0) / Palette B12 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PB43/ PB42/ PB41/ PB40/

1

0

1

0

PB123 PB122 PB121 PB120

(Register Address: AH)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PB44/

1

0

1

0

PB124

(Register Address: BH)

NOTE) Refer to the tables in “(6) GRAYSCALE PALETTE” for default setting.

Ver.2004-01-06

- 74 -

NJU6824

Palette B5 (PS=0) / Palette B13 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PB53/ PB52/ PB51/ PB50/

1

0

1

0

PB133 PB132 PB131 PB130

(Register Address: CH)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

1

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PB54/

1

0

1

0

PB134

(Register Address: DH)

Palette B6 (PS=0) / Palette B14 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PB63/ PB62/ PB61/ PB60/

1

0

1

PB143 PB142 PB141 PB140

(Register Address: 0H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PB64/

1

0

1

PB144

(Register Address: 1H)

Palette B7 (PS=0) / Palette B15 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PB73/ PB72/ PB71/ PB70/

1

0

1

PB153 PB152 PB151 PB150

(Register Address: 2H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PB74/

1

0

1

PB154

(Register Address: 3H)

NOTE) Refer to the tables in “(6) GRAYSCALE PALETTE” for default setting.

Ver.2004-01-06

- 75 -

NJU6824

Palette C0 (PS=0) / Palette C8 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PC03/ PC02/ PC01/ PC00/

1

0

1

PC83 PC82 PC81 PC80

(Register Address: 4H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PC04/

1

0

1

PC84

(Register Address: 5H)

Palette C1 (PS=0) / Palette C9 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PC13/ PC12/ PC11/ PC10/

1

0

1

PC93 PC92 PC91 PC90

(Register Address: 6H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PC14/

1

0

1

PC94

(Register Address: 7H)

Palette C2 (PS=0) / Palette C10 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PC23/ PC22/ PC21/ PC20/

1

0

1

PC103 PC102 PC101 PC100

(Register Address: 8H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PC24/

1

0

1

PC104

(Register Address: 9H)

Palette C3 (PS=0) / Palette C11 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PC33/ PC32/ PC31/ PC30/

1

0

1

PC113 PC112 PC111 PC110

(Register Address: AH)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PC34/

1

0

1

PC114

(Register Address: BH)

Palette C4 (PS=0) / Palette C12 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PC43/ PC42/ PC41/ PC40/

1

0

1

PC123 PC122 PC121 PC120

(Register Address: CH)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

1

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PC44/

1

0

1

PC124

(Register Address: DH)

NOTE) Refer to the tables in “(6) GRAYSCALE PALETTE” for default setting.

Ver.2004-01-06

- 76 -

NJU6824

Palette C5 (PS=0) / Palette C13 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PC53/ PC52/ PC51/ PC50/

1

0

1

0

PC133 PC132 PC131 PC130

(Register Address: 0H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PC54/

1

0

1

0

PC134

(Register Address: 1H)

Palette C6 (PS=0) / Palette C14 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PC63/ PC62/ PC61/ PC60/

1

0

1

0

PC143 PC142 PB141 PB140

(Register Address: 2H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

1

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PC64/

1

0

1

0

PC144

(Register Address: 3H)

Palette C7 (PS=0) / Palette C15 (PS=1)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

PC73/ PC72/ PC71/ PC70/

1

0

1

0

PC153 PC152 PC151 PC150

(Register Address: 4H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

0

D₄

1

D₃

*

D₂

*

D₁

*

D₀

PC74/

1

0

1

0

PC154

(Register Address: 5H)

NOTE) Refer to the tables in “(6) GRAYSCALE PALETTE” for default setting.

Ver.2004-01-06

- 77 -

NJU6824

(15-16) Initial COM

The “Initial COM” instruction specifies the common driver for a scan start common.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

1

D₄

0

D₃

D₂

D₁

D₀

1

0

1

0

SC3 SC2 SC1 SC0

(Default: SC3-SC0=0H / Register Address: 6H)

Table 30 Initial COM

SC3

0

SC2

0

SC1

0

SC0

0

Initial COM (SHIFT=0)

COM₀

Initial COM (SHIFT=1)

COM₁₂₇

COM₁₂₃

COM₁₁₉

COM₁₁₁

COM₁₀₃

COM₉₅

0

1

COM₄

0

1

0

COM₈

0

1

COM₁₆

0

1

0

COM₂₄

0

1

0

1

COM₃₂

0

1

0

COM₄₀

COM₈₇

0

1

COM₄₈

COM₇₉

1

0

COM₅₆

COM₇₁

1

0

1

COM₆₄

COM₆₃

1

0

1

0

COM₇₂

COM₅₅

1

0

1

COM₈₀

COM₄₇

1

0

COM₈₈

COM₃₉

1

0

1

COM₉₆

COM₃₁

1

0

COM₁₀₄

COM₁₁₂

COM₂₃

1

COM₁₅

(15-17) Duty-1 /Display Clock ON/OFF

This instruction controls ON (Duty-1) /OFF (Duty-0) and Display Clock ON/OFF.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

1

D₄

1

D₃

*

D₂

*

D₁

D₀

1

0

1

0

DSE SON

(Default: SON,DSE=0H / Register Address: 7H)

D₀(SON)

SON=0

SON=1

: CL, FLM, FR, and CLK are fixed at “L” level.

: CL, FLM, FR, and CLK are enabled.

D₁(DSE)

The duty cycle ratio is subtracted by 1 (Duty-1) from the original duty cycle ratio by setting “1” at the “DSE” bit.

DSE=0

DSE=1

: OFF (Duty-0)

: ON (Duty-1)

NOTE) For the last common timing at “DSE=0”, all common drivers generate non-selective waveforms, and segment drivers

generate the same waveforms as for the previous common timing. For instance, in 1/129 duty cycle, the segment

waveforms for 129^thcommon timing are the same as for 128^thcommon timing (last line).

(15-18) Display Mode Control /Boost Clock Control

The “Display Mode Control” instruction sets up display modes such as the variable or fixed grayscale mode and the

variable 8- or 16-grayscale mode. The D₂(MON) bit of the “Display Control (1)” is used in combination. Refer to “(5)

GRAY SCALE CONTROL CIRCUIT” and “(15-7) Display Control (1).” The D₁and D₀(FDC1 and FDC2) bits set the

boost clock.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

1

0

1

0

PWM C256 FDC1 FDC2

(Default: PWM,C256=0H / Register Address: 8H)

Ver.2004-01-06

- 78 -

NJU6824

D₃(PWM)

PWM=0

PWM=1

: Variable grayscale Mode (Variable 8-/16-grayscale Mode)

: Fixed 8-grayscale Mode

D₂(C256)

C256=0

C256=1

: Variable 16-grayscale Mode at “PWM=0” (4096 colors)

: Variable 8-grayscale Mode at “PWM=0” (256 colors)

D₁, D₀(FDC1, FDC2)

Table 31 FDC1, FDC2

FDC1 FDC2

Boost Clock

0

1

0

1

0

1

1x

2x

4x

1/2x

(15-19) Bus Length

This instruction selects 8- or 16-bit bus length, and sets oscillator configuration as well.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

0

D₄

1

D₃

*

D₂

D₁

D₀

1

0

1

0

ABS CKS WLS

(Default: ABS,CKS,WLS=0H / Register Address: 9H)

D₀(WLS)

WLS=0: 8-bit Bus Length

WLS=1: 16-bit Bus Length

D₁(CKS)

CKS =0: Internal Oscillator using an internal resistor

CKS =1: External Clock, or Internal Oscillator using an external resistor

NOTE) Refer to “(11) OSCILLATOR”.

D₂(ABS)

ABS=0: ABS Mode OFF (Normal)

ABS=1: ABS Mode ON

(15-20) EVR Control

The “EVR Control” instruction adjusts V_LCDto optimize display contrast. This instruction is finally effective when

both upper and lower bytes are transmitted in order to prevent high V_LCD. The setting order is upper byte first, then lower

byte. Refer to “(12-2-3) Electrical Variable Resistor (EVR)”.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

1

0

1

0

DV₃

DV₂

DV₁

DV0

(Default: DV₃-DV0=0H / Register Address: AH)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

1

D₄

1

D₃

*

D₂

D₁

D₀

1

0

1

0

DV6

DV₅

DV₄

(Default: DV6-DV₄=0H / Register Address: BH)

Table 32 EVR Control

DV6

0

DV₅

0

DV₄

0

DV₃

DV₂

0

DV₁

0

DV0

0

V_LCD

0

:

Low

0

1

:

1

High

Ver.2004-01-06

- 79 -

NJU6824

Formula of VLCD

V_LCD[V] = 0.5x V_REG+ M (V_REG– 0.5x V_REG) / 127

V

_BA= VEE x 0.9

V_BA

V_REF

V_REG

N

: Output of the reference voltage generator

: Input of the voltage regulator

: Output of the voltage regulator

: Boost level

V_REG= VREF x N

M

: EVR Value

(15-21) Frequency Control

The “Frequency Control” instruction adjusts the frame frequency.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

1

D₅

0

D₄

1

D₃

*

D₂

D₁

D₀

1

0

1

0

Rf2

Rf1

Rf0

(Default: DV₃-DV0=0H / Register Address: DH)

Table 33 Frequency Control

Rf 2

0

Rf 1

0

Rf 0

0

Feedback Resistor Value

Reference Value

0

1

0.8 x Reference Value

0.9 x Reference Value

1.1 x Reference Value

1.2 x Reference Value

0.7 x Reference Value

1.3 x Reference Value

Inhibited

0

1

0

1

0

1

0

1

0

1

(15-22) Discharge ON/OFF

Discharge circuit is used to discharge out of the stabilizing capacitors placed on the V_LCD, V₁, V₂, V₃,V₄and V_OUT

.

Refer to “(12-4) Discharge Circuit”.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

1

D₅

1

D₄

0

D₃

*

D₂

*

D₁

D₀

1

0

1

0

DIS2 DIS

(Default: DIS2,DIS1=0H / Register Address: EH)

D₀(DIS)

DIS=0

: Discharge OFF

: Discharge ON

DIS=1

(Discharge from V_LCD, V₁, V₂, V₃and V₄)

D₁(DIS2)

DIS2=0

: Discharge OFF

: Discharge ON

DIS2=1

(Discharge from V_OUTthrough the internal resistor between V_OUTand V_EE)

NOTE) Resistance is 100KΩ typical.

Ver.2004-01-06

- 80 -

NJU6824

(15-23) Register Address

The “Register Address” instruction specifies a register address.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

1

0

1

0

RA3 RA2 RA1 RA0

(Default: RA3-RA0=BH / Register Address: CH)

(15-24) Register Read

The “Register Read” instruction reads out instruction data from the register which address is specified by the

“Register Address” instruction.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

0/1 0/1 0/1

D₇

*

D₆

*

D₅

*

D₄

*

D₃

D₂

D₁

D₀

0

1

Internal register data read

(15-25) Window End Column Address

The “Window End Column Address” instruction specifies the column address of the end point. Refer to “(4-2)

Window Area for DDRAM Access”. The setting order is lower byte first, then upper byte.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

0

D₄

0

D₃

D₂

D₁

D₀

1

0

1

0

1

EX3 EX2 EX1 EX0

(Default: EX3-EX0=0H / Register Address: 0H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

0

D₄

1

D₃

D₂

D₁

D₀

1

0

1

0

1

EX7 EX6 EX5 EX4

(Default: EX7-EX4=0H / Register Address: 1H)

(15-26) Window End Row Address

The “Window End Row Address” instruction specifies the row address of the end point. Refer to “(4-2) Window

Area for DDRAM Access”. The setting order is lower byte first, then upper byte.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

1

0

1

0

1

EY3 EY2 EY1 EY0

(Default: EY3-EY0=0H / Register Address: 2H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

0

D₅

1

D₄

1

D₃

*

D₂

D₁

D₀

1

0

1

0

1

EY6 EY5 EY4

(Default: EY6-EY4=0H / Register Address: 3H)

(15-27) Initial Line-reverse Address

The “Initial Line-reverse Address” instruction specifies the start line of the line-reverse display area. The setting

order is lower byte first, then upper byte.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

0

D₄

0

D₃

D₂

D₁

D₀

1

0

1

0

1

LS3

LS2

LS1

LS0

(Default: LS3-LS0=0H / Register Address: 4H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

0

D₄

1

D₃

*

D₂

D₁

D₀

1

0

1

0

1

LS6

LS5

LS4

(Default: LS6-LS4=0H / Register Address: 5H)

Ver.2004-01-06

- 81 -

NJU6824

(15-28) Last Line-reverse Address

The “Last Line-reverse Address” instruction specifies the end line of the line-reverse display area. The setting order

is lower byte first, then upper byte.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

1

D₄

0

D₃

D₂

D₁

D₀

1

0

1

0

1

LE3

LE2

LE1

LE0

(Default: LE3-LE0=0H / Register Address: 6H)

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

0

D₆

1

D₅

1

D₄

1

D₃

*

D₂

D₁

D₀

1

0

1

0

1

LE6

LE5

LE4

(Default: LE6-LE4=0H / Register Address: 7H)

(15-29) Line Reverse ON/OFF

The “Line Reverse ON/OFF” instruction enables the line-reverse display, and blink function as well. Note that the

line reverse display cannot be used for entire display area. In this case, use the reverse display function by the D₃(REV)

bit of the “Display Control (2)” instruction.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

0

D₄

0

D₃

*

D₂

*

D₁

D₀

1

0

1

0

1

BT LREV

(Default: BT,LREV=0H / Register Address: 8H)

D₀(LREV)

LREV =0

LREV =1

: Line Reverse OFF (Normal)

: Line Reverse ON

D₁(BT)

BT =0

BT =1

: No Blink

: Blink once every 32 frames

NJRC

STN COLOR

←

Initial Line-reverse Address

Last Line-reverse Address

LCD DRIVER

LOW POWER

Blink / 32 Frames

HIGH PERFORMANCE

Fig 20 On-screen Image in Using Line-reverse Display and Blink Function

Ver.2004-01-06

- 82 -

NJU6824

(15-30) Upper/Lower Palette Select /Icon Segment Access ON/OFF

The “Upper/Lower Palette Select” instruction selects either upper or lower palette register.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

0

D₄

1

D₃

*

D₂

*

D₁

D₀

1

0

1

0

1

ICON PS

(Default: PS=0 / Register Address: 9H)

D₀(PS)

PS=0

PS=1

: Lower Palettes (PA00, PA01, PA02, PA03, …, PC74)

: Upper Palettes (PA80, PA81, PA82, PA83, …, PC154)

D₁(ICON)

ICON=0

ICON=1

: Icon Segment Access OFF (DDRAM Access)

: Icon Segment Access ON

NOTE) The Icon segment access is enabled by setting “1” at the D₁(ICON) bit of this instruction, then the address (00H) or

(01H) should be specified by the “Window Start Column Address” instruction.

(15-31) PWM Control

The “PWM control” instruction selects PWM type, as shown in Fig 21.

CSb

0

RS

1

RDb WRb RE2 RE1 RE0

D₇

1

D₆

0

D₅

1

D₄

0

D₃

D₂

D₁

D₀

PWM PWM PWM PWM

1

0

1

0

1

S

A

B

C

(Default: PWMS,PWMA,PWMB,PWMC=0H / Register Address: AH)

D₃(PWMS)

PWMS=0

PWMS=1

: Type 1

: Type 2

D₂(PWMA), D₁(PWMB), D₀(PWMC)

PWMZ=0 (Z=A, B and C): Type 1-O

PWMZ=1 (Z=A, B and C): Type 1-E

PWM Type 1 (PWMS=0)

Odd Line

Even Line

CL

V_LCD

V₂

Type-0

Type-E

SEG

V_LCD

V₂

PWM Type 2 (PWMS=1)

CL

V_LCD

SEG

V₂

Fig 21 PWM Control

Ver.2004-01-06

- 83 -

NJU6824

(16) PARTIAL DISPLAY FUNCTION

The partial display function activates specified area on an LCD screen, or equivalently, common drivers are simply

scanning this specified area. This function allows LCD modules to work in a minimum duty cycle ratio to minimize

power consumption. The partial display function is carried out by the combination of the “Duty Cycle Ratio”, “LCD Bias

Ratio”, “Boost Level” and “EVR Control” instructions. For more information, refer to “(15-11) Duty Cycle Ratio”,

“(15-12) Boost Level”, “(15-13) LCD Bias Ratio” and “(15-20) EVR Control”. Typical setting sequence is shown in

“(19-4) Partial Display Sequence”.

NJRC

LCD DRIVER

Low Power and

Low Voltage

LCD DRIVER

Normal

Partial Display

Fig 22 On-screen Image in Using Partial Display Function

(17) SWAP FUNCTION

The swap function switches the palettes Aj and the palettes Cj (j=0-15), and is controlled by the D₁(SWAP) bit of

the “Display Control (2)” instruction. This function reduces the restrictions on the IC position of an LCD module. Fig 23

“Overview of Swap Function” illustrates general outlines of internal operations, and (17-1-1) through (17-1-4) show

each configuration on a mode-by-mode basis.

SWAP=“0”

SWAP=“1”

- Swapping palette A and palette C

LCD Panel

- Default

LCD Panel

1 RGB

SEG SEG SEG

A127 B127 C127

SEG SEG SEG

A127 B127 C127

SEG Driver

A0

B0

C0

A0

B0

C0

(00H)

(7FH)

(00H)

B

(7FH)

Selected Palette

A

B

C

A

B

C

A

C

A

B

C

Grayscale

Control

Grayscale

Control

Circuit

DATA

(00H)

DATA

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

(00H)

(7FH)

Display Data

in DDRAM

Display Dat a

in DDRAM

LSB

MSB

LSB

MSB

DATA

Display Data

from CPU

Display Dat a

from CPU

DATA

(00H)

DATA

(7FH)

DATA

(00H)

DATA

(7FH)

MSB

LSB

MSB

LSB

MSB

LSB

SEG SEG SEG

SEG Driver

:SEGAi, SEGBi, SEGCi (i=127)

Ai

Bi

Ci

A

B

C

Selected Palette :Palette Aj, Palette Bj, Palette Cj (j=0-15)

:Column Address

(00H) – (7FH)

Fig 23 Overview of SWAP Function

Ver.2004-01-06

- 84 -

NJU6824

(17-1) Swap Function in Variable 16-grayscale Mode

16-bit Bus Length

SWAP=0

SEGAi

SEGBi

SEGCi

(i=0-127)

⇑

0/31 (Default)

⇑

7/31 (Default)

⇑

31/31 (Default)

⇑

Grayscale Level

Palette A0

Palette B3

Palette C15

Grayscale Palette

↑

0

↑

0

↑

0

↑

1

↑

1

↑

1

0

1

Display Data

in Grayscale Control Circuit

MSB

↑

LSB

↑

MSB

↑

LSB

↑

MSB

↑

LSB

↑

0

1

Display Data

from MPU to LSI

D₁₅

D₁₁

D₁₄

D₁₀

D₁₃

D₉

D₁₂

D₈

D₁₀

D₇

D₉

D₆

D₈

D₅

D₇

D₄

D₃

D₂

D₁

D₀

ABS=1

SWAP=1

SEGAi

SEGBi

SEGCi

(i=0-127)

⇑

7/31 (Default)

⇑

0/31 (Default)

⇑

31/31 (Default)

⇑

Grayscale Level

Grayscale Palette

Palette C15

Palette B3

Palette A0

↑

1

↑

1

↑

0

↑

0

↑

1

0

Display Data

in Grayscale Control Circuit

LSB

MSB

LSB

MSB

LSB

MSB

|

0

1

Display Data

from MPU to LSI

D₁₅

D₁₁

D₁₄

D₁₀

D₁₃

D₉

D₁₂

D₈

D₁₀

D₇

D₉

D₆

D₈

D₅

D₇

D₄

D₃

D₂

D₁

D₀

ABS=1

NOTE1) Without a special note on the left, the ABS and C256 bits are regarded as “0”.

Ver.2004-01-06

- 85 -

NJU6824

8-bit Bus Length

SWAP=0

SEGAi

SEGBi

SEGCi

(i=0-127)

⇑

7/31 (Default)

⇑

0/31 (Default)

⇑

31/31 (Default)

⇑

Grayscale Level

Grayscale Palette

Palette A0

Palette B3

Palette C15

↑

0

↑

0

↑

0

↑

1

↑

1

↑

1

0

1

Display Data

in Grayscale Control Circuit

MSB

↑

LSB

↑

MSB

↑

LSB

↑

MSB

↑

LSB

↑

0

1

Display Data

from MPU to LSI

D₇

D₃

D₆

D₂

D₅

D₁

D₄

D₀

D₂

D₇

D₁

D₆

D₀

D₅

D₇

D₄

D₃

D₂

D₁

D₀

ABS=1

SWAP=1

SEGAi

SEGBi

SEGCi

(i=0-127)

⇑

7/31 (Default)

⇑

0/31 (Default)

⇑

31/31 (Default)

⇑

Grayscale Level

Palette C15

Palette B3

Palette A0

Grayscale Palette

↑

1

↑

1

↑

0

↑

0

↑

1

0

Display Data

in Grayscale Control Circuit

LSB

MSB

LSB

MSB

LSB

MSB

|

0

1

Display Data

from MPU to LSI

D₇

D₃

D₆

D₂

D₅

D₁

D₄

D₀

D₂

D₇

D₁

D₆

D₀

D₅

D₇

D₄

D₃

D₂

D₁

D₀

ABS=1

NOTE1) Without a special note on the left, the ABS and C256 bits are regarded as “0”.

Ver.2004-01-06

- 86 -

NJU6824

(17-2) Swap Function in Variable 8-Grayscale Mode

8-bit Bus Length

SWAP=0

SEGAi

SEGBi

SEGCi

(i=0-127)

⇑

3/31 (Default)

⇑

7/31 (Default)

⇑

31/31 (Default)

⇑

Grayscale Level

Palette A0

Palette B3

Palette C15

Grayscale Palette

↑

0

↑

*

↑

0

↑

*

↑

1

↑

*

0

1

*

Display Data

in Grayscale Control Circuit

MSB

↑

LSB

↑

MSB

↑

LSB

↑

MSB

↑

LSB

↑

0

↑

0

↑

0

↑

1

↑

1

↑

*

0

*

0

*

1

*

Display Data

from MPU to LSI

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

SWAP=1

SEGAi

SEGBi

SEGCi

(i=0-127)

⇑

7/31 (Default)

⇑

3/31 (Default)

⇑

31/31 (Default)

⇑

Grayscale Level

Grayscale Palette

Palette C15

Palette B3

Palette A0

↑

1

↑

*

↑

0

↑

*

↑

*

1

0

Display Data

in Grayscale Control Circuit

LSB

MSB

LSB

MSB

LSB

MSB

|

0

*

0

1

*

1

*

Display Data

from MPU to LSI

D₇

D₆

D₅

D₄

D₃

D₂

D₁

D₀

NOTE1) Without a special note on the left, the ABS and C256 bits are regarded as “0”.

Ver.2004-01-06

- 87 -

NJU6824

(17-3) Swap Function in Fixed 8-grayscale Mode

16-bit Bus Length

SWAP=0

SEGAi

SEGBi

SEGCi

(i=0-127)

⇑

0/7

⇑

1/7

⇑

7/7

⇑

Grayscale Level

-

↑

0

↑

0

↑

0

↑

1

↑

1

↑

1

0

1

Display Data

in Grayscale Control Circuit

MSB

↑

LSB

↑

MSB

↑

LSB

↑

MSB

↑

LSB

↑

0

1

Display Data

from MPU to LSI

D₁₅

D₁₁

D₁₄

D₁₀

D₁₃

D₉

D₁₂

D₈

D₁₀

D₇

D₉

D₆

D₈

D₅

D₇

D₄

D₃

D₂

D₁

D₀

ABS=1

SWAP=1

SEGAi

SEGBi

SEGCi

(i=0-127)

⇑

7/7

⇑

1/7

⇑

0/7

⇑

Grayscale Level

-

↑

1

↑

1

↑

0

↑

0

↑

1

0

Display Data

in Grayscale Control Circuit

LSB

MSB

LSB

MSB

LSB

MSB

|

0

1

Display Data

from MPU to LSI

D₁₅

D₁₁

D₁₄

D₁₀

D₁₃

D₉

D₁₂

D₈

D₁₀

D₇

D₉

D₆

D₈

D₅

D₇

D₄

D₃

D₂

D₁

D₀

ABS=1

NOTE1) Without a special note on the left, the ABS and C256 bits are regarded as “0”.

NOTE2) The data indicated with a slash mark ( / ) is invalid.

Ver.2004-01-06

- 88 -

NJU6824

8-bit Bus Length

SWAP=0

SEGAi

SEGBi

SEGCi

(i=0-127)

⇑

0/7

⇑

1/7

⇑

7/7

⇑

Grayscale Level

-

↑

0

↑

0

↑

0

↑

1

↑

1

↑

1

0

1

Display Data

in Grayscale Control Circuit

MSB

↑

LSB

↑

MSB

↑

LSB

↑

MSB

↑

LSB

↑

0

1

Display Data

from MPU to LSI

D₇

D₃

D₇

D₆

D₂

D₆

D₅

D₁

D₅

D₄

D₀

*

D₂

D₇

D₄

D₁

D₆

D₃

D₀

D₅

D₂

D₇

D₄

*

D₄

D₃

D₁

D₃

D₂

D₀

D₂

D₁

*

D₁

D₀

*

ABS=1

C256=1

SWAP=1

SEGAi

SEGBi

SEGCi

(i=0-127)

⇑

7/7

⇑

1/7

⇑

0/7

⇑

Grayscale Level

-

↑

1

↑

1

↑

0

↑

0

↑

1

0

Display Data

in Grayscale Control Circuit

LSB

MSB

LSB

MSB

LSB

MSB

|

0

1

Display Data

from MPU to LSI

D₇

D₃

D₇

D₆

D₂

D₆

D₅

D₁

D₅

D₄

D₀

*

D₂

D₇

D₄

D₁

D₆

D₃

D₀

D₅

D₂

D₇

D₄

*

D₄

D₃

D₁

D₃

D₂

D₀

D₂

D₁

*

D₁

D₀

*

ABS=1

C256=1

NOTE1) Without a special note on the left, the ABS and C256 bits are regarded as “0”.

NOTE2) The data indicated with a slash mark ( / ) is invalid.

Ver.2004-01-06

- 89 -

NJU6824

(17-4) Swap Function in B&W Mode

16-bit Bus Length

SWAP=0

SEGAi

SEGBi

SEGCi

(i=0-127)

⇑

0/1 (OFF)

1/1 (ON)

Grayscale Level

⇑

-

↑

0

↑

0

↑

0

↑

1

↑

1

↑

1

0

1

Display Data

in Grayscale Control Circuit

MSB

↑

LSB

↑

MSB

↑

LSB

↑

MSB

↑

LSB

↑

0

1

Display Data

from MPU to LSI

D₁₅

D₁₁

D₁₄

D₁₀

D₁₃

D₉

D₁₂

D₈

D₁₀

D₇

D₉

D₆

D₈

D₅

D₇

D₄

D₃

D₂

D₁

D₀

ABS=1

SWAP=1

SEGAi

SEGBi

SEGCi

(i=0-127)

⇑

1/1 (ON)

0/1 (OFF)

Grayscale Level

⇑

-

↑

1

↑

1

↑

0

↑

0

↑

1

0

Display Data

in Grayscale Control Circuit

LSB

MSB

LSB

MSB

LSB

MSB

|

0

1

Display Data

from MPU to LSI

D₁₅

D₁₁

D₁₄

D₁₀

D₁₃

D₉

D₁₂

D₈

D₁₀

D₇

D₉

D₆

D₈

D₅

D₇

D₄

D₃

D₂

D₁

D₀

ABS=1

NOTE1) Without a special note on the left, the ABS and C256 bits are regarded as “0”.

NOTE2) The data indicated with a slash mark ( / ) is invalid.

Ver.2004-01-06

- 90 -

NJU6824

8-bit Bus Length

SWAP=0

SEGAi

SEGBi

SEGCi

(i=0-127)

⇑

0/1 (OFF)

1/1 (ON)

Grayscale Level

-

↑

0

↑

0

↑

0

↑

1

↑

1

↑

1

0

1

Display Data

in Grayscale Control Circuit

MSB

↑

LSB

↑

MSB

↑

LSB

↑

MSB

↑

LSB

↑

0

1

Display Data

from MPU to LSI

D₇

D₃

D₇

D₆

D₂

D₆

D₅

D₁

D₅

D₄

D₀

*

D₂

D₇

D₄

D₁

D₆

D₃

D₀

D₅

D₂

D₇

D₄

*

D₄

D₃

D₁

D₃

D₂

D₀

D₂

D₁

*

D₁

D₀

*

ABS=1

C256=1

SWAP=1

SEGAi

SEGBi

SEGCi

(i=0-127)

⇑

1/1 (ON)

0/1 (OFF)

Grayscale Level

⇑

-

↑

1

↑

1

↑

0

↑

0

↑

1

0

Display Data

in Grayscale Control Circuit

LSB

MSB

LSB

MSB

LSB

MSB

|

0

1

Display Data

from MPU to LSI

D₇

D₃

D₇

D₆

D₂

D₆

D₅

D₁

D₅

D₄

D₀

*

D₂

D₇

D₄

D₁

D₆

D₃

D₀

D₅

D₂

D₇

D₄

*

D₄

D₃

D₁

D₃

D₂

D₀

D₂

D₁

*

D₁

D₀

*

ABS=1

C256=1

NOTE1) Without a special note on the left, the ABS and C256 bits are regarded as “0”.

NOTE2) The data indicated with a slash mark ( / ) is invalid.

(18) RELATION BETWEEN ROW ADDRESS AND COMMON DRIVER

The relation between row address and common driver is changed by the D₃(SHIFT) bit of the “Display Control

(1)” and the “Duty Cycle Ratio”, “Initial Display Line” and “Initial COM” instructions.

When the “Initial Display Line” is set to (LA6:LA0=00H: Address “0”), the row address corresponding to an initial

COM is “0”. However, if the “Initial Display Line” is other than “0”, the row address is shifted from “0” by just that

address. For instance, when the initial display line address is (LA6:LA0=05H: Address “5”) and the initial COM is

(SC3:SC0=1H), the row address on the initial COM is “5” and the initial COM is “COM₄”.

(18-1) through (18-5) illustrate the examples of the relation between row address and common driver.

Ver.2004-01-06

- 91 -

NJU6824

(18-1) SHIFT=0, Initial Display Line “0”, Duty Cycle Ratio “1/129”

SHIFT=”0”(Common forward scan), DS₃, ₂

,

₁, 0=”0000”, LA₆….LA₀=”00000000”(Initial display line 0)

SC3 - SC0

0000

0

0001

124

0010

120

0011

112

0100

104

0101

96

0110

88

0111

80

1000

72

1001

64

1010

56

1011

48

1100

40

1101

32

1110

24

1111

16

COM0

COM1

COM2

COM3

127

0

COM4

COM5

COM6

COM7

127

0

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

COM33

COM34

COM35

COM36

COM37

COM38

COM39

COM40

COM41

COM42

COM43

COM44

COM45

COM46

COM47

COM48

COM49

COM50

COM51

COM52

COM53

COM54

COM55

COM56

COM57

COM58

COM59

COM60

COM61

COM62

COM63

COM64

COM65

COM66

COM67

COM68

COM69

COM70

COM71

COM72

COM73

COM74

COM75

COM76

COM77

COM78

COM79

COM80

COM81

COM82

COM83

COM84

COM85

COM86

COM87

COM88

COM89

COM90

COM91

COM92

COM93

COM94

COM95

COM96

:

127

0

127

0

127

0

127

0

127

0

127

0

127

0

127

0

127

0

127

0

127

0

COM103

COM104

:

127

0

COM111

COM112

:

127

0

COM125

COM126

COM127

127

123

127

119

127

111

127

103

127

95

127

87

127

79

127

71

127

63

127

55

127

47

127

39

127

31

127

23

127

15

127

(129^thCOM period) *1

Fig 24 Relation between Row address and Common Driver (1)

NOTE1) DS: Duty Cycle Ratio / SC: Initial COM / LA: Initial Display Line Address

NOTE2) Segment waveforms for 129^thCOM timing are the same as for 128^thCOM timing (Row address “127”).

Ver.2004-01-06

- 92 -

NJU6824

(18-2) SHIFT=0, Initial Display Line “0”, Duty Cycle Ratio “1/17”

SHIFT=”0”(Common forward scan), DS₃, ₂

,

₁, 0=”1110”, LA₆….LA₀=”00000000”(Initial display line 0)

SC3 - SC0

0000

0

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

COM0

COM1

COM2

COM3

COM4

0

COM5

COM6

COM7

COM8

0

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

COM33

COM34

COM35

COM36

COM37

COM38

COM39

COM40

COM41

COM42

COM43

COM44

COM45

COM46

COM47

COM48

COM49

COM50

COM51

COM52

COM53

COM54

COM55

COM56

COM57

COM58

COM59

COM60

COM61

COM62

COM63

COM64

COM65

COM66

COM67

COM68

COM69

COM70

COM71

COM72

COM73

COM74

COM75

COM76

COM77

COM78

COM79

COM80

COM81

COM82

COM83

COM84

COM85

COM86

COM87

COM88

:

15

0

15

0

15

0

15

0

15

0

15

0

15

0

15

0

15

0

15

0

COM95

COM96

:

15

0

COM103

COM104

:

15

0

COM111

COM112

:

15

0

COM119

:

15

COM127

15

(17th COM period) *1

15

Fig 25 Relation between Row address and Common Driver (2)

NOTE1) DS: Duty Cycle Ratio / SC: Initial COM / LA: Initial Display Line Address

NOTE2) Segment waveforms for 17^thCOM timing are the same as for 16^thCOM timing (Row address “15”).

Ver.2004-01-06

- 93 -

NJU6824

(18-3) SHIFT=1, Initial Display Line “0”, Duty Cycle Ratio “1/129”

SHIFT=”1”(Common backward scan), DS₃, ₂

,

₁, 0=”0000”, LA₆….LA₀=”00000000”(Initial display line 0)

SC3 – SC0

0000

127

0001

123

0010

119

0011

111

0100

103

0101

95

0110

87

0111

79

1000

71

1001

63

1010

55

1011

47

1100

39

1101

31

1110

23

1111

15

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

:

COM15

COM16

:

0

127

COM23

COM24

:

0

127

COM31

COM32

:

0

127

COM39

COM40

COM41

COM42

COM43

COM44

COM45

COM46

COM47

COM48

COM49

COM50

COM51

COM52

COM53

COM54

COM55

COM56

COM57

COM58

COM59

COM60

COM61

COM62

COM63

COM64

COM65

COM66

COM67

COM68

COM69

COM70

COM71

COM72

COM73

COM74

COM75

COM76

COM77

COM78

COM79

COM80

COM81

COM82

COM83

COM84

COM85

COM86

COM87

COM88

COM89

COM90

COM91

COM92

COM93

COM94

COM95

COM96

COM97

COM98

COM99

COM100

COM101

COM102

COM103

COM104

COM105

COM106

COM107

COM108

COM109

COM110

COM111

COM112

COM113

COM114

COM115

COM116

COM117

COM118

COM119

COM120

COM121

COM122

COM123

COM124

COM125

COM126

COM127

0

127

0

127

0

127

0

127

0

127

0

127

0

127

0

127

0

127

0

127

0

127

0

127

0

127

124

127

120

127

112

127

104

127

96

127

88

127

80

127

72

127

64

127

56

127

48

127

40

127

32

127

24

127

16

127

(129th COM period) *1

Fig 26 Relation between Row address and Common Driver (3)

NOTE1) DS: Duty Cycle Ratio / SC: Initial COM / LA: Initial Display Line Address

NOTE2) Segment waveforms for 129^thCOM timing are the same as for 128^thCOM timing (Row address “127”).

Ver.2004-01-06

- 94 -

NJU6824

(18-4) SHIFT=0, Initial Display Line “5”, Duty Cycle Ratio “1/129”

SHIFT=”0”(Common forward scan), DS₃, ₂

,

₁, 0=”0000”, LA₆….LA₀=”00000101”(Initial display line 5)

SC3 – CS0

0000

5

0001

1

0010

0011

117

0100

109

0101

101

0110

93

0111

85

1000

77

1001

69

1010

61

1011

53

1100

45

1101

37

1110

29

1111

21

COM0

125

126

127

0

COM1

COM2

COM3

COM4

5

COM5

COM6

COM7

COM8

5

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

COM33

COM34

COM35

COM36

COM37

COM38

COM39

COM40

COM41

COM42

COM43

COM44

COM45

COM46

COM47

COM48

COM49

COM50

COM51

COM52

COM53

COM54

COM55

COM56

COM57

COM58

COM59

COM60

COM61

COM62

COM63

COM64

COM65

COM66

COM67

COM68

COM69

COM70

COM71

COM72

COM73

COM74

COM75

:

127

0

5

127

0

5

127

0

5

127

0

5

127

0

5

127

0

5

127

0

5

127

0

5

127

0

COM80

COM81

COM82

COM83

:

5

127

0

COM88

COM89

COM90

COM91

:

COM96

COM97

COM98

COM99

:

5

127

0

5

127

0

COM104

COM105

COM106

COM107

:

5

127

0

COM112

:

5

COM122

COM123

COM124:

COM125

COM126

COM127

127

0

127

0

4

124

4

116

4

108

4

100

4

92

4

84

4

76

4

68

4

60

4

52

4

44

4

38

4

28

4

20

4

(129th COM period) *1

Fig 27 Relation between Row address and Common Driver (4)

NOTE1) DS: Duty Cycle Ratio / SC: Initial COM / LA: Initial Display Line Address

NOTE2) Segment waveforms for 129^thCOM timing are the same as for 128^thCOM timing.

Ver.2004-01-06

- 95 -

NJU6824

(18-5) SHIFT=0, Initial Display Line “0”, Duty Cycle Ratio “1/128” (Dity-1 ON)

HIFT=”0”(Common forward scan), DS₃, ₂

,

₁, 0=”0000”, LA₆….LA₀=”00000000”(Initial display line 0) DSE=”1”

SC3 – SC0

0000

0

0001

124

0010

120

0011

112

0100

104

0101

96

0110

88

0111

80

1000

72

1001

64

1010

56

1011

48

1100

40

1101

32

1110

24

1111

16

COM0

COM1

COM2

COM3

127

0

COM4

COM5

COM6

COM7

127

0

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

COM33

COM34

COM35

COM36

COM37

COM38

COM39

COM40

COM41

COM42

COM43

COM44

COM45

COM46

COM47

COM48

COM49

COM50

COM51

COM52

COM53

COM54

COM55

COM56

COM57

COM58

COM59

COM60

COM61

COM62

COM63

COM64

COM65

COM66

COM67

COM68

COM69

COM70

COM71

COM72

COM73

COM74

COM75

COM76

COM77

COM78

COM79

COM80

COM81

COM82

COM83

COM84

COM85

COM86

COM87

COM88

COM89

COM90

COM91

COM92

COM93

COM94

COM95

COM96

:

127

0

127

0

127

0

127

0

127

0

127

0

127

0

127

0

127

0

127

0

127

0

COM103

COM104

:

127

0

COM111

COM112

:

COM125

COM126

COM127

127

0

127

123

119

111

103

95

87

79

71

63

55

47

39

31

23

15

Fig 28 Relation between Row address and Common Driver (5)

NOTE1) DS: Duty Cycle Ratio / SC: Initial COM / LA: Initial Display Line Address

Ver.2004-01-06

- 96 -

NJU6824

(19) TYPICAL INSTRUCTION SEQUENCES

(19-1) Initialization Sequence in Using Internal LCD Power Supply

Power ON (V_DD, V_EE) with RESb "L"

WAIT (NOTE2)

(NOTE1)

RESET

WAIT (NOTE3)

-------------- Instruction Code --------------

D₇D₆D₅D₄D₃D₂D₁D₀

--------- Setting (Example) ---------

Display Setting

INSTRUCTION TABLE SELECT

1

0

1

0

1

0

1

0

1

0

1

0

*

0

1

0

1

0

1

0

*

0

*

- Instruction Table Select (0,0,0)

- 1/113 Duty

Duty Cycle Ratio

N-line Inversion (Lower)

N-line Inversion (Upper)

INSTRUCTION TABLE SELECT

Display Mode Control

- N=7

0

1

- Instruction Table Select (1,0,0)

- Fixed 8-grayscale Mode

- 256-color Mode ON

Power Setting

EVR Control (Upper)

1

0

1

0

1

0

1

0

1

0

1

*

1

0

*

1

0

1

0

1

0

1

0

- M=95

EVR Control (Lower)

INSTRUCTION TABLE SELECT

Boost Level

- Instruction Table Select (0,0,0)

- 5-times Booster

LCD Bias Ratio

- 1/7 Bias

Power Control

WAIT (NOTE4)

Power Control

0

- Voltage Booster ON

1

0

1

0

1

0

- Voltage Converter ON

WAIT (NOTE5)

END

NOTE1) If different power sources are applied to the V_DDand the V_EE, turn on the V_DDfirst.

NOTE2) Wait until the V_DDand V_EEare stabilized.

NOTE3) Wait 10 [us] or more.

NOTE4) Wait until the V_OUTis stabilized.

NOTE5) Wait until the V_LCDand V₁-V₄are stabilized.

Ver.2004-01-06

- 97 -

NJU6824

(19-2) Initialization Sequence in Using External LCD Power Supply

Power ON (V_DD) with RESb "L"

WAIT (NOTE1)

RESET

WAIT (NOTE2)

External LCD Power Supply ON

WAIT (NOTE3)

-------------- Instruction Code -------------- --------- Setting (Example) ---------

D₇D₆D₅D₄D₃D₂D₁D₀

Display Setting

INSTRUCTION TABLE SELECT

1

0

1

0

1

0

1

0

1

0

1

0

*

0

1

0

1

0

1

0

*

0

*

- Instruction Table Select (0,0,0)

Duty Cycle Ratio

N-line Inversion (Lower)

N-line Inversion (Upper)

INSTRUCTION TABLE SELECT

- 1/113 Duty

- N=7

0

1

- Instruction Table Select (1,0,0)

Display Mode Control

END

- Fixed 8-grayscale Mode

- 256-color Mode ON

NOTE1) Wait until the V_DDis stabilized.

NOTE2) Wait 10 [us] or more.

NOTE3) Wait until the external LCD power supply (V_OUT, V_LCD, V₁-V₄) are stabilized.

Ver.2004-01-06

- 98 -

NJU6824

(19-3) Display Data Write Sequence

Optional Status

-------------- Instruction Code -------------- --------- Setting (Example) ---------

D₇D₆D₅D₄D₃D₂D₁D₀

INSTRUCTION TABLE SELECT

Initial Display Line (Lower)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

- Instruction Table Select (0,0,0)

-Initial Display Line (00)H

Initial Display Line (Upper)

- Read-modify-write ON

- Horizontal Direction

- X&Y Increment

Increment/Decrement Control

Window Start Column Address (Lower)

Window Start Column Address (Upper)

Window Start Row Address (Lower)

Window Start Row Address (Upper)

INSTRUCTION TABLE SELECT

Window End Column Address (Lower)

Window End Column Address (Upper)

Window End Row Address (Lower)

Window End Row Address (Upper)

Display Data Write

1

0

1

-

Window Start Column Address (00)H

- Window Start Row Address (00)H

- Instruction Table Select (1,0,1)

-Window End Column Address (04)H

- Window End Row Address (04)H

- Writing Display Data on the DDRAM

for Checker Flag in B&W Mode (Example)

00H

04H

← X →

:

00H

↑

Y

:

Repeating All “0” and All “1” Alternately

↓

04H

:

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Display Data Write

INSTRUCTION TABLE SELECT

- Instruction Table Select (0,0,0)

- Display ON

Display Control (1)

END

Ver.2004-01-06

- 99 -

NJU6824

(19-4) Partial Display Sequence

Optional Status

-------------- Instruction Code -------------- --------- Setting (Example) ---------

D₇D₆D₅D₄D₃D₂D₁D₀

INSTRUCTION TABLE SELECT

Display Control (1)

1

0

1

0

1

0

1

0

1

0

- Instruction Table Select (0,0,0)

- Display OFF

Power Control

- Voltage Converter OFF

- Voltage Booster OFF

Power Control

WAIT (NOTE1)

Display Setting

Duty Cycle Ratio

1

0

1

0

1

0

1

0

1

0

1

0

*

0

1

0

- 1/65 Duty

Initial Display Line (Lower)

Initial Display Line (Upper)

INSTRUCTION TABLE SELECT

Initial COM

- Initial Display Line (00)H

0

- Instruction Table Select (1,0,0)

- Initial COM: COM0

Power Setting

EVR Control (Upper)

1

0

1

0

1

0

1

0

1

0

1

*

1

0

*

0

1

0

1

0

1

0

1

0

1

0

- M=60

EVR Control (Lower)

INSTRUCTION TABLE SELECT

Boost Level

- Instruction Table Select (0,0,0)

- 3-times Booster

LCD Bias Ratio

*

- 1/5 Bias

Power Control

WAIT (NOTE2)

Power Control

WAIT (NOTE3)

Display Control (1)

END

0

- Voltage Booster ON

1

0

1

0

1

0

1

0

1

0

1

- Voltage Converter ON

- Display ON

NOTE1) Wait until the voltage booster is completely turned off. Make sure what is the wait time in the particular application.

NOTE2) Wait until the V_OUTis stabilized.

NOTE3) Wait until the V_LCDand V₁-V₄are stabilized.

Ver.2004-01-06

- 100 -

NJU6824

(19-5) Power OFF Sequence

Optional Status

-------------- Instruction Code -------------- --------- Setting (Example) ---------

D₇D₆D₅D₄D₃D₂D₁D₀

INSTRUCTION TABLE SELECT

Display Control (1)

1

0

1

0

1

0

1

0

*

0

1

*

0

1

0

1

0

1

- Instruction Table Select (0,0,0)

- Display OFF

Power Control

- Voltage Converter OFF

- Voltage Booster OFF

- Power Save ON

Power Control

INSTRUCTION TABLE SELECT

- Instruction Table Select (1,0,0)

- Discharge ON

Discharge ON/OFF

WAIT (NOTE)

Power OFF (V_DD-V_SS, V_EE-V_SSH

)

END

NOTE) Wait until the Discharge is completed.

Ver.2004-01-06

- 101 -

NJU6824

ꢀ ABSOLUTE MAXIMUM RATINGS

PARAMETER

Supply Voltage (1)

Supply Voltage (2)

Supply Voltage (3)

Supply Voltage (4)

Supply Voltage (5)

Supply Voltage (6)

Input Voltage

SYMBOL

V_DD

CONDITION

TERMINAL

V_DD

RATING

-0.3 to +4.0

UNIT

V

V_EE

-0.3 to +4.0

V

V_SS=0V

V_SSH=0V

Ta = +25°C

V_OUT

-0.3 to +20.0

-0.3 to V_LCD+ 0.3

-0.3 to V_DD+ 0.3

-45 to +125

V

V_REG

V

V_LCD

V

V₁, V₂, V₃, V₄

V_I

V₁, V₂, V₃, V₄

*1

V

Storage Temperature

Tstg

°C

NOTE1) D₀to D₁₅, CSb, RS, RDb, WRb, OSC1, RESb, TEST1, and TEST2

NOTE2) To stabilize the LSI operation, place decoupling capacitors between V_DDand V_SSand between V_EEand V_SSH

.

ꢀ RECOMMENDED OPERATING CONDITIONS

PARAMETER

SYMBOL

V_DD1

TERMINAL

MIN

1.7

2.4

5

TYP

MAX

3.3

UNIT NOTE

V

1

2

3

4

V_DD

Supply Voltage

V_DD2

3.3

V_EE

V_LCD

V_OUT

V_REG

V_REF

3.3

V

V_LCD

18.0

_OUT× 0.9

3.3

V

V_OUT

V_REG

V_REF

V

Operating Voltage

V

2.1

-30

V

5

Operating Temperature

Topr

85

°C

NOTE1) Applied to the condition when the reference voltage generator is not used.

NOTE2) Applied to the condition when the reference voltage generator is used.

NOTE3) Applied to the condition when the voltage booster is used.

NOTE4) The following relation among the LCD bias voltages must be maintained.

V_SSH<V₄<V₃<V₂<V₁<V_LCD<V_OUT

NOTE5) Relation: V_REF<V_EEmust be maintained.

Ver.2004-01-06

- 102 -

NJU6824

ꢀDC CHARACTERISTICS

V_SS=0V, V_SSH=0V, V_DD=+1.7 to +3.3V, Ta=-30 to +85°C

SYM

BOL

NOTE

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

“H” Level Input Voltage

“L” Level Input Voltage

“H” Level Output Voltage

“L” Level Output Voltage

“H” Level Output Voltage

“L” Level Output Voltage

Input Leakage Current

Output Leakage Current

V_IH

0.8 V_DD

0

V_DD

V

1

2

3

4

5

V_IL

0.2V_DD

V_OH1I_OH= -0.4mA

V_OL1I_OL= 0.4mA

V_OH2I_OH= -0.1mA

V_OL2I_OL= 0.1mA

I_LI

I_LO

V_DD- 0.4

V

0.4

V

V_DD- 0.4

V

0.4

10

2

V

-10

V_I= V_SSor V_DD

µA

V_LCD= 10V

V_LCD= 6V

1

2

Driver ON-resistance

R_ON1

6

|∆V_ON| = 0.5V

kΩ

4

CSb=V_DD

,

I_STB

V

_DD= 3V

15

7

µA

Stand-by Current

Ta=25°C

f_OSC1

f_OSC2

f_OSC3

f_r1

f_r2

f_r3

490

110

15.9

600

135.5

19.4

575

135

19.6

710

160

22.9

8

9

10

V_DD= 3V

Ta = 25°C

Oscillation Frequency

Using Internal Resistor

kHz

Rf=15kΩ

Rf=68kΩ

Rf=510kΩ

N-time boost (N=2 to 6)

RL = 500kΩ (V_OUT- V_SSH

V_DD= 3V, 6-time boost

All pixels ON

Oscillation Frequency

Using External Resistor

kHz

V

11

12

Voltage Booster

Output Voltage

(N x V_EE

)

V_OUT

I_DD1

I_DD2

I_DD3

I_DD4

I_DD5

I_DD6

x 0.95

)

Operating Current (1)

Operating Current (2)

Operating Current (3)

Operating Current (4)

Operating Current (5)

Operating Current (6)

V_BAOutput Voltage

760

930

1140

1400

780

V_DD= 3V, 6-time boost

Checker flag display

V_DD= 3V, 5-time boost

All pixels ON

V_DD= 3V, 5-time boost

Checker flag display

V_DD= 3V, 4-time boost

All pixels ON

V_DD= 3V, 4-time boost

Checker flag display

520

13

µA

650

980

360

540

450

680

(0.9 V_EE

)

(0.9 V_EE

)

V_BAV_EE= 2.4 to 3.3V

_EE= 2.4 to 3.3V

0.9 V_EE

V

14

15

x 0.98

x 1.02

V

(V_REFx N)

x 0.97

(V_REFx N)

x 1.03

V_REGOutput Voltage

V_REGV_REF= 0.9 x V_EE

(V_REFx N)

N-time boost (N=2 to 6)

V₂

V₃

V_D12

V_D34

V_D24

-100

-30

0

+100

+30

LCD Bias Voltages

mV

16

Ver.2004-01-06

- 103 -

NJU6824

ꢀOSCILLATION FREQUENCY AND FRAME FREQUENCY

FRAME FREQUENCY (FLM)

DUTY CYCLE RATIO (1/D) <DSE=0>

OSCILLATOR

/EXTERNAL

CLOCK

SYM

BOL

DISPLAY MODE

1/129 to 1/81

1/73 to 1/41

1/33 to 1/25

1/17

f_OSC/ (62xD)

f_OSC/ (62xDx2)

f_OSC/ (62xDx4)

f_OSC/ (62xDx8)

f_OSC1Variable 8-/16-level Grayscale Mode

f_OSC2Fixed 8-level Grayscale Mode

f_OSC3B&W Mode

Using

f_OSC/ (14xD)

f_OSC/ (14xDx2)

f_OSC/ (14xDx4)

f_OSC/ (14xDx8)

Internal Oscillator

f_OSC/ (2xD)

f_CK/ (62xD)

f_OSC/ (2xDx2)

f_CK/ (62xDx2)

f_OSC/ (2xDx4)

f_CK/ (62xDx4)

f_OSC/ (2xDx8)

f_CK/ (62xDx8)

f_CK1Variable 8-/16-level Grayscale Mode

f_CK2Fixed 8-level Grayscale Mode

f_CK3B&W Mode

Using

f_CK/ (14xD)

f_CK/ (2xD)

f_CK/ (14xDx2)

f_CK/ (2xDx2)

f_CK/ (14xDx4)

f_CK/ (2xDx4)

f_CK/ (14xDx8)

f_CK/ (2xDx8)

External Clock

Ver.2004-01-06

- 104 -

NJU6824

NOTE1) D₀-D₁₅, CSb, RS, RDb, WRb, P/S, SEL68 and RESb

NOTE2) D₀-D₁₅

NOTE3) CL, FLM, FR and CLK

NOTE4) CSb, RS, SEL68, RDb, WRb, P/S, RESb and OSC1

NOTE5) D₀-D₁₅in high impedance

NOTE6) SEGA₀-SEGA₁₂₇, SEGB₀-SEGB₁₂₇, SEGC₀-SEGC₁₂₇, COM₀-COM₁₂₇, SEGSA₀, SEGSA₁, SEGSB₀, SEGSB₁,

SEGSC₀and SEGSC₁

This parameter defines the resistance between each COM/SEG and each LCD bias (V_LCD, V₁, V₂, V₃and V₄).

- 0.5V Difference / 1/9 LCD Bias

NOTE7) V_DD

Oscillator is halted.

- CSb=1 (Disabled) / No-load on COM/SEG

NOTE8) CLK

This parameter defines the oscillation frequency by using the internal resistor, in the Variable grayscale mode.

- (Rf2, Rf1, Rf0)=(0,0,0)

NOTE9) CLK

This parameter defines the oscillation frequency by using the internal resistor, in the 8-level fixed grayscale mode.

- (Rf2, Rf1, Rf0)=(0,0,0)

NOTE10) CLK

This parameter defines the oscillation frequency by using the internal resistor, in the B&W mode.

- (Rf2, Rf1, Rf0)=(0,0,0)

NOTE11) OSC2

- V_DD=3V / Ta=25°C

NOTE12) V_OUT

This parameter is applied to the condition that the internal LCD power supply and the internal oscillator are used.

- V_EE=2.4V to 3.3V / EVR= (1,1,1,1,1,1,1) / 1/5 to 1/12 LCD Bias / 1/129 Duty Cycle / No-load on COM/SEG /

RL=500kΩ between V_OUTand V_SSH/ CA1=CA2=1.0uF / CA3=0.1uF / DCON=”1” / AMPON=”1”

NOTE13) V_SS, V_SSH

This parameter is applied to the condition that the internal LCD power supply and the internal oscillator are used.

- EVR= (1,1,1,1,1,1,1) / All Pixels ON or Checker Flag Display / No-load on COM/SEG / No-access from MPU /

V_DD=V_EE/ V_REF=0.9V_EE/ CA1=CA2=1.0uF / CA3=0.1uF / DCON=”1” / AMPON=”1” / NLIN=”0” / 1/129 Duty cycle /

Ta=25°C

NOTE14) V_BA

- V_BA=V_REF/ Boost Level (N)=”1”,/ DCON=”0” / V_OUT=13.5V

NOTE15) V_REG

- V_EE=2.4V to 3.3V / V_REF=0.9V_EE/ V_OUT=18V / 1/5 to 1/12 LCD bias ratio / 1/129 duty cycle / EVR=(1,1,1,1,1,1,1) /

Checker flag display / No-load on COM/SEG / Boost Level (N)=”2” to “6” / CA1=CA2=1.0uF / CA3=0.1uF /

DCON=”0” / AMPON=”1” / NLIN=”0”

NOTE16) V_LCD, V₁, V₂, V₃and V₄

- V_EE=3.0V / V_REF=0.9V_EE/ V_OUT=15V/ 1/5 to 1/12 LCD Bias / EVR= (1,1,1,1,1,1,1) / Display OFF / No-load on

COM/SEG / Boost Level (N)=”5” / CA1=CA2=1.0uF / CA3=0.1uF / DCON=”0” / AMPON=”1”

V_LCD

V₁

V_D12: (1)-(2)

V_D34: (3)-(4)

V_D24: (2)-(4)

(1)

(2)

V₂

V₃

(3)

(4)

V₄

V_SSH

Ver.2004-01-06

- 105 -

NJU6824

ꢀAC CHARACTERISTICS

(1) Write Operation (Parallel Interface / 80-series MPU)

t_AS8

t_AH8

CSb

RS

WRb

t_WRLW8

t_WRHW8

t_DS8

t_DH8

D₀to D₁₅

t_CYC8

(V_DD=2.5 to 3.3V, Ta=-30 to +85°C)

CONDITION

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH8

t_AS8

0

ns

CSb

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC8

t_WRLW8

t_WRHW8

90

35

ns

WRb

Data setup time

Data hold time

t_DS8

t_DH8

30

5

ns

D₀to D₁₅

(V_DD=2.2 to 2.5V, Ta=-30 to +85°C)

PARAMETER

SYMBOL

MIN.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH8

t_AS8

0

ns

CSb

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC8

t_WRLW8

t_WRHW8

160

70

ns

WRb

Data setup time

Data hold time

t_DS8

t_DH8

40

5

ns

D₀to D₁₅

(V_DD=1.7 to 2.2V, Ta=-30 to +85°C)

PARAMETER

SYMBOL

MIN.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH8

t_AS8

0

ns

CSb

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC8

t_WRLW8

t_WRHW8

180

80

ns

WRb

Data setup time

Data hold time

t_DS8

t_DH8

70

10

ns

D₀to D₁₅

NOTE) Each timing is specified based on 20% and 80% of V_DD

.

Ver.2004-01-06

- 106 -

NJU6824

(2) Read Operation (Parallel Interface / 80-series MPU)

t_AH8

t_AS8

CSb

RS

t_WRLR8

RDb

t_WRHR8

t_RDH8

D₀to D₁₅

t_RDD8

t_CYC8

(V_DD=2.5 to 3.3V, Ta=-30 to +85°C)

CONDITION

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH8

t_AS8

0

ns

CSb

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC8

t_WRLR8

t_WRHR8

180

80

ns

RDb

Read Data delay time

Read Data hold time

t_RDD8

t_RDH8

60

ns

CL=15pF

D₀to D₁₅

0

(V_DD=2.2 to 2.5V, Ta=-30 to +85°C)

CONDITION

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH8

t_AS8

0

ns

CSb

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC8

t_WRLR8

t_WRHR8

180

80

ns

RDb

Read Data delay time

Read Data hold time

t_RDD8

t_RDH8

60

ns

CL=15pF

D₀to D₁₅

0

(V_DD=1.7 to 2.2V, Ta=-30 to +85°C)

CONDITION

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH8

t_AS8

0

ns

CSb

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC8

t_WRLR8

t_WRHR8

250

120

ns

RDb

Read Data delay time

Read Data hold time

t_RDD8

t_RDH8

110

ns

CL=15pF

D₀to D₁₅

0

NOTE) Each timing is specified based on 20% and 80% of V_DD

.

Ver.2004-01-06

- 107 -

NJU6824

(3) Write Operation (Parallel Interface / 68-series MPU)

t_AS6

t_AH6

CSb

RS

R/W

(WRb)

t_ELW6

t_EHW6

E

(RDb)

t_DS6

t_DH6

D₀to D₁₅

t_CYC6

(V_DD=2.5 to 3.3V, Ta=-30 to +85°C)

CONDITION

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH6

t_AS6

0

ns

CSb

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC6

t_ELW6

t_EHW6

90

35

ns

E

Data setup time

Data hold time

t_DS6

t_DH6

40

5

ns

D₀to D₁₅

(V_DD=2.2 to 2.5V, Ta=-30 to +85°C)

CONDITION

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH6

t_AS6

0

ns

CSb

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC6

t_ELW6

t_EHW6

160

70

ns

E

Data setup time

Data hold time

t_DS6

t_DH6

50

5

ns

D₀to D₁₅

(V_DD=1.7 to 2.2V, Ta=-30 to +85°C)

CONDITION

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH6

t_AS6

0

ns

CSb

RS

System cycle time

Enable ”L” level pulse width

Enable ”H” level pulse width

t_CYC6

t_ELW6

t_EHW6

180

80

ns

E

Data setup time

Data hold time

t_DS6

t_DH6

70

10

ns

D₀to D₁₅

NOTE) Each timing is specified based on 20% and 80% of V_DD

.

Ver.2004-01-06

- 108 -

NJU6824

(4) Read Operation (Parallel Interface / 68-series MPU)

t_AS6

t_AH6

CSb

RS

R/W

(WRb)

t_ELR6

t_EHR6

E

(RDb)

t_RDH6

D₀to D₁₅

t_RDD6

t_CYC6

(V_DD=2.5 to 3.3V, Ta=-30 to +85°C)

PARAMETER

SYMBOL

CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

t_AH6

t_AS6

0

ns

CSb

RS

Address setup time

System cycle time

t_CYC6

t_ELR6

t_EHR6

180

80

ns

E

Enable ”L” level pulse width

Enable ”H” level pulse width

80

Read Data delay time

Read Data hold time

t_RDD6

t_RDH6

ns

70

CL=15pF

D₀to D₁₅

0

(V_DD=2.2 to 2.5V, Ta=-30 to +85°C)

PARAMETER

SYMBOL

CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH6

t_AS6

0

ns

CSb

RS

System cycle time

t_CYC6

t_ELR6

t_EHR6

180

80

ns

E

Enable ”L” level pulse width

Enable ”H” level pulse width

80

Read Data delay time

Read Data hold time

t_RDD6

t_RDH6

ns

70

CL=15pF

D₀to D₁₅

0

(V_DD=1.7 to 2.2V, Ta=-30 to +85°C)

PARAMETER

SYMBOL

CONDITION

MIN.

MAX.

UNIT

TERMINAL

Address hold time

Address setup time

t_AH6

t_AS6

0

ns

CSb

RS

250

120

System cycle time

t_CYC6

t_ELR6

t_EHR6

ns

E

Enable ”L” level pulse width

Enable ”H” level pulse width

110

Read Data delay time

Read Data hold time

t_RDD6

t_RDH6

ns

CL=15pF

D₀to D₁₅

0

NOTE) Each timing is specified based on 20% and 80% of V_DD

.

Ver.2004-01-06

- 109 -

NJU6824

(5) Serial Interface

CSb

t_CSH

t_CSS

RS

t_ASS

t_AHS

t_SLW

t_SHW

SCL

t_CYCS

t_DSS

t_DHS

SDA

(V_DD=2.5 to 3.3V, Ta=-30 to +85°C)

PARAMETER

Serial clock cycle

SYMBOL CONDITION

MIN.

MAX.

UNIT

TERMINAL

t_CYCS

t_SHW

t_SLW

t_ASS

t_AHS

t_DSS

t_DHS

100

45

20

ns

SCL ”H” level pulse width

SCL ”L” level pulse width

Address setup time

Address hold time

Data setup time

SCL

RS

SDA

Data hold time

CSb – SCL time

CSb hold time

t_CSS

20

ns

CSb

t_CSH

20

ns

(V_DD=2.2 to 2.5V, Ta=-30 to +85°C)

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

UNIT

TERMINAL

Serial clock cycle

t_CYCS

t_SHW

t_SLW

t_ASS

t_AHS

t_DSS

t_DHS

100

45

20

ns

SCL ”H” level pulse width

SCL ”L” level pulse width

Address setup time

Address hold time

Data setup time

SCL

RS

SDA

Data hold time

CSb – SCL time

CSb hold time

t_CSS

20

ns

CSb

t_CSH

20

ns

(V_DD=1.7 to 2.2V, Ta=-30 to +85°C)

PARAMETER

SYMBOL CONDITION

MIN.

MAX.

UNIT

TERMINAL

Serial clock cycle

t_CYCS

t_SHW

t_SLW

t_ASS

t_AHS

t_DSS

t_DHS

160

75

35

ns

SCL ”H” level pulse width

SCL ”L” level pulse width

Address setup time

Address hold time

Data setup time

SCL

RS

SDA

Data hold time

CSb – SCL time

CSb hold time

t_CSS

35

ns

CSb

t_CSH

35

ns

NOTE) Each timing is specified based on 20% and 80% of V_DD

.

Ver.2004-01-06

- 110 -

NJU6824

(6) Display Control Timing

CLK

t_DCL

CL

t_DFLM

FLM

t_FR

FR

Output timing

(V_DD=2.4 to 3.3V, Ta=-30 to +85°C)

PARAMETER

SYMBOL

CONDITION

MIN.

MAX.

UNIT

TERMINAL

FLM delay time

FR delay time

CL delay time

t_DFLM

CL=15pF

0

500

200

ns

FLM

FR

CL

t_FR

t_DCL

Output timing

(V_DD=1.7 to 2.4V, Ta=-30 to +85°C)

PARAMETER

SYMBOL

CONDITION

MIN.

MAX.

UNIT

TERMINAL

FLM delay time

FR delay time

CL delay time

t_DFLM

CL=15pF

0

1000

200

ns

FLM

FR

CL

t_FR

t_DCL

NOTE) Each timing is specified based on 20% and 80% of V_DD

.

Ver.2004-01-06

- 111 -

NJU6824

(7) Input Clock Timing

t_CKLW

t_CKHW

OSC₁

(V_DD=1.7 to 3.3V, Ta=-30 to +85°C)

PARAMETER

SYMBOL

CONDITION

MIN.

MAX.

UNIT

TERMINAL

OSC1 “H” level pulse width (1)

OSC1 “L” level pulse width (1)

OSC1 “H” level pulse width (2)

OSC1 “L” level pulse width (2)

OSC1 “H” level pulse width (3)

OSC1 “L” level pulse width (3)

t_CKHW1

t_CKLW1

t_CKHW2

t_CKLW2

t_CKHW3

t_CKLW3

0.70

3.13

21.8

1.02

4.55

31.4

OSC1

µs

(NOTE2)

OSC1

(NOTE3)

OSC1

(NOTE4)

NOTE1) Each timing is specified based on 20% and 80% of V_DD

.

NOTE2) Applied to Variable 8-/16-level grayscale mode (MON=”0”,PWM=”0”)

NOTE3) Applied to fixed 8-level grayscale mode (MON=”0”,PWM=”1”)

NOTE4) Applied to B&W mode (MON=”1”)

(8) Reset Input Timing

t_RW

RESb

t_R

Internal circuit

During reset

End of reset

status

(V_DD=2.4 to 3.3V, Ta=-30 to +85°C)

PARAMETER

SYMBOL

CONDITION

MIN.

MAX.

UNIT

Terminal

Reset time

t_R

1.0

µs

RESb “L” level pulse width

t_RW

10.0

RESb

(V_DD=1.7 to 2.4V, Ta=-30 to +85°C)

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

Terminal

Reset time

t_R

1.5

µs

RESb “L” level pulse width

t_RW

10.0

RESb

NOTE) Each timing is specified based on 20% and 80% of V_DD

.

(9) Delay Time of Gate

PARAMETER

Delay time of gate

SYMBOL

Ta=+25°C, V_SS=0V, V_DD=3.0V

MIN

TYP

MAX

UNIT

10

ns

Ver.2004-01-06

- 112 -

NJU6824

ꢀ INPUT/OUTPUT BLOCK DIAGRAMS

Output Block Diagram

Terminals : FLM, CL, FR, CLK

V_DD

Input Block Diagram

Terminals CSb, RS, RDb, WRb, SEL68, P/S,RESb

V_DD

Output control signal

Output signal

Input signal

O

I

V_SS(0V)

V_SS(0V

Input/Output Block Diagram

Terminals : D₀- D₁₅

V_DD

Input signal

I/O

V_SS(0V)

Input control signal

V_DD

Output control signal

Output signal

V_SS(0V)

COM/SEG Driver Block Diagram

Terminals : SEGA₀/B₀/C₀- SEGA₁₂₇/B₁₂₇/C₁₂₇, COM₀- COM₁₂₇

V_LCD

V₁/V₂

Output control

signal 1

Output control signal 2

Output control signal 4

O

Output control

signal 3

V_SSH(0V)

V₃/V₄

Ver.2004-01-06

- 113 -

NJU6824

ꢀ MPU CONNECTIONS

Parallel Interface / 80-series MPU

1.7V - 3.3V

(NJU6824)

V_CC

V_DD

A0

RS

A1-A7

Decoder

8

7

(80-MPU)

CSb

D₀-D₇

IORQb

D₀-D₇

RDb

WRb

RESb

GND

V_SS

RESET

Parallel Interface / 68-series MPU

1.7V - 3.3V

(NJU6824)

V_CC

V_DD

A0

RS

A1-A15

15

Decoder

8

CSb

(68-MPU)

VMA

D₀-D₇

E

RDb(E)

R/W

WRb (R/W)

RESb

V_SS

GND

RESET

Serial Interface

1.7V - 3.3V

(NJU6824)

V_CC

V_DD

RS

A0

A1-A7

Decoder

RESET

7

CSb

(MPU)

PORT1

PORT2

RESb

SDA

SCL

RESb

V_SS

GND

Ver.2004-01-06

- 114 -

NJU6824

[CAUTION]

The specifications on this databook are only

given for information , without any guarantee

as regards either mistakes or omissions. The

application circuits in this databook are

described only to show representative usages

of the product and not intended for the

guarantee or permission of any right including

the industrial rights.

Ver.2004-01-06

- 115 -


型号：	NJU6824H
厂家：	NEW JAPAN RADIO
描述：	Liquid Crystal Driver, 518-Segment, CMOS, TCP 驱动接口集成电路
文件：	总115页 (文件大小：1429K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NJU6824H [NJRC]

相关型号：

NJU6825

NJU6825CJ

NJU6825CJ-Z

NJU6825H

NJU6854

NJU6854CJ

NJU7001

NJU7001/02/04

NJU7001D

NJU7001M

NJU7001M(T2)

NJU7001M(TE2)