CLC416AJ [NSC]
Dual Low-Power, 120MHz Op Amp; 双路低功耗， 120MHz的运算放大器
| 型号： | CLC416AJ |
| 厂家： | 
National Semiconductor |
| 描述： | Dual Low-Power, 120MHz Op Amp |
| 文件： | 总6页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1998
N
CLC416
Dual Low-Power, 120MHz Op Amp
Features
General Description
■
0.01%, 0.03° D , Dφ
The CLC416 is a dual, wideband (120MHz) op amp. The
CLC416 consumes only 39mW per channel and can source or
sink an output current of 60mA. These features make the
CLC416 a versatile, high-speed solution for demanding
applications that are sensitive to both power and cost.
G
■
Very low input bias current: 100nA
■
■
■
■
■
High input impedance: 6MΩ
120MHz -3dB bandwidth (A = +2)
Low power
High output current: 60mA
Low-cost
v
Utilizing National’s proven architectures, this dual current
feedback amplifier surpasses the performance of alternative
solutions and sets new standards for low power. This power-
conserving dual op amp achieves low distortion with -80dBc and
-80dBc second and third harmonics respectively. Many high
source impedance applications will benefit from the CLC416’s
6MΩ input impedance. And finally, designers will have a bipolar
part with an exceptionally low 100nA non-inverting bias current.
Applications
■
Desktop video systems
■
Video distribution
■
Flash A/D driver
■
High-speed driver
■
High-source impedance applications
■
Professional video processing
■
High resolution monitors
With 0.1dB flatness to 30MHz and low differential gain and phase
errors, the CLC416 is an ideal part for professional video
Frequency Response (Av = +2V/V)
processing and distribution. The 120MHz -3dB bandwidth (A =
v
+2) coupled with a 400V/µs slew rate also makes the CLC416
a perfect choice in cost-sensitive applications such as video
monitors, fax machines, copiers, and CATV systems.
Typical Application Diagram
Instrumentation Amplifier
Pinout
DIP & SOIC
V1
+
1/2
CLC416
-
Vo1
inv1
+VCC
Vo2
348Ω
348Ω
348Ω
348Ω
Vout = 3(V2 - V1)
V
-
348Ω
CLC405
+
348Ω
Vnon-inv
1
Vinv2
-
-VCC
Vnon-inv
2
1/2
R1
348Ω
CLC416
+
V2
© 1998 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com
(A = +2, R = 348Ω: Vcc = + 5V, RL = 100Ω unless specified)
CLC416 Electrical Characteristics
V
f
PARAMETERS
CONDITIONS
TYP
MIN/MAX RATINGS
0 to 70˚C -40 to 85˚C
UNITS
NOTES
Ambient Temperature
CLC416AJ
+25˚C
+25˚C
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
V
V
out < 1.0Vpp
out < 5.0Vpp
120
52
30
65
40
15
45
36
45
35
MHz
MHz
MHz
1
±0.1dB bandwidth
Vout < 1.0Vpp
gain flatness
peaking
V
out < 1.0Vpp
DC to 200MHz
<30MHz
0.1
0
0.7
0.3
0.8
0.6
1.0
0.6
dB
dB
rolloff
linear phase deviation
differential gain
differential phase
<20MHz
4.43MHz, RL=150Ω
4.43MHz, RL=150Ω
0.3
0.01
0.03
0.6
0.04
0.08
0.7
0.04
0.11
0.7
0.04
0.12
deg
%
deg
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
overshoot
2V step
2V step
2V step
2V step
1V step
4.3
22
3
400
700
6.5
30
12
7.2
38
12
7.4
41
12
ns
ns
%
V/µs
V/µs
slew rate
AV = +2
AV = -1
300
260
250
DISTORTION AND NOISE RESPONSE
2
nd harmonic distortion
2Vpp, 1MHz
2Vpp, 1MHz
2Vpp, 10MHz
2Vpp, 10MHz
-80
-80
-65
-57
dBc
dBc
dBc
dBc
3rd harmonic distortion
2nd harmonic distortion
3rd harmonic distortion
equivalent input noise
voltage
-55
-50
-50
-45
-47
-45
>1MHz
5
12
3
6.3
15
3.8
66
6.6
16
4.0
66
6.7
17
4.2
66
nV/√Hz
pA/√Hz
pA/√Hz
dB
inverting current
non-inverting current
crosstalk, input referred
>1MHz
>1MHz
2Vpp, 10MHz
72
STATIC DC PERFORMANCE
input offset voltage
average drift
input bias current
average drift
input bias current
1
30
100
3
5
900
5
7
50
1600
8
8
50
2800
11
mV
µV/˚C
nA
nA/˚C
µA
A
A
A
non-inverting
inverting
1
6
8
average drift
17
52
50
3.9
40
47
45
4.6
45
45
43
4.9
nA/˚C
dB
dB
power supply rejection ratio
common-mode rejection ratio
supply current per channel
DC
DC
RL= ∞
47
45
4.5
mA
A
MISCELLANEOUS PERFORMANCE
input resistance
input capacitance
non-inverting
non-inverting
6
1
2.2
3
2
±1.8
2.4
2
±1.7
+2.9/-2.7
+3.8/-3.2
38
1
2
±1.5
+2.4/-1.7
+3.7/-2.8
20
MΩ
pF
V
V
V
common mode input range
output voltage range
output voltage range
output current
±
RL = 100Ω
RL = ∞
+3.5,-2.9 +3.1/-2.8
+4.0,-3.4
60
+3.9/-3.3
44
mA
Ω
output resistance, closed loop
0.06
0.2
0.25
0.4
+
+
Recommended gain range 1 to 40V/V
Transistor count = 110
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
supply voltage
Notes
±
7V
1) At temps < 0 C, spec is guaranteed for R = 500Ω.
˚
L
A) J-level: spec is 100% tested at +25 C.
˚
I
out is short circuit protected to ground
common-mode input voltage
maximum junction temperature
storage temperature range
±
Vcc
˚
˚
+175 C
-65 C to +150 C
˚
lead temperature (soldering 10 sec)
ESD rating (human body model)
+300 C
˚
1000V
Ordering Information
Package Thermal Resistance
Model
Temperature Range
Description
8-pin PDIP
8-pin SOIC
Package
Plastic (AJP)
Surface Mount (AJE)
θJC
θJA
CLC416AJP
CLC416AJE
-40 C to +85 C
˚
˚
80°C/W
95°C/W
95°C/W
115°C/W
-40 C to +85 C
˚
˚
http://www.national.com
2
(Vcc = ±5V, Av = +2, R = 348Ω, R = 100Ω; unless specified)
CLC416 Typical Performance Characteristics
f
L
Inverting Frequency Response
Frequency Response
Frequency Response vs. RL
Vo = 0.5Vpp
Vo = 0.5Vpp
Vo = 1Vpp
Av = +2
Av = 1
Rf = 1.65kΩ
Av = -2
Rf = 348Ω
RL = 1kΩ
RL = 100Ω
RL = 50Ω
Av = -1
Rf = 2kΩ
Av = 2
Rf = 348Ω
0
Av = -4
Rf = 255Ω
-90
RL = 1kΩ
-180
-270
-360
-450
-540
-630
0
0
-90
-90
RL = 100Ω
RL = 50Ω
-180
-270
-360
-450
-180
-270
-360
-450
Av = 10
Av = -10
Rf = 200Ω
Rf = 100Ω
Av = 4
Rf = 200Ω
1
10
100
1
10
100
1
10
100
Frequency (MHz)
Frequency (MHz)
Frequency (MHz)
Open Loop Transimpedance Gain, Z(s)
Frequency Response vs. Vout
Frequency Response vs. CL
130
110
90
200
160
120
80
Av = +2
Vo = 1Vpp
Rs = 107Ω
CL = 10pF
1Vpp
Gain
Rs = 39.25Ω
CL = 47pF
2Vpp
Phase
Rs = 27.4Ω
5Vpp
CL = 100pF
Rs = 8Ω
70
CL = 1000pF
0.2Vpp
-
Vo
Rs
CLC416
+
Ii
50
40
CL
1k
100Ω
348Ω
348Ω
30
0
1k
10k
100k
1M
10M
100M
1
10
100
1
10
100
Frequency (Hz)
Frequency (MHz)
Frequency (MHz)
Maximum Output Voltage vs. RL
Recommended Rs vs. Capacitive Load
2nd & 3rd Harmonic Distoration
-40
-50
-60
-70
-80
-90
4
2
120
100
80
60
40
20
0
3rd, RL = 100Ω
Vo = 2Vpp
0
2nd, RL = 100Ω
2nd, RL = 1kΩ
-2
-4
3rd, RL = 1kΩ
0
100
200
300
400
500
600
10
100
1000
1
10
Load (Ω)
CL (pF)
Frequency (MHz)
2nd Harmonic Distortion vs. Pout
3rd Harmonic Distortion vs. Pout
Differential Gain & Phase
-40
-50
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0.30
0.27
0.24
0.21
0.18
0.15
0.12
0.09
0.06
0.03
0
-55
-60
-65
-70
-75
-80
-85
-90
Po
Po
50Ω
50Ω
10MHz
50Ω
50Ω
10MHz
5MHz
348Ω
348Ω
348Ω
348Ω
-60
5MHz
-70
Gain Negative
Sync
Phase Negative Sync
-80
1MHz
1MHz
-90
Phase Positive Sync
Gain Positive Sync
3 4
500kHz
500kHz
-100
-10
-5
0
5
10
-10
-5
0
5
10
1
2
Output Power (dBm)
Output Power (dBm)
Number of 150Ω Loads
Small Signal Pulse Response
Large Signal Pulse Response
PSRR and CMRR
0.08
0.06
0.04
0.02
0
2
1
60
50
40
30
20
10
Av = +1
PSRR
CMRR
Av = +2
0
-0.02
-0.04
-0.06
-0.08
-1
-2
Av = -2
Av = -1
Time (5ns/div)
Time (5ns/div)
10k
100k
1M
10M
100M
Frequency (Hz)
3
http://www.national.com
(Vcc = ±5V, Av = +2, R = 348Ω, R = 100Ω; unless specified)
CLC416 Typical Performance Characteristics
f
L
Equivalent Input Noise
Typical DC Errors vs. Temperature
Power Derating Curves
100
10
1
100
6
5
4
3
2
1
1.0
0.8
1
IBN
0
AJP
AJE
0.6
0.4
Inverting Current = 12pA/√Hz
-1
-2
-3
10
1
IBI
Voltage = 5nV/√Hz
Non-Inverting Current = 3pA/√Hz
0.2
0
VIO
100
1k
10k
100k
1M
10M
-50
0
50
100
0
20
40
60
80 100 120 140 160 180
Frequency (Hz)
Temperature (°C)
Ambient Temperature (°C)
CLC416 OPERATION
Description
Feedback Resistor Selection
The CLC416 is a dual current feedback amplifier with
the following features:
The feedback resistor, R , determines the loop gain
and frequency response of a current feedback
amplifier. Optimum performance of the CLC416, at a
f
■
Differential gain and phase errors of 0.01%
gain of +2V/V, is achieved with R equal to 348Ω. The
f
and 0.03° into a 150Ω load
frequency response plots in the typical performance
■
Low, 3.9mA, supply current per amplifier
section illustrate the recommended R for several
f
gains. Within limits, R can be adjusted to optimize the
frequency response.
f
The professional video quality differential gain and
phase errors and low power capabilities of the CLC416
make this product a good choice for video applications.
■
Decrease R to peak frequency response and
f
extend bandwidth
Gain
■
Increase R to roll off frequency response and
f
The non-inverting and inverting gain equations for the
CLC416 are as follows:
reduce bandwidth
As a rule of thumb, if the recommended R is doubled,
the bandwidth will be cut in half.
f
R
f
Non-inverting Gain: 1+
R
g
R
Channel Matching
f
Inverting Gain:
−
Channel matching and crosstalk efficiency are largely
dependent on board layout. The layout of National’s
dual amplifier evaluation boards are designed to produce
optimum channel matching and isolation. Typical
channel matching for the CLC416 is shown in Figure 2.
R
g
Where R is the feedback resistor and R is the gain
f
g
setting resistor. Figure 1 shows the general non-invert-
ing gain configuration including the recommended
bypass capacitors.
+Vcc
Channel A
Channel B
6.8µF
Channel A
0
0.1µF
Vin
+
Channel B
-90
Vo
-180
CLC416
Av = +2
RL = 100Ω
Vo = 2Vpp
Rin
-270
-
Rf
RL
-360
-450
1
10
100
0.1µF
Rg
Frequency (MHz)
Figure 2: Channel Matching
6.8µF
-Vcc
The CLC416’s channel-to-channel isolation is better
than 70dB for input frequencies of 4MHz. Input
referred crosstalk vs. frequency is illustrated in Figure 3.
Figure 1: Recommended Non-Inverting Gain Circuit
http://www.national.com
4
-20
-40
evaluation boards for the CLC416 (CLC730038 - DIP,
CLC730036 - SOIC) and suggests their use as a guide
for high frequency layout and as an aid for device test-
ing and characterization.
-60
Supply bypassing is required for best performance.
The bypass capacitors provide a low impedance return
current path at the supply pins. They also provide high
frequency filtering on the power supply traces. Other
layout factors play a major role in high frequency
performance. The following are recommended as a
basis for high frequency layout:
-80
-100
-120
1
10
100
Frequency (MHz)
1. Include 6.8µF tantalum and 0.1µF ceramic
capacitors on both supplies.
2. Place the 6.8µF capacitors within 0.75 inches
of the power pins.
3. Place the 0.1µF capacitors within 0.1 inches
of the power pins.
4. Remove the ground plane under and around
the part, especially near the input and output
pins to reduce parasitic capacitance.
5. Minimize all trace lengths to reduce series
inductances.
Figure 3: Input Referred Crosstalk vs. Frequency
Driving Cables and Capacitive Loads
When driving cables, double termination is used to
prevent reflections. For capacitive load applications, a
small series resistor at the output of the CLC416 will
improve stability. The R vs. Capacitive Load plot,
s
in the Typical Performance section, gives the
recommended series resistance value for optimum
flatness at various capacitive loads.
Power Dissipation
Additional information is included in the evaluation
board literature.
The power dissipation of an amplifier can be described
in two conditions:
■
Quiescent Power Dissipation -
SPICE Models
P (No Load Condition)
SPICE models provide a means to evaluate amplifier
designs. Free SPICE models are available for
National’s monolithic amplifiers that:
Q
■
Total Power Dissipation -
P (with Load Condition)
T
The following steps can be taken to determine the
power consumption for each CLC416 amplifier:
■
Support Berkeley SPICE 2G and its many
derivatives
■
Reproduce typical DC, AC, Transient, and
Noise performance
Support room temperature simulations
1. Determine the quiescent power
P = I (V - V )
Q
cc
CC
EE
■
2. Determine the RMS power at the output stage
= (V - V ) (I ), where V and I
load
P
The readme file that accompanies the diskette lists
released models, and provides a list of modeled para-
meters. The application note OA-18, Simulation
SPICE Models for National’s Op Amps, contains
schematics and a reproduction of the readme file.
O
cc
load
load
load
are the RMS voltage and current across the
external load.
3. Determine the total RMS power
P = P + P
T
Q
O
Add the total RMS powers for both channels to deter-
mine the power dissipated by the dual.
Applications Circuits
The maximum power that the package can dissipate at
a given temperature is illustrated in the Power
Derating curves in the Typical Performance section.
The power derating curve for any package can be
derived by utilizing the following equation:
Instrumentation Amplifier
An instrumentation circuit is shown on the front page
and reproduced in Figure 4. The DC CMRR can be
fine tuned by adjusting R .
1
V1
+
1/2
CLC416
(175° − Tamb)
P =
-
348Ω
348Ω
348Ω
348Ω
θ
JA
Vout = 3(V2 - V1)
-
where: T
= Ambient temperature (°C)
= Thermal resistance, from junction to
ambient, for a given package (°C/W)
348Ω
amb
CLC405
+
348Ω
θ
JA
-
1/2
R1
348Ω
CLC416
V2
+
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance. National provides
Figure 4: Instrumentation Amplifier
5
http://www.national.com
Differential Line Receiver
Figure 5 illustrates a Differential Line Receiver. The
circuit will convert differential signals to single-ended signals.
C
+
1/2
CLC416
R
-
R
R
R
R
R
-
R
1/2
-
-
CLC416
+
Ro
Vo = 2Vin
1/2
1/2
CLC416
+
CLC416
+
R1
Vin
R
R
+
Vo
C
CLC405
-
Av = -1V/V
Av = -1V/V
R
R
+Vin
-Vin
Rf
1
R =
R1 = QR
2πf C
r
Figure 5: Differential Line Receiver
Bandpass Filter
Figure 6: Bandpass Filter Topology
Figure 6 illustrates a low-sensitivity bandpass filter and
design equations. This topology utilizes the CLC416’s
closely matched amplifiers to obtain low op-amp
sensitivity at high frequencies. The CLC405 is used as
a buffer to obtain low output impedance. The overall
circuit gain is unity. For additional gain, the CLC405
can be configured as a non-inverting amplifier.
1.8dB
935kHz
0
-10
-20
-30
-40
To design the filter, choose C and then determine values
for R and R based on the desired resonant frequency
1
(f ) and Q factor.
r
Figure 7 illustrates a bandpass filter with Q = 10 and
1
10
f = 1MHz. The component values used are listed
r
Frequency (MHz)
below:
R = 4.9kΩ
R = 499Ω
1
Figure 7: Bandpass Response
C = 330pF
R = 2kΩ
f
Customer Design Applications Support
National Semiconductor is committed to design excellence. For sales, literature and technical support, call the
National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
Life Support Policy
National’s products are not authorized for use as critical components in life support devices or systems without the express written approval
of the president of National Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
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Tel: 81-043-299-2309
Fax: 81-043-299-2408
N
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said
circuitry and specifications.
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6
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