CLC5633IN [NSC]
Triple, High Output, Programmable Gain Buffer; 三重，高输出，可编程增益缓冲器
| 型号： | CLC5633IN |
| 厂家： | 
National Semiconductor |
| 描述： | Triple, High Output, Programmable Gain Buffer |
| 文件： | 总17页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2000
CLC5633
Triple, High Output, Programmable Gain Buffer
n 3.0mA/ch supply current
n 130MHz bandwidth (Av=+2)
The CLC5633 is a triple, low cost, high speed (130MHz)
n −92/−96dBc HD2/HD3 (1MHz)
General Description
buffer which features user programmable gains of +2, +1,
and −1V/V. The CLC5633 also has a new output stage that
delivers high output drive current (130mA/ch) from a single
n 20ns settling to 0.05%
n 410V/µs slew rate
n Stable for capacitive loads up to 1000pf
5V supply. Its current feedback architecture, fabricated in an
advanced complementary bipolar process, maintains consis-
tent performance over a wide range of gains and signal
levels, and has a linear phase response up to one half of the
−3dB frequency.
±
n Single 5V to 5V supplies
Applications
n Video line driver
The CLC5633 offers 0.1dB gain flatness to 20MHz and
differential gain and phase errors of 0.03% and 0.06˚. These
features area ideal for professional and consumer video
applications.
n Coaxial cable driver
n Twisted pair driver
n Transformer/coil driver
n High capacitive load driver
n Portable/battery powered applications
n A/D driver
The CLC5633 offers superior dynamic performance with a
130MHz small-signal bandwidth, 410V/µs slew rate and
5.0ns rise/fall times (2VSTEP). The combination of low quies-
cent power, high output current drive, and high speed per-
formance make the CLC5633 well suited for many battery
powered personal communication/computing systems.
Maximum Output Voltage vs. RL
The ability to drive low impedance, highly capacitive loads,
with minimum distortion makes the CLC5633 ideal for cable
applications. The CLC5633 will drive a 100Ω load with only
−73/−92dBc second/third harmonic distortion (AV = +2,
VOUT= 2VPP, f = 1MHz). With a 25Ω load, and the same
conditions, it produces only −75/−75dBc second/third har-
monic distortion. It is also optimized for driving high currents
into single-ended transformers and coils.
When driving the input of high resolution A/D converters, the
CLC5633 provides excellent −92/−96dBc second/third har-
monic distortion (AV = +2, VOUT = 2VPP, f = 1MHz, RL
=
1kΩ) and fast settling time.
Features
n 130mA output current
n 0.03%, 0.06˚ differential gain, phase
DS015005-1
Connection Diagram
DS015005-3
Pinout
DIP & SOIC
© 2000 National Semiconductor Corporation
DS015005
www.national.com
Typical Application
DS015005-2
Single Supply Cable Driver
Ordering Information
Package
Temperature Range
Packaging
Marking
NSC
Industrial
Drawing
N14A
14-pin plastic DIP
14-pin plastic SOIC
−40˚C to +85˚C
−40˚C to +85˚C
CLC5633IN
CLC5633IM
CLC5633IMX
M14A, M14B
www.national.com
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Lead Temperature (soldering 10 sec)
ESD (human body model)
+300˚C
2000V
Operating Ratings
Supply Voltage (VCC-VEE
)
+14V
140mA
Thermal Resistance
Output Current (See note 4)
Common-Mode Input Voltage
Maximum Junction Temperature
Storage Temperature Range
Package
MDIP
(θJC
)
(θJA
)
VEE to VCC
+150˚C
60˚C/W
55˚C/W
110˚C/W
125˚C/W
SOIC
−65˚C to +150˚C
+5 Electrical Characteristics
(AV = +2, RL =100Ω, VS = +5V1, VCM = VEE + (VS/2), RL tied to VCM, unless specified.
Symbol
Parameter
Conditions
CLC5633IN/IM
Typ
Min/Max Ratings (Note 2)
Units
Ambient Temperature
+25˚C
+25˚C
0 to
−40 to
70˚C
85˚C
Frequency Domain Response
-3dB Bandwidth
VO = 0.5VPP
VO = 2.0VPP
VO = 0.5VPP
100
97
80
79
17
0.5
0.5
0.3
–
70
74
17
1.0
0.6
0.4
–
70
72
13
1.0
0.6
0.4
–
MHz
MHz
MHz
dB
−0.1dB Bandwidth
Gain Peaking
20
<
<
<
200MHz, VO = 0.5VPP
30MHz, VO = 0.5VPP
30MHz, VO = 0.5VPP
0
Gain Rolloff
0.2
0.15
0.04
0.1
dB
Linear Phase Deviation
Differential Gain
deg
%
NTSC, RL = 150Ω to −1V
NTSC, RL = 150Ω to −1V
Differential Phase
–
–
–
deg
Time Domain Response
Rise and Fall Time
Settling Time to 0.05%
Overshoot
2V Step
1V Step
2V Step
2V Step
4.8
20
5
6.4
24
7
6.8
40
7.3
60
ns
ns
11
14
%
Slew Rate
290
170
150
140
V/µs
Distortion And Noise Response
2nd Harmonic Distortion
2VPP, 1MHz
−72
−84
−71
−87
−95
−78
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
2VPP, 1MHz; RL = 1KΩ
2VPP, 5MHz
-
−54
-
-
−52
-
-
−52
-
3rd Harmonic Distortion
2VPP, 1MHz
2VPP, 1MHz; RL=1KΩ
2VPP, 5MHz
-
-
-
−61
−54
−54
Equivalent Input Noise
Voltage (eni)
>
>
>
1MHz
1MHz
1MHz
4.9
6.6
5.9
8.5
6.4
9.3
6.4
9.3
nV/
Non-Inverting Current (ibn
Inverting Current (ibi)
)
pA/
pA/
11.1
14.7
15.8
15.8
Crosstalk (Input Referred)
10MHz, 1VPP
10MHz, 1VPP
−54
−52
-
-
-
-
-
-
dB
Crosstalk, all Hostile (Input
Referred)
dB
Static, DC Performance
Input Offset Voltage (Note 3)
Average Drift
13
80
5
30
-
35
-
35
-
mV
µV/˚C
µA
Input Bias Current
18
24
24
(Non-Inverting)(Note 3)
Average Drift
30
-
-
-
nA/˚C
3
www.national.com
+5 Electrical Characteristics (Continued)
(AV = +2, RL =100Ω, VS = +5V1, VCM = VEE + (VS/2), RL tied to VCM, unless specified.
Symbol
Static, DC Performance
Gain Accuracy (Note 3)
Parameter
Conditions
Typ
Min/Max Ratings (Note 2)
Units
±
±
±
±
2.0
0.3
1.5
2.0
µA
Ω
±
±
±
Internal Resistors (Rf, Rg
Power Supply Rejection Ratio
Common Mode Rejection Ratio
1000
48
20%
45
26%
43
30%
43
DC
DC
RL
dB
dB
mA
44
41
39
39
∞
Supply Current (Per
Amplifier)(Note 3)
=
3.0
3.4
3.6
3.6
Miscellaneous Performance
Input Resistance (Non-Inverting)
1.0
2.2
0.62
3.3
0.56
3.3
0.56
3.3
MΩ
Input Capacitance
(Non-Inverting)
pF
Input Voltage Range, High
Input Voltage Range, Low
Output Voltage Range, High
Output Voltage Range, Low
Output Voltage Range, High
Output Voltage Range, Low
Output Current (Note 4)
4.2
0.8
4.0
1.0
4.1
0.9
100
400
4.1
0.9
3.9
1.1
4.0
1.0
80
4.0
1.0
3.8
1.2
4.0
1.0
65
4.0
1.0
3.8
1.2
3.9
1.1
40
V
V
RL = 100Ω
RL = 100Ω
V
V
∞
∞
RL
RL
=
=
V
V
mA
mΩ
Output Resistance, Closed Loop
DC
600
600
600
±
5 Electrical Characteristics
±
(AV = +2, RL = 100Ω, VCC
=
5V, unless specified)
Symbol
Parameter
Conditions
CLC5633IN/IM
Typ
Min/Max Ratings (Note 2)
Units
Ambient Temperature
+25˚C
+25˚C
0 to
−40 to
85˚C
70˚C
Frequency Domain Response
-3dB Bandwidth
VO = 1.0VPP
VO = 4.0VPP
VO = 1.0VPP
130
80
100
60
90
55
12
1.0
0.5
0.6
–
90
55
12
1.0
0.5
0.6
–
MHz
MHz
MHz
dB
−0.1dB Bandwidth
Gain Peaking
20
17
<
<
<
200MHz, VO = 1.0VPP
30MHz, VO = 1.0VPP
30MHz, VO = 1.0VPP
0
0.5
0.3
0.4
0.08
0.1
Gain Rolloff
0.1
0.2
0.03
0.06
dB
Linear Phase Deviation
Differential Gain
deg
%
NTSC, RL = 150Ω
NTSC, RL = 150Ω
Differential Phase
–
–
deg
Time Domain Response
Rise and Fall Time
Settling Time to 0.05%
Overshoot
2V Step
2V Step
2V Step
2V Step
5.0
20
6.5
30
7.0
44
7.7
67
ns
ns
14
17
18
19
%
Slew Rate
410
310
240
225
V/µs
Distortion And Noise Response
2nd Harmonic Distortion
2VPP, 1MHz
−73
−92
−69
−92
−96
−72
–
–
–
–
–
–
dBc
dBc
dBc
dBc
dBc
dBc
2VPP, 1MHz; RL = 1kΩ
2VPP, 5MHz
−58
–
−56
–
−56
–
3rd Harmonic Distortion
Equivalent Input noise
2VPP, 1MHz
2VPP, 1MHz; RL = 1kΩ
2VPP, 5MHz
–
–
–
−66
−65
−65
www.national.com
4
±
5 Electrical Characteristics (Continued)
±
5V, unless specified)
(AV = +2, RL = 100Ω, VCC
=
Symbol
Parameter
Conditions
Typ
Min/Max Ratings (Note 2)
Units
Distortion And Noise Response
>
>
>
Voltage (eni)
1MHz
1MHz
1MHz
4.9
6.6
5.9
8.5
6.4
9.3
6.4
9.0
nV/
Non-Inverting Current (ibn
Inverting Current (ibi)
)
pA/
pA/
11.1
14.7
15.8
15.8
Crosstalk (Input Referred)
10MHz, 1VPP
10MHz, 1VPP
−54
−52
-
-
-
-
-
-
dB
Crosstalk, all Hostile (input
referred)
dB
Static, DC Performance
Input Offset Voltage
Average Drift
7
80
5
30
-
35
-
35
-
mV
µV/˚C
µA
Input Bias Current
(Non-Inverting)
18
25
25
Average Drift
40
-
-
-
nA/˚C
%
±
±
±
±
2.0
Gain Accuracy
0.3
1.5
2.0
±
±
±
Internal Resistors (Rf, Rg)
Power Supply Rejection Ratio
Common Mode Rejection Ratio
Supply Current (per amplifier)
1000
48
20%
45
26%
43
30%
43
Ω
DC
DC
dB
44
41
39
39
dB
∞
RL
=
3.2
3.8
4.0
4.0
mA
Miscellaneous Performance
Input Resistance (Non-inverting)
1.1
1.9
0.63
2.85
0.57
2.85
0.57
2.85
MΩ
Input Capacitance
(Non-Inverting)
pF
±
±
±
±
±
±
±
±
±
±
±
±
Common Mode Input Range
Output Voltage Range
4.2
3.8
4.0
4.1
3.6
3.8
4.1
3.6
3.8
4.0
3.5
3.7
V
V
RL = 100Ω
∞
Output Voltage Range
RL
=
V
Output Current (Note 4)
Output Resistance, Closed Loop
130
400
100
600
80
50
mA
mΩ
DC
600
600
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: AJ-level: spec. is 100% tested at +25˚C.
Note 4: The short circuit current can exceed the maximum safe output current
Note 5: V = V
− V
EE
S
CC
5
www.national.com
+5V Typical Performance Characteristics
Frequency Response
Frequency Response vs. RL
Av = +1
Vo = 0.5Vpp
Gain
Vo = 0.5Vpp
Gain
RL = 1kΩ
Av = -1
Phase
Phase
0
0
-90
-90
RL = 25Ω
RL = 100Ω
Av = +2
-180
-270
-360
-450
-180
-270
-360
-450
1M
10M
100M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
DS015005-4
DS015005-5
Gain Flatness & Linear Phase
Frequency Response vs. VO (AV = 2)
0.05
0
Vo = 0.5Vpp
Gain
Vo = 0.1Vpp
Vo = 1Vpp
-0.05
-0.1
-0.15
-0.2
Phase
Vo = 2Vpp
Vo = 2.5Vpp
1M
10M
100M
0
10
20
30
Frequency (Hz)
Frequency (MHz)
DS015005-7
DS015005-6
Frequency Response vs.
VO (AV = 1)
Frequency Response vs. VO (AV = −1)
Vo = 0.1Vpp
Vo = 0.1Vpp
Vo = 1Vpp
Vo = 1.5Vpp
Vo = 2Vpp
Vo = 2Vpp
Vo = 2.5Vpp
Vo = 2.5Vpp
1M
10M
100M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
DS015005-8
DS015005-9
www.national.com
6
+5V Typical Performance Characteristics (Continued)
PSRR & CMRR
Equivalent Input Noise
3.6
12.5
10
60
CMRR
PSRR
50
40
30
20
10
3.5
3.4
3.3
3.2
Inverting Current 8.7pA/√Hz
Non-Inverting Current 7pA/√Hz
Voltage 3.35nV/√Hz
7.5
5
0
2.5
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
DS015005-10
DS015005-11
2nd & 3rd Harmonic Distortion
2nd & 3rd Harmonic Distortion, RL = 25Ω
-50
-40
Vo = 2Vpp
3rd, 10MHz
-60
2nd, 10MHz
-50
2nd
L = 100Ω
R
-70
-80
2nd
RL = 1kΩ
-60
2nd, 1MHz
3rd, 1MHz
-70
-80
3rd
RL = 1kΩ
-90
3rd
RL = 100Ω
-100
1M
10M
0
0.5
1
1.5
2
2.5
Frequency (Hz)
Output Amplitude (Vpp)
DS015005-12
DS015005-13
2nd & 3rd Harmonic Distortion, RL = 100Ω
2nd & 3rd Harmonic Distortion, RL = 1kΩ
-50
-55
3rd, 10MHz
3rd, 10MHz
2nd, 10MHz
-60
-70
-65
2nd, 1MHz
2nd, 1MHz
3rd, 1MHz
-80
-75
-85
-95
2nd, 10MHz
-90
-100
-110
3rd, 1MHz
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
Output Amplitude (Vpp
)
Output Amplitude (Vpp
)
DS015005-14
DS015005-15
7
www.national.com
+5V Typical Performance Characteristics (Continued)
Large & Small Signal Pulse Response
Output Impedance vs. Frequency
50
40
30
20
10
0
Large Signal
Small Signal
Time (10ns/div)
1k
10k
100k
1M
10M
100M
DS015005-16
Frequency (Hz)
DS015005-17
IBN, VIO vs. Temperature
2.5
7.5
1.5
0
7
6.5
6
0.5
IBN
-1.5
-2.5
5.5
5
VIO
-60
-40
-20
0
20
40
60
80
100
Temperature (ϒC)
DS015005-18
±
±
5V Typical Performance Characteristics (AV = +2, RL = 100Ω, VCC
=
5V, unless specified)
Frequency Response
Frequency Response vs. RL
Av = +1
Vo = 1.0Vpp
Gain
Vo = 1.0Vpp
Gain
Av = -1
RL = 1kΩ
RL = 100Ω
Phase
Phase
0
0
-45
-90
-135
-180
-225
-90
-180
-270
-360
RL = 25Ω
Av = +2
-450
1M
10M
100M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
DS015005-19
DS015005-20
www.national.com
8
±
±
5V Typical Performance Characteristics (AV = +2, RL = 100Ω, VCC
=
5V, unless
specified) (Continued)
Gain Flatness & Linear Phase
Frequency Response vs. VO (AV = 2)
0
VO = 1Vpp
Vo = 0.1Vpp
-0.1
-0.2
-0.3
-0.4
-0.5
Gain
Vo = 2Vpp
Vo = 5Vpp
Vo = 1Vpp
Phase
100M
1M
10M
0
5
10
15
20
25
30
Frequency (Hz)
Frequency (MHz)
DS015005-22
DS015005-21
Frequency Response vs. VO (AV = 1)
Frequency Response vs. VO (AV = −1)
Vo = 1Vpp
Vo = 0.1Vpp
Vo = 1Vpp
Vo = 5Vpp
Vo = 0.1Vpp
Vo = 5Vpp
Vo = 2Vpp
Vo = 2Vpp
1M
10M
100M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
DS015005-23
DS015005-24
Large & Small Signal Pulse Response
Differential Gain and Phase
0.02
-0.02
Large Signal
f = 3.58MHz
0
-0.04
-0.06
-0.08
-0.1
Phase Neg Sync
-0.02
Small Signal
Gain Neg Sync
-0.04
-0.06
-0.08
-0.1
-0.12
-0.14
-0.16
Phase Pos Sync
Gain Pos Sync
-0.12
Time (10ns/div)
1
2
3
4
DS015005-25
Number of 150 Ω Loads
DS015005-26
9
www.national.com
±
±
5V, unless
5V Typical Performance Characteristics (AV = +2, RL = 100Ω, VCC
=
specified) (Continued)
2nd & 3rd Harmonic Distortion vs. Frequency
2nd & 3rd Harmonic Distortion, RL = 25Ω
-45
2nd, 10MHz
-50
3rd, 10MHz
-55
-60
-65
-70
2nd, 1MHz
-75
-80
3rd, 1MHz
-85
0
0.5
1
1.5
2
2.5
Output Amplitude (Vpp
)
DS015005-28
DS015005-27
2nd & 3rd Harmonic Distortion, RL = 100Ω
2nd & 3rd Harmonic Distortion, RL = 1kΩ
-60
-60
3rd, 10MHz
-65
2nd, 10MHz
-70
2nd, 10MHz
-70
3rd, 10MHz
-80
-75
2nd, 1MHz
-80
-90
-100
-110
2nd, 1MHz
-85
3rd, 1MHz
3rd, 1MHz
-90
-95
0
0.5
1
1.5
2
2.5
0
1
2
3
4
5
Output Amplitude (Vpp
)
Output Amplitude (Vpp
)
DS015005-29
DS015005-30
Short Term Settling Time
Long Term Settling Time
0.2
0.15
0.1
0.2
0.15
0.1
Vo = 2V step
Vo = 2V step
0.05
0
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.05
-0.1
-0.15
-0.2
1
10
100
1000
10000
1µ
10µ
100
µ
1m
10m
Time (ns)
Time (s)
DS015005-31
DS015005-32
www.national.com
10
±
±
5V, unless
5V Typical Performance Characteristics (AV = +2, RL = 100Ω, VCC
=
specified) (Continued)
IBN, VOS vs. Temperature
Channel Matching
7.5
2.5
1.5
7.0
6.5
6.0
5.5
5.0
Channel 2
0.5
Channel 3
-0.5
-1.5
-2.5
Channel 1
VOS
IBN
-60
-20
20
60
100
1M
10M
100M
Temperature (ϒC)
DS015005-33
Frequency (Hz)
DS015005-34
All Hostile Crosstalk
Pulse Crosstalk
Active Output
Channel 1
-30
-40
-50
-60
-70
Inactive Output
Channel 2
Inactive Output
Channel 3
Time (10ns/div)
-80
1M
DS015005-36
10M
100M
Frequency (Hz)
DS015005-35
Application Division
CLC5633 Operation
Current Feedback Amplifiers
The CLC5633 is a current feedback buffer fabricated in an
advanced complementary bipolar process. The CLC5633
Some of the key features of current feedback technology
are:
±
operates from a single 5V supply or dual 5V supplies.
•
•
•
•
•
Independence of AC bandwidth and voltage gain
Inherently stable at unity gain
Adjustable frequency response with feedback resistor
High slew rate
Operating from a single 5V supply, the CLC5633 has the
following features:
•
Gains of +1, −1, and 2V/V are achievable without exter-
nal resistors
Fast settling
•
Provides 100mA of output current while consuming only
15mW of power
Current feedback operation can be described using a simple
equation. The voltage gain for a non-inverting or inverting
current feedback amplifier is approximated by Equation 1.
•
•
Offers low −84/−95dBc 2nd and 3rd harmonic distortion
>
<
Provides BW 90MHz and 1MHz distortion −70dBc at
VO = 2VPP
Vo
Av
Rf
±
The CLC5633 performance is further enhanced in 5V sup-
ply applications as indicated in the 5V Electrical Charac-
teristics table and 5V Typical Performance plots.
=
±
V
in
1+
±
Z(jω)
(1)
If gains other than +1, −1, or +2V/V are required, then the
CLC5602 can be used. The CLC5602 is a current feedback
amplifier with near identical performance and allows for ex-
ternal feedback and gain setting resistors.
where:
•
•
AV is the closed loop DC voltage gain
Rf is the feedback resistor
11
www.national.com
Application Division (Continued)
Note: Rb provides DC bias for the non-inverting input. Rb, RL and Rt are tied to Vcm
for minimum power consumption and maximum output swing.
•
•
Z(jω) is the CLC5633’s open loop transimpedance gain
Z(jω)/Rf is the loop gain
Channel 2 and 3 not shown.
VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
1kΩ
1kΩ
6.8µF
+
-
The denominator of Equation 1 is approximately equal to 1 at
low frequencies. Near the −3dB corner frequency, the inter-
action between Rf and Z(jω) dominates the circuit perfor-
mance. The value of the feedback resistor has a large affect
on the circuits performance. Increasing Rf has the following
affects:
+
1kΩ
1kΩ
0.1µF
- +
1kΩ
1kΩ
+
-
Vin
Rb
Vcm
Vo
8
•
•
•
•
•
Decreases loop gain
Rt
Vcm
RL
Vcm
Decreases bandwidth
CLC5633
Reduces gain peaking
Select Rt to yield desired Rin = Rt||Rg, where Rg = 1kΩ.
DS015005-39
Lowers pulse response overshoot
Affects frequency response phase linearity
FIGURE 1. DC Coupled, AV = −1V/V Configuration
CLC5633 Design Information
Note: Rt and RL are tied to Vcm for minimum power
consumption and maximum output swing.
Closed Loop Gain Selection
The CLC5633 is a current feedback op amp with Rf = Rg
=
Channel 2 and 3 not shown.
1kΩ on chip (in the package). Select from three closed loop
gains without using any external gain or feedback resistors.
Implement gains of +2, +1, and −1V/V by connecting pins 5
and 6 (or 9 and 10, or 12 and 13) as described in the chart
below.
VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
1kΩ
1kΩ
6.8µF
+
-
+
1kΩ
1kΩ
0.1µF
- +
Gain AV
Input Connections
Vin
Non-Inverting
(pins 5, 10, &
12)
Inverting (pins 6,
9, & 13)
1kΩ
1kΩ
+
-
Rt
Vo
8
−1V/V
+1V/V
+2V/V
ground
input signal
NC (open)
ground
RL
Vcm
Vcm
CLC5633
input signal
input signal
DS015005-40
The gain accuracy of the CLC5633 is excellent and stable
over temperature change. The internal gain setting resistors,
Rf and Rg are diffused silicon resistors with a process varia-
FIGURE 2. DC Coupled, AV = +1V/V Configuration
±
tion of 20% and a temperature coefficient of −2000ppm/˚C.
Note: Rt and RL and Rg are tied to Vcm for minimum power
consumption and maximum output swing.
Although their absolute values change with processing and
temperature, their ratio (Rf/Rg) remains constant. If an exter-
nal resistor is used in series with Rg, gain accuracy over
temperature will suffer.
Channel 2 and 3 not shown.
VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
1kΩ
1kΩ
Single Supply Operation (VCC=+5V, VEE=GND)
6.8µF
+
-
+
The specifications given in the +5V Electrical Characteris-
tics table for single supply operation are measured with a
common mode voltage (Vcm) of 2.5V. Vcm is the voltage
around which the inputs are applied and the output voltages
are specified.
1kΩ
1kΩ
0.1µF
- +
Vin
Operating from a single +5V supply, the Common Mode
Input Range (CMIR) of the CLC5633 is typically +0.8V to
+4.2V. The typical output range with RL=100Ω is +1.0V to
+4.0V.
1kΩ
1kΩ
+
-
Vcm
Rt
Vo
8
For single supply DC coupled operation, keep input signal
levels above 0.8V DC, AC coupling and level shifting the
signal are recommended. The non-inverting and inverting
configurations for both input conditions are illustrated in the
following 2 sections.
RL
Vcm
Vcm
CLC5633
DS015005-41
FIGURE 3. DC Coupled, AV = +2V/V Configuration
DC Coupled Single Supply Operation
Figure 1, Figure 2, and Figure 3 on the following page, show
the recommended configurations for input signals that re-
main above 0.8V DC. Note: Rb provides DC bias for the
non-inverting input. Rb, RL and Rt are tied to Vcm for mini-
mum power consumption and maximum output swing. Chan-
nel 2 and 3 not shown.
AC Coupled Single Supply Operation
Figure 4, Figure 5, and Figure 6 show possible non-inverting
and inverting configurations for input signals that go below
0.8V DC.
www.national.com
12
Dual Supply Operation
Application Division (Continued)
The CLC5633 operates on dual supplies as well as signal
supplies. The non-inverting and inverting configurations are
shown in Figure 7, Figure 8, and Figure 9.
Note: Channel 2 and 3 not shown.
VCC
1
Note: Rb provides DC bias for the
non-inverting input. Select Rt to
yield desired Rin = Rt||1kΩ.
14
13
12
11
10
9
1kΩ
1kΩ
6.8µF
Channel 2 and 3 not shown.
+
-
+
2
3
4
5
6
7
VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
VCC
1kΩ
1kΩ
6.8µF
+
-
+
1kΩ
1kΩ
0.1µF
- +
R
1kΩ
1kΩ
0.1µF
- +
1kΩ
1kΩ
+
-
Vin
R
0.1µF
1kΩ
1kΩ
+
-
Vin
Rb
CC
Vo
Vo
8
+
8
Rt
6.8µF
V
= −V + 2.5
in
o
CLC5633
1
CLC5633
VEE
FIGURE 7. Dual Supply, AV = −1V/V Configuration
,
Low frequency cutoff =
2πR C
DS015005-45
g
C
where R = 1kΩ.
g
DS015005-42
FIGURE 4. AC Coupled, AV = −1V/V Configuration
Note: Channel 2 and 3 not shown.
The input is AC coupled to prevent the need for level shifting
the input signal at the source. The resistive voltage divider
VCC
1
biases the non-inverting input to VCC ÷ 2 = 2.5V (For VCC
+5V).
=
14
13
12
11
10
9
1kΩ
1kΩ
6.8µF
+
-
+
2
3
Note: Channel 2 and 3 not shown.
1kΩ
1kΩ
0.1µF
- +
4
VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
Vin
1kΩ
1kΩ
5
6.8µF
+
-
+
0.1µF
1kΩ
1kΩ
+
-
6
7
Rt
VCC
Vo
+
8
1kΩ
1kΩ
0.1µF
- +
6.8µF
R
CC
Vin
CLC5633
VEE
DS015005-46
1kΩ
1kΩ
+
-
R
FIGURE 8. Dual Supply, AV = +1V/V Configuration
C
Vo
8
V
= 2V + 2.5
in
o
1
CLC5633
Low frequency cutoff =
,
2πR
C
C
Note: Channel 2 and 3 not shown.
in
R >> R
source
R
whereR
=
in
2
VCC
DS015005-43
1
2
3
4
5
6
7
14
13
12
11
10
9
1kΩ
1kΩ
6.8µF
+
-
FIGURE 5. AC Coupled, AV = +1V/V Configuration
+
1kΩ
1kΩ
0.1µF
- +
Note: Channel 2 and 3 not shown.
Vin
VCC
0.1µF
1kΩ
1kΩ
1
2
3
4
5
6
7
14
13
12
11
10
9
+
-
1kΩ
1kΩ
Rt
6.8µF
+
-
+
Vo
+
8
VCC
6.8µF
CLC5633
VEE
1kΩ
1kΩ
0.1µF
- +
R
CC
Vin
DS015005-47
1kΩ
1kΩ
+
-
FIGURE 9. Dual Supply, AV= + 2V/V Configuration
R
C
Vo
8
Load Termination
V
= 2V + 2.5
in
o
The CLC5633 can source and sink near equal amounts of
current. For optimum performance, the load should be tied to
1
CLC5633
Low frequency cutoff =
,
2πR
C
C
in
R >> R
source
R
whereR
=
in
VCM
.
2
DS015005-44
FIGURE 6. AC Coupled, AV = +2V/V Configuration
13
www.national.com
Application Division (Continued)
Note: Channel 2 and 3 not shown.
1
2
3
4
5
6
7
14
13
12
11
10
9
1kΩ
1kΩ
Driving Cables and Capacitive Loads
+
-
Z0
R1
R3
When driving cables, double termination is used to prevent
reflections. For capacitive load applications, a small series
resistor at the output of the CLC5633 will improve stability
and settling performance. The Frequency Response vs. CL
plot, shown below in Figure 10, gives the recommended
series resistance value for optimum flatness at various ca-
pacitive loads.
+
-
V2
1kΩ
1kΩ
-
+
R2
Z0
R4
1kΩ
1kΩ
+
-
+
-
V1
8
R5
Z0
CLC5633
R6
C6
Vo
R7
Vo = 1Vpp
CL = 10pF
Rs = 49.9Ω
DS015005-49
FIGURE 11. Transmission Line Matching
Power Dissipation
CL = 100pF
Rs = 21Ω
CL = 1000pF
Rs = 6.7Ω
Follow these steps to determine the power consumption of
the CLC5633:
+
Rs
1. Calculate the quiescent (no-load) power: Pamp=ICC (VCC
VEE
2. Calculate the RMS power at the output stage: PO=(VCC
-
-
CL
1k
)
1k
1k
-
VLOAD)(ILOAD), where Vload and Iload are the RMS voltage
and current across the external load.
1M
10M
100M
3. Calculate the total RMS power: Pt=Pamp+PO
Frequency (Hz)
DS015005-48
The maximum power that the DIP and SOIC, packages can
dissipate at a given temperature is illustrated in Figure 12.
The power derating curve for any CLC5633 package can be
derived by utilizing the following equation:
FIGURE 10. Frequency Response vs. CL
Transmission Line Matching
One method for matching the characteristic impedance (Zo)
of a transmission line or cable is to place the appropriate
resistor at the input or output of the amplifier. Figure 11
shows typical inverting and non-inverting circuit configura-
tions for matching transmission lines.
where
Tamb = Ambient temperature (˚C)
Non-Inverting gain applications:
θJA = Thermal resistance, from junction to ambient, for a
given package (˚C/W)
•
Connect pin 2 as indicated in the table in the Closed
Loop Gain Selection section.
•
•
Make R1, R2, R6, and R7 equal to ZO.
Use R3 to isolate the amplifier from reactive loading
caused by the transmission line, or by parasitics.
Inverting gain applications:
•
•
•
Connect R3 directly to ground.
Make the resistors R4, R6, and R7 equal to ZO.
Make R5\Rg=ZO.
The input and output matching resistors attenuate the signal
by a factor of 2, therefore additional gain is needed. Use C6
to match the output transmission line over a greater fre-
quency range. C6 compensates for the increase of the am-
plifier’s output impedance with frequency.
DS015005-51
FIGURE 12. Power Derating Curve
www.national.com
14
•
•
Reproduce typical DC, AC, Transient, and Noise perfor-
mance
Application Division (Continued)
Layout Considerations
Support room temperature simulations
A proper printed circuit layout is essential for achieving high
frequency performance. National provides evaluation boards
for the CLC5633 (CLC730075-DIP, CLC730074-SOIC) and
suggests their use as a guide for high frequency layout and
as an aid for device testing and characterization.
The readme file that accompanies the diskette lists released
models, and provides a list of modeled parameters. The
application note OA-18, Simulation SPICE Models for Na-
tional’s Op Amps, contains schematics and a reproduction of
the readme file.
General layout and supply bypassing play major roles in high
frequency performance. Follow the steps below as a basis
for high frequency layout:
Application Circuits
Single Supply Cable Driver
Figure 13 below shows the CLC5633 driving 10m of 75Ω
coaxial cable. The CLC5633 is set for a gain of +2V/V to
compensate for the divide-by-two voltage drop at VO. The
response after 10m of cable is illustrated in Figure 14.
•
•
•
•
Include 6.8µF tantalum and 0.1µF ceramic capacitors on
both supplies.
Place the 6.8µF capacitors within 0.75 inches of the
power pins.
+5V
Place the 0.1µF capacitors less than 0.1 inches from the
power pins.
Note: Channel 2 and 3 not shown.
1
2
3
4
5
6
7
14
13
12
11
10
9
1kΩ
1kΩ
6.8µF
+
-
+
Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance.
+5V
5kΩ
5kΩ
1kΩ
1kΩ
0.1µF
- +
0.1µF
Vin
10m of 75Ω
1kΩ
1kΩ
Coaxial Cable
+
-
•
Use flush-mount printed circuit board pins for prototyping,
never use high profile DIP sockets.
75Ω
0.1µF
Vo
0.1µF
8
75Ω
Evaluation Board Information
CLC5633
A data sheet is available for the CLC730075/CLC730074
evaluation boards. The evaluation board data sheets pro-
vide:
DS015005-52
FIGURE 13. Single Supply Cable Driver
•
•
•
Evaluation board schematics
Evaluation board layouts
Vin = 10MHz, 0.5Vpp
General information about the boards
The evaluation boards are designed to accommodate dual
supplies. The boards can be modified to provide single
supply operation. For best performance; 1) do not connect
the unused supply, 2) ground the unused supply pin.
Special Evaluation Board
Considerations for the CLC5633
To optimize off-isolation of the CLC5633, cut the Rf trace on
both the CLC730074 and the CLC730075 evaluation
boards. This cut minimizes capacitive feedthrough between
the input and the output.
SPICE Models
20ns/div
SPICE models provide a means to evaluate amplifier de-
signs. Free SPICE models are available for National’s mono-
lithic amplifiers that:
DS015005-53
FIGURE 14. Response After 10m of Cable
•
Support Berkeley SPICE 2G and its many derivatives
15
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
14-Pin SOIC
NSC Package Number M14A
14-Pin SOIC
NSC Package Number M14B
www.national.com
16
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Pin MDIP
NSC Package Number N14A
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2. A critical component is any component of a life
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