DS91D176TMA [NSC]
Multipoint-LVDS (M-LVDS) Transceivers; 多点LVDS （ M- LVDS ）收发器
| 型号： | DS91D176TMA |
| 厂家： | 
National Semiconductor |
| 描述： | Multipoint-LVDS (M-LVDS) Transceivers |
| 文件： | 总14页 (文件大小：373K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2007
DS91D176/DS91C176
Multipoint-LVDS (M-LVDS) Transceivers
nals. The DS91D176 has a M-LVDS type 1 receiver input with
no offset. The DS91C176 receiver contains an M-LVDS type
2 failsafe circuit with an internal 100 mV offset that provides
a LOW output for both short and open input conditions.
General Description
The DS91C176 and DS91D176 are high-speed M-LVDS dif-
ferential transceivers designed for multipoint applications with
multiple drivers or receivers. Multipoint LVDS (M-LVDS) is a
new bus interface standard (TIA/EIA-899) based on LVDS but
including several enhancements to improve multipoint per-
formance. M-LVDS devices have superior drive capability
and can support up to 32 loads. Along with increased drive,
M-LVDS devices are required to have a controlled edge rate
to minimize reflections and EMI. The 1 nSec minimum edge
rate is tolerant of stub lengths up to 2 inches in length. M-
LVDS devices also have a very large common mode range
for additional noise margin in heavily loaded and noisy back-
plane environments.
Features
Meets TIA/EIA-899 M-LVDS Standard
■
■
■
■
■
■
■
■
Capable of driving 32 LVDS loads
Controlled Edge Rates Tolerant to Stubs
Wide Common Mode for Increased Noise Immunity
DS91D176 has type 1 receiver input
DS91C176 has type 2 receiver with fail-safe
Up to 200 Mbps operation
The DS91C176/DS91D176 are half-duplex transceivers that
accept LVTTL/LVCMOS signals at the driver inputs and con-
vert them to differential M-LVDS signal levels. The receiver
inputs accept low voltage differential signals (LVDS, B-LVDS,
M-LVDS, LV-PECL) and convert them to 3V LVCMOS sig-
Industrial temperature range
Single 3.3V supply
■
■
8-lead SOIC package
Typical Application in AdvancedTCA Clock Distribution
20024630
© 2007 National Semiconductor Corporation
200246
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Connection and Logic Diagram
20024601
Top View
Order Number DS91D176TMA, DS91C176TMA
See NS Package Number M08A
Ordering Information
Order Number
Receiver Input
type 1
type 2
Function
Package Type
SOIC/M08A
SOIC/M08A
DS91D176TMA
DS91C176TMA
Data (0V threshold receiver)
Control (100 mV offset fail-safe receiver)
M-LVDS Receiver Types
The EIA/TIA-899 M-LVDS standard specifies two different
types of receiver input stages. A type 1 receiver has a con-
ventional threshold that is centered at the midpoint of the input
amplitude, VID/2. A type 2 receiver has a built in offset that is
100mV greater then VID/2. The type 2 receiver offset acts as
a failsafe circuit where open or short circuits at the input will
always result in the output stage being driven to a low logic
state.
20024640
FIGURE 1. M-LVDS Receiver Input Thresholds
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2
ESD Ratings:
(HBM 1.5kΩ, 100pF)
(EIAJ 0Ω, 200pF)
(CDM 0Ω, 0pF)
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
≥ 8 kV
≥ 250 V
≥ 1000 V
Supply Voltage, VCC
−0.3V to +4V
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−1.8V to +4.1V
−1.8V to +4.1V
−0.3V to (VCC + 0.3V)
Recommended Operating
Conditions
Control Input Voltages
Driver Input Voltage
Driver Output Voltages
Receiver Input Voltages
Receiver Output Voltage
Min Typ Max Units
Supply Voltage, VCC
3.0 3.3 3.6
V
V
Voltage at Any Bus Terminal
ꢀ(Separate or Common-Mode)
Differential Input Voltage VID
LVTTL Input Voltage High VIH
LVTTL Input Voltage Low VIL
Operating Free Air
−1.4
+3.8
Maximum Package Power Dissipation at +25°C
SOIC Package
Derate SOIC Package
Thermal Resistance
ꢀθJA
833 mW
6.67 mW/°C above +25°C
2.4
VCC
0.8
V
V
V
2.0
0
150°C/W
ꢀθJC
63°C/W
150°C
−65°C to +150°C
Temperature TA
−40 +25 +85
°C
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature
(Soldering, 4 seconds)
260°C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3, 4, 8)
Symbol
Parameter
Conditions
Min
Typ
Max Units
M-LVDS Driver
|VAB
|
Differential output voltage magnitude
480
650
mV
RL = 50Ω, CL = 5pF
Figure 2 and Figure 4
Change in differential output voltage magnitude
between logic states
ΔVAB
−50
0.3
0
+50
2.1
mV
V
VOS(SS)
Steady-state common-mode output voltage
1.8
RL = 50Ω, CL = 5pF
Figure 2 and Figure 3
Change in steady-state common-mode output
voltage between logic states
|ΔVOS(SS)
|
0
+50
mV
(VOS(PP) @ 500KHz clock)
VOS(PP)
VA(OC)
VB(OC)
VP(H)
Peak-to-peak common-mode output voltage
135
mV
V
Maximum steady-state open-circuit output voltage Figure 5
Maximum steady-state open-circuit output voltage
Voltage overshoot, low-to-high level output
0
0
2.4
2.4
V
1.2VSS
V
RL = 50Ω, CL = 5pF, CD = 0.5pF
Figure 7 and Figure 8 (Note 9)
VP(L)
Voltage overshoot, high-to-low level output
−0.2VS
V
S
IIH
High-level input current (LVTTL inputs)
Low-level input current (LVTTL inputs)
Input Clamp Voltage (LVTTL inputs)
Differential short-circuit output current
VIH = 2.0V
VIL = 0.8V
IIN = -18mA
Figure 6
-15
15
15
μA
μA
V
IIL
-15
-1.5
-43
VIKL
IOS
43
mA
M-LVDS Receiver
VIT+
Positive-going differential input voltage threshold
See Function Tables
Type 1
Type 2
Type 1 −50
20
94
50
mV
mV
mV
mV
V
150
VIT−
Negative-going differential input voltage threshold See Function Tables
20
Type 2
50
94
VOH
VOL
IOZ
High-level output voltage (LVTTL output)
Low-level output voltage (LVTTL output)
TRI-STATE output current
IOH = −8mA
IOL = 8mA
2.4
2.7
0.28
0.4
10
V
VO = 0V or 3.6V
−10
μA
IOSR
Short-circuit receiver output current (LVTTL output) VO = 0V
-48
-90
mA
3
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Symbol
Parameter
Conditions
Min
Typ
Max Units
M-LVDS Bus (Input and Output) Pins
IA
Transceiver input/output current
Transceiver input/output current
VA = 3.8V, VB = 1.2V
32
µA
µA
µA
µA
µA
µA
µA
VA = 0V or 2.4V, VB = 1.2V
VA = −1.4V, VB = 1.2V
VB = 3.8V, VA = 1.2V
−20
−32
+20
IB
32
VB = 0V or 2.4V, VA = 1.2V
VB = −1.4V, VA = 1.2V
−20
−32
−4
+20
IAB
Transceiver input/output differential current (IA − IB)
Transceiver input/output power-off current
+4
32
VA = VB, −1.4V ≤ V ≤ 3.8V
VA = 3.8V, VB = 1.2V,
IA(OFF)
µA
µA
µA
µA
µA
µA
µA
DE = VCC = 1.5V
VA = 0V or 2.4V, VB = 1.2V,
DE = VCC = 1.5V
−20
−32
+20
VA = −1.4V, VB = 1.2V,
DE = VCC = 1.5V
IB(OFF)
Transceiver input/output power-off current
Transceiver input/output power-off differential
VB = 3.8V, VA = 1.2V,
DE = VCC = 1.5V
32
VB = 0V or 2.4V, VA = 1.2V,
DE = VCC = 1.5V
−20
−32
−4
+20
VB = −1.4V, VA = 1.2V,
DE = VCC = 1.5V
IAB(OFF)
VA = VB, −1.4V ≤ V ≤ 3.8V,
VCC = 1.5V, DE = 1.5V
+4
current (IA(OFF) − IB(OFF)
)
CA
Transceiver input/output capacitance
Transceiver input/output capacitance
Transceiver input/output differential capacitance
VCC = OPEN
9
9
pF
pF
pF
CB
CAB
CA/B
5.7
Transceiver input/output capacitance balance (CA/
CB)
1.0
SUPPLY CURRENT (VCC
)
ICCD
ICCZ
ICCR
Driver Supply Current
20
6
29.5
9.0
mA
mA
mA
RL = 50Ω, DE = VCC, RE = VCC
DE = GND, RE = VCC
TRI-STATE Supply Current
Receiver Supply Current
DE = GND, RE = GND
14
18.5
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4
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 3, 8)
Symbol
Parameter
Conditions
Min
Typ
Max Units
DRIVER AC SPECIFICATION
tPLH
Differential Propagation Delay Low to High
Differential Propagation Delay High to Low
Pulse Skew |tPLHD − tPHLD| (Notes 5, 9)
Part-to-Part Skew (Notes 6, 9)
Rise Time (Note 9)
1.3
1.3
3.4
3.1
5.0
5.0
420
1.3
3.0
3.0
8
ns
ns
RL = 50Ω, CL = 5 pF,
CD = 0.5 pF
tPHL
Figure 7 and Figure 8
tSKD1 (tsk(p)
tSKD3
tTLH (tr)
tTHL (tf)
tPZH
)
300
ps
ns
1.0
1.0
1.8
1.8
ns
Fall Time (Note 9)
ns
Enable Time (Z to Active High)
Enable Time (Z to Active Low )
Disable Time (Active Low to Z)
Disable Time (Active High to Z)
Random Jitter, RJ (Note 9)
ns
RL = 50Ω, CL = 5 pF,
CD = 0.5 pF
tPZL
8
ns
Figure 9 and Figure 10
tPLZ
8
ns
tPHZ
8
ns
tJIT
100 MHz Clock Pattern (Note 7)
2.5
5.5
psrms
Mbps
fMAX
Maximum Data Rate
200
RECEIVER AC SPECIFICATION
tPLH
Propagation Delay Low to High
CL = 15 pF
2.0
2.0
4.7
5.3
0.6
7.5
7.5
1.7
1.3
2.5
2.5
10
ns
ns
Figures 11, 12 and Figure 13
tPHL
Propagation Delay High to Low
Pulse Skew |tPLHD − tPHLD| (Notes 5, 9)
Part-to-Part Skew (Notes 6, 9)
Rise Time (Note 9)
tSKD1 (tsk(p)
tSKD3
tTLH (tr)
tTHL (tf)
tPZH
)
ns
ns
0.5
0.5
1.2
1.2
ns
Fall Time (Note 9)
ns
Enable Time (Z to Active High)
Enable Time (Z to Active Low)
Disable Time (Active Low to Z)
Disable Time (Active High to Z)
Maximum Data Rate
ns
RL = 500Ω, CL = 15 pF
Figure 14 and Figure 15
tPZL
10
ns
tPLZ
10
ns
tPHZ
10
ns
fMAX
200
Mbps
Note 1: “Absolute Maximum Ratings” are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise
specified.
Note 3: All typicals are given for VCC = 3.3V and TA = 25°C.
Note 4: The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this datasheet.
Note 5: tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
the same channel.
Note 6: tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 7: Stimulus and fixture Jitter has been subtracted.
Note 8: CL includes fixture capacitance and CD includes probe capacitance.
Note 9: Not production tested. Guaranteed by a statistical analysis on a sample basis at the time of characterization.
5
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Test Circuits and Waveforms
20024614
FIGURE 2. Differential Driver Test Circuit
20024624
FIGURE 3. Differential Driver Waveforms
20024622
FIGURE 4. Differential Driver Full Load Test Circuit
20024612
FIGURE 5. Differential Driver DC Open Test Circuit
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20024625
FIGURE 6. Differential Driver Short-Circuit Test Circuit
20024616
FIGURE 7. Driver Propagation Delay and Transition Time Test Circuit
20024618
FIGURE 8. Driver Propagation Delays and Transition Time Waveforms
7
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20024619
FIGURE 9. Driver TRI-STATE Delay Test Circuit
20024621
FIGURE 10. Driver TRI-STATE Delay Waveforms
20024615
FIGURE 11. Receiver Propagation Delay and Transition Time Test Circuit
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20024617
FIGURE 12. Type 1 Receiver Propagation Delay and Transition Time Waveforms
20024623
FIGURE 13. Type 2 Receiver Propagation Delay and Transition Time Waveforms
20024613
FIGURE 14. Receiver TRI-STATE Delay Test Circuit
9
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20024620
FIGURE 15. Receiver TRI-STATE Delay Waveforms
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Function Tables
DS91D176/DS91C176 Transmitting
Inputs
DE
Outputs
RE
X
D
B
A
H
L
2.0V
2.0V
0.8V
2.0V
0.8V
X
L
H
Z
X
X
Z
X — Don't care condition
Z — High impedance state
DS91D176 Receiving
DS91C176 Receiving
Inputs
Inputs
DE
Output
Output
RE
A − B
R
H
L
RE
DE
A − B
R
H
L
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
≥ +0.05V
≥ +0.15V
≤ −0.05V
≤ +0.05V
0.8V
2.0V
0.8V
0.8V
0V
X
Z
0.8V
2.0V
0.8V
0.8V
0V
L
Z
X
X
X — Don't care condition
Z — High impedance state
X — Don't care condition
Z — High impedance state
DS91D176 Receiver Input Threshold Test Voltages
Applied Voltages
Resulting Differential Input
Voltage
Resulting Common-Mode
Receiver
Output
Input Voltage
VIA
VIB
VID
VIC
R
2.400V
0.000V
3.800V
3.750V
−1.400V
−1.350V
0.000V
2.400V
3.750V
3.800V
−1.350V
−1.400V
2.400V
−2.400V
0.050V
1.200V
1.200V
3.775V
3.775V
−1.375V
−1.375V
H
L
H
L
−0.050V
−0.050V
0.050V
H
L
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
DS91C176 Receiver Input Threshold Test Voltages
Applied Voltages
Resulting Differential Input
Resulting Common-Mode
Input Voltage
Receiver
Output
Voltage
VIA
VIB
VID
VIC
R
2.400V
0.000V
3.800V
3.800V
−1.250V
−1.350V
0.000V
2.400V
3.650V
3.750V
−1.400V
−1.400V
2.400V
−2.400V
0.150V
0.050V
0.150V
0.050V
1.200V
1.200V
3.725V
3.775V
−1.325V
−1.375V
H
L
H
L
H
L
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
11
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Pin Descriptions
Pin No.
Name
R
Description
1
2
Receiver output pin
RE
Receiver enable pin: When RE is high, the receiver is disabled. When
RE is low or open, the receiver is enabled.
3
DE
Driver enable pin: When DE is low, the driver is disabled. When DE
is high, the driver is enabled.
4
5
6
7
8
D
GND
A
Driver input pin
Ground pin
Non-inverting driver output pin/Non-inverting receiver input pin
Inverting driver output pin/Inverting receiver input pin
Power supply pin, +3.3V ± 0.3V
B
VCC
Application Information
STUB LENGTH
typical loaded backplane, then the maximum stub length is
312 ps/160 ps/inch or 1.95 inches (approximately 2 inches).
To determine the maximum stub for your backplane, the prop-
agation velocity for the backplane is required (refer to appli-
cation notes AN-905 and AN-808).
Stub lengths should be kept to a minimum. For a general ap-
proximation, if the electrical length of a trace is greater than
1/5 of the transition edge, then the trace is considered a
transmission line. If the velocity equals 160 ps per inch for a
Typical Performance Characteristics
Supply Current vs. Frequency
Output VOD vs. Load Resistance
20024662
20024663
Supply Current measured using a clock pattern with driver terminated to 50ohms .VCC = 3.3V, TA = +25°C
VCC = 3.3V, TA = +25°C.
FIGURE 16. SOIC performance Characteristics
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12
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS91D176TMA, DS91C176TMA
See NS package Number M08A
13
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Notes
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