LM49350RL/NOPB [NSC]
IC SPECIALTY CONSUMER CIRCUIT, PBGA36, 3.5 X 3.5 MM, ROHS COMPLIANT, MICRO SMDXT-36, Consumer IC:Other;
| 型号： | LM49350RL/NOPB |
| 厂家： | 
National Semiconductor |
| 描述： | IC SPECIALTY CONSUMER CIRCUIT, PBGA36, 3.5 X 3.5 MM, ROHS COMPLIANT, MICRO SMDXT-36, Consumer IC:Other 解码器 编解码器 放大器 |
| 文件： | 总104页 (文件大小：3383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 29, 2009
LM49350
High Performance Audio Codec Sub-System with a
Ground-Referenced Stereo Headphone Amplifier & an
Ultra Low EMI Class D Loudspeaker Amplifier with Dual
I2S/PCM Digital Audio Interfaces
SNR (Stereo DAC at 48kHz)
SNR (Stereo ADC at 48kHz)
Shutdown Current
PSRR at 217 Hz, A_VDD = 3.3V, (HP from
AUX)
96dB (typ)
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1.0 General Description
94dB (typ)
2.3µA (typ)
97dB (typ)
The LM49350 is a high performance audio subsystem that
supports both analog and digital audio functions. The
LM49350 includes a high quality stereo DAC, a high quality
stereo ADC, a stereo headphone amplifier that supports
ground referenced output cap-less operation, a dual mode
earpiece speaker amplifier, and a low EMI Class D loud-
speaker amplifier. It is designed for demanding applications
in mobile phones and other portable devices.
4.0 Features
High performance 96dB SNR stereo DAC
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High performance 94dB SNR stereo ADC
The LM49350 features dual bi-directional I2S or PCM audio
interfaces for full range audio and an I2C compatible interface
for control. The stereo DAC path features an SNR of 96dB
with 24-bit 48 kHz input. The headphone amplifier delivers
69mWRMS (typ) to a 32Ω single-ended stereo load with less
than 1% distortion (THD+N) when A_VDD = 3.3V. The ear-
piece speaker amplifier delivers 58mWRMS (typ) to a 32Ω
bridged-tied load with less than 1% distortion (THD+N) when
A_VDD = 3.3V. The loudspeaker amplifier delivers up to
495mW into an 8Ω load with less than 1% distortion when
LS_VDD = 3.3V and up to 1.2W when LS_VDD = 5.0V.
Up to 192kHz stereo audio playback
Up to 48kHz stereo recording
Dual bidirectional I2S or PCM compatible audio interfaces
Read/write I2C compatible control interface
Flexible digital mixer with sample rate conversion
Dual sigma-delta PLLs for operation from any clock at any
sample rate
Digital 3D stereo enhancement
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Dual 5 band parametric equalizers
Cascadable DSP effects that allow 10 band parametric
equalization
ALC/Compressor/Limiter on both DAC and ADC paths
The LM49350 employs advanced techniques to reduce pow-
er consumption, to reduce controller overhead, to speed de-
velopment time, and to eliminate click and pop. Boomer audio
power amplifiers were designed specifically to provide high
quality output power with a minimal amount of external com-
ponents. It is therefore ideally suited for mobile phone and
other low voltage applications where minimal power con-
sumption, PCB area and cost are primary requirements.
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Ultra low EMI, Class D loudspeaker amplifier with spread
spectrum control
Ground referenced output cap-less headphone amplifier
operation
Earpiece speaker amplifier with reduced power
consumption mode for mono differential line out
applications
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2.0 Applications
Stereo auxiliary inputs or mono differential input
Smart Phones
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Differential stereo microphone inputs with single-ended
option
Automatic level control for digital audio inputs, stereo
microphone inputs, and stereo auxiliary inputs
Mobile Phones and VOIP Phones
Portable GPS Navigator and Portable Gaming Devices
Portable DVD/CD/AAC/MP3/MP4 Players
Digital Cameras/Camcorders
■
Flexible audio routing from input to output
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16 Step volume control for microphones with 2dB steps
32 Step volume control for auxiliary inputs in 1.5dB steps
Micro-power shutdown mode
3.0 Key Specifications
PHP at A_VDD = 3.3V, Stereo 32Ω, 1% THD 69mW/ch (typ)
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PLS at LS_VDD = 5V, 8Ω, 1% THD
PLS at LS_VDD = 4.2V, 8Ω, 1% THD
PLS at LS_VDD = 3.3V, 8Ω, 1% THD
PEP at A_VDD = 3.3V, 32Ω BTL, 1% THD
1.2W (typ)
825mW (typ)
495mW (typ)
58mW (typ)
Available in the 3.5 x 3.5 mm 36 bump micro SMD package
■ꢀSupply Voltage Range
ꢀꢀD_VDD = 1.7V to 2.0V
ꢀꢀLS_VDD and A_VDD = 2.7V to 5.5V
ꢀꢀI/O_VDD = 1.6V to 4.5V
Boomer® is a registered trademark of National Semiconductor Corporation.
© 2009 National Semiconductor Corporation
201941
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5.0 LM49350 Overview
20194111
FIGURE 1. LM49350 Block Diagram
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6.0 Typical Application
20194102
FIGURE 2. Example Application in Multimedia Phone with a Dedicated Earpiece and Mono Loudspeaker
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20194103
FIGURE 3. Example Application in Multimedia Phone Using Stereo Loudspeaker
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20194104
FIGURE 4. Example Application in a Multimedia Phone Using a Dedicated RF Module for Voice Modern Functions
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20194105
FIGURE 5. Example Application in a Portable Media Player with a Differential Stereo Line Input
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Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Applications .................................................................................................................................... 1
3.0 Key Specifications ........................................................................................................................... 1
4.0 Features ........................................................................................................................................ 1
5.0 LM49350 Overview .......................................................................................................................... 2
6.0 Typical Application ........................................................................................................................... 3
7.0 Connection Diagrams ..................................................................................................................... 10
7.1 PIN TYPE DEFINITIONS ........................................................................................................ 11
8.0 Absolute Maximum Ratings ............................................................................................................ 12
9.0 Operating Ratings ......................................................................................................................... 12
10.0 Electrical Characteristics: A_VDD = LS_VDD = 3.3V; D_VDD = I/O_VDD = 1.8V (Notes 1, 2) ..................... 12
11.0 Timing Characteristics: DVDD = I/OVDD = 1.8V (Notes 1, 2) ................................................................. 16
12.0 Typical Performance Characteristics .............................................................................................. 17
13.0 System Control ............................................................................................................................ 24
13.1 I2C SIGNALS ....................................................................................................................... 24
13.2 I2C DATA VALIDITY ............................................................................................................. 24
13.3 I2C START AND STOP CONDITIONS ..................................................................................... 24
13.4 TRANSFERRING DATA ........................................................................................................ 24
13.5 I2C TIMING PARAMETERS .................................................................................................. 26
14.0 Device Register Map .................................................................................................................... 27
15.0 Basic PMC Setup Register ............................................................................................................ 32
16.0 PMC Clocks Register ................................................................................................................... 33
17.0 PMC Clock Divide Register ........................................................................................................... 33
18.0 LM49350 Clock Network .............................................................................................................. 34
19.0 PLL Setup Registers .................................................................................................................... 36
20.0 Analog Mixer Control Registers ..................................................................................................... 42
20.1 CLASS D LOUDSPEAKER AMPLIFIER .................................................................................. 42
20.2 SPREAD SPECTRUM MODULATION .................................................................................... 42
20.3 CLASS D POWER DISSIPATION AND EFFICIENCY ............................................................... 42
20.4 HEADPHONE AMPLIFIER FUNCTION ................................................................................... 43
20.5 CHARGE PUMP CAPACITOR SELECTION ............................................................................ 43
20.6 CHARGE PUMP FLYING CAPACITOR (C6) ............................................................................ 43
20.7 CHARGE PUMP FLYING CAPACITOR (C5) ............................................................................ 43
20.8 AUXILIARY OUTPUT AMPLIFIER .......................................................................................... 44
21.0 ADC Control Registers ................................................................................................................. 48
22.0 DAC Control Registers ................................................................................................................. 50
23.0 Digital Mixer Control Registers ...................................................................................................... 51
23.1 DIGITAL MIXER ................................................................................................................... 51
24.0 Audio Port Control Registers ......................................................................................................... 55
25.0 Digital Effects Engine ................................................................................................................... 60
25.1 DIGITAL SIGNAL PROCESSOR (DSP) ................................................................................... 60
25.2 ALC OVERVIEW .................................................................................................................. 62
26.0 DAC Effects Registers .................................................................................................................. 78
27.0 GPIO Registers ........................................................................................................................... 95
FIGURE 24. Demo Board Schematic ..................................................................................................... 97
28.0 Demonstration Board Layout ......................................................................................................... 98
29.0 Revision History ........................................................................................................................ 101
30.0 Physical Dimensions .................................................................................................................. 102
List of Figures
FIGURE 1. LM49350 Block Diagram ............................................................................................................. 2
FIGURE 2. Example Application in Multimedia Phone with a Dedicated Earpiece and Mono Loudspeaker ......................... 3
FIGURE 3. Example Application in Multimedia Phone Using Stereo Loudspeaker ...................................................... 4
FIGURE 4. Example Application in a Multimedia Phone Using a Dedicated RF Module for Voice Modern Functions ............. 5
FIGURE 5. Example Application in a Portable Media Player with a Differential Stereo Line Input .................................... 6
FIGURE 6. I2C Signals: Data Validity ............................................................................................................ 24
FIGURE 7. I2C Start and Stop Conditions ...................................................................................................... 24
FIGURE 8. I2C Chip Address ..................................................................................................................... 24
FIGURE 9. Example I2C Write Cycle ............................................................................................................ 25
FIGURE 10. Example I2C Read Cycle .......................................................................................................... 26
FIGURE 11. I2C Timing Diagram ................................................................................................................. 26
FIGURE 12. Internal Clock Network ............................................................................................................. 35
FIGURE 13. PLL1 Loop ........................................................................................................................... 36
FIGURE 14. PLL2 Loop ............................................................................................................................ 36
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FIGURE 15. EMI/RFI Filter for the Class D Amplifier ......................................................................................... 43
FIGURE 16. Digital Mixer .......................................................................................................................... 51
FIGURE 17. I2S Serial Data Format (24 bit example) ........................................................................................ 55
FIGURE 18. Left Justified Data Format (24 bit example) .................................................................................... 55
FIGURE 19. Right Justified Data Format (24 bit example) .................................................................................. 55
FIGURE 20. PCM Serial Data Format (16 bit example) ...................................................................................... 55
FIGURE 21. ADC DSP Effects Chain ........................................................................................................... 60
FIGURE 22. DAC DSP Effects Chain ........................................................................................................... 60
FIGURE 23. ALC Example ........................................................................................................................ 62
FIGURE 24. Demo Board Schematic ............................................................................................................ 97
FIGURE 25. Top Silkscreen Layer ............................................................................................................... 98
FIGURE 26. Top Layer ............................................................................................................................. 98
FIGURE 27. Inner Layer 1 ......................................................................................................................... 99
FIGURE 28. Inner Layer 2 ......................................................................................................................... 99
FIGURE 29. Bottom Silkscreen Layer ......................................................................................................... 100
FIGURE 30. Bottom Layer ...................................................................................................................... 100
List of Tables
TABLE 1. Device Register Map .................................................................................................................. 27
TABLE 2. PMC_SETUP (0x00h) ................................................................................................................. 32
TABLE 3. PMC_SETUP (0x01h) ................................................................................................................. 33
TABLE 4. PMC_SETUP (0x02h) (Default data value is 0x50h) ............................................................................. 33
TABLE 5. DAC Clock Requirements ............................................................................................................. 34
TABLE 6. ADC Clock Requirements ............................................................................................................. 34
TABLE 7. PLL Settings for Common System Clock Frequencies .......................................................................... 37
TABLE 8. PLL_CLOCK_SOURCE (0x03h) .................................................................................................... 38
TABLE 9. PLL1_M (0x04h) ........................................................................................................................ 38
TABLE 10. PLL1_N (0x05h) ...................................................................................................................... 38
TABLE 11. PLL1_N_MOD (0x06h) .............................................................................................................. 39
TABLE 12. PLL1_P1 (0x07h) ..................................................................................................................... 39
TABLE 13. PLL1_P2 (0x08h) ..................................................................................................................... 39
TABLE 14. PLL2_M (0x09h) ...................................................................................................................... 40
TABLE 15. PLL2_N (0x0Ah) ...................................................................................................................... 40
TABLE 16. PLL2_N_MOD (0x0Bh) .............................................................................................................. 40
TABLE 17. PLL2_P (0x0Ch) ...................................................................................................................... 41
TABLE 18. CLASS_D_OUTPUT (0x10h) ....................................................................................................... 42
TABLE 19. LEFT HEADPHONE_OUTPUT (0x11h) .......................................................................................... 43
TABLE 20. RIGHT HEADPHONE_OUTPUT (0x12h) ........................................................................................ 43
TABLE 21. AUX_OUTPUT (0x13h) .............................................................................................................. 44
TABLE 22. OUTPUT_OPTIONS (0x14h) ....................................................................................................... 44
TABLE 23. ADC_INPUT (0x15h) ................................................................................................................. 44
TABLE 24. MIC_L_INPUT (0x16h) .............................................................................................................. 45
TABLE 25. MIC_R_INPUT (0x17h) .............................................................................................................. 45
TABLE 26. AUX_L_INPUT (0x18h) .............................................................................................................. 46
TABLE 27. AUX_R_INPUT (0x19h) ............................................................................................................. 47
TABLE 28. ADC Basic (0x20h) ................................................................................................................... 48
TABLE 29. ADC_CLK_DIV (0x21h) ............................................................................................................. 48
TABLE 30. ADC TRIM (0x22h) ................................................................................................................... 49
TABLE 31. DAC Basic (0x30h) ................................................................................................................... 50
TABLE 32. DAC_CLK_DIV (0x31h) ............................................................................................................. 50
TABLE 33. Input Levels 1 (0x40h) ............................................................................................................... 52
TABLE 34. Input Levels 2 (0x41h) ............................................................................................................... 52
TABLE 35. Audio Port 1 Input (0x42h) .......................................................................................................... 53
TABLE 36. Audio Port 2 Input (0x43h) .......................................................................................................... 53
TABLE 37. DAC Input Select (0x44h) ........................................................................................................... 54
TABLE 38. Decimator Input Select (0x45h) .................................................................................................... 54
TABLE 39. BASIC_SETUP (0x50h/0x60h) ..................................................................................................... 56
TABLE 40. CLK_GEN_1 (0x51h/0x61h) ........................................................................................................ 56
TABLE 41. CLK_GEN_1 (0x52h/62h) ........................................................................................................... 57
TABLE 42. CLK_GEN_1 (0x53h/63h) ........................................................................................................... 57
TABLE 43. DATA_WIDTHS (0x54h/64h) ....................................................................................................... 58
TABLE 44. TX_MODE (0x55h/x65h) ............................................................................................................ 59
TABLE 45. ADC EFFECTS (0x70h) ............................................................................................................. 60
TABLE 46. DAC EFFECTS (0x71h) ............................................................................................................. 60
TABLE 47. HPF MODE (0x80h) .................................................................................................................. 61
TABLE 48. ADC_ALC_1 (0x81h) ................................................................................................................. 62
TABLE 49. ADC_ALC_2 (0x82h) ................................................................................................................. 63
TABLE 50. ADC_ALC_3 (0x83h) ................................................................................................................. 64
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TABLE 51. ADC_ALC_4 (0x84h) ................................................................................................................. 65
TABLE 52. ADC_ALC_5 (0x85h) ................................................................................................................. 66
TABLE 53. ADC_ALC_6 (0x86h) ................................................................................................................. 67
TABLE 54. ADC_ALC_7 (0x87h) ................................................................................................................. 67
TABLE 55. ADC_ALC_8 (0x88h) ................................................................................................................. 67
TABLE 56. ADC_L_LEVEL (0x89h) (Default data value is 0x33h) ......................................................................... 68
TABLE 57. ADC_R_LEVEL (0x8Ah) (Default data value is 0x33h) ........................................................................ 69
TABLE 58. EQ_BAND_1 (0x8Bh) ................................................................................................................ 70
TABLE 59. EQ_BAND_2 (0x8Ch) ................................................................................................................ 71
TABLE 60. EQ_BAND_3 (0x8Dh) ................................................................................................................ 72
TABLE 61. EQ_BAND_4 (0x8Eh) ................................................................................................................ 73
TABLE 62. EQ_BAND_5 (0x8Fh) ................................................................................................................ 74
TABLE 63. SOFTCLIP1 (0x90h) ................................................................................................................. 75
TABLE 64. SOFTCLIP2 (0x91h) ................................................................................................................. 76
TABLE 65. SOFTCLIP3 (0x92h) ................................................................................................................. 77
TABLE 66. DAC_ALC_1 (0xA0h) ................................................................................................................ 77
TABLE 67. DAC_ALC_2 (0xA1h) ................................................................................................................ 79
TABLE 68. DAC_ALC_3 (0xA2h) ................................................................................................................ 80
TABLE 69. DAC_ALC_4 (0xA3h) ................................................................................................................ 81
TABLE 70. DAC_ALC_5 (0xA4h) ................................................................................................................ 82
TABLE 71. DAC_ALC_6 (0xA5h) ................................................................................................................ 83
TABLE 72. DAC_ALC_7 (0xA6h) ................................................................................................................ 83
TABLE 73. DAC_ALC_8 (0xA7h) ................................................................................................................ 83
TABLE 74. DAC_L_LEVEL (0xA8h) (Default data value is 0x33h) ......................................................................... 84
TABLE 75. DAC_R_LEVEL (0xA9h) (Default data value is 0x33h) ........................................................................ 85
TABLE 76. DAC_3D (0xAAh) ..................................................................................................................... 86
TABLE 77. EQ_BAND_1 (0xABh) ............................................................................................................... 87
TABLE 78. EQ_BAND_2 (0xACh) ............................................................................................................... 88
TABLE 79. EQ_BAND_3 (0xADh) ............................................................................................................... 89
TABLE 80. EQ_BAND_4 (0xAEh) ............................................................................................................... 90
TABLE 81. EQ_BAND_5 (0xAFh) ................................................................................................................ 91
TABLE 82. SOFTCLIP1 (0xB0h) ................................................................................................................. 92
TABLE 83. SOFTCLIP2 (0xB1h) ................................................................................................................. 93
TABLE 84. SOFTCLIP3 (0xB2h) ................................................................................................................. 94
TABLE 85. GPIO (0xE0h) ......................................................................................................................... 94
TABLE 86. Spread Spectrum (0xF1h) ........................................................................................................... 95
TABLE 87. ADC Compensation Filter C0 LSBs (0xF8h) ..................................................................................... 95
TABLE 88. ADC Compensation Filter C0 MSBs (0xF9h) .................................................................................... 95
TABLE 89. ADC Compensation Filter C1 LSBs (0xFAh) ..................................................................................... 96
TABLE 90. ADC Compensation Filter C1 MSBs (0xFBh) .................................................................................... 96
TABLE 91. ADC Compensation Filter C2 LSBs (0xFCh) .................................................................................... 96
TABLE 92. ADC Compensation Filter C2 MSBs (0xFDh) .................................................................................... 96
TABLE 93. AUX_LINEOUT (0xFE) .............................................................................................................. 96
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7.0 Connection Diagrams
36 Bump micro SMD
36 Bump micro SMD Marking
201941q7
Top View
XY — Date Code
TT — Die Traceability
G — Boomer
20194101
J8 — LM49350RL
Top View (Bump Side Down)
Order Number LM49350RL
See NS Package Number RLA36TTA
Ordering Information
Order Number
Package
Package DWG #
Transport Media
MSL Level
Green Status
36 Bump micro
SMDxt
RoHS and
no Sb/Br
LM49350RL
RLA36TTA
250 units on tape and reel
3000 units on tape and reel
1
1
36 Bump micro
SMDxt
RoHS and
no Sb/Br
LM49350RLX
RLA36TTA
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Pin Descriptions
Pin
Pin Name
HPR
Type
Direction
Output
Input
Description
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
F1
F2
F3
F4
F5
F6
Analog
Supply
Supply
Analog
Digital
Digital
Analog
Analog
Analog
Digital
Digital
Digital
Analog
Analog
Analog
Digital
Digital
Digital
Analog
Analog
Analog
Digital
Digital
Supply
Supply
Supply
Analog
Analog
Digital
Supply
Analog
Analog
Analog
Analog
Digital
Supply
Headphone right output
A_VDD
Headphone and mixer power supply input
Headphone and mixer ground
AGND
Input
VREF_FLT
GPIO
Input/Output Filter point for the microphone power supply and internal references
Input/Output General purpose input or output
Input/Output I2C interface data line
SDA
HPL
Output
Input
Headphone left output
Right analog input
Left analog input
AUX_R
AUX_L
Input
PORT2_SYNC
PORT2_SDI
SCL
Input/Output Audio Port 2 SYNC Signal (can be master or slave)
Input
Input
Audio Port 2 serial data input
I2C interface clock line
HP_VSS
Output
Output
Output
Output
Negative power supply pin for the headphone amplifier
Auxiliary positive output
AUX_OUT+
AUX_OUT-
PORT2_SDO
PORT2_CLK
MCLK
Auxiliary negative output
Audio port 2 serial data out
Input/Output Audio port 2 clock signal (can be master or slave)
Input Input clock from 0.5MHz to 50 MHz
CP-
Input/Output Charge pump flying capacitor negative input
Input/Output Charge pump flying capacitor positive input
CP+
MIC_BIAS
PORT1_SYNC
PORT1_SDO
DGND
Output
Microphone ultra clean supply (2.2V)
Input/Output Audio Port 1 sync signal (can be master or slave)
Output
Input
Audio Port 1 serial data output
Digital ground
LSGND
Input
Loudspeaker ground
LS_VDD
Input
Loudspeaker power supply input
Right microphone negative input
Left microphone negative input
Audio Port 1 serial data input
Digital power supply input
Loudspeaker positive output
Loudspeaker negative output
Right microphone positive input
Left microphone positive input
RIGHT_MIC-
LEFT_MIC-
PORT1_SDI
D_VDD
Input
Output
Input
Input
LS +
Output
Output
Input
LS -
RIGHT_MIC +
LEFT_MIC +
PORT1_CLK
I/O_VDD
Input
Input/Output Audio Port 1 clock signal (can be master or slave)
Input Digital interface power supply input
7.1 PIN TYPE DEFINITIONS
sive components can be connected
to these pins.
Analog Input —
A pin that is used by the analog and
is never driven by the device. Sup-
plies are part of this classification.
Digital Input —
A pin that is used by the digital but is
never driven by the device.
Analog Output —
A pin that is driven by the device and
should not be driven by external
sources.
Digital Output —
A pin that is driven by the device and
should not be driven by another de-
vice to avoid contention.
Analog Input/Output — A pin that is typically used for filtering
a DC signal within the device. Pas-
Digital Input/Output —
A pin that is either open drain (SDA)
or a bidirectional CMOS in/out. In
the latter case the direction is se-
lected by a control register within the
LM49350.
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Junction Temperature
Thermal Resistance
ꢁθJA – RLA36 (soldered down
to PCB with 2in2 1oz. copper
plane)
Soldering Information
See Applications Note AN-1112.
150°C
8.0 Absolute Maximum Ratings (Notes
1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
60°C/W
Analog Supply Voltage
(A_VDD and LS_VDD
)
6.0V
2.2V
9.0 Operating Ratings
Temperature Range
Digital Supply Voltage
D_VDD
−40°C to +85°C
I/O Supply Voltage
I/O_VDD
Supply Voltage
A_VDD and LS_VDD
D_VDD
5.5V
−65°C to +150°C
Internally Limited
2.7V to 5.5V
1.7V to 2.0V
1.6V to 4.5V
Storage Temperature
Power Dissipation (Note )
I/O_VDD
ESD Ratings
Human Body Model (Note )
Machine Model (Note )
2000V
200V
10.0 Electrical Characteristics: A_VDD = LS_VDD = 3.3V; D_VDD = I/O_VDD = 1.8V
(Notes 1, 2) The following specifications apply for RL(LS) = 8Ω, RL(HP) = 32Ω, f = 1kHz, unless otherwise specified. Limits apply
for TA = 25°C.
LM49350
Units
Symbol
Parameter
Conditions
Typical
Limit
(Limits)
(Note 6) (Note 7)
DC CHARACTERISTICS (Digital current combines D_VDD and I/O_VDD. Analog current combines A_VDD and LS_VDD
)
Shutdown Mode,
fMCLK = 13MHz, PLL Off
DISD
DIST
Digital Shutdown Current
Digital Standby Current
2
15
1
µA (max)
mA (max)
fMCLK = 12.288MHz, PMC On only
0.25
fMCLK = 11.2896MHz, fS = 44.1kHz,
Stereo DAC On, OSRDAC = 128,
PLL Off, HP On
Digital Active Current (MP3 Mode)
Digital Active Current (FM Mode)
0.9
0.2
1.5
2
0.5
2
mA (max)
mA (max)
mA (max)
fMCLK = 13MHz
Analog Audio modes
DIDD
Digital Active Current (FM Record
Mode)
fMCLK = 12.288MHz, fS = 48kHz,
Stereo ADC On, OSRADC = 128,
PLL Off, Stereo Analog Inputs On
Digital Active Current (CODEC
Mode)-
fMCLK = 11.2896MHz, fS = 44.1kHz,
Mono ADC On, Stereo DAC On,
OSR = 128, PLL Off, MIC On
2.7
3.8
mA (max)
AISD
AIST
Analog Shutdown Current
Shutdown Mode
0.3
5
μA (max)
Analog Standby Quiescent Current Reference Voltages On only
0.85
1.5
mA (max)
fMCLK = 11.2896MHz, fS = 44.1kHz,
Analog Supply Current (MP3 Mode) Stereo DAC On, OSRDAC = 128,
PLL Off, HP On
7.8
5.3
9.8
10
7
mA (max)
mA (max)
mA (max)
Analog Supply Current (FM Mode)
Stereo Analog Inputs On, HP On
fMCLK = 12.288MHz, fS = 48kHz,
Stereo ADC On, OSRADC = 128,
PLL Off, Stereo Analog Inputs On
AIDD
Analog Supply Current (FM Record
Mode)
12
fMCLK = 11.2896MHz, fS = 44.1kHz,
Mono ADC On, Stereo DAC On,
OSR = 128, PLL Off, MIC On
Analog Supply Current (CODEC
Mode)
13
15
mA (max)
mA (max)
fMCLK = 13MHz,
PLLIDD
PLL Total Active Current
2.9
5.5
fPLLOUT = 12MHz, PLL On only
HPIDD
LSIDD
Headphone Quiescent Current
Loudspeaker Quiescent Current
Stereo HP On only
LS On only
3.5
2.9
mA
mA
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LM49350
Typical Limit
(Note 6) (Note 7)
Units
(Limits)
Symbol
MICIDD
Parameter
Conditions
Microphone Quiescent Current
ADC Total Active Current
DAC Total Active Current
mono MIC + MIC Bias On
fS = 48kHz, Stereo
0.5
9
mA
mA
mA
ADCIDD
DACIDD
fS = 48kHz, Stereo
5.5
Auxiliary Input Amplifier Quiescent
Current
AUXINIDD
Stereo Auxiliary Inputs enabled
0.7
mA
AUX_LINE_OUT enabled
Earpiece mode enabled
0.5
1.0
mA
mA
Auxiliary Output Amplifier Quiescent
Current
AUXOUTIDD
LOUDSPEAKER AMPLIFIER
LSEFF
Loudspeaker Efficiency
PO = 400mW, RL = 8Ω
PO = 400mW, f = 1kHz,
RL = 8Ω, Mono Input Signal
83
%
%
THD+N
Total Harmonic Distortion + Noise
0.07
RL = 8Ω, f = 1kHz, THD+N = 1%, Mono Input Signal
LS_VDD = 3.3V
LS_VDD = 4.2V
LS_VDD = 5V
495
825
1.2
400
mW (min)
mW
W
PO
Output Power
RL = 4Ω, f = 1kHz, THD+N = 1%, Mono Input Signal
LS_VDD = 3.3V
LS_VDD = 4.2V
LS_VDD = 5V
800
1.4
2
mW
W
W
VRIPPLE = 200mVP-P
fRIPPLE = 217Hz
PSRR
Power Supply Rejection Ration
73
55
85
dB (min)
Mono Input Terminated
VREF = 1.0μF
Reference = VOUT (1% THD+N )
Gain = 0dB, A-weighted
Mono Input Terminated
SNR
eOS
Signal-to-Noise Ratio
Output Noise
95
35
dB (min)
µV
Gain = 0dB, A-weighted,
Mono Input Terminated
VOS
TWU
Offset Voltage
Turn-On Time
Gain = 0dB, form Mono Input
PMC Clock = 300kHz
10
28
50
mV (max)
ms
HEADPHONE AMPLIFIERS
PO = 7.5mW, f = 1kHz,
RL = 32Ω
THD+N
PO
Total Harmonic Distortion + Noise
0.025
69
0.1
60
% (max)
Stereo Analog Input Signal
RL = 32Ω, f = 1kHz, THD+N = 1%,
Stereo Analog Input Signal
VRIPPLE = 200mVP-P, fRIPPLE = 217Hz
Stereo Analog Inputs Terminated,
VREF = 1.0μF, Mono Differential Input
Mode
Headphone Output Power
mW (min)
PSRR
SNR
Power Supply Rejection Ratio
97
75
dB (min)
Reference = VOUT (1% THD+N )
Gain = 0dB, A-weighted
Stereo Inputs Terminated
106
96
98
90
dB (min)
dB (min)
Signal-to-Noise Ratio
Reference = VOUT (0dBFS ) Gain =
0dB,
A-weighted, I2S Input = Digital Zero
13
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LM49350
Typical Limit
(Note 6) (Note 7)
Units
(Limits)
Symbol
Parameter
Conditions
Gain = 0dB, A-weighted,
Stereo Inputs Terminated
8
µV
µV
eOS
Output Noise
Gain = 0dB, A-weighted,
I2S Input = Digital Zero
16
PO = 60mW, f = 1kHz,
RL = 32Ω
XTALK
Crosstalk
71
dB
Stereo Analog Input Signal
Channel-to-Channel Gain Matching
ΔACH-CH
0.03
dB
AUX Gain = 0dB
From Differential Mono Input
0.5
6
6
mV (max)
VOS
Output Offset Voltage
Turn-On Time
DAC Gain = 0dB, From DAC Input
fMCLK = 12.288MHz, PLL off
1
mV (max)
ms
TWU
PMC Clock = 300kHz
28
AUXILIARY OUTPUTS
AUX_LINE_OUT
0.004
0.08
58
%
%
RL = 5kΩ, VOUT = 1VRMS
THD+N
POUT
Total Harmonic Distortion + Noise
Earpiece mode, f = 1kHz
RL = 32Ω BTL, POUT = 20mW
Earpiece mode, f = 1kHz
Output Power
45
62
mW (min)
RL = 32Ω BTL, THD+N = 1%
VRIPPLE = 200mVP-P, fRIPPLE = 217Hz
Mono Input terminated, CREF = 1μF
AUX_LINE_OUT
100
94
dB
PSRR
SNR
Power Supply Rejection Ratio
VRIPPLE = 200mVP-P, fRIPPLE = 217Hz
Mono Input terminated, CREF = 1μF
Earpiece mode
dB (min)
dB
Gain = 0dB, VREF = VOUT (1%THD+N)
A-weighted, Mono Input Terminated
Gain = 0dB, VREF = VOUT (1%THD+N)
A-weighted, Mono Input Terminated
Signal-to-Noise Ratio
Output Noise
100
13
7
∈
μV
OUT
Gain = 0dB, From Mono Input
AUX_LINE_OUT
mV
VOS
Output Offset Voltage
Turn-On Time
Gain = 0dB, From Mono Input
Earpiece mode
3
15
mV (max)
ms
TWU
PMC Clock = 300kHz
28
STEREO ADC
Differential Line Input
VIN = 200mVRMS, f = 1kHz
Gain = 0dB
ADC Total Harmonic Distortion +
Noise
THD+NADC
0.03
300
%
HPF On, fS = 48kHz
Lower -3dB Point
Hz
PBADC
ADC Passband
ADC Ripple
0.41*fS
0.1
HPF On, Upper -3dB Point
ADC Compensated
kHz
dB
RADC
Reference = VOUT (0dBFS ) Gain =
6dB,
90
dB
A-weighted From MIC, fS = 8kHz
SNRADC
ADC Signal-to-Noise Ratio
Reference = VOUT (0dBFS ) Gain =
0dB,
94
dB
A-weighted From Stereo Input, fS =
48kHz
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14
LM49350
Typical Limit
(Note 6) (Note 7)
Units
(Limits)
Symbol
Parameter
Conditions
ADCLEVEL
VRMS
ADC Full Scale Input Level
1
STEREO DAC
I2S Input
DAC Total Harmonic Distortion +
Noise
THD+NDAC
VIN = 500mFFSRMS, f = 1kHz
Gain = 0dB
0.05
%
DACLEVEL
RDAC
DAC Full Scale Output Level
DAC Ripple
VRMS
dB
1
0.1
PBDAC
DAC Passband
Upper –3dB Point
0.45*fS
96
kHz
dB
SNRDAC
MIC BIAS
VBIAS
DAC Signal-to-Noise Ratio
fS = 48kHz, A-weighted
Microphone Bias Voltage
MIC input selected
2.2
V
VOLUME CONTROL
Minimum Gain
Maximum Gain
Minimum Gain
Maximum Gain
Minimum Gain
Maximum Gain
Minimum Gain
Maximum Gain
–46.5
12
dB
dB
VCRAUX
VCRDAC
VCRADC
VCRMIC
Stereo Input Volume Control Range
DAC Volume Control Range
ADC Volume Control Range
MIC Volume Control Range
–76.5
18
dB
dB
–76.5
18
dB
dB
6
dB
36
dB
SSAUX
SSDAC
SSADC
SSMIC
SVAUX
SVMIC
AUX Volume Control Stepsize
DAC Volume Control Stepsize
DAC Volume Control Stepsize
MIC Volume Control Stepsize
AUX Volume Setting Variation
MIC Volume Setting Variation
1.5
1.5
1.5
2
dB
dB
dB
dB
±1
dB (max)
dB (max)
±1
ANALOG INPUTS
AUXR Gain = 12dB
AUXR Gain = 0dB
AUXR Gain = –46.5dB
AUXL Gain = 12dB
AUXL Gain = 0dB
17.5
38
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
AUXR_RIN
AUXL_RIN
Right Auxiliary Input Impedance
Right Auxiliary Input Impedance
64
17.5
38
AUXL Gain = –46.5dB
64
MICR_RIN
MICL_RIN
Right Microphone Input Impedance All MIC gain settings
Left Microphone Input Impedance All MIC gain settings
50
50
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower.
Note 4: Human body model, applicable std. JESD22-A114C.
Note 5: Machine model, applicable std. JESD22-A115-A.
Note 6: Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis.
15
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11.0 Timing Characteristics: DVDD = I/OVDD = 1.8V (Notes 1, 2) The following specifications
apply for RL(SP) = 8Ω, RL(HP) = 32Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C.
LM49350
Units
Symbol
PLL
fIN
Parameter
Conditions
Typical
Limit
(Limits)
(Note 6)
(Note 7)
Minimum MCLK Frequency
Maximum MCLK Frequency
0.5
50
MHz (min)
MHz (max)
PLL Input Frequency Range
DIGITAL AUDIO INTERFACE TIMING
tBCLKR
BCK rise time
BCK fall time
BCK duty cycle
3
3
ns (max)
ns (max)
%
tBCLKCF
tBCLKDS
50
WS Propagation Delay from BCK
falling edge
tDL
10
10
10
ns (max)
ns (min)
ns (min)
tDST
tDHT
DATA Setup Time to BCK Rising Edge
DATA Hold Time from BCK Rising
Edge
CONTROL INTERFACE TIMING
SCL Frequency
400
0.6
kHz (max)
Hold Time (repeated START
Condition)
1
μs (min)
2
3
Clock Low Time
Clock High Time
1.3
μs (min)
ns (min)
600
Setup Time for a Repeated START
Condition
4
600
ns (min)
300
900
ns (min)
ns (max)
Output
Input
5
Data Hold Time
0
900
ns (min)
ns (max)
6
7
Data Setup Time
100
20+0.1CB
300
ns (min)
ns (min)
ns (max)
Rise Time of SDA and SCL
15+0.1CB
300
ns (min)
ns (max)
8
Fall Time SDA and SCL
9
Setup Time for STOP Condition
600
ns (min)
Bus Free Time Between a STOP and
START Condition
10
1.3
μs (min)
10
200
pF (min)
pF(max)
CB
Bus Capacitance
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16
12.0 Typical Performance Characteristics
DAC Frequency Response
fS = 48kHz, OSR = 128
DAC Frequency Response
fS = 8kHz, OSR = 128
20194140
20194139
Stereo Audio ADC Frequency Response
fS = 48kHz, OSR = 128, CIN = 1μF, MIC gain = 6dB
Stereo Audio ADC Frequency Response
fS = 8kHz, OSR = 128, CIN = 1μF, MIC gain = 6dB
20194142
20194141
Stereo Audio ADC HPF Frequency Response
fS = 48kHz, OSR = 128, CIN = 1μF, MIC gain = 6dB
(Top-No HPF, Upper-HPF_Mode = '101',
Lower-HPF_Mode = '110)'
Mono Voice ADC Frequency Response
fS = 48kHz, OSR = 128, CIN = 1μF, MIC gain = 6dB
Bottom-HPF_Mode = '111'
20194144
20194143
17
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Mono Voice ADC Frequency Response
fS = 8kHz, OSR = 128, CIN = 1μF, MIC gain = 6dB
Mono Voice ADC HPF Frequency Response
fS = 48kHz, OSR = 128, CIN = 1μF, MIC gain = 6dB
(Top-No HPF)
(From Left to Right:
HPF_Mode = '000', '001', '010', '011', '100')
20194145
20194146
Mono Voice ADC HPF Frequency Response
fS = 8kHz, OSR = 128, CIN = 1μF, MIC gain = 6dB
(Top-No HPF)
ADC Output THD+N vs Frequency
Differential Line Input, Aux Gain = 0dB
VIN = 200mVRMS, fS = 48kHz
(From Left to Right:
HPF_Mode = '000', '001', '010', '011', '100')
20194155
20194147
ADC Output THD+N vs Frequency
Differential MIC Input, MIC Gain = 6dB
VIN = 100mVRMS, fS = 48kHz
ADC Output THD+N vs VIN
Differential Line Input, Aux Gain = 0dB
VIN = 1kHz, fS = 48kHz
20194156
20194148
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18
ADC Output THD+N vs VIN
Differential MIC Input, MIC Gain = 6dB
VIN = 1kHz, fS = 48kHz
Loudspeaker THD+N vs Frequency
Differential Aux Input, Aux Gain = 0dB
VDD = 3.3V, POUT = 400mW, RL = 8Ω
20194159
20194149
Loudspeaker THD+N vs Frequency
Differential Aux Input, Aux Gain = 0dB
VDD = 5V, POUT = 400mW, RL = 8Ω
Loudspeaker THD+N vs Frequency
Differential Aux Input, Aux Gain = 0dB
LS_VDD = 3.3V, POUT = 500mW, RL = 4Ω
20194161
20194181
Loudspeaker THD+N vs Output Power
Differential Aux Input, Aux Gain = 0dB
VDD = 3.3V, VIN = 1kHz, RL = 8Ω
Loudspeaker THD+N vs Output Power
Differential Aux Input, Aux Gain = 0dB
VDD = 4.2V, VIN = 1kHz, RL = 8Ω
20194165
20194166
19
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Loudspeaker THD+N vs Output Power
Differential Aux Input, Aux Gain = 0dB
VDD = 5V, VIN = 1kHz, RL = 8Ω
Loudspeaker THD+N vs Output Power
Differential Aux Input, Aux Gain = 0dB
LS_VDD = 3.3V, RL = 4Ω, f = 1kHz
20194167
20194182
Loudspeaker THD+N vs Output Power
Differential Aux Input, Aux Gain = 0dB
LS_VDD = 4.2V, RL = 4Ω, f = 1kHz
Loudspeaker THD+N vs Output Power
Differential Aux Input, Aux Gain = 0dB
LS_VDD = 5V, RL = 4Ω, f = 1kHz
20194183
20194184
Loudspeaker PSRR vs Frequency
LS_VDD = 3.3V, Aux Gain = 0dB
Differential Aux Input to Ground
VRIPPLE = 200mVPP
Loudspeaker PSRR vs Frequency
LS_VDD = 4.2V, Aux Gain = 0dB
Differential Aux Input to Ground
VRIPPLE = 200mVPP
20194151
20194152
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20
Loudspeaker PSRR vs Frequency
LS_VDD = 5V, Aux Gain = 0dB
Differential Aux Input to Ground
VRIPPLE = 200mVPP
Headphone THD+N vs Frequency
Stereo Aux Input, Aux Gain = 0dB
VDD = 3.3V, POUT = 7.5mW, RL = 32Ω
20194157
20194153
Headphone THD+N vs Frequency
Stereo Aux Input, Aux Gain = 0dB
VDD = 5V, POUT = 7.5mW, RL = 32Ω
Headphone THD+N vs Frequency
Differential Aux Input, Aux Gain = 0dB
A_VDD = 3.3V, POUT = 7.5mW, RL = 16Ω
20194158
20194179
Headphone THD+N vs Output Power
Stereo Aux Input, Aux Gain = 0dB
VDD = 3.3V, VIN = 1kHz, RL = 32Ω
Headphone THD+N vs Output Power
Stereo Aux Input, Aux Gain = 0dB
VDD = 5V, VIN = 1kHz, RL = 32Ω
20194173
20194174
21
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Headphone THD+N vs Output Power
Headphone PSRR vs Frequency
Differential Aux Input to Ground, Aux Gain = 0dB
VRIPPLE = 200mVPP
A_VDD = 3.3V, Stereo Aux Input, Aux Gain = 0dB
RL = 16Ω, f = 1kHz
20194175
20194180
Headphone Crosstalk vs Frequency
Stereo Aux Inputs, Aux Gain = 0dB, RL = 32Ω
Earpiece THD+N vs Frequency
Differential Aux Input, Aux Gain = 0dB
A_VDD = 3.3V, POUT = 20mW, RL = 32Ω
20194169
20194176
Earpiece THD+N vs Output Power
Differential Aux Input, Aux Gain = 0dB
A_VDD45 = 3.3V, RL = 32Ω, f = 1kHz
Earpiece PSRR vs Frequency
Differential Aux Input to Ground, Aux Gain = 0dB
VRIPPLE = 200mVPP
20194177
20194178
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22
AUXOUT THD+N vs Frequency
Differential Aux Input, Aux Gain = 0dB
VDD = 5V, VOUT = 1VRMS, RL = 5kΩ
AUXOUT THD+N vs Output Voltage
Differential Aux Input, Aux Gain = 0dB
VIN = 1kHz, RL = 5kΩ
20194162
20194168
AUXOUT PSRR vs Frequency
Differential Aux Input to Ground, Aux Gain = 0dB
VRIPPLE = 200mVPP
20194154
23
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these signals need a pull-up resistor according to I2C speci-
13.0 System Control
fication. The I2C slave address for LM49350 is 00110102.
Method 1. I2C Compatible Interface
13.2 I2C DATA VALIDITY
13.1 I2C SIGNALS
In I2C mode the LM49350 pin SCL is used for the I2C clock
SCL and the pin SDA is used for the I2C data signal SDA. Both
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when SCL is LOW.
20194123
FIGURE 6. I2C Signals: Data Validity
13.3 I2C START AND STOP CONDITIONS
START and STOP bits. The I2C bus is considered to be busy
after START condition and free after STOP condition. During
data transmission, I2C master can generate repeated START
conditions. First START and repeated START conditions are
equivalent, function-wise.
START and STOP bits classify the beginning and the end of
the I2C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from LOW
to HIGH while SCL is HIGH. The I2C master always generates
20194124
FIGURE 7. I2C Start and Stop Conditions
13.4 TRANSFERRING DATA
After the START condition, the I2C master sends a chip ad-
dress. This address is seven bits long followed by an eight bit
which is a data direction bit (R/W). The LM49350 address is
00110102. For the eighth bit, a “0” indicates a WRITE and a
“1” indicates a READ. The second byte selects the register to
which the data will be written. The third byte contains data to
write to the selected register.
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9th clock pulse, signifying an acknowledge. A
receiver which has been addressed must generate an ac-
knowledge after each byte has been received.
20194125
FIGURE 8. I2C Chip Address
Register changes take effect at the SCL rising edge during
the last ACK from slave.
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24
20194126
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by slave)
rs = repeated start
FIGURE 9. Example I2C Write Cycle
25
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When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle
waveform.
20194127
FIGURE 10. Example I2C Read Cycle
20194128
FIGURE 11. I2C Timing Diagram
13.5 I2C TIMING PARAMETERS
Symbol
Parameter
Limit
Units
Min
0.6
1.3
600
600
300
0
Max
1
2
Hold Time (repeated) START Condition
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
pF
Clock Low Time
3
Clock High Time
4
Setup Time for a Repeated START Condition
Data Hold Time (Output direction, delay generated by LM49350)
Data Hold Time (Input direction, delay generated by the Master)
Data Setup Time
5
900
900
5
6
100
20+0.1Cb
15+0.1Cb
600
7
Rise Time of SDA and SCL
300
300
8
Fall Time of SDA and SCL
9
Set-up Time for STOP condition
10
CB
Bus Free Time between a STOP and a START Condition
Capacitive Load for Each Bus Line
1.3
10
200
NOTE: Data guaranteed by design
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26
14.0 Device Register Map
TABLE 1. Device Register Map
Address
Register
7
6
5
4
3
2
1
0
BASIC SETUP
0x00h
0x01h
0x02h
PMC
CHIP
PORT2
PORT1
MCLK
OVR
OSC
ENB
PLL2
ENB
PLL1
ENB
CHIP
SETUP
ACTIVE
CLK OVR CLK OVR
ENABLE
PMC
CLOCKS
PMC_CLK_SEL
PMC
PMC_CLK_DIV(R)
CLK_DIV
PLLs
0x03h
0x04h
0x05h
0x06h
PLL2_CLK_SEL
PLL1 M
PLL1 N
PLL1_CLK_SEL
PLL1 M
PLL1 N
PLL1
PLL2 P2[8] PLL1 P1[8]
PLL1 N_MOD
N_MOD
0x07h
0x08h
0x09h
0x0Ah
0x0Bh
PLL1 P1
PLL1 P2
PLL2 M
PLL2 N
PLL1 P1 [7:0]
PLL1 P2[7:0]
PLL2 M
PLL2 N
PLL2
PLL2 P[8]
PLL2 N_MOD
N_MOD
0x0Ch
PLL2 P
PLL2 P[7:0]
ANALOG MIXER
0x10h
0x11h
CLASSD
AUXL_LS AUXR_LS MICL_LS MICR_LS DACL_LS DACR_LS
AUXL_HP AUXR_HP MICL_HPL MICR_HPL DACL_HP DACR_HP
HEAD
PHONESL
L
L
L
L
0x12h
HEAD
AUXL_HP AUXR_HP MICL_HPR MICR_HPR DACL_HP DACR_HP
R
R
R
R
PHONESR
AUX_OUT
0x13h
0x14h
AUXL_AX AUXR_AX MICL_AX MICR_AX DACL_AX DACR_AX
OUTPUT
OPTIONS
CP_FORC AUX-6dB
E
LS-6dB
HP-6dB
EPMODE
0x15h
ADC
AUXL_AD AUXR_AD MICL_ADC MICR_ADC DACL_AD DACR_AD
CR
CL
R
L
CR
CL
0x16h
0x17h
0x18h
MICL_LVL
MICR_LVL
AUXL_LVL
MUTE
MUTE
SE/DIFF
SE/DIFF
MIC_L_LEVEL
MIC_R_LEVEL
FROM
LINEL
AUX_L_LEVEL
0x19h
AUXR_LV DIFF_MOD FROM
AUX_R_LEVEL
L
E
LINER
ADC
0x20h
0x21h
0x22h
ADC
BASIC
DSPONLY
ADC_CLK_SEL
MUTE_R
ADC_CLK_DIV (T)
MUTE_L ADC_OSR
MONO
ADC
CLOCK
ADC_DSP
ADC_TRI
M
DAC
0x30h
DAC_BASI DSPONLY
C
DAC_CLK_SEL
MUTE_R
MUTE_L
DAC_OSR
27
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Address
Register
7
6
5
4
3
2
1
0
0x31h
DAC_CLO
CK
DAC_CLK_DIV (S)
0x32h
DAC_DSP
DAC_TRI
M
DIGITAL MIXER
PORT2_RX_L_LVL
INTERP_R_LVL
0x40h
0x41h
0x42h
0x43h
0x44h
0x45h
IPLVL1
IPLVL2
PORT2_RX_R_LVL
INTERP_L_LVL
PORT1_RX_R_LVL
ADC_R_LVL
R_SEL
PORT1_RX_L_LVL
ADC_L_LVL
L_SEL
OPPORT1
OPPORT2
OPDAC
MONO
MONO
ADCR
SWAP
SWAP
R_SEL
L_SEL
SWAP
PORT2R
PORT1R
ADCL
PORT2L
PORT1L
OPDECI
MXRCLK_SEL
AUDIO PORT 1
R_SEL
L_SEL
0x50h
BASIC
STEREO_ STEREO_ CLK_PH SYNC_MS CLK_MS
SYNC_MO SYNC_PH
TX_ENB
RX_ENB
STEREO
DE
ASE
0x51h
0x52h
0x53h
0x54h
0x55h
0x56h
CLK_GEN
1
CLK_SEL
HALF_CYCLE_DIVDER
CLK_GEN
2
SYNTH_D
ENOM
SYNTH_NOM
SYNC_RATE
RX_WIDTH
SYNC_GE
N
SYNC_WIDTH(MONO MODE)
TX_WIDTH
MSB_POSITION
MSB_POSITION
DATA_WI
DTH
TX_EXTRA_BITS
RX_MODE A/ULAW
TX_MODE A/ULAW
COMPAN
D
RX_MODE
TX_MODE
COMPAN
D
AUDIO PORT 2
0x60h
BASIC
STEREO_ STEREO_ CLK_PH SYNC_MS CLK_MS
SYNC_MO SYNC_PH
TX_ENB
RX_ENB
STEREO
DE
ASE
0x61h
0x62h
0x63h
0x64h
0x65h
0x66h
CLK_GEN
1
CLK_SEL
HALF_CYCLE_DIVDER
CLK_GEN
2
SYNTH_D
ENOM
SYNTH_NOM
SYNC_RATE
RX_WIDTH
SYNC_GE
N
SYNC_WIDTH(MONO MODE)
TX_WIDTH
MSB_POSITION
DATA_WI
DTH
TX_EXTRA_BITS
RX_MODE A/ULAW
TX_MODE A/ULAW
COMPAN
D
RX_MODE
TX_MODE
COMPAN
D
MSB_POSITION
EFFECTS ENGINE
0x70h
0x71h
ADC FX
DAC FX
ADC
ADC
ADC
PK ENB
DAC
ADC
ADC
SCLP ENB EQ ENB
ALC ENB HPF_ENB
DAC
DAC
DAC
DAC
SCLP ENB 3D ENB
ADC EFFECTS
EQ ENB
PK ENB
ALC ENB
0x80h
0x81h
HPF
ADC
HPF MODE
SOURCE SOURCE STEREO
OVR SEL LINK
LIMITER
SAMPLE_RATE
ALC 1
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28
Address
Register
ADC
7
6
5
4
3
2
1
0
0x82h
NG_ENB
NOISE_FLOOR
ALC_TARGET_LEVEL
ATTACK_RATE
ALC 2
ADC
0x83h
0x84h
0x85h
0x86h
0x87h
0x88h
0x89h
0x8Ah
0x8Bh
0x8Ch
0x8Dh
0x8Eh
0x8Fh
0x90h
0x91h
0x92h
ALC 3
ADC
ALC 4
ADC
PK_DECAY_RATE
DECAY_RATE/RELEASE_RATE
HOLDTIME
ALC 5
ADC
ALC 6
ADC
MAX_LEVEL
ALC 7
ADC
MIN_LEVEL
ALC 8
ADC L
LEVEL
ADC R
LEVEL
ADC_L_LEVEL
ADC_R_LEVEL
EQ BAND
1
LEVEL
LEVEL
LEVEL
LEVEL
LEVEL
FREQ
EQ BAND
2
Q
Q
Q
FREQ
FREQ
FREQ
FREQ
EQ BAND
3
EQ BAND
4
EQ BAND
5
SOFTCLIP
1
SOFT
KNEE
THRESHOLD
RATIO
LEVEL
SOFTCLIP
2
SOFTCLIP
3
ADC EFFECT MONITORS
ADC LEFT LEVEL MONITOR
ADC RIGHT LEVEL MONITOR
0x98h
0x99h
0x9Ah
LVLMONL
LVLMONR
FXCLIP
SCLP_R
CLIP
SCLP_L
CLIP
EQ_R
CLIP
EQ_L
CLIP
GAIN_R
CLIP
GAIN_L
CLIP
ADC_R
CLIP
ADC_L
CLIP
0x9Bh
0x9Ch
ALCMONL SCLP_R
SCLP_L
ADC LEFT ALC MONITOR
DISTORT DISTORT
ALCMONR SCLP_L
SCLP_R
ADC RIGHT ALC MONITOR
DISTORT DISTORT
DAC EFFECTS
STEREO
0xA0h
0xA1h
0xA2h
0xA3h
DAC
ALC 1
DAC
LIMITER
SAMPLE_RATE
NOISE_FLOOR
LINK
NG_ENB
ALC 2
DAC
AGC_TARGET_LEVEL
ATTACK_RATE
ALC 3
DAC
ALC 4
29
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Address
Register
DAC
7
6
5
4
3
2
1
0
0xA4h
PK_DECAY_RATE
DECAY_RATE/RELEASE_RATE
ALC 5
DAC
0xA5h
0xA6h
0xA7h
0xA8h
0xA9h
0xAAh
0xABh
0xACh
0xADh
0xAEh
0xAFh
0xB0h
0xB1h
0xB2h
HOLDTIME
ALC 6
DAC
MAX_LEVEL
ALC 7
DAC
MIN_LEVEL
ALC 8
DAC L
LEVEL
DAC R
LEVEL
DAC_3D
DAC_L_LEVEL
DAC_R_LEVEL
EFFECT_LEVEL
ATTEN
FILTER_TYPE
LEVEL
EFFECT_
MODE
EQ BAND
1
FREQ
EQ BAND
2
Q
Q
Q
LEVEL
LEVEL
LEVEL
LEVEL
FREQ
FREQ
FREQ
FREQ
EQ BAND
3
EQ BAND
4
EQ BAND
5
SOFTCLIP
1
SOFT
KNEE
THRESHOLD
RATIO
SOFTCLIP
2
SOFTCLIP
3
LEVEL
DAC EFFECT MONITORS
0xB8h
0xB9h
0xBAh
LVLMONL
LVLMONR
FXCLIP
DAC LEFT LEVEL MONITOR
DAC RIGHT LEVEL MONITOR
SCLP_R
CLIP
SCLP_L
CLIP
EQ_R
CLIP
EQ_L
CLIP
3D_R
CLIP
3D_L
CLIP
GAIN_R
CLIP
GAIN_L
CLIP
0xBBh
0xBCh
ALCMONL SCLP_R
SCLP_L
DAC LEFT ALC MONITOR
DISTORT DISTORT
ALCMONR SCLP_L
SCLP_R
DAC RIGHT ALC MONITOR
DISTORT DISTORT
GPIO
0xE0h
0xF1h
GPIO
SS
TEMP
SHORT
GPIO_RX GPIO_TX
GPIO_MODE
SPREAD SPECTRUM
SS_DISAB
LE
RSVD
RSVD
ADC COMPENSATION FILTER
ADC_C0_LSB
0xF8h
0xF9h
0xFAh
ADC_C0_L
SB
ADC_C0_
MSB
ADC_C0_MSB
ADC_C1_LSB
ADC_C1_L
SB
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30
Address
Register
7
6
5
4
3
2
1
0
0xFBh
ADC_C1_
MSB
ADC_C1_MSB
ADC_C2_LSB
ADC_C2_MSB
0xFCh
0xFDh
0xFEh
ADC_C2_L
SB
ADC_C2_
MSB
AUX_LINE
_OUT
AUX_LINE
_OUT
RSVD
Unless otherwise specified, the default values of the I2C reg-
isters is 0x00h.
31
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15.0 Basic PMC Setup Register
This register is used to control the LM49350's Basic Power Management Setup:
TABLE 2. PMC_SETUP (0x00h)
Bits
Field
Description
When this bit is set the power management will enable the MCLK I/O or internal
oscillator1. It will then use this clock to sequence the enabling of the analog references and
bias points. When this bit is cleared the PMC will bring the analog down gently and disable
the MCLK or oscillator.
0
CHIP_ENABLE
CHIP _ENABLE
Chip Status
Turn Chip Off
Turn Chip On
0
1
This enables the primary PLL
PLL1_ENABLE
PLL1 Status
PLL1 Off
1
2
PLL1_ENB
PLL2_ENB
0
1
PLL1 On
This enables the secondary PLL
PLL2_ENABLE
PLL2 Status
PLL2 Off
0
1
PLL2 On
This enables the internal 300kHz Oscillator. For analog only chip modes, the oscillator can
be used instead of an external system clock to drive the chip's power management (PMC).
OSC_ENABLE
Oscillator Status
Oscillator Off
Oscillator On
3
OSC_ENB
0
1
This forces the MCLK input to enable, regardless of requirement. If set, the audio ports and
digital mixer can be activated even if the chip is in shutdown mode. This assumes that MCLK
is selected as the clock source and that there is an active clock signal driving the MCLK pin.
Setting this bit reduces power consumption, by allowing audio ports and digital mixer to
operate while the analog sections of the chip is powered down.
4
5
MCLK_OVR
MCLK_OVR
Comment
0
1
I/O control is automatic
MCLK input forced on.
This forces the clock input of Audio Port 1 input to enable, regardless of other port settings.
PORT1_CLK_OVR
Comment
PORT1_CLK_OVR
0
1
I/O control is automatic
PORT_CLK input forced on
This forces the clock input of Audio Port 2 input to enable, regardless of other port settings.
PORT2_CLK_OVR
Comment
6
7
PORT2_CLK_OVR
CHIP_ACTIVE
0
1
I/O control is automatic
PORT_CLK input forced on
This bit is used to read back the enable status of the chip.
1. If the PMC is set to operate from one of the audio ports then it will wait for the port to be enabled or the relevant over ride bit to
be set, forcing the port clock input to enable.
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32
16.0 PMC Clocks Register
This register is used to control the LM49350's Basic Power Management Setup:
TABLE 3. PMC_SETUP (0x01h)
Bits
Field
Description
This selects the source of the PMC input clock.
1:0
PMC_CLK_SEL
PMC_CLK_SEL
PMC Input Clock Source
MCLK (Default divide is 40)
Internal 300kHz Oscillator
DAC SOURCE CLOCK
ADC SOURCE CLOCK
00
01
10
11
17.0 PMC Clock Divide Register
This register is used to control the LM49350's Power Management Circuits Clocks:
TABLE 4. PMC_SETUP (0x02h) (Default data value is 0x50h)
Description
Bits
Field
PMC_CLK_DIV
7:0
This programs the half cycle divider that precedes the PMC. The PMC should run from a
300kHz clock. The default of this divider is 0x50h (divide by 40) to get a ≈300kHz PMC clock
from a 12MHz or 12.288MHz MCLK.
Program this divider with the division you want, multiplied by 2, and subtract 1.
PMC_CLK_DIV
00000000
00000001
00000010
00000011
00000100
00000101
—
Divide by
1
1
1.5
2
2.5
3
—
11111101
11111110
11111111
126
127.5
128
33
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The DAC path clock (DAC_SOURCE_CLK) and ADC path
clock (ADC_SOURCE_CLK) can be driven directly by the
MCLK input, the PORT1_CLK input, the PORT2_CLK input,
PLL1's output, or PLL2's output.
18.0 LM49350 Clock Network
(Refer to Figure 12)
The audio DAC and ADC operate at a clock frequency of
2*OSR*fS where OSR is the oversampling ratio and fS is the
sampling frequency of the DAC or ADC. The DAC can operate
at four different OSR settings (128, 125, 64, 32). The ADC
can operate at three different OSR settings (128, 125, 64).
For example, if the stereo DAC or ADC is set at OSR = 128,
a 12.288MHz clock is required for 48kHz data. If a 12.288MHz
clock is not available, then one of the LM49350's dual PLLs
can be used to generate the desired clock frequency. Other-
wise, if a 12.288MHz is available, then the PLL can be by-
passed to reduce power consumption. The DAC clock divider
(S divider) or ADC clock divider (T divider) can also be used
to generate the correct clock. If an 18.432 MHz clock is avail-
able, the S or T divider could be set to 1.5 in order to generate
a 12.288MHz clock from 18.432MHz without using a PLL.
For instances where a PLL must be used, the PLL input clock
can come from three sources. The clock input to PLL1 or PLL2
can come from the MCLK input, the PORT1_CLK input, or the
PORT2_CLK input.
The LM49350's Power Management Circuit (PMC) requires
a clock that is independent from the DAC or ADC. It is rec-
ommended to provide a ≈300kHz clock at Point C. The PMC
clock divider (R divider) is available to generate the correct
clock to the PMC block. The PMC clock path can be driven
directly by the MCLK input, the internal 300kHz oscillator, the
DAC_SOURCE_CLK, or the ADC_SOURCE_CLK.
TABLE 5. DAC Clock Requirements
DAC Sample Rate
(kHz)
Clock Required at A
(OSR = 128)
Clock Required at A
(OSR= 125)
Clock Required at A
(OSR = 64)
Clock Required at A
(OSR = 32)
8
11.025
12
2.048 MHz
2.8224 MHz
3.072 MHz
4.096 MHz
5.6448 MHz
6.144 MHz
8.192 MHz
11.2896 MHz
12.288 MHz
24.576 MHz
—
2 MHz
2.75625 MHz
3 MHz
1.024 MHz
1.4112 MHz
1.536 MHz
2.048 MHz
2.8224 MHz
3.072 MHz
4.096 MHz
5.6448 MHz
6.144 MHz
12.288 MHz
24.576 MHz
0.512 MHz
0.7056 MHz
0.768 MHz
1.024 MHz
1.4112 MHz
1.536 MHz
2.048MHz
16
4 MHz
22.05
24
5.5125 MHz
6 MHz
32
8 MHz
44.1
48
11.025 MHz
12 MHz
24 MHz
—
2.8224 MHz
3.072 MHz
6.144 MHz
12.288 MHz
96
192
TABLE 6. ADC Clock Requirements
Clock Required at B Clock Required at B
ADC Sample Rate
(kHz)
Clock Required at B
(OSR = 64)
(OSR = 128)
2.048 MHz
2.8224 MHz
3.072 MHz
4.096 MHz
5.6448 MHz
6.144 MHz
8.192 MHz
11.2896 MHz
12.288 MHz
(OSR= 125)
8
11.025
12
2 MHz
1.024 MHz
1.4112 MHz
1.536 MHz
2.048 MHz
2.8224 MHz
3.072 MHz
4.096 MHz
5.6448 MHz
6.144 MHz
2.75625 MHz
3 MHz
16
4 MHz
22.05
24
5.5125 MHz
6 MHz
32
8 MHz
44.1
48
11.025 MHz
12 MHz
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34
20194129
FIGURE 12. Internal Clock Network
35
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19.0 PLL Setup Registers
20194130
FIGURE 13. PLL1 Loop
20194131
FIGURE 14. PLL2 Loop
The LM49350 contains two PLLs for flexible operation of its dual audio ports. PLL1 has a P1 and P2 output divider thereby allowing
PLL1 to generate two distinct clock outputs. The equations for PLL1's generated output clocks are as follows:
fOUT1 = (fIN . N1 / M1 . P1)
fOUT2 = (fIN . N1 / M1 . P2)
where:
N1 = PLL1_N + PLL1_N_MOD
M1 = (PLL1_M + 1) / 2
P1 = (PLL1_P1 + 1) / 2
P2 = (PLL1_P2 + 1) / 2
The equations for PLL2's generated output clock are as follows:
fOUT3 = (fIN.N2 / M2.P)
where:
N2 = PLL2_N + PLL2_N_MOD
M2 = (PLL2_M + 1) / 2
P = (PLL2_P + 1) / 2
The VCO frequency and comparison frequencies are as follows:
fVCO = fOUT.P
fCOMP = fIN/M
Keep fVCO between 140MHz to 240MHz and keep fCOMP between 700kHz to 5MHz.
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36
TABLE 7. PLL Settings for Common System Clock Frequencies
fIN (MHz)
12
fOUT (MHz)
12288000
12287970
12288000
12288000
12288000
12288000
12288000
12288000
12288000
11289600
11289600
11289603
11289589
11289600
11289600
11289600
11289600
11289600
11289600
12289600
12000000
12000000
12000000
12000000
12000000
12000000
12000000
12000000
12000000
12000000
11025000
11025000
11025000
11025000
11025000
11025000
11025000
11025000
11025000
11025000
11025000
M
2.5
15.5
12.5
13.5
3.5
12.5
20.5
16.5
22.5
12.5
10
N
N_MOD
P
Error (Hz)
32
0
26
0
12.5
12
0
–30
0
13
175
128
128
32
14.4
16.2
16.8
19.2
19.68
19.8
27
12
0
12.5
12.5
12
0
0
0
96
0
0
160
128
128
147
147
144
213
147
196
126
147
147
196
196
195
125
102
68
0
12.5
12.5
12.5
12.5
16
0
0
0
0
0
12
0
0
12.288
13
0
0
9
19
28
0
18.5
16.5
15
+3
–11
0
13.5
14.4
16.2
16.8
19.2
19.68
19.8
27
15.5
12.5
22.5
12.5
20
0
12.5
15
0
0
0
0
12.5
12.5
12.5
12.5
17.5
16
0
20.5
27.5
37.5
10.5
8
0
0
0
0
0
0
11.2896
12.288
13
0
0
0
0
6.5
4.5
6
0
17
0
13.5
14.4
16.2
16.8
19.2
19.68
19.8
11.2896
12
0
17
0
85
0
17
0
13.5
7
170
85
0
17
0
0
17
0
8
85
0
17
0
20.5
16.5
8
200
170
125
147
114
96
0
16
0
0
17
0
0
16
0
10
0
16
0
12.288
13
8
27
15
0
16
0
6.5
10
17.5
18
0
13.5
14.4
16.2
16.8
19.2
19.68
19.8
147
49
0
4
0
16
0
4
49
0
18
0
16
189
147
189
147
0
18
0
16
0
16
0
16
0
18
0
16
0
16.5
0
37
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TABLE 8. PLL_CLOCK_SOURCE (0x03h)
Description
Bits
Field
1:0
PLL1_CLK_SEL
This selects the source of the input clock to PLL1
PLL1_CLK_SEL
PLL1 Input Clock Source
MCLK
00
01
10
11
PORT1_CLK
PORT2_CLK
RESERVED
TABLE 9. PLL1_M (0x04h)
Description
Bits
Field
6:0
PLL1_M
This programs the PLL1 M divider to divide from 1 to 64.
PLL1_M
000000
000001
000010
000011
000100
000101
—
PLL1 Input Divider Vaue
1
1
1.5
2
2.5
3
—
63
63.5
64
1111101
1111110
1111111
TABLE 10. PLL1_N (0x05h)
Bits
Field
Description
7:0
PLL1_N
This programs the PLL1 N divider to divide from 1 to 250.
PLL1_N
00000000 to 00001010
00001011
Feedback Divider Value
10
11
00001100
12
00001101
13
00001110
14
00001111
15
—
—
11111000
248
249
250
11111001
11111010 to 11111111
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38
TABLE 11. PLL1_N_MOD (0x06h)
Description
Bits
Field
4:0
PLL1_N_MOD
This programs the sigma-delta modulator in PLL1
PLL1_N_MOD
00000
00001
00010
00011
00100
00101
—
Fractional Part of N
0
1/32
2/32
3/32
4/32
5/32
—
11101
11110
11111
20/32
30/32
31/32
5
6
PLL1_P1[8]
PLL1_P2[8]
This sets the MSB of the 1st P Divider on PLL1 which is part of a standard half-cycle divider
control.
This sets the MSB of the 2nd P Divider on PLL1 which is part of a standard half-cycle divider
control.
TABLE 12. PLL1_P1 (0x07h)
Description
Bits
Field
7:0
PLL1_P1[7:0]
This programs the 8 LSBs of the PLL1's P1 Divider. These LSBs combine with PLL1_P1[8] which
allows the P1 divider to divide by up to 256
PLL1_P1
000000000
000000001
000000010
000000011
000000100
000000101
—
P1 Divider Value
1
1
1.5
2
2.5
3
—
111111101
111111110
111111111
255
255.5
256
TABLE 13. PLL1_P2 (0x08h)
Bits
Field
Description
7:0
PLL1_P2[7:0]
This programs 8 LSBs of PLL1's P2 Divider. These LSBs combine with PLL1_P2[8] which allows
the P2 divider to divide by up to 256
PLL1_P2
000000000
000000001
000000010
000000011
000000100
000000101
—
P2 Divider Value
1
1
1.5
2
2.5
3
—
111111101
111111110
111111111
255
255.5
256
39
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TABLE 14. PLL2_M (0x09h)
Description
Bits
Field
6:0
PLL2_M
This programs the PLL2 M divider to divide from 1 to 64.
PLL2_M
0000000
0000001
0000010
0000011
0000100
0000101
—
PLL2 Input Divider Value
1
1
1.5
2
2.5
3
—
63
63.5
64
1111101
0000010
1111111
TABLE 15. PLL2_N (0x0Ah)
Bits
Field
Description
7:0
PLL2_N
This programs PLL2's N divider to divide from 10 to 250.
PLL2_N
00000000 to 00001010
00001011
Comment
10
11
00001100
12
00001101
13
00001110
14
00001111
15
—
—
11111000
248
249
250
11111001
11111010 to 11111111
TABLE 16. PLL2_N_MOD (0x0Bh)
Bits
Field
Description
4:0
PLL2_N_MOD
This programs the sigma-delta modulator in PLL2
PLL2_N_MOD
Fractional Part of N
00000
0
00001
1/32
2/32
3/32
4/32
5/32
—
00010
00011
00100
00101
—
11101
29/32
30/32
31/32
11110
11111
5
PLL2_P[8]
This is the MSB of the P Divider on PLL2.
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40
TABLE 17. PLL2_P (0x0Ch)
Description
Bits
Field
7:0
PLL2_P[7:0]
This programs the 8 LSBs of PLL2's P Divider. These LSBs combine with PLL2_P[8] which
allows the P divider to divide by up to 256
PLL2_P
000000000
000000001
000000010
000000011
000000100
000000101
—
P Divides by
1
1
1.5
2
2.5
3
—
111111101
111111110
111111111
255
255.5
256
41
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20.0 Analog Mixer Control Registers
This register is used to control the LM49350's Analog Mixer:
TABLE 18. CLASS_D_OUTPUT (0x10h)
Bits
0
Field
Description
DACR_LS
DACL_LS
MICR_LS
MICL_LS
AUXR_LS
AUXL_LS
The right DAC output is added to the loudspeaker output.
1
The left DAC output is added to the loudspeaker output.
2
The right MIC input is added to the loudspeaker output. Setting this bit enables MIC BIAS.
The left MIC input is added to the loudspeaker output. Setting this bit enables MIC BIAS.
The right AUX input is added to the loudspeaker output.
3
4
5
The left AUX input is added to the loudspeaker output.
20.1 CLASS D LOUDSPEAKER AMPLIFIER
signal. Sub-sonic (DC) and super-sonic components
(>22kHz) are not useful. The difference between the power
flowing from the power supply and the audio band power be-
ing transduced is dissipated in the LM49350 and in the trans-
ducer load. The amount of power dissipation in the LM49350's
class D amplifier is very low. This is because the ON resis-
tance of the switches used to form the output waveforms is
typically less than 0.25Ω. This leaves only the transducer load
as a potential "sink" for the small excess of input power over
audio band output power. The LM49350 dissipates only a
fraction of the excess power requiring no additional PCB area
or copper plane to act as a heat sink.
The LM49350 features a filterless modulation scheme. The
differential outputs of the device switch at 300kHz from VDD
to GND. When there is no input signal applied, the two outputs
(LS+ and LS-) switch with a 50% duty cycle, with both outputs
in phase. Because the outputs of the LM49350 are differen-
tial, the two signals cancel each other. This results in no net
voltage across the speaker, thus there is no load current dur-
ing an idle state, conserving power.
With an input signal applied, the duty cycle (pulse width) of
the LM49350 outputs changes. For increasing output volt-
ages, the duty cycle of LS+ increases, while the duty cycle
of LS- decreases. For decreasing output voltages, the con-
verse occurs, the duty cycle of LS- increases while the duty
cycle of LS+ decreases. The difference between the two
pulse widths yields the differential output voltage.
EMI/RFI Filtering
If system level PCB layout constraints require the LM49350’s
Class D output bumps to be placed far away from the speaker
or the Class D output traces to be routed near EMI/RFI sen-
sitive components, an external EMI/RFI filter should be used.
A series ferrite bead placed close to the Class D output bumps
along with a shunt capacitor to ground placed close to the
ferrite bead will reduce the EMI/RFI emissions of the Class D
amplifier’s switching outputs. The ferrite bead must be rated
with a current rating high enough to properly drive the loud-
speaker. The ferrite bead that is rated for 1A or greater is
recommended. The DC resistance of the ferrite bead is an-
other important specification that must be taken into consid-
eration. A low DC resistance will minimize any power losses
dissipated by the EMI/RFI filter thereby preserving the power
efficiency advantages of the Class D amplifier. Selecting a
ferrite bead with high DC resistance will decrease output
power delivered to speaker and reduce the Class D amplifier’s
efficiency. The shunt capacitor needs to have low ESR. A
10pF ceramic capacitor with a X7R dielectric is recommended
as a starting point. Care needs to be taken to ensure that the
value of the shunt capacitor does not exceed 47pF when us-
ing a low resistance ferrite bead in order to prevent permanent
damage to the low side FETs of the Class D output stage.
20.2 SPREAD SPECTRUM MODULATION
The LM49350 features a fitlerless spread spectrum modula-
tion scheme that eliminates the need for output filters, ferrite
beads or chokes. The switching frequency varies by ±30%
about a 300kHz center frequency, reducing the wideband
spectral content, improving EMI emissions radiated by the
speaker and associated cables and traces. Where a fixed fre-
quency class D exhibits large amounts of spectral energy at
multiples of the switching frequency, the spread spectrum ar-
chitecture of the LM49350 spreads that energy over a larger
bandwidth. The cycle-to-cycle variation of the switching peri-
od does not affect the audio reproduction or efficiency.
20.3 CLASS D POWER DISSIPATION AND EFFICIENCY
In general terms, efficiency is considered to be the ratio of
useful work output divided by the total energy required to pro-
duce it with the difference being the power dissipated, typi-
cally, in the IC. The key here is “useful” work. For audio
systems, the energy delivered in the audible bands is con-
sidered useful including the distortion products of the input
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20194110
FIGURE 15. EMI/RFI Filter for the Class D Amplifier
TABLE 19. LEFT HEADPHONE_OUTPUT (0x11h)
Bits
0
Field
Description
DACR_HPL
DACL_HPL
MICR_HPL
MICL_HPL
AUXR_HPL
AUXL_HPL
The right DAC output is added to the left headphone output.
1
The left DAC output is added to the left headphone output.
2
The right MIC input is added to the left headphone output. Setting this bit enables MIC BIAS.
The left MIC input is added to the left headphone output. Setting this bit enables MIC BIAS.
The right AUX input is added to the left headphone output.
3
4
5
The left AUX input is added to the left headphone output.
TABLE 20. RIGHT HEADPHONE_OUTPUT (0x12h)
Bits
0
Field
Description
DACR_HPR
DACL_HPR
The right DAC output is added to the right headphone output.
The left DAC output is added to the right headphone output.
1
The right MIC input is added to the right headphone output. Setting this bit enables the MIC
BIAS output.
2
3
MICR_HPR
MICL_HPR
The left MIC input is added to the right headphone output. Setting this bit enables the MIC
BIAS output.
4
5
AUXR_HPR
AUXL_HPR
The right AUX input is added to the right headphone output.
The left AUX input is added to the right headphone output.
20.4 HEADPHONE AMPLIFIER FUNCTION
20.6 CHARGE PUMP FLYING CAPACITOR (C6)
The LM49350 headphone amplifier features National’s
ground referenced architecture that eliminates the large DC-
blocking capacitors required at the outputs of traditional head-
phone amplifiers. A low-noise inverting charge pump creates
a negative supply (HP_VSS) from the positive supply voltage
(LS_VDD). The headphone amplifiers operate from these
bipolar supplies, with the amplifier outputs biased about GND,
instead of a nominal DC voltage (typically VDD/2), like tradi-
tional amplifiers. Because there is no DC component to the
headphone output signals, the large DC-blocking capacitors
(typically 220μF) are not necessary, conserving board space
and system cost, while improving frequency response.
The flying capacitor (C6) affects the load regulation and out-
put impedance of the charge pump. A C6 value that is too low
results in a loss of current drive, leading to a loss of amplifier
headroom. A higher valued C6 improves load regulation and
lowers charge pump output impedance to an extent. Above
2.2μF, the RDS(ON) of the charge pump switches and the ESR
of C6 and C5 dominate the output impedance. A lower value
capacitor can be used in systems with low maximum output
power requirements. Please refer to the demonstration board
schematic shown in Figure 23.
20.7 CHARGE PUMP FLYING CAPACITOR (C5)
The value and ESR of the hold capacitor (C5) directly affects
the ripple on CPVSS. Increasing the value of C5 reduces out-
put ripple. Decreasing the ESR of C5 reduces both output
ripple and charge pump output impedance. A lower value ca-
pacitor can be used in systems with low maximum output
20.5 CHARGE PUMP CAPACITOR SELECTION
Use low ESR ceramic capacitors (less than 100mΩ) for opti-
mum performance.
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power requirements. Please refer to the demonstration board
schematic shown in Figure 23.
TABLE 21. AUX_OUTPUT (0x13h)
Bits
0
Field
Description
DACR_AUX
DACL_AUX
MICR_AUX
MICL_AUX
AUXR_AUX
AUXL_AUX
The right DAC output is added to the AUX output.
1
The left DAC output is added to the AUX output.
2
The right MIC input is added to the AUX output. Setting this bit enables the MIC BIAS output.
The left MIC input is added to the AUX output. Setting this bit enables the MIC BIAS output.
The right AUX input is added to the AUX output.
3
4
5
The left AUX input is added to the AUX output.
20.8 AUXILIARY OUTPUT AMPLIFIER
amplifier which then isolates it from any ground noise, thereby
improving signal to noise ratio (SNR) and power supply re-
jection ratio (PSRR).
The LM49350’s auxiliary output (AUXOUT) amplifier provides
differential drive capability to loads that are connected across
its outputs. This results in output signals at the AUX_OUT+
and AUX_OUT- pins that are 180 degrees out of phase with
respect to each other. This effectively doubles the maximum
possible output swing for a specific supply voltage when com-
pared to single-ended output configurations. The differential
output configuration also allows the load to be isolated from
ground since both the AUX_OUT+ and AUX_OUT- pins are
biased at the same DC potential. This eliminates the need for
any large and expensive DC blocking capacitors at the AUX-
OUT amplifier outputs. The load can then be directly con-
nected to the positive and negative outputs of the AUXOUT
The AUXOUT amplifier has two modes of operation. The pri-
mary mode of operation is high current drive mode (Earpiece
Mode) where the AUXOUT amplifier can be used to differen-
tially drive a mono earpiece speaker. The secondary mode of
operation is low current drive mode where the AUXOUT am-
plifier operates in a power saving mode (AUX_LINE_OUT
Mode) to provide a differential output that is used as a mono
differential line level input to a standalone mono differential
input class D amplifier (LM4675) for stereo loudspeaker ap-
plications.
TABLE 22. OUTPUT_OPTIONS (0x14h)
Bits
Field
Description
0
EPMODE
If set the HPR output is driven with the negative input of the HPL output stage.
If set, both HPL and HPR are attenuated by 6dB. This is useful when adding stereo signals
that need more headroom due to being highly correlated.
1
2
HP_NEG_6dB
LS_NEG_6dB
If set the class D output is attenuated by 6dB. This is useful when adding stereo signals that
need more headroom due to being highly correlated.
If set the AUX output is attenuated by 6dB. This is useful when adding stereo signals that
need more headroom due to being highly correlated.
3
4
AUX_NEG_6dB
CP_FORCE
If set, a -LS_VDD rail will be created on HP_VSS, even if the HP output stage is not required.
TABLE 23. ADC_INPUT (0x15h)
Bits
0
Field
Description
DACR_ADCR
DACL_ADCL
MICR_ADCR
MICL_ADCL
AUXR_ADCR
AUXL_ADCL
The right DAC output is added to the ADC right input.
1
The left DAC output is added to the ADC left input.
2
The right MIC input is added to the ADC right input. Setting this bit enables MIC BIAS.
The left MIC input is added to the ADC left input. Setting this bit enables MIC BIAS.
The right AUX input is added to the ADC right input.
3
4
5
The left AUX input is added to the ADC left input.
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TABLE 24. MIC_L_INPUT (0x16h)
Description
Bits
Field
3:0
MIC_L_LEVEL
This sets the gain of the left microphone preamp.
MIC_L_LEVEL
Gain
6dB
0000
0001
8dB
0010
10dB
12dB
14dB
16dB
18dB
20dB
22dB
24dB
26dB
28dB
30dB
32dB
34dB
36dB
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4
5
SE_DIFF
MUTE
If set, the MIC_L negative input is ignored.
If set, the left microphone preamp is muted.
TABLE 25. MIC_R_INPUT (0x17h)
Bits
Field
Description
3:0
MIC_R_LEVEL
This sets the gain of the right microphone preamp.
MIC_R_LEVEL
Gain
6dB
0000
0001
8dB
0010
10dB
12dB
14dB
16dB
18dB
20dB
22dB
24dB
26dB
28dB
30dB
32dB
34dB
36dB
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4
5
SE_DIFF
MUTE
If set, the MIC_R negative input is ignored.
If set, the right microphone preamp is muted.
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TABLE 26. AUX_L_INPUT (0x18h)
Description
Bits
Field
5:0
AUX_L_LEVEL This programs the left AUX input level. All gain changes are performed at zero crossings.
AUX_L_LEVEL
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011000
011001
011010
011100
011101
011110
011111
Level
–46.5dB
–45dB
–43.5dB
–42dB
–40.5dB
–39dB
–37.5dB
–36dB
–34.5dB
–33dB
–31.5dB
–30dB
–28.5dB
–27dB
–25.5dB
–24dB
–22.5dB
–21dB
–19.5dB
–18dB
–16.5dB
–15dB
–13.5dB
–12dB
–10.5dB
–9dB
AUX_L_LEVEL
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Level
1.5dB
3dB
4.5dB
6dB
7.5dB
9dB
10.5dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
–7.5dB
–6dB
–4.5dB
–3dB
–1.5dB
0dB
6
FROM_LINE_L If set, the LEFT_MIC/LINE differential input is routed to the AUX_L input amplifier for line level volume
control. This bit overrides the DIFF_MODE (bit 7 of 0x19h) setting.
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TABLE 27. AUX_R_INPUT (0x19h)
Description
Bits
Field
5:0
AUX_R_LEVEL This programs the right AUX input level. All gain changes are performed at zero crossings.
AUX_R_LEVEL
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011000
011001
011010
011100
011101
011110
011111
Level
–46.5dB
–45dB
–43.5dB
–42dB
–40.5dB
–39dB
–37.5dB
–36dB
–34.5dB
–33dB
–31.5dB
–30dB
–28.5dB
–27dB
–25.5dB
–24dB
–22.5dB
–21dB
–19.5dB
–18dB
–16.5dB
–15dB
–13.5dB
–12dB
–10.5dB
–9dB
AUX_R_LEVEL
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Level
1.5dB
3dB
4.5dB
6dB
7.5dB
9dB
10.5dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
12dB
–7.5dB
–6dB
–4.5dB
–3dB
–1.5dB
0dB
6
7
FROM_LINE_R If set, the RIGHT_MIC/LINE differential input is routed to the AUX_R input amplifier for line level volume
control. This bit overrides the DIFF_MODE (bit 7) setting.
DIFF_MODE If set, the stereo single-ended inputs AUX_L and AUX_R convert to a mono differential input pair MONO_IN
+ and MONO_IN-.
(MONO_IN+) - (MONO_IN-) is routed to the AUX_L input amplifier.
(MONO_IN-) - (MONO_IN+) is routed to the AUX_R input amplifier.
(unless overriden by the respective FROM_LINE bits).
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21.0 ADC Control Registers
This register is used to control the LM49350's ADC:
TABLE 28. ADC Basic (0x20h)
Description
Bits
Field
0
MONO
This sets mono or stereo operation of the ADC.
MONO
0
ADC Operation
Stereo Audio
1
Mono Voice (Right ADC channel disabled, Left ADC channel active)
This sets the oversampling ratio of the ADC.
1
OSR
OSR
Stereo Audio ADC
Oversampling Ratio
Mono Voice ADC Oversampling Ratio
0
1
128
64
125
128
2
3
MUTE_L
MUTE_R
If set, a digital mute is applied to the Left (or mono) ADC output.
If set, a digital mute is applied to the Right ADC output.
6.4
ADC_CLK_SEL
This selects the source of the ADC clock domain, ADC_SOURCE_CLK.
ADC_CLK_SEL
Source
000
001
010
011
100
MCLK
PORT1_RX_CLK
PORT2_RX_CLK
PLL1_OUTPUT2
PLL2_OUTPUT
7
ADC_DSP_ONLY
If set the ADC's analog circuitry is disabled to reduce power consumption, however, ADC DSP
functionality is maintained. This can be used to perform asyncronous resampling between audio
rates of a common family. Setting this bit is also useful whenever applying Automatic Level Control
(ALC) to an analog only audio path.
TABLE 29. ADC_CLK_DIV (0x21h)
Description
Bits
Field
7:0
ADC_CLK_DIV
This programs the half cycle divider that preceeds the ADC. The input of this divider should be
around 12MHz. The default of this divider is 0x00.
Program this divider with the division you want, multiplied by 2, and subtract 1.
ADC_CLK_DIV
00000000
00000001
00000010
00000011
—
Divides by
1
1
1.5
2
—
11111101
11111110
11111111
127
127.5
128
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TABLE 30. ADC TRIM (0x22h)
Description
Bits
Field
7:0
ADC_TRIM
If set, the ADC is compensated with recommended compensation filter coefficients. The
recommended ADC compensation filter coefficients are programmed as follows:
Register 0xF8h set to 0x00h
Register 0xF9h set to 0x01h
Register 0xFAh set to 0x96h
Register 0xFBh set to 0xFBh
Register 0xFCh set to 0x30h
Register 0xFDh set to 0x62h
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22.0 DAC Control Registers
This register is used to control the LM49350's DAC:
TABLE 31. DAC Basic (0x30h)
Description
Bits
Field
1:0
MODE
This programs the over sampling ratio of the stereo DAC.
MODE
DAC Oversampling Ratio
00
125
128
64
01
10
11
32
2
3
MUTE_L
MUTE_R
This digitally mutes the Left DAC output.
This digitally mutes the Right DAC output.
6:4
DAC_CLK_SEL
This selects the source of the DAC clock domain, DAC_SOURCE_CLK.
DAC_CLK_SEL
Source
000
001
010
011
100
MCLK
PORT1_RX_CLK
PORT2_RX_CLK
PLL1_OUTPUT1
PLL2_OUTPUT
7
DSP_ONLY
If set, the DAC's analog circuitry is disabled to reduce power consumption, however DAC DSP
functionality is maintained. This can be used to perform asyncronous resampling between audio rates
of a common family.
TABLE 32. DAC_CLK_DIV (0x31h)
Description
Bits
Field
7:0
DAC_CLK_DIV
This programs the half cycle divider that precedes the DAC. The input of this divider should be
around 12MHz. The default of this divider is 0x00.
Program this divider with the division you want, multiplied by 2, and subtract 1.
DAC_CLK_DIV
00000000
00000001
00000010
00000011
—
Divides by
1
1
1.5
2
—
11111101
11111110
11111111
127
127.5
128
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50
Another key feature of the digital mixer is sample rate con-
version (SRC) between audio ports. This allows simultaneous
operation of the dual audio ports even if each port is operating
at a different sample rate. The LM49350 can be used as an
audio port bridge with SRC capability. The digital mixer allows
either straight pass through between audio ports or, if desired,
DSP effects can be added to the digital audio signal during
audio port bridge operation. The digital mixer automatically
handles stereo I2S to mono PCM conversion between audio
ports and vice versa.
23.0 Digital Mixer Control Registers
23.1 DIGITAL MIXER
The LM49350’s digital mixer allows for flexible routing of dig-
ital audio signals between both audio ports, DAC, and ADC.
This mixer handles which digital data path (Port1 RX data,
Port2 RX data, or ADC output) is routed to the DAC input. The
digital mixer also selects the appropriate digital data path
(Port1 RX data, Port2 RX data, ADC output, DAC DSP output,
or ADC DSP output) that is used for data transmission on Au-
dio Port 1 and 2. Audio inputs to the digital mixer can be
attenuated down to -18dB to avoid clipping conditions.
20194137
FIGURE 16. Digital Mixer
The LM49350 includes two separate and independent DSP
blocks, one for the DAC and the other for the ADC. The digital
mixer also allows both DSP blocks to be cascaded together
in either order so that the DSP effects from both blocks can
be combined into the same signal path. For example, the 5
band parametric EQ of each DSP block can be combined to-
gether to form a 10 band parametric EQ for added flexibility.
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This register is used to control the LM49350's digital mixer:
TABLE 33. Input Levels 1 (0x40h)
Bits
Field
Description
1:0
PORT1_RX_L
_LVL
This programs the input level of the data arriving from the left receive channel of Audio Port 1.
PORT1_RX_L_LVL
Level
0dB
00
01
10
11
–6dB
–12dB
–18dB
3:2
5:4
7:6
PORT1_RX_R
_LVL
This programs the input level of the data arriving from the right receive channel of Audio Port 1.
PORT1_RX_R_LVL
Level
0dB
00
01
10
11
–6dB
–12dB
–18dB
PORT2_RX_L
_LVL
This programs the input level of the data arriving from the left receive channel of Audio Port 2.
PORT2_RX_L_LVL
Level
0dB
00
01
10
11
–6dB
–12dB
–18dB
PORT2_RX_R
_LVL
This programs the input level of the data arriving from the right receive channel of Audio Port 2.
PORT2_RX_R_LVL
Level
0dB
00
01
10
11
–6dB
–12dB
–18dB
TABLE 34. Input Levels 2 (0x41h)
Bits
Field
Description
1:0
3:2
5:4
ADC_L_LVL
This programs the input level of the data arriving from the left ADC channel.
ADC_L_LVL
Level
0dB
00
01
–6dB
–12dB
–18dB
10
11
ADC_R_LVL
This programs the input level of the data arriving from the right ADC channel.
ADC_R_LVL
Level
0dB
00
01
10
11
–6dB
–12dB
–18dB
INTERP_L_LVL This programs the input level of the data arriving from the left DAC's interpolator output.
INTERP_L_LVL
Level
0dB
00
01
10
11
–6dB
–12dB
–18dB
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52
Bits
Field
Description
7:6
INTERP_R_LVL This programs the input level of the data arriving from the right DAC's interpolator output.
INTERP_R_LVL
Level
0dB
00
01
10
11
–6dB
–12dB
–18dB
TABLE 35. Audio Port 1 Input (0x42h)
Bits
Field
Description
1:0
L_SEL
This selects which input is fed to the Left TX Channel of Audio Port 1.
L_SEL
Selected Input
None
00
01
ADC_L
10
PORT2_RX_L
DAC_INTERP_L
11
3:2
R_SEL
This selects which input is fed to the Right TX Channel of Audio Port 1.
R_SEL
Selected Input
None
00
01
ADC_R
10
PORT2_RX_R
DAC_INTERP_R
11
4
5
SWAP
MONO
If set, this swaps the Left and Right outputs to Audio Port 1.
If set, the right channel is ignored and the left channel becomes (left+right)/2.
TABLE 36. Audio Port 2 Input (0x43h)
Bits
Field
Description
1:0
L_SEL
This selects which input is fed to Audio Port 2's Left TX Channel.
L_SEL
Selected Input
None
00
01
ADC_L
10
PORT1_RX_L
DAC_INTERP_L
11
3:2
R_SEL
This selects which input is fed to Audio Port 2's Right TX Channel.
R_SEL
00
Selected Input
None
01
ADC_R
10
PORT1_RX_R
11
DAC_INTERP_R
4
5
SWAP
MONO
If set, this swaps the Left and Right outputs to audio port 2.
If set, the right channel is ignored and the left channel becomes (left+right)/2.
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TABLE 37. DAC Input Select (0x44h)
Bits
0
Field
Description
This adds Audio Port 1's left RX channel to the DAC's left input.
This adds Audio Port 2's left RX channel to the DAC's left input.
This adds the ADC's left output to the DAC's left input
PORT1_L
PORT2_L
ADC_L
1
2
3
PORT1_R
PORT2_R
ADC_R
This adds Audio Port 1's right RX channel to the DAC's right input.
This adds Audio Port 2's right RX channel to the DAC's right input.
This adds the ADC's right output to the DAC's right input.
If set, this swaps the Left and Right inputs to the DAC.
4
5
6
SWAP
TABLE 38. Decimator Input Select (0x45h)
Bits
Field
Description
1:0
L_SEL
This selects which input is fed to the left ADC's decimator input.
L_SEL
Selected Input
None
00
01
PORT1_RX_L
PORT2_RX_L
DAC_INTERP_L
10
11
3:2
5:4
R_SEL
This selects which input is fed to the right ADC's decimator input.
R_SEL
00
Selected Input
None
01
PORT1_RX_R
PORT2_RX_R
DAC_INTERP_R
10
11
MXR_CLK_SEL This selects sets the source of the Digital Mixer Clock. The 'Auto' setting will automatically select the source
with the highest clock frequency. Whenever the DAC interpolator (DAC_OSR_L or DAC_OSR_R) is
selected then MXR_CLK_SEL should be set to '10'.
MXR_CLK_SEL
Selected Input
Auto
00
01
10
11
MCLK
DAC
ADC
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24.0 Audio Port Control Registers
20194171
FIGURE 17. I2S Serial Data Format (24 bit example)
20194172
FIGURE 18. Left Justified Data Format (24 bit example)
20194170
FIGURE 19. Right Justified Data Format (24 bit example)
20194134
FIGURE 20. PCM Serial Data Format (16 bit example)
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The following registers are used to control the LM49350's audio ports. Audio Port 1 and Audio Port 2 are identical. Port 1 is
programmed through the (0x5Xh) registers. Port 2 is programmed through the (0x6Xh) registers.
TABLE 39. BASIC_SETUP (0x50h/0x60h)
Bits
0
Field
Description
STEREO
If set, the audio port will receive and transmit stereo data.
1
RX_ENABLE
If set the input is enabled (enables the SDI port and input shift register and any clock
generation required).
2
TX_ENABLE
If set the output is enabled (enables the SDO port and output shift register and any clock
generation required).
3
4
5
CLOCK_MS
SYNC_MS
If set the audio port will transmit the clock when either the RX or TX is enabled.
If set the audio port will transmit the sync signal when either the RX or TX is enabled.
This sets how data is clocked by the Audio Port.
CLOCK_PHASE
CLOCK_PHASE
Audio Data Mode
0
1
I2S (TX on falling edge, RX on rising edge)
PCM (TX on rising edge, RX on falling edge)
6
7
STEREO_SYNC_PHASE
If set, this reverses the left and right channel data of the Audio Port.
STEREO_SYNC_PHASE
0
Audio Port Data Orientation
Left channel data goes to left channel output.
Right channel data goes to right channel output.
1
Right channel data goes to left channel output.
Left channel data goes to right channel output.
SYNC_INVERT
If this bit is set the SYNC is inverted before the receiver and transmitter.
SYNC_INVERT
Sync Orientation
0
1
SYNC Low = Left, SYNC High = Right
SYNC Low = Right, SYNC High = Left
TABLE 40. CLK_GEN_1 (0x51h/0x61h)
Bits
Field
Description
5:0
HALF_CYCLE_CLK_ This programs the half-cycle divider that generates the master clocks in the audio port. The input
DIV
of this divider should be around 12MHz. The default of this divider is 0x00, i.e. bypassed.
Program this divider with the division you want, multiplied by 2, and subtract 1.
HALF_CYCLE_CLK_DIV
Divides By
000000
000001
000010
000011
—
BYPASS
1
1.5
2
—
111101
111110
11111
31
31.5
32
6
CLOCK_SEL
This selects the clock source of the master mode Audio Port Clock generator's half-cycle divider.
0 = DAC_SOURCE_CLK
1 = ADC_SOURCE_CLK
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56
TABLE 41. CLK_GEN_1 (0x52h/62h)
Description
Bits
Field
2:0
SYNTH_NUM
Along with SYNTH_DENOM, this sets the clock divider that generates the Port 1 or Port 2 clock in
master mode.
SYNTH_NUM
Numerator
000
001
010
011
100
101
110
111
SYNTH_DENOM (1/1)
100/SYNTH_DENOM
96/SYNTH_DENOM
80/SYNTH_DENOM
72/SYNTH_DENOM
64/SYNTH_DENOM
48/SYNTH_DENOM
0/SYNTH_DENOM
3
SYNTH_DENOM
Along with SYNTH_NUM, this sets the clock divider that generates the Port 1 or Port 2 clock in master
mode.
SYNTH_DENOM
Denominator
128
0
1
125
TABLE 42. CLK_GEN_1 (0x53h/63h)
Description
Bits
Field
2:0
SYNC_RATE
This sets the number of clock cycles before the sync pattern repeats. This depends if the audio port
data is mono or stereo.
In MONO mode:
SYNC_RATE
Number of Clock Cycles
000
8
001
12
16
18
20
24
25
32
010
011
100
101
110
111
In STEREO mode:
SYNC_RATE
000
Number of Clock Cycles
16
24
32
36
40
48
50
64
001
010
011
100
101
110
111
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Bits
Field
Description
5:3
SYNC_WIDTH
In MONO mode, this programs the width (in number of bits) of the SYNC signal.
SYNC_WIDTH
Width of SYNC (in bits)
000
001
010
011
100
101
110
111
1
2
4
7
8
11
15
16
TABLE 43. DATA_WIDTHS (0x54h/64h)
Bits
Field
Description
2:0
RX_WIDTH
This programs the expected bits per word of the serial data input SDI.
RX_WIDTH
Bits
24
20
18
16
14
13
12
8
000
001
010
011
100
101
110
111
5:3
TX_WIDTH
This programs the bits per word of the serial data output SDO.
TX_WIDTH
000
Description
24
20
18
16
14
13
12
8
001
010
011
100
101
110
111
7:6
TX_EXTRA_BITS This programs the TX data output padding.
TX_EXTRA_BITS
Description
00
01
10
11
0
1
High-Z
High-Z
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TABLE 44. TX_MODE (0x55h/x65h)
Bits
Field
Description
0
TX_MODE
This sets the TX data input justification with respect to the SYNC signal.
TX_MODE
Description
MSB Justified
LSB Justified
0
1
5:1
MSB_POSITION This specifies the bit location of the MSB from the start of the frame (MSB Justified) or from the end of
the frame (LSB Justified).
MSB_POSITION
Description
00000
0(Left Justified/PCM Long)
00001
1(I2S/PCM Short)
00010
2
00011
3
00100
4
00101
5
00110
6
00111
7
01000
8
01001
9
01010
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
6
7
COMPAND
If set, audio data will be companded.
This sets the audio companding mode.
μLaw/A-Law
Compand Mode
μLaw/A-Law
0
μLaw
1
A-Law
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quality digital audio effects engine. The data paths on each
DSP engine are 24 bits wide for ultimate flexibility. Both DSP
engines feature digital volume control, automatic level control
(ALC), digital soft clip compression, and a 5-band parametric
EQ. The ADC DSP engine adds a dedicated high-pass filter
to reduce wind noise or pop noise during uplink. The DAC
DSP engine adds a digital 3D algorithm that allows for stereo
widening of the original audio signal. The effects chain of each
DSP engine is shown by the diagrams below.
25.0 Digital Effects Engine
25.1 DIGITAL SIGNAL PROCESSOR (DSP)
The LM49350 is designed to handle the entire audio signal
conditioning and processing within the audio system, thereby
freeing up the workload of any other applications processor
contained within the system. The LM49350 features two in-
dependent DSPs, one for the DAC and the other for the ADC.
Each DSP is fully featured and performs as a professional
20194135
FIGURE 21. ADC DSP Effects Chain
20194136
FIGURE 22. DAC DSP Effects Chain
The ADC and DAC DSP engines can be cascaded together
in any order via the digital mixer to combine different audio
effects to the same signal path. For example, a signal can be
processed with high-pass filtering from the ADC effects en-
gine with 3D stereo widening from the DAC effects engine.
The 5-band parametric EQs from each DSP engine can be
combined to form a single 10-band parametric EQ or a single
5-band parametric EQ with ±30dB (instead of ±15dB) gain
control for each band.
TABLE 45. ADC EFFECTS (0x70h)
Bits
0
Field
Description
ADC_HPF_ENB
ADC_ALC_ENB
ADC_PK_ENB
ADC_EQ_ENB
ADC_SCLP_ENB
This enables the ADC's High Pass Filter.
1
This enables the ADC's Auto Level Control.
This enables the ADC's Peak Detector.
This enables the ADC's 5-band Parametric EQ.
This enables the ADC's Soft Clip Feature.
2
3
4
TABLE 46. DAC EFFECTS (0x71h)
Bits
0
Field
Description
DAC_ALC_ENB
DAC_PK_ENB
DAC_EQ_ENB
DAC_3D_ENB
ADC_SCLP_ENB
This enables the DAC's Auto Level Control.
This enables the DAC's Peak Detector.
1
2
This enables the DAC's 5-band Parametric EQ.
This enables the DAC's Stereo Widening Circuit.
This enables the DAC's Soft Clip Feature.
3
4
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TABLE 47. HPF MODE (0x80h)
Description
Bits
Field
2:0
HPF_MODE
This configures the ADC's High Pass Filter.
HPF_MODE
000
FILTER CHARACTERISTICS
8kHz Voice
001
12kHz Voice
010
16kHz Voice
011
24kHz Voice
100
32kHz Voice
101
32kHz Audio
110
48kHz Audio
111
96kHz Audio
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25.2 ALC OVERVIEW
detector in order to avoid noise pumping. So it is important to
set NOISE_FLOOR to correlate with the signal to noise ratio
of the corresponding audio path. In some instances (ie. Con-
ference calls), it may be desirable to mute audio input signals
that consist solely of background noise from the audio output.
This is accomplished by enabling the ALC’s noise gate
(NG_ENB). When the noise gate is enabled, signals lower
than the noise floor level will be muted from the audio output.
The Automatic Level Control (ALC) system can be used to
regulate the audio output level to a user defined target level.
The ALC feature is especially useful whenever the level of the
audio input is unknown, unpredictable, or has a large dynamic
range. The main purpose of the ALC is to optimize the dy-
namic range of the audio input to audio output path.
There are two separate and independent ALC circuits in the
LM49350. One of the ALC circuits is located within the DAC
DSP effects block. The other ALC circuit is integrated into the
ADC DSP effects block. The DAC ALC controls the DAC dig-
ital gain. The ADC ALC controls the auxiliary input amplifier
gain or microphone preamplifier gain. The dual ALCs can be
used to regulate the level of the analog (Stereo Auxiliary,
mono differential, Stereo MIC/LINE) and digital (Port1 Data
In, Port2 Data In) audio inputs. The ALC regulated output can
be routed to any of the LM49350’s amplifier outputs for play-
back. The ALC regulated output can also be routed to Audio
Port1 or Audio Port2 for digital data transmission via I2S or
PCM.
If the audio input signal is below the target level, the ALC will
increase the gain of the corresponding volume control until
the signal reaches the target level. The rate at which the ALC
performs gain increases is known as decay rate (DECAY
RATE). But before each ALC gain increase the ALC must wait
a predetermined amount of time (HOLD TIME). If the audio
input signal is above the target level, the ALC will decrease
the gain of the corresponding volume control until the signal
reaches the target level. The rate at which the ALC performs
attenuation is known as attack rate (ATTACK RATE). The
ALC’s peak detector tracks increases in audio input signal
amplitude instantaneously, but tracks decreases in audio in-
put signal amplitude at programmable rate (PEAK DECAY
TIME). ATTACK RATE, DECAY RATE, HOLD TIME, and
PEAK DECAY TIME are fully adjustable which allows flexible
operation of the ALC circuit. The ALC’s timers are based on
the sample rate of the DAC or ADC, so the closest corre-
sponding sample rate must be programmed into the ALC
SAMPLE RATE setting (for DAC ALC) or the ALC MODE set-
ting (for ADC ALC).
Only audio inputs that are considered signals (rather than
noise) are sent to the ALC’s peak detector block. The peak
detector compares the level of the audio input versus the ALC
target level (TARGET_LEVEL). Signals lower than the target
level will be amplified and signals higher than the target level
will be attenuated. Any audio input that is lower than the level
specified by the noise floor level (NOISE_FLOOR) will be
considered as noise and will be gated from the ALC’s peak
20194138
FIGURE 23. ALC Example
TABLE 48. ADC_ALC_1 (0x81h)
Description
This programs the timers on the ALC with the closest sample rate of the ADC.
Bits
Field
2:0
SAMPLE_RATE
SAMPLE_RATE
ADC Fs
8kHz
000
001
010
011
100
101
110
111
12kHz
16kHz
24kHz
32kHz
48kHz
96kHz
192kHz
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62
Bits
Field
Description
3
LIMITER
If set, the circuit will never apply gain to the signal, no matter how small, but it will attenuate the
signal as soon as it reaches target and release it at the decay rate, once signal level reduces below
target. The I2C gain setting (at the time the LIMITER is enabled) is the maximum gain that the ALC
will apply. Care should be taken when choosing the optimum I2C gain setting whenever enabling
the Limiter.
4
5
STEREO LINK
SOURCE_SEL
If set, the ALC circuit uses the stereo average of the input signals to control the gain of the stereo
output. This maintains stereo imaging. If this bit is cleared, then both channels operate as dual
mono.
If SOURCE_OVR is set then this manually overrides the selection of the input amplifier that is used
to alter the gain for ALC operation.
0 = Both ALCs control AUX gain
1 = Both ALCs control MIC gain
6
SOURCE_OVR
If set, the output of the ALC is not set automatically but is controlled by the SOURCE_SEL bit. If
cleared each ALC controls the input gain of the amplifier (AUX or MIC) that is set to that ADC
channel (or MIC if both are selected).
TABLE 49. ADC_ALC_2 (0x82h)
Description
Bits
Field
3:0
NOISE_FLOOR
This sets the anticipated noise floor. Signals lower than the noise floor specified will be gated from
the ALC to avoid noise pumping.
NOISE_FLOOR
0000
Noise Floor (dB)
–39
–42
–45
–48
–51
–54
–57
–60
–63
–66
–69
–72
–75
–78
–81
–84
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4
NG_ENB
This enables the Noise Gate.
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TABLE 50. ADC_ALC_3 (0x83h)
Description
Bits
Field
4:0
TARGET_LEVEL
This sets the desired target output level. Signals lower than this will be amplified and signals larger
than this will be attenuated.
TARGET_LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Target Level (dB)
–1.5
–3
–4.5
–6
–7.5
–9
–10.5
–12
–13.5
–15
–16.5
–18
–19.5
–21
–22.5
–24
–25.5
–27
–28.5
–30
–31.5
–33
–34.5
–36
–37.5
–39
–40.5
–42
–43.5
–45
–46.5
–48
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64
TABLE 51. ADC_ALC_4 (0x84h)
Description
This sets the rate at which the ALC will reduce gain if it detects the input signal is large.
Bits
Field
4:0
ATTACK_RATE
ATTACK_RATE
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Time between gain steps (μs)
21
42
83
167
250
333
417
542
729
958
1250
1604
1896
2208
2792
3708
4792
5688
6563
8396
11000
14167
17083
20000
25000
32000
45000
60000
75000
87500
100000
114583
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TABLE 52. ADC_ALC_5 (0x85h)
Description
Bits
Field
4:0
DECAY_RATE
This sets the rate at which the ALC will increase gain if it detects the input signal is too
small.
DECAY_RATE
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
PK_DECAY_RATE
000
Time between gain steps (μs)
104
125
167
250
292
396
500
708
896
1250
1396
2000
2708
3500
4750
6250
8000
11000
14000
18500
25000
32000
42000
55000
72500
100000
125000
160000
225000
300000
375000
500000 (0.5s)
Max Time to track decay
1.3ms
7:5
PK_DECAY_RATE
001
2.6ms
010
5.3ms
011
10.6ms
21.3ms
42.6.3ms
85.5ms
2.73 secs
100
101
110
111
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66
TABLE 53. ADC_ALC_6 (0x86h)
Field Description
Bits
4:0
HOLD_TIME This sets how long the ALC circuit waits before
increasing the gain.
HOLD_TIME
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Time (ms)
1
1.25
1.6
2
2.5
3.2
4
5
6.25
8
10
12.5
16
20
25
32
40
50
64
80
100
125
160
200
250
320
400
500
640
800
1000
1250
TABLE 54. ADC_ALC_7 (0x87h)
Bits
Field
Description
5:0
MAX_LEVEL
This sets the maximum allowed gain of the volume control to the output
amplifier. If the volume control is less than 6 bits the relevant LSBs are used
as the limit and the MSBs are ignored.
TABLE 55. ADC_ALC_8 (0x88h)
Description
Bits
Field
5:0
MIN_LEVEL
This sets the minimum allowed gain of the volume control to the output
amplifier. If the volume control is less than 6 bits the relevant LSBs are used
as the limit and the MSBs are ignored.
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TABLE 56. ADC_L_LEVEL (0x89h) (Default data value is 0x33h)
Field Description
ADC_L_LEVEL This sets the post ADC digital gain of the left channel.
Bits
5:0
ADC_L_LEVEL
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
Level
-76.5dB
-75dB
ADC_L_LEVEL
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Level
-28.5dB
-27dB
-25.5dB
-24dB
-22.5dB
-21dB
-20.5dB
-18dB
-16.5dB
-15dB
-13.5dB
-12dB
-10.5dB
-9dB
-73.5dB
-72dB
-70.5dB
-69dB
-67.5dB
-66dB
-64.5dB
-63dB
-61.5dB
-60dB
-58.5dB
-57dB
-55.5dB
-54dB
-7.5dB
-6dB
-52.5dB
-51dB
-4.5dB
-3dB
-49.5dB
-48dB
-1.5dB
0dB
-46.5dB
-45dB
1.5dB
3dB
-43.5dB
-42dB
4.5dB
6dB
-40.5dB
-39dB
7.5dB
9dB
-37.5dB
-36dB
10.5dB
12dB
-34.5dB
-33dB
13.5dB
15dB
-31.5dB
-30dB
16.5dB
18dB
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TABLE 57. ADC_R_LEVEL (0x8Ah) (Default data value is 0x33h)
Field Description
ADC_R_LEVEL This sets the post ADC digital gain of the right channel.
Bits
5:0
ADC_R_LEVEL
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
Level
-76.5dB
-75dB
ADC_R_LEVEL
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Level
-28.5dB
-27dB
-25.5dB
-24dB
-22.5dB
-21dB
-20.5dB
-18dB
-16.5dB
-15dB
-13.5dB
-12dB
-10.5dB
-9dB
-73.5dB
-72dB
-70.5dB
-69dB
-67.5dB
-66dB
-64.5dB
-63dB
-61.5dB
-60dB
-58.5dB
-57dB
-55.5dB
-54dB
-7.5dB
-6dB
-52.5dB
-51dB
-4.5dB
-3dB
-49.5dB
-48dB
-1.5dB
0dB
-46.5dB
-45dB
1.5dB
3dB
-43.5dB
-42dB
4.5dB
6dB
-40.5dB
-39dB
7.5dB
9dB
-37.5dB
-36dB
10.5dB
12dB
-34.5dB
-33dB
13.5dB
15dB
-31.5dB
-30dB
16.5dB
18dB
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TABLE 58. EQ_BAND_1 (0x8Bh)
Description
This sets the Sub-bass shelving filter's cut-off frequency.
Bits
Field
1:0
FREQ
FREQ
00
Frequency (Hz)
60
80
01
10
100
120
11
6:2
LEVEL
This sets the gain at fc.
LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
1dB
2dB
3dB
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
13dB
14dB
15dB
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70
TABLE 59. EQ_BAND_2 (0x8Ch)
Description
This sets the Bass peak filter's center frequency.
Bits
Field
1:0
FREQ
FREQ
Frequency (Hz)
100
150
200
250
300
101
110
111
6:2
LEVEL
This sets the gain at fc.
LEVEL
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Programs the width of the peak filter.
Q
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
1dB
2dB
3dB
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
13dB
14dB
15dB
7
Q
Bandwidth
2/3 Octave
4/3 Octave
0
1
71
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TABLE 60. EQ_BAND_3 (0x8Dh)
Description
This sets the Mid peak filter's center frequency.
Bits
Field
1:0
FREQ
FREQ
Frequency (Hz)
100
600
800
1k
101
110
111
1.2k
6:2
LEVEL
This sets the gain at fc.
LEVEL
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
1dB
10010
2dB
10011
3dB
10100
4dB
10101
5dB
10110
6dB
10111
7dB
11000
8dB
11001
9dB
11010
10dB
11dB
12dB
13dB
14dB
15dB
11011
11100
11101
11110
11111
7
Q
This programs the width of the peak filter.
Q
0
Bandwidth
2/3 Octave
4/3 Octave
1
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72
TABLE 61. EQ_BAND_4 (0x8Eh)
Description
This sets the Treble peak filter's center frequency.
Bits
Field
1:0
FREQ
FREQ
Frequency (Hz)
00
2k
01
2.7k
3.4k
4.1k
10
11
6:2
LEVEL
This sets the gain at fc.
LEVEL
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
1dB
10010
2dB
10011
3dB
10100
4dB
10101
5dB
10110
6dB
10111
7dB
11000
8dB
11001
9dB
11010
10dB
11dB
12dB
13dB
14dB
15dB
11011
11100
11101
11110
11111
7
Q
This programs the width of the peak filter.
Q
0
Bandwidth
2/3 Octave
4/3 Octave
1
73
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TABLE 62. EQ_BAND_5 (0x8Fh)
Description
This sets the presence shelving filter's cut-off frequency.
Bits
Field
1:0
FREQ
FREQ
00
Frequency (Hz)
7k
9k
01
10
11k
20k
11
6:2
LEVEL
This sets the gain at fc.
LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
1dB
2dB
3dB
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
13dB
14dB
15dB
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74
TABLE 63. SOFTCLIP1 (0x90h)
Bits
Field
Description
3:0
THRESHOLD
This sets the threshold level of the
audio compressor. Audio signals
above the threshold will be
compressed.
THRESHOLD
Threshold Level
(dB)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
-36dB
-30dB
-24dB
-20dB
-18dB
-17dB
-16dB
-15dB
-14dB
-12dB
-10dB
-8dB
-6dB
-4dB
-2.5dB
-1dB
4
SOFT_KNEE
If set, the audio compressor will
automatically apply higher
compression ratios to audio signals
higher than the threshold level. As the
audio signal approaches levels higher
than the threshold, SOFT_KNEE will
increase the compression RATIO. The
highest compression that the
SOFT_KNEE algorithm will apply is the
compression that is set by RATIO.
75
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TABLE 64. SOFTCLIP2 (0x91h)
Bits
Field
Description
4:0
RATIO
This sets the ratio at which the audio is
compressed to when it passes beyond
the threshold. In SOFT_KNEE mode
this is the final level of compression.
RATIO
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Ratio
1:1 (Bypass)
1:1.2
1:1.4
1:1.7
1:2.0
1:2.4
1:2.8
1:3.4
1:4.0
1:4.7
1:5.7
1:6.7
1:8.0
1:9.5
1:11.3
1:13.5
1:16.0
1:19.0
1:22.8
1:27.0
1:32.0
1:37.9
1:45.5
1:53.9
1:64.0
1:75.0
1:91.0
1:108
1:128
1:152
1:182
1:215
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76
TABLE 65. SOFTCLIP3 (0x92h)
Bits
Field
Description
4:0
LEVEL
This sets the post compressor gain
level.
LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Level (dB)
-22.5dB
-21dB
-19.5dB
-18dB
-16.5dB
-15dB
-13.5dB
-12dB
-10.5dB
-9dB
-7.5dB
-6dB
-4.5dB
-3dB
-1.5dB
0dB
1.5dB
3dB
4.5dB
6dB
7.5dB
9dB
10.5dB
12dB
13.5dB
15dB
16.5dB
18dB
19.5dB
21dB
22.5dB
24dB
77
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26.0 DAC Effects Registers
TABLE 66. DAC_ALC_1 (0xA0h)
Bits
Field
Description
2:0
SAMPLE_ RATE This programs the timers on the ALC
with the closest DAC sample rate.
SAMPLE_ RATE
DAC Fs
8kHz
000
001
010
011
100
101
110
111
12kHz
16kHz
24kHz
32kHz
48kHz
96kHz
192kHz
3
LIMITER
If set, the circuit will never apply gain to
the signal, no matter how small, but it
will attenuate the signal as soon as it
reaches target and release it at the
decay rate, once signal level reduces
below target. The I2C gain setting (at
the time the LIMITER is enabled) is the
maximum gain that the ALC will apply.
Care should be taken when choosing
the optimum I2C gain setting whenever
enabling the Limiter.
4
STEREO LINK If set, the ALC circuit uses the stereo
average of the input signals to control
the gain of the stereo output. This
maintains stereo imaging. If this bit is
cleared, then both channels operate as
dual mono.
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78
TABLE 67. DAC_ALC_2 (0xA1h)
Bits
Field
Description
3:0
NOISE_FLOOR This sets the anticipated noise floor.
Signals lower than the specified noise
floor will be gated from the ALC to
avoid noise pumping.
NOISE_FLOOR
0000
Noise Floor (dB)
-39
-42
-45
-48
-51
-54
-57
-60
-63
-66
-69
-72
-75
-78
-81
-84
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4
NG_ENB
This enables the Noise Gate
79
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TABLE 68. DAC_ALC_3 (0xA2h)
Bits
Field
Description
4:0
TARGET_LEVEL This sets the desired output level.
Signals lower than this will be amplified
and signals larger than this will be
attenuated.
TARGET_LEVEL Target Level (dB)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
-1.5
-3
-4.5
-6
-7.5
-9
-10.5
-12
-13.5
-15
-16.5
-18
-19.5
-21
-22.5
-24
-25.5
-27
-28.5
-30
-31.5
-33
-34.5
-36
-37.5
-39
-40.5
-42
-43.5
-45
-46.5
-48
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80
TABLE 69. DAC_ALC_4 (0xA3h)
Bits
Field
Description
4:0
ATTACK_RATE This sets the rate at which the ALC will
reduce gain if it detects the input signal
is too large.
ATTACK_RATE
Time between
gain steps(us)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
21
42
83
167
250
333
417
542
729
958
1250
1604
1896
2208
2792
3708
4792
5688
6563
8396
11000
14167
17083
20000
25000
32000
45000
60000
75000
87500
100000
114583
81
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TABLE 70. DAC_ALC_5 (0xA4h)
Bits
Field
DECAY_RATE
Description
4:0
This sets the rate at which the ALC will increase gain
if it detects the input signal is too small.
DECAY_RATE
Time between gain steps
(us)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
104
125
167
250
292
396
500
708
896
1250
1396
2000
2708
3500
4750
6250
8000
11000
14000
18500
25000
32000
42000
55000
72500
100000
125000
160000
225000
300000
375000
500000 (0.5s)
7:5
PK_DECAY_RATE This sets how precise the ALC will track amplitude
reductions of the audio input. The shorter the length
of time for PK_DECAY_RATE, the more responsive
the ALC will be when applying gain increases
whenever the audio falls below target level.
PK_DECAY_RATE
Time
1.3ms
000
001
010
011
100
101
110
111
2.6ms
5.3ms
10.6ms
21.3ms
42.6ms
85.5ms
2.73secs
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82
TABLE 71. DAC_ALC_6 (0xA5h)
Bits
Field
Description
4:0
HOLD_TIME
This sets how long the ALC circuit
waits before increasing the gain.
HOLDTIME
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Time (ms)
1
1.25
1.6
2
2.5
3.2
4
5
6.25
8
10
12.5
16
20
25
32
40
50
64
80
100
125
160
200
250
320
400
500
640
800
1000
1250
TABLE 72. DAC_ALC_7 (0xA6h)
Bits
Field
Description
5:0
MAX_LEVEL
This sets the maximum allowed gain to
the digital level control when the ALC
is used.
TABLE 73. DAC_ALC_8 (0xA7h)
Bits
Field
Description
5:0
MIN_LEVEL
This sets the minimum allowed gain
to the digital level control when the
ALC is used.
83
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TABLE 74. DAC_L_LEVEL (0xA8h) (Default data value is 0x33h)
Field Description
DAC_L_LEVEL This sets the pre DAC digital gain.
Bits
5:0
DAC_L_LEVEL
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
Level
-76.5dB
-75dB
DAC_L_LEVEL
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Level
-28.5dB
-27dB
-25.5dB
-24dB
-22.5dB
-21dB
-20.5dB
-18dB
-16.5dB
-15dB
-13.5dB
-12dB
-10.5dB
-9dB
-73.5dB
-72dB
-70.5dB
-69dB
-67.5dB
-66dB
-64.5dB
-63dB
-61.5dB
-60dB
-58.5dB
-57dB
-55.5dB
-54dB
-7.5dB
-6dB
-52.5dB
-51dB
-4.5dB
-3dB
-49.5dB
-48dB
-1.5dB
0dB
-46.5dB
-45dB
1.5dB
3dB
-43.5dB
-42dB
4.5dB
6dB
-40.5dB
-39dB
7.5dB
9dB
-37.5dB
-36dB
10.5dB
12dB
-34.5dB
-33dB
13.5dB
15dB
-31.5dB
-30dB
16.5dB
18dB
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84
TABLE 75. DAC_R_LEVEL (0xA9h) (Default data value is 0x33h)
Field Description
DAC_R_LEVEL This sets the pre DAC digital gain.
Bits
5:0
DAC_R_LEVEL
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
Level
-76.5dB
-75dB
DAC_R_LEVEL
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Level
-28.5dB
-27dB
-25.5dB
-24dB
-22.5dB
-21dB
-20.5dB
-18dB
-16.5dB
-15dB
-13.5dB
-12dB
-10.5dB
-9dB
-73.5dB
-72dB
-70.5dB
-69dB
-67.5dB
-66dB
-64.5dB
-63dB
-61.5dB
-60dB
-58.5dB
-57dB
-55.5dB
-54dB
-7.5dB
-6dB
-52.5dB
-51dB
-4.5dB
-3dB
-49.5dB
-48dB
-1.5dB
0dB
-46.5dB
-45dB
1.5dB
3dB
-43.5dB
-42dB
4.5dB
6dB
-40.5dB
-39dB
7.5dB
9dB
-37.5dB
-36dB
10.5dB
12dB
-34.5dB
-33dB
13.5dB
15dB
-31.5dB
-30dB
16.5dB
18dB
85
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TABLE 76. DAC_3D (0xAAh)
Bits
Field
Description
0
EFFECT_MODE This sets the digital 3D stereo
enhancement mode.
EFFECT_MODE
Type
0
1
Loudspeaker
Headphone
2:1
6:3
EFFECT_LEVEL This sets the applied level of 3D effect.
EFFECT_LEVEL
Level
25%
00
01
10
11
37.50%
50%
75%
FILTER_TYPE This sets the 3D effect filter response.
FILTER_TYPE
0000
Response
200Hz HPF
300Hz HPF
600Hz HPF
900Hz HPF
0001
0010
0011
0100
200Hz-500Hz
BPF
0101
0110
200Hz-1kHz BPF
200Hz-1.6kHz
BPF
0111
200Hz-2.5kHz
BPF
1000
1001
300Hz-1kHz BPF
300Hz-1.6kHz
BPF
1010
300Hz-2.5kHz
BPF
1011
1100
600Hz-1kHz BPF
600Hz-1.6kHz
BPF
1101
1110
1111
600Hz-2.5kHz
BPF
900Hz-1.6kHz
BPF
900Hz-2.5kHz
BPF
7
ATTENUATE
If set, the inputs are reduced by 6dB
before 3D effects are applied in order
to avoid clipping.
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TABLE 77. EQ_BAND_1 (0xABh)
Description
This sets the Sub-bass shelving filter's cut-off frequency.
Bits
Field
1:0
FREQ
FREQ
00
Frequency (Hz)
60
80
01
10
100
120
11
6:2
LEVEL
This sets the gain at fC.
LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
1dB
2dB
3dB
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
13dB
14dB
15dB
87
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TABLE 78. EQ_BAND_2 (0xACh)
Description
This sets the Bass peak filter's center frequency.
Bits
Field
1:0
FREQ
FREQ
Frequency (Hz)
00
150
200
250
300
01
10
11
6:2
LEVEL
This sets the gain at fC.
LEVEL
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
1dB
10010
2dB
10011
3dB
10100
4dB
10101
5dB
10110
6dB
10111
7dB
11000
8dB
11001
9dB
11010
10dB
11dB
12dB
13dB
14dB
15dB
11011
11100
11101
11110
11111
7
Q
This programs the width of the peak filter.
Q
0
Bandwidth
2/3 Octave
4/3 Octave
1
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88
TABLE 79. EQ_BAND_3 (0xADh)
Description
This sets the Mid peak filter's center frequency.
Bits
Field
1:0
FREQ
FREQ
Frequency (Hz)
00
600
800
1k
01
10
11
1.2k
6:2
LEVEL
This sets the gain at fC.
LEVEL
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
1dB
10010
2dB
10011
3dB
10100
4dB
10101
5dB
10110
6dB
10111
7dB
11000
8dB
11001
9dB
11010
10dB
11dB
12dB
13dB
14dB
15dB
11011
11100
11101
11110
11111
7
Q
This programs the width of the peak filter.
Q
0
Bandwidth
2/3 Octave
4/3 Octave
1
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TABLE 80. EQ_BAND_4 (0xAEh)
Description
This sets the Treble peak filter's center frequency.
Bits
Field
1:0
FREQ
FREQ
Frequency (Hz)
00
2k
01
2.7k
3.4k
4.1k
10
11
6:2
LEVEL
This sets the gain at fC.
LEVEL
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
1dB
10010
2dB
10011
3dB
10100
4dB
10101
5dB
10110
6dB
10111
7dB
11000
8dB
11001
9dB
11010
10dB
11dB
12dB
13dB
14dB
15dB
11011
11100
11101
11110
11111
7
Q
This programs the width of the peak filter.
Q
0
Bandwidth
2/3 Octave
4/3 Octave
1
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90
TABLE 81. EQ_BAND_5 (0xAFh)
Description
This sets the presence shelving filter's cut-off frequency.
Bits
Field
1:0
FREQ
FREQ
00
Frequency (Hz)
7k
9k
01
10
11k
20k
11
6:2
LEVEL
This sets the gain at fC.
LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
1dB
2dB
3dB
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
13dB
14dB
15dB
91
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TABLE 82. SOFTCLIP1 (0xB0h)
Bits
Field
Description
3:0
TRESHOLD
This sets the threshold level of the
audio compressor. Audio signals
above the threshold will be
compressed.
THRESHOLD
Threshold Level
(dB)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
-36dB
-30dB
-24dB
-20dB
-18dB
-17dB
-16dB
-15dB
-14dB
-12dB
-10dB
-8dB
-6dB
-4dB
-2.5dB
-1dB
4
SOFT_KNEE
If set, the audio compressor will
automatically apply higher
compression ratios to audio signals
higher than the threshold level. As the
audio signal approaches levels higher
than the threshold, SOFT_KNEE will
increase the compression RATIO. The
highest compression that the
SOFT_KNEE algorithm will apply is the
compression that is set by RATIO.
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92
TABLE 83. SOFTCLIP2 (0xB1h)
Bits
Field
Description
4:0
RATIO
This sets the ratio at which the audio is
compressed to when it passes beyond
the threshold. In soft clip mode this is
the final level of compression.
RATIO
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Ratio
1:1 (Bypass)
1:1.2
1:1.4
1:1.7
1:2.0
1:2.4
1:2.8
1:3.4
1:4.0
1:4.7
1:5.7
1:6.7
1:8.0
1:9.5
1:11.3
1:13.5
1:16.0
1:19.0
1:22.8
1:27.0
1:32.0
1:37.9
1:45.5
1:53.9
1:64
1:75.9
1:91.0
1:108
1:128
1:152
1:182
1:215
93
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TABLE 84. SOFTCLIP3 (0xB2h)
Table 40:
Bits
4:0
Field
Description
LEVEL
This sets the post compressor gain
level.
LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Level (dB)
-22.5dB
-21dB
-19.5dB
-18dB
-16.5dB
-15dB
-13.5dB
-12dB
-10.5dB
-9dB
-7.5dB
-6dB
-4.5dB
-3dB
-1.5dB
0dB
1.5dB
3dB
4.5dB
6dB
7.5dB
9dB
10.5dB
12dB
13.5dB
15dB
16.5dB
18dB
19.5dB
21dB
22.5dB
24dB
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94
27.0 GPIO Registers
TABLE 85. GPIO (0xE0h)
Bits
Field
GPIO_MODE
Description
3:0
This sets the mode of the GPIO Pin.
GPIO_MODE
0000
GPIO Function
OFF (input disabled)
GPIO_RX
0001
0010
GPIO_TX
0011
HP_ENB (out)
HP_ENB (out)
LS_ENB (out)
LS_ENB (out)
0100
0101
0110
0111
SHORT_CCT or
THERMAL (out)
1000
SHORT_CCT or
THERMAL or CLIP
(out)
1001
1010
CLIP (out)
ADC_NG_ACTIVE
(out)
1011
ADC_NG_ACTIVE
(out)
1100
1101
1110
1111
MIC_MUTE (in)
MIC_MUTE (in)
CHIP_ENB (in)
CHIP_ENB (in)
4
GPIO_TX
If set, the GPIO pin will transmit a logic
high whenever GPIO_MODE is set to
'0010'.
5
6
GPIO_RX
This bit reports what logic level is present
on the GPIO pin.
SHORT_CCT
If set, the GPIO records that a short circuit
event has occurred on the class D
outputs.
7
THERMAL_EVENT If set records that a temperature event has
occurred on the die. Clear on Write (1).
TABLE 86. Spread Spectrum (0xF1h)
Bits
1:0
2
Field
RSVD
Description
Reserved
SS_DISABLE
If this bit is set, Spread Spectrum mode
will be disabled from the Class D amplifier.
TABLE 87. ADC Compensation Filter C0 LSBs (0xF8h)
Bits
Field
Description
Bits 7:0 of C0[15:0]
7:0
ADC_CO_LSB
TABLE 88. ADC Compensation Filter C0 MSBs (0xF9h)
Bits
Field
Description
Bits 15:0 of C0[15:0]
7:0
ADC_CO_MSB
95
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TABLE 89. ADC Compensation Filter C1 LSBs (0xFAh)
Bits
Field
Description
Bits 7:0 of C1[15:0]
7:0
ADC_C1_LSB
TABLE 90. ADC Compensation Filter C1 MSBs (0xFBh)
Bits
Field
Description
Bits 15:0 of C1[15:0]
7:0
ADC_C1_MSB
TABLE 91. ADC Compensation Filter C2 LSBs (0xFCh)
Bits
Field
Description
Bits 7:0 of C2[15:0]
7:0
ADC_C2_LSB
TABLE 92. ADC Compensation Filter C2 MSBs (0xFDh)
Bits
Field
Description
Bits 15:0 of C2[15:0]
7:0
ADC_C2_MSB
TABLE 93. AUX_LINEOUT (0xFE)
Bits
4:0
5
Field
Description
RSVD
Reserved
AUX_LINE_OUT If set, the earpiece amplifier operates in a
low current drive mode for line out
applications in order to reduce power
consumption.
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96
97
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28.0 Demonstration Board Layout
20194106
FIGURE 25. Top Silkscreen Layer
20194115
FIGURE 26. Top Layer
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98
20194116
FIGURE 27. Inner Layer 1
20194117
FIGURE 28. Inner Layer 2
99
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20194120
FIGURE 29. Bottom Silkscreen Layer
20194118
FIGURE 30. Bottom Layer
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100
29.0 Revision History
Rev
1.0
Date
Description
09/03/08
09/04/08
09/22/08
10/24/08
12/15/08
05/27/09
05/29/09
Initial release.
1.01
1.02
1.03
1.04
1.05
1.06
Text edits.
Text edits.
Text edits.
Text edits and replaced the top silkscreen layer.
Added the EMI/RFI section and the corresponding graphic.
Text edits.
101
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30.0 Physical Dimensions inches (millimeters) unless otherwise noted
micro SMD–36 Package
Order Number LM49350RL
NS Package Number RLA36TTA
X1 = 3.459±.03mm, X2 = 3.459±.03mm, X3 = 0.65±.075mm
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102
Notes
103
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Notes
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