LM49352_14 [TI]
Mono Class D Audio Codec Subsystem with Ground Referenced Headphone Amplifiers Earpiece Driver, and Audio DSP;
| 型号： | LM49352_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Mono Class D Audio Codec Subsystem with Ground Referenced Headphone Amplifiers Earpiece Driver, and Audio DSP |
| 文件： | 总112页 (文件大小：2162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM49352
LM49352 Mono Class D Audio Codec Subsystem with Ground Referenced
Headphone Amplifiers, Earpiece Driver, and Audio DSP
Literature Number: SNAS467D
June 30, 2010
LM49352
Mono Class D Audio Codec Subsystem with Ground
Referenced Headphone Amplifiers, Earpiece Driver, and
Audio DSP
SNR (Stereo DAC at 48kHz)
PSRR at 217 Hz, A_VDD = 3.3V, (HP from 100dB (typ)
AUX)
103dB (typ)
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■
1.0 General Description
The LM49352 is a high performance mixed signal audio sub-
system. The LM49352 includes a high quality stereo DAC, a
high quality stereo ADC, a stereo headphone amplifier, which
supports True Ground operation, a low EMI Class D loud-
speaker amplifier, and an earpiece speaker amplifier. It com-
bines advanced audio processing, conversion, mixing, and
amplification in the smallest possible footprint while extending
the battery life of feature rich portable devices.
4.0 Features
Ultra efficient, spread spectrum Class D loudspeaker
■
amplifier that operates at 93% efficiency
Low voltage, true ground headphone amplifier operation
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High performance 103dB SNR stereo DAC
The LM49352 features dual bi-directional I2S or PCM audio
interfaces and an I2C compatible interface for control. The
stereo DAC path features an SNR of 103dB with 24-bit 48 kHz
input. The headphone amplifier delivers 65mWRMS (typ) to a
32Ω single-ended stereo load with less than 1% distortion
(THD+N) when HP_VDD = 2.8V. The loudspeaker amplifier
delivers up to 970mW into an 8Ω load with less than 1% dis-
tortion when LS_VDD = 4.2V.
High performance 97dB SNR stereo ADC
Up to 96kHz stereo audio playback
Up to 48kHz stereo recording
Dual bidirectional I2S or PCM compatible audio interfaces
Read/write I2C compatible control interface
Flexible digital mixer with sample rate conversion
Sigma-delta PLL clock network that supports system
clocks up to 50MHz including 13MHz, 19.2MHz, and
26MHz
■
The LM49352 employs advanced techniques to extend bat-
tery life, to reduce controller overhead, to speed development
time, and to eliminate click and pop artifacts. Boomer audio
power amplifiers are designed specifically for mobile devices
and require minimal PCB area and external components.
Dual stereo 5 band parametric equalizers
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Cascadable DSP effects that allow stereo 10 band
parametric equalization
ALC/Limiter/Compressor on both DAC and ADC paths
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2.0 Applications
Dedicated Earpiece Speaker Amplifier
Smart Phones
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Stereo auxiliary inputs and mono differential input
Mobile Phones and VOIP Phones
Differential microphone input with single-ended option
Portable GPS Navigator and Portable Gaming Devices
Automatic level control for digital audio inputs, mono
differential input, microphone input, and stereo auxiliary
inputs
■
Portable DVD/CD/AAC/MP3/MP4 Players
Digital Cameras/Camcorders
■
Flexible audio routing from input to output
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3.0 Key Specifications
16 Step volume control for microphone with 2dB steps
Class D Amplifier Efficiency
93% (typ)
58mW (typ)
65mW/ch (typ)
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32 Step volume control for auxiliary inputs in 1.5dB steps
PEP at A_VDD = 3.3V, 32Ω, 1% THD
PHP at HP_VDD = 2.8V, Stereo 32Ω,
1% THD
4 Step volume control for class D loudspeaker amplifier
8 Step volume control for headphone amplifier
Micro-power shutdown mode
PLS at LS_VDD = 5V, 8Ω, 1% THD
PLS at LS_VDD = 4.2V, 8Ω, 1% THD
PLS at LS_VDD = 3.3V, 8Ω, 1% THD
1.4W (typ)
970mW (typ)
590mW (typ)
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Available in the 3.3 x 3.3 mm 36 bump micro SMD package
Boomer® is a registered trademark of National Semiconductor Corporation.
© 2010 National Semiconductor Corporation
300727
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5.0 LM49352 Overview
30072777
FIGURE 1. LM49352 Block Diagram
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6.0 Typical Application
30072785
FIGURE 2. Example Application in Multimedia Phone with Dedicated Earpiece Speaker and Mono Loudspeaker
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30072786
FIGURE 3. Example Application in Multimedia Phone Using Multiple Media Sources
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30072787
FIGURE 4. Example Application in a Multimedia Phone with Stereo Loudspeaker
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30072788
FIGURE 5. Example Application in a Portable Media Player with Stereo Loudspeakers
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Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Applications .................................................................................................................................... 1
3.0 Key Specifications ........................................................................................................................... 1
4.0 Features ........................................................................................................................................ 1
5.0 LM49352 Overview .......................................................................................................................... 2
6.0 Typical Application ........................................................................................................................... 3
7.0 Connection Diagrams ..................................................................................................................... 10
7.1 PIN TYPE DEFINITIONS ........................................................................................................ 12
8.0 Absolute Maximum Ratings ............................................................................................................ 13
9.0 Operating Ratings ......................................................................................................................... 13
10.0 Electrical Characteristics: A_VDD = LS_VDD = 3.3V; HP_VDD = D_VDD = I/O_VDD = 1.8V ...................... 13
11.0 Typical Performance Characteristics .............................................................................................. 19
12.0 System Control ............................................................................................................................ 29
12.1 I2C SIGNALS ....................................................................................................................... 29
12.2 I2C DATA VALIDITY ............................................................................................................. 29
12.3 I2C START AND STOP CONDITIONS ..................................................................................... 29
12.4 TRANSFERRING DATA ........................................................................................................ 29
12.5 I2C TIMING PARAMETERS .................................................................................................. 31
13.0 Device Register Map .................................................................................................................... 32
14.0 Basic PMC Setup Register ............................................................................................................ 36
15.0 PMC Clocks Register ................................................................................................................... 37
16.0 PMC Clock Divide Register ........................................................................................................... 37
17.0 LM49352 Clock Network .............................................................................................................. 38
18.0 PLL Setup Registers .................................................................................................................... 40
19.0 Analog Mixer Control Registers ..................................................................................................... 44
20.0 ADC Control Registers ................................................................................................................. 53
21.0 DAC Control Registers ................................................................................................................. 55
22.0 Digital Mixer Control Registers ...................................................................................................... 56
23.0 Audio Port Control Registers ......................................................................................................... 60
24.0 Digital Effects Engine ................................................................................................................... 66
25.0 DAC Effects Registers .................................................................................................................. 87
26.0 GPIO Registers ......................................................................................................................... 102
27.0 Schematic Diagram .................................................................................................................... 104
28.0 Demonstration Board Layout ....................................................................................................... 105
29.0 Revision History ........................................................................................................................ 108
30.0 Physical Dimensions .................................................................................................................. 109
List of Figures
FIGURE 1. LM49352 Block Diagram ............................................................................................................. 2
FIGURE 2. Example Application in Multimedia Phone with Dedicated Earpiece Speaker and Mono Loudspeaker ................ 3
FIGURE 3. Example Application in Multimedia Phone Using Multiple Media Sources .................................................. 4
FIGURE 4. Example Application in a Multimedia Phone with Stereo Loudspeaker ...................................................... 5
FIGURE 5. Example Application in a Portable Media Player with Stereo Loudspeakers ................................................ 6
FIGURE 6. I2C Signals: Data Validity ............................................................................................................ 29
FIGURE 7. I2C Start and Stop Conditions ...................................................................................................... 29
FIGURE 8. I2C Chip Address ..................................................................................................................... 29
FIGURE 9. Example I2C Write Cycle ............................................................................................................ 30
FIGURE 10. Example I2C Read Cycle .......................................................................................................... 30
FIGURE 11. I2C Timing Diagram ................................................................................................................. 30
FIGURE 12. Internal Clock Network ............................................................................................................. 39
FIGURE 13. PLL Loop ............................................................................................................................ 40
FIGURE 14. EMI/RFI Filter for the Class D Amplifier ......................................................................................... 45
FIGURE 15. Application Circuit for Headphone Detection ................................................................................... 51
FIGURE 16. Digital Mixer .......................................................................................................................... 56
FIGURE 17. I2S Serial Data Format (24 bit example) ........................................................................................ 60
FIGURE 18. Left Justified Data Format (24 bit example) .................................................................................... 60
FIGURE 19. Right Justified Data Format (24 bit example) .................................................................................. 60
FIGURE 20. PCM Serial Data Format (16 bit example) ...................................................................................... 60
FIGURE 21. ADC DSP Effects Chain ........................................................................................................... 66
FIGURE 22. DAC DSP Effects Chain ........................................................................................................... 66
FIGURE 23. ALC Example ........................................................................................................................ 68
FIGURE 24. ALC Limiter ........................................................................................................................... 69
FIGURE 25. Audio Compressor Effect .......................................................................................................... 82
FIGURE 26. Soft Knee Example with Compression Ratio Setting of 1:3.4 ............................................................... 83
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FIGURE 27. Demo Board Schematic .......................................................................................................... 104
FIGURE 28. Top Silkscreen ..................................................................................................................... 105
FIGURE 29. Top Layer ........................................................................................................................... 105
FIGURE 30. Inner Layer 2 ....................................................................................................................... 106
FIGURE 31. Inner Layer 3 ....................................................................................................................... 106
FIGURE 32. Bottom Layer ...................................................................................................................... 107
FIGURE 33. Bottom Silkscreen ................................................................................................................. 107
List of Tables
TABLE 1. Device Register Map .................................................................................................................. 32
TABLE 2. Nonzero I2C Default Registers ....................................................................................................... 35
TABLE 3. PMC_SETUP (0x00h) ................................................................................................................. 36
TABLE 4. PMC_SETUP (0x01h) ................................................................................................................. 37
TABLE 5. PMC_SETUP (0x02h) ................................................................................................................ 37
TABLE 6. DAC Clock Requirements ............................................................................................................. 38
TABLE 7. ADC Clock Requirements ............................................................................................................. 38
TABLE 8. PLL Settings for Common System Clock Frequencies .......................................................................... 40
TABLE 9. PLL_CLOCK_SOURCE (0x03h) .................................................................................................... 41
TABLE 10. PLL_M (0x04h) ........................................................................................................................ 42
TABLE 11. PLL_N (0x05h) ........................................................................................................................ 42
TABLE 12. PLL_N_MOD (0x06h) ................................................................................................................ 42
TABLE 13. PLL_P1 (0x07h) ....................................................................................................................... 43
TABLE 14. PLL_P2 (0x08h) ....................................................................................................................... 43
TABLE 15. CLASS_D_OUTPUT (0x10h) ....................................................................................................... 44
TABLE 16. LEFT HEADPHONE_OUTPUT (0x11h) .......................................................................................... 45
TABLE 17. RIGHT HEADPHONE_OUTPUT (0x12h) ........................................................................................ 45
TABLE 18. AUX_OUTPUT (0x13h) .............................................................................................................. 46
TABLE 19. OUTPUT_OPTIONS (0x14h) ....................................................................................................... 47
TABLE 20. ADC_INPUT (0x15h) ................................................................................................................. 48
TABLE 21. MIC_INPUT (0x16h) ................................................................................................................. 48
TABLE 22. AUX_LEVEL (0x18h) ................................................................................................................. 49
TABLE 23. MONO_LEVEL (0x19h) .............................................................................................................. 50
TABLE 24. HP_SENSE (0x1Bh) ................................................................................................................. 52
TABLE 25. ADC Basic (0x20h) ................................................................................................................... 53
TABLE 26. ADC_CLK_DIV (0x21h) ............................................................................................................. 53
TABLE 27. ADC_MIXER (0x23h) ................................................................................................................ 54
TABLE 28. DAC Basic (0x30h) .................................................................................................................. 55
TABLE 29. DAC_CLK_DIV (0x31h) ............................................................................................................. 55
TABLE 30. Input Levels 1 (0x40h) ............................................................................................................... 57
TABLE 31. Input Levels 2 (0x41h) ............................................................................................................... 57
TABLE 32. Audio Port 1 Input (0x42h) .......................................................................................................... 58
TABLE 33. Audio Port 2 Input (0x43h) .......................................................................................................... 58
TABLE 34. DAC Input Select (0x44h) ........................................................................................................... 59
TABLE 35. Decimator Input Select (0x45h) .................................................................................................... 59
TABLE 36. BASIC_SETUP (0x50h/0x60h) ..................................................................................................... 61
TABLE 37. CLK_GEN_1 (0x51h/0x61h) ........................................................................................................ 61
TABLE 38. CLK_GEN_1 (0x52h/62h) ........................................................................................................... 62
TABLE 39. CLK_GEN_1 (0x53h/63h) ........................................................................................................... 62
TABLE 40. DATA_WIDTHS (0x54h/64h) ....................................................................................................... 63
TABLE 41. RX_MODE (0x55h/x65h) ............................................................................................................ 64
TABLE 42. TX_MODE (0x56h/x66h) ............................................................................................................ 65
TABLE 43. ADC EFFECTS (0x70h) ............................................................................................................. 66
TABLE 44. DAC EFFECTS (0x71h) ............................................................................................................. 67
TABLE 45. HPF MODE (0x80h) .................................................................................................................. 67
TABLE 46. ADC_ALC_1 (0x81h) ................................................................................................................. 70
TABLE 47. ADC_ALC_2 (0x82h) ................................................................................................................. 70
TABLE 48. ADC_ALC_3 (0x83h) ................................................................................................................. 71
TABLE 49. ADC_ALC_4 (0x84h) ................................................................................................................. 72
TABLE 50. ADC_ALC_5 (0x85h) ................................................................................................................. 73
TABLE 51. ADC_ALC_6 (0x86h) ................................................................................................................ 74
TABLE 52. ADC_ALC_7 (0x87h) ................................................................................................................ 74
TABLE 53. ADC_ALC_8 (0x88h) ................................................................................................................. 74
TABLE 54. ADC_L_LEVEL (0x89h) ............................................................................................................ 75
TABLE 55. ADC_R_LEVEL (0x8Ah) ............................................................................................................. 76
TABLE 56. EQ_BAND_1 (0x8Bh) ................................................................................................................ 77
TABLE 57. EQ_BAND_2 (0x8Ch) ................................................................................................................ 78
TABLE 58. EQ_BAND_3 (0x8Dh) ................................................................................................................ 79
TABLE 59. EQ_BAND_4 (0x8Eh) ................................................................................................................ 80
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TABLE 60. EQ_BAND_5 (0x8Fh) ................................................................................................................ 81
TABLE 61. SOFTCLIP1 (0x90h) ................................................................................................................. 84
TABLE 62. SOFTCLIP2 (0x91h) ................................................................................................................. 85
TABLE 63. SOFTCLIP3 (0x92h) ................................................................................................................. 86
TABLE 64. DAC_ALC_1 (0xA0h) ................................................................................................................ 87
TABLE 65. DAC_ALC_2 (0xA1h) ................................................................................................................ 87
TABLE 66. DAC_ALC_3 (0xA2h) ................................................................................................................ 88
TABLE 67. DAC_ALC_4 (0xA3h) ............................................................................................................... 89
TABLE 68. DAC_ALC_5 (0xA4h) ............................................................................................................... 90
TABLE 69. DAC_ALC_6 (0xA5h) ............................................................................................................... 91
TABLE 70. DAC_ALC_7 (0xA6h) ............................................................................................................... 91
TABLE 71. DAC_ALC_8 (0xA7h) ................................................................................................................ 91
TABLE 72. DAC_L_LEVEL (0xA8h) ............................................................................................................ 92
TABLE 73. DAC_R_LEVEL (0xA9h) ............................................................................................................ 93
TABLE 74. EQ_BAND_1 (0xABh) ............................................................................................................... 94
TABLE 75. EQ_BAND_2 (0xACh) ............................................................................................................... 95
TABLE 76. EQ_BAND_3 (0xADh) ............................................................................................................... 96
TABLE 77. EQ_BAND_4 (0xAEh) ............................................................................................................... 97
TABLE 78. EQ_BAND_5 (0xAFh) ................................................................................................................ 98
TABLE 79. SOFTCLIP1 (0xB0h) ................................................................................................................. 99
TABLE 80. SOFTCLIP2 (0xB1h) ............................................................................................................... 100
TABLE 81. SOFTCLIP3 (0xB2h) ............................................................................................................... 101
TABLE 82. GPIO1 (0xE0h) ...................................................................................................................... 102
TABLE 83. GPIO2 (0xE1h) ...................................................................................................................... 103
TABLE 84. RESET (0xF0h) ..................................................................................................................... 103
TABLE 85. Spread Spectrum (0xF1h) ......................................................................................................... 103
TABLE 86. FORCE (0xFE) ...................................................................................................................... 103
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7.0 Connection Diagrams
36 Bump micro SMD
36 Bump micro SMD Marking
300727q7
Top View
XY — Date Code
TT — Die Traceability
G — Boomer
30072711
Order Number LM49352RL
See NS Package Number RLA36MMA
L5 — LM49352RL
LM49352RL Pinout Diagram
30072710
Top View (Bump Side Down)
Ordering Information
Order Number
Package
Package DWG #
Transport Media
MSL Level
Green Status
36 Bump micro
SMDxt
RoHS and
no Sb/Br
LM49352RL
RLA36MMA
RLA36MMA
250 units on tape and reel
1000 units on tape and reel
1
1
36 Bump micro
SMDxt
RoHS and
no Sb/Br
LM49352RLX
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Pin Descriptions
Pin
Pin Name
Type
Direction
Description
A1
HPR
Analog
Output
Headphone right output
DAC (Analog), ADC (Analog), PLL (Analog), input stages, analog
mixer (AUX and class D), and Earpiece amplifier power supply input
A_VDD
AGND
A2
A3
Supply
Supply
Input
Input
DAC (Analog), ADC (Analog), PLL (Analog), input stages, analog
mixer (AUX and class D), and Earpiece amplifier ground
A4
A5
A6
B1
B2
B3
B4
B5
B6
C1
C2
C3
DAC REF
ADC REF
SDA
Analog
Analog
Digital
Analog
Analog
Analog
Digital
Digital
Digital
Analog
Supply
Analog
Input/Output Filter point for the DAC reference
Input
Filter point for the ADC reference. Connect this pin to A_VDD.
Input/Output I2C interface data line
HPL
Output
Input
Headphone left output
AUX_R/AUX+
AUX_L/AUX-
PORT2_SYNC
PORT2_SDI
SCL
Right analog input or positive differential auxiliary input
Left analog input or negative differential auxiliary input
Input
Input/Output Audio Port 2 sync signal (can be master or slave)
Input
Input
Audio Port 2 serial data input
I2C interface clock line
HP_VSS
Output
Input
Negative power supply pin for the headphone amplifier
Headphone amplifier power supply pin
Earpiece negative output or Auxiliary negative output
HP_VDD
EP-/AUXOUT-
Output
PORT2_SDO /
GPIO
C4
Digital
Input / Output Audio port 2 serial data output or General Purpose Input Output
C5
C6
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
PORT2_CLK
MCLK
Digital
Digital
Analog
Analog
Analog
Digital
Digital
Supply
Supply
Supply
Analog
Analog
Digital
Input/Output Audio port 2 clock signal (can be master or slave)
Input
Input clock from 0.5MHz to 50 MHz
CP-
Input/Output Fly capacitor negative input
Input/Output Fly capacitor positive input
CP+
EP+/AUXOUT+
PORT1_SYNC
PORT1_SDO
DGND
Output
Earpiece positive output or Auxiliary positive output
Input/Output Audio Port 1 sync signal (can be master or slave)
Output
Input
Input
Input
Input
Input
Input
Audio Port 1 serial data output
Digital ground
LSGND
Loudspeaker ground
LS_VDD
Loudspeaker amplifier and analog mixer (headphone) supply input
Mono differential negative input
Microphone negative input
MONO-
MIC-
PORT1_SDI
Audio Port 1 serial data input
DAC (Digital), ADC (Digital), PLL (Digital), digital mixer, DSP core,
and I2C register power supply input
D_VDD
E6
Supply
Input
F1
F2
F3
F4
F5
F6
LS +
LS -
Analog
Analog
Analog
Analog
Digital
Supply
Output
Output
Input
Loudspeaker positive output
Loudspeaker negative output
Mono differential positive input
Microphone positive input
MONO+
MIC +
Input
PORT1_CLK
I/O_VDD
Input/Output Audio Port 1 clock signal (can be master or slave)
Input
Digital I/O (MCLK, I2S/PCM, I2C) interface power supply input
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7.1 PIN TYPE DEFINITIONS
sive components can be connected
to these pins.
Analog Input —
A pin that is used by the analog and
is never driven by the device. Sup-
plies are part of this classification.
Digital Input —
A pin that is used by the digital but is
never driven by the device.
Analog Output —
A pin that is driven by the device and
should not be driven by external
sources.
Digital Output —
A pin that is driven by the device and
should not be driven by another de-
vice to avoid contention.
Analog Input/Output — A pin that is typically used for filtering
a DC signal within the device. Pas-
Digital Input/Output —
A pin that is either open drain (SDA)
or a bidirectional CMOS in/out. In
the latter case the direction is se-
lected by a control register within the
LM49352.
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Machine Model (Note 5)
Junction Temperature
Thermal Resistance
200V
150°C
8.0 Absolute Maximum Ratings (Note
1, Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ꢀθJA – RLA36 (soldered down
to PCB with 2in2 1oz. copper plane)
60°C/W
Soldering Information
Analog Supply Voltage
See Applications Note AN-1112.
(A_VDD and LS_VDD
)
6.0V
2.2V
5.5V
Digital Supply Voltage
D_VDD
9.0 Operating Ratings
Temperature Range
−40°C to +85°C
I/O Supply Voltage
I/O_VDD
Supply Voltage
A_VDD, LS_VDD, and AVDD_REF
D_VDD
I/O_VDD
HP_VDD
2.7V to 5.5V
1.6V to 2.0V
1.6V to 4.5V
1.7V to 2.8V
Headphone Supply Voltage
HP_VDD
3.0V
−65°C to +150°C
Internally Limited
Storage Temperature
Power Dissipation (Note 3)
ESD Ratings
Human Body Model (Note 4)
HPR and HPL pins
All other pins
8kV
2.5kV
10.0 Electrical Characteristics: A_VDD = LS_VDD = 3.3V; HP_VDD = D_VDD = I/
O_VDD = 1.8V (Note 1, Note 2) The following specifications apply for RL(LS) = 8Ω, RL(HP) = 32Ω, f = 1kHz, unless
otherwise specified. Limits apply for TA = 25°C.
LM49352
Units
Symbol
Parameter
Conditions
Typical
Limit
(Limit)
(Note 6) (Note 7)
DC CHARACTERISTICS (Digital current combines D_VDD and I/O_VDD. Analog current combines A_VDD, HP_VDD, and
LS_VDD
)
Shutdown Mode,
fMCLK = 13MHz, PLL Off
DISD
Digital Shutdown Current
2
µA
fMCLK = 11.2896MHz, fS = 44.1kHz,
Stereo DAC On, OSRDAC = 64,
PLL Off, HP On
Digital Active Current (MP3 Mode)
Digital Active Current (FM Mode)
1.2
0.2
1.3
1.4
0.5
1.5
mA (max)
mA (max)
mA (max)
fMCLK = 13MHz
Analog Audio modes
fMCLK = 12.288MHz, fS = 48kHz,
Stereo ADC On, OSRADC = 128,
PLL Off, Stereo Analog Inputs On
DIDD
Digital Active Current
(FM Record Mode)
fMCLK = 12.288MHz, fS = 8kHz,
Mono ADC On, Mono DAC On,
OSRDAC = 64
Digital Active Current
(CODEC Mode)
0.5
0.1
0.8
5
mA (max)
OSRADC = 128, PLL Off, MIC On
AISD
Analog Shutdown Current
Shutdown Mode
μA (max)
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LM49352
Typical Limit
(Note 6) (Note 7)
Units
(Limit)
Symbol
Parameter
Conditions
fMCLK = 11.2896MHz, fS = 44.1kHz
Stereo DAC On, OSRDAC = 64
PLL Off, Stereo HP On
From A_VDD
Analog Supply Current (MP3 Mode)
4.3
1.5
6
mA (max)
mA (max)
From HP_VDD
2.7
fMCLK = 13MHz, PLL Off
Stereo Auxiliary Inputs On,
PLL Off, Stereo HP On
Analog Supply Current (FM Mode)
From A_VDD
1.7
1.5
2.6
2.7
mA (max)
mA (max)
AIDD
From HP_VDD
fMCLK = 12.288MHz, fS = 48kHz,
Stereo ADC On, OSRADC = 128,
PLL Off, Stereo Analog Inputs On
Analog Supply Current
(FM Record Mode)
7.2
9.3
mA (max)
fMCLK = 12.288MHz, fS = 8kHz,
Mono ADC On, Mono DAC On,
OSRDAC = 64
Analog Supply Current
(CODEC Mode)
6.6
8.7
mA (max)
OSRADC = 128, PLL Off, MIC On,
EP On
fMCLK = 13MHz,
fPLLOUT = 12MHz, PLL On only
PLLIDD
PLL Total Active Current
From A_VDD
1.9
1.4
1.5
2.2
0.4
2.7
2
mA (max)
mA (max)
mA
From D_VDD
HPIDD
LSIDD
Headphone Quiescent Current
Loudspeaker Quiescent Current
Microphone Quiescent Current
Stereo HP On only
LS On only
mA
MICIDD
Mono MIC
mA
fS = 48kHz, Stereo
From A_VDD
ADCIDD
DACIDD
ADC Total Active Current
DAC Total Active Current
5.8
1.3
mA
mA
From D_VDD
fS = 48kHz, Stereo
From A_VDD
3.1
1
mA
mA
From D_VDD
Mono/Auxiliary Input Amplifier
Quiescent Current
Mono and AUX Input Amplifiers
enabled
AUXINIDD
0.6
mA
AUXOUT enabled
Earpiece Mode
0.4
1.1
mA
mA
Auxiliary Output Amplifier Quiescent
Current
AUXOUTIDD
LOUDSPEAKER AMPLIFIER
PO = 970mW, RL = 8Ω,
LS_VDD = 4.2V
LSEFF
Loudspeaker Efficiency
93
%
%
PO = 300mW, f = 1kHz,
RL = 8Ω, Mono Input Signal
THD+N
Total Harmonic Distortion + Noise
0.03
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LM49352
Typical Limit
(Note 6) (Note 7)
RL = 8Ω, f = 1kHz, THD+N = 1%, Mono Input Signal
Units
(Limit)
Symbol
Parameter
Conditions
LS_VDD = 5V
LS_VDD = 4.2V
LS_VDD = 3.3V
1.4
970
590
W
mW
510
mW (min)
PO
Output Power
RL = 4Ω, f = 1kHz, THD+N = 1%,
Mono Input Signal
LS_VDD = 5V
2.4
1.65
980
W
W
LS_VDD = 4.2V
LS_VDD = 3.3V
mW
VRIPPLE = 200mVP-P
fRIPPLE = 217Hz
Mono Input Terminated
VREF = 1.0μF, Input Referred
LS Gain = 12dB
75
74
60
dB (min)
dB
PSRR
Power Supply Rejection Ratio
VRIPPLE = 200mVP-P
fRIPPLE = 217Hz
From DAC, DAC gain = 0dB
Reference = VOUT (1% THD+N )
Mono gain = 0dB, A-weighted
Mono Input Terminated, LS Gain = 8dB
LS_VDD = 4.2V
LS_VDD = 3.3V
95
93
dB
88
dB (min)
SNR
Signal-to-Noise Ratio
Reference = VOUT (1% THD+N )
DAC Gain = 0dB, A-weighted
fS = 48kHz, OSR = 128
LS Gain = 8dB
LS_VDD = 4.2V
LS_VDD = 3.3V
91
89
dB
dB
eOS
VOS
Mono gain = 0dB, A-weighted,
Mono Input Terminated, Input Referred
Output Noise
Offset Voltage
43
10
µV
Mono gain = 0dB, from Mono Input
50
mV (max)
HEADPHONE AMPLIFIERS
PO = 15mW, f = 1kHz,
RL = 32Ω
THD+N Total Harmonic Distortion + Noise
0.025
0.1
% (max)
Stereo Analog Input Signal
RL = 32Ω, f = 1kHz, THD+N = 1%,
Stereo Analog Input Signal, In phase
HP_VDD = 2.8V
65
24
mW
HP_VDD = 1.8V
20
mW (min)
PO
Headphone Output Power
RL = 16Ω, f = 1kHz, THD+N = 1%,
Stereo Analog Input Signal, In phase
HP_VDD = 2.8V
73
24
mW
mW
HP_VDD = 1.8V
15
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LM49352
Typical Limit
(Note 6) (Note 7)
Units
(Limit)
Symbol
Parameter
Conditions
VRIPPLE = 200mVP-P, fRIPPLE = 217Hz
Mono Input Terminated, Mono gain = 0dB
VREF = 1.0μF, Mono Differential Input Mode,
Ripple applied to AVDD only
100
88
85
dB (min)
dB
PSRR
Power Supply Rejection Ratio
Ripple applied to AVDD and HPVDD
VRIPPLE = 200mVP-P, fRIPPLE = 217Hz
From DAC, DAC gain = 0dB
Ripple applied to AVDD
81
98
dB
HPVDD, and DVDD
Reference = VOUT (1% THD+N )
Gain = 0dB, A-weighted
Stereo Inputs Terminated
93
93
dB (min)
SNR
Signal to Noise Ratio
Output Noise
Reference = VOUT (1% THD+N)
Gain = 0dB,
97
dB (min)
A-weighted, I2S Input = Digital Zero
Gain = 0dB, A-weighted,
Stereo Inputs Terminated
11
12
µV
µV
eOS
Gain = 0dB, A-weighted,
I2S Input = Digital Zero
PO = 7.5mW, f = 1kHz,
RL = 32Ω
XTALK
Crosstalk
85
dB
Stereo Analog Input Signal
Channel-to-Channel Gain Matching
ΔACH-CH
0.03
1.4
dB
AUX Gain = 0dB
From mono Input
6
6
mV (max)
VOS
Output Offset Voltage
DAC Gain = 0dB
From DAC Input, fMCLK = 12.288MHz
1.6
mV (max)
%
AUXILIARY OUTPUT/EARPIECE AMPLIFIER
AUX_LINE_OUT, f = 1kHz
From Mono In
0.002
RL = 5kΩ, VOUT = 1VRMS
THD+N
Total Harmonic Distortion
Output Power
Earpiece mode, f = 1kHz
From Mono In
0.02
58
%
mW (min)
dB
RL = 32Ω BTL, POUT = 20mW
Earpiece mode, f = 1kHz
POUT
50
90
RL = 32Ω BTL, THD+N = 1%
VRIPPLE = 200mVP-P, fRIPPLE = 217Hz
Mono Input terminated, CREF = 1.0μF
AUX_LINE_OUT
100
PSRR
SNR
Power Supply Rejection Ratio
VRIPPLE = 200mVP-P, fRIPPLE = 217Hz
Mono Input terminated, CREF = 1.0μF
Earpiece mode,
–6dB cut enabled
100
dB
Gain = 0dB, VREF = VOUT (1% THD+N)
A-weighted, Mono Input Terminated
Gain = 0dB, VREF = VOUT (1% THD+N)
A-weighted, Mono Input Terminated
Signal to Noise Ratio
Output Noise
105
7
dB
∈
μV
OUT
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16
LM49352
Typical Limit
(Note 6) (Note 7)
Units
(Limit)
Symbol
Parameter
Conditions
MONO gain = 0dB, From Mono Input
AUX_LINE_OUT
4
mV
VOS
Output Offset Voltage
Turn-On time
Gain = 0dB, From Mono Input
Earpiece mode
4
12
mV (max)
ms
TWU
PMC Clock = 300kHz
28
STEREO ADC
Mono Differential Input
VIN = 1VRMS, f = 1kHz
Gain = 0dB, fS = 48kHz
ADC Total Harmonic Distortion +
Noise
THD+NADC
0.007
220
%
HPF On, fS = 48kHz
Lower -3dB Point
Hz
PBADC
ADC Passband
ADC Ripple
0.41*fS
0.1
HPF On, Upper -3dB Point
OSRDAC = 128
kHz
dB
RADC
Reference = VOUT (0dBFS )
Gain = 6dB,
98
dB
A-weighted From MIC, fS = 8kHz
SNRADC
ADC Signal to Noise Ratio
ADC Full Scale Input Level
Reference = VOUT (0dBFS )
Gain = 0dB,
A-weighted From Stereo Input,
fS = 48kHz
97
dB
ADCLEVEL
VRMS
1.6
STEREO DAC
I2S Input, AUXOUT, OSRDAC = 64
VIN = 500mFFSRMS, f = 1kHz
Gain = 0dB
DAC Total Harmonic Distortion +
Noise
THD+NDAC
0.01
%
DACLEVEL
RDAC
DAC Full Scale Output Level
DAC Ripple
VRMS
dB
1.08
0.1
PBDAC
DAC Passband
Upper –3dB Point
0.45*fS
103
kHz
dB
SNRDAC
DAC Signal to Noise Ratio
fS = 48kHz, A-weighted, AUXOUT
VOLUME CONTROL
Minimum Gain
Maximum Gain
Minimum Gain
Maximum Gain
Minimum Gain
Maximum Gain
Minimum Gain
Maximum Gain
Minimum Gain
Maximum Gain
Minimum Gain
Maximum Gain
Minimum Gain
Maximum Gain
–46.5
18
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
VCRAUX
VCRMONO
VCRDAC
VCRADC
VCRMIC
VCRLS
Stereo Input Volume Control Range
MONO Input Volume Control Range
DAC Volume Control Range
–46.5
18
–76.5
18
–76.5
18
ADC Volume Control Range
6
MIC Volume Control Range
36
0
Loudspeaker Amplifier Volume
Control Range
12
–18
0
Headphone Amplifier Volume
Control Range
VCRHP
SSLS
Loudspeaker Amplifier Volume
Control Stepsize
4
Headphone Amplifier Volume
Control Stepsize
Refer to
Table 19
SSHP
dB
dB
SSAUX
AUX Input Volume Control Stepsize
1.5
17
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LM49352
Typical Limit
(Note 6) (Note 7)
Units
(Limit)
Symbol
Parameter
Conditions
MONO Input Volume Control
Stepsize
SSMONO
1.5
dB
SSDAC
SSADC
SSMIC
SVAUX
SVMONO
SVMIC
DAC Volume Control Stepsize
ADC Volume Control Stepsize
MIC Volume Control Stepsize
AUX Volume Setting Variation
MONO Volume Setting Variation
MIC Volume Setting Variation
1.5
1.5
2
dB
dB
dB
±1
±1
±1
dB (max)
dB (min)
dB (max)
ANALOG INPUTS
AUX Gain = 18dB
10
38
64
10
38
64
50
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
AUX_RIN
Auxiliary Input Impedance
AUX Gain = 0dB
AUX Gain = –46.5dB
MONO Gain = 18dB
MONO Gain = 0dB
MONO Gain = –46.5dB
All MIC gain settings
MONO_RIN
MIC_RIN
Mono Input Impedance
Microphone Input Impedance
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower.
Note 4: Human body model, applicable std. JESD22-A114C.
Note 5: Machine model, applicable std. JESD22-A115-A.
Note 6: Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis.
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18
11.0 Typical Performance Characteristics
Class D Loudspeaker Amplifier Efficiency
vs Output Power
DAC Frequency Response
fS = 48kHz
Blue >> OSR = 64
THD+N < 10%, RL = 8Ω
Green >> LSVDD = 3.3V
Gray >> LSVDD = 4.2V
Blue >> LSVDD = 5V
Light Blue >> OSR = 128
100
90
80
70
60
50
40
30
20
10
0
300727b3
0
400
800
1200 1600
2000
OUTPUT POWER (mW)
300727b2
DAC Frequency Response
fS = 8kHz
DAC THD+N vs Frequency
fS = 8kHz, OSR = 128
I2S Input = 500mFFS
Blue >> OSR = 64
Light Blue >> OSR = 128
300727b5
300727b4
19
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DAC THD+N vs Frequency
fS = 8kHz, OSR = 64
DAC THD+N vs Input Level
fS = 48kHz, OSR = 64
I2S Input = 1kHz
I2S Input = 500mFFS
300727b6
300727b8
Stereo Audio ADC Frequency Response
fS = 48kHz, OSR = 64
From MIC, MIC Gain = 6dB, CIN = 1µF
Stereo Audio ADC Frequency Response
fS = 8kHz, OSR = 128
From MIC, MIC Gain = 6dB, CIN = 1µF
300727b9
300727c0
Mono Voice ADC Frequency Response
fS = 48kHz, OSR = 128
From MIC, MIC Gain = 6dB, CIN = 1µF
Mono Voice ADC Frequency Response
fS = 8kHz, OSR = 128
From MIC, MIC Gain = 6dB, CIN = 1µF
300727c1
300727c2
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20
Stereo Audio HPF ADC Frequency Response
fS = 48kHz, OSR = 128
From MONO/AUX, MONO>AUX Gain = 0dB, CIN = 1µF
Blue >> No HPF
Mono Voice HPF ADC Frequency Response
fS = 48kHz, OSR = 128
From MIC, MIC Gain = 6dB, CIN = 1µF
Gray >> No HPF
Light Blue >> HPF Mode = '101'
Green >> HPF Mode = '110'
Light Green >> HPF Mode = '111'
Blue >> HPF Mode = '000'
Light Blue >> HPF Mode = '001'
Green >> HPF Mode = '010'
Light Green >> HPF Mode = '011'
Yellow >> HPF Mode = '100'
300727c3
300727c4
Mono Voice HPF ADC Frequency Response
fS = 8kHz, OSR = 128
ADC THD+N vs Frequency
fS = 48kHz, OSR = 128
From MONO/AUX, MONO/AUX Gain = 6dB, VIN = 1VRMS
From MIC, MIC Gain = 6dB, CIN = 1µF
Gray >> No HPF
Blue >> HPF Mode = '000'
Light Blue >> HPF Mode = '001'
Green >> HPF Mode = '010'
Light Green >> HPF Mode = '011'
Yellow >> HPF Mode = '100'
300727c5
300727e9
21
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ADC THD+N vs Frequency
fS = 48kHz, OSR = 128
From MIC, MIC Gain = 6dB, VIN = 500mVRMS
ADC THD+N vs Input Voltage
fS = 48kHz, OSR = 128
From MONO/AUX, MONO/AUX Gain = 0dB, fIN = 1kHz
300727c6
300727c7
ADC THD+N vs Input Voltage
fS = 48kHz, OSR = 128
From MIC, MIC Gain = 6dB, VIN = 1kHz
Loudspeaker THD+N vs Input Voltage
From MONO/AUX Input, MONO/AUX Gain = 0dB
LS Gain = 8dB, LSVDD = 3.3V, POUT = 300VRMS, RL = 8Ω
300727c9
300727c8
Loudspeaker THD+N vs Input Voltage
From MONO/AUX Input, MONO/AUX Gain = 0dB
LS Gain = 8dB, LSVDD = 4.2V, POUT = 300VRMS, RL = 8Ω
Loudspeaker THD+N vs Input Voltage
From MONO/AUX Input, MONO/AUX Gain = 0dB
LS Gain = 8dB, LSVDD = 5V, POUT = 300VRMS, RL = 8Ω
300727d0
300727d1
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22
Loudspeaker THD+N vs Input Voltage
From MONO/AUX Input, MONO/AUX Gain = 0dB
LS Gain = 8dB, LSVDD = 3.3V, POUT = 300VRMS, RL = 4Ω
Loudspeaker THD+N vs Output Power
From MONO/AUX Input, MONO/AUX Gain = 0dB
LS Gain = 8dB, fIN = 1kHz, RL = 8Ω
Blue >> LSVDD = 3.3V
Light Blue >> LSVDD = 4.2V
Green >> LSVDD = 5V
300727d2
300727f0
Loudspeaker THD+N vs Output Power
fS = 48kHz, OSR = 128
Loudspeaker PSRR vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, LS Gain = 12dB
LSVDD = 3.3V, VRIPPLE = 200mVPP, Input Referred
From MONO/AUX Input, MONO/AUX Gain = 0dB
LS Gain = 8dB, fIN = 1kHz, RL = 4Ω
Blue >> LSVDD = 3.3V
Light Blue >> LSVDD = 4.2V
Green >> LSVDD = 5V
300727d3
300727f1
23
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Loudspeaker PSRR vs Frequency
fS = 48kHz, OSR = 128
Loudspeaker PSRR vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, LS Gain = 12dB
LSVDD = 5V, VRIPPLE = 200mVPP, Input Referred
MONO/AUX Input, MONO/AUX Gain = 0dB, LS Gain = 12dB
LSVDD = 4.2V, VRIPPLE = 200mVPP, Input Referred
300727d5
300727d4
Headphone PSRR vs Frequency
HeadphoneTHD+N vs Frequency
MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 3.3V, POUT = 15mW, RL = 32Ω
Stereo In Phase
DAC Input, DAC Gain = 0dB, LS Gain = 12dB
LSVDD = 3,3V, AVDD = 3.3V, DVDD = 1.8V, VRIPPLE
200mVPP
Ripple on LSVDD, AVDD, DVDD, Input Referred
=
300727d7
300727d6
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24
Headphone THD+N vs Frequency
MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 2.8V, POUT = 15mW, RL = 32Ω
Stereo In Phase
Headphone THD+N vs Frequency
MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 1.8V, POUT = 15mW, RL = 16Ω
Stereo In Phase
300727d9
300727d8
Headphone THD+N vs Frequency
MONO/AUX, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 2.8V, POUT = 15mW, RL = 16Ω
Stereo in Phase
Headphone THD+N vs Output Power
MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB
Stereo In Phase, fIN = 1kHz, RL = 32Ω
Blue >> HPVDD = 1.8V
Light Blue >> HPVDD = 2.8V
300727e0
300727r0
25
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Headphone THD+N vs Output Power
Headphone PSRR vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 1.8V, AVDD = 3.3V, VRIPPLE = 200mVPP
Ripple on HPVDD, AVDD
Stereo In Phase, fIN = 1kHz, RL = 16Ω
Blue >> HPVDD = 1.8V
Light Blue >> HPVDD = 2.8V
300727e1
300727q9
Headphone PSRR vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB
HPVDD = 1.8V, AVDD = 3.3V, VRIPPLE = 200mVPP
Ripple on AVDD only
Headphone PSRR vs Frequency
DAC Input, DAC Gain = 0dB, HP Gain = 0dB
HPVDD = 1.8V, AVDD = 3.3V, DVDD = 1.8V, VRIPPLE
200mVPP
=
Ripple on HPVDD, AVDD, DVDD
300727e2
300727e3
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26
Headphone Crosstalk vs Frequency
Earpiece THD+N vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, HP Gain = 0dB MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB
HPVDD = 1.8V, AVDD = 3.3V, POUT = 15mW, RL = 32Ω
AVDD = 3.3V, POUT = 20mW, RL = 32Ω
Earpiece Mode
300727e4
300727e5
Earpiece THD+N vs Output Power
Earpiece PSRR vs Frequency
MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = –6dB
AVDD = 3.3V, VRIPPLE = 200mVPP, Earpiece Mode
AVDD = 3.3V, fIN = 1kHz, RL = 32Ω
Earpiece Mode
300727e6
300727q8
27
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Auxiliary Output THD+N vs Frequency
Auxiliary Output THD+N vs Output Voltage
MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB
AVDD = 3.3V, VOUT = 1VRMS, RL = 5kΩ
AVDD = 3.3V, fIN = 1kHz, RL = 5kΩ
AUXOUT Mode
AUXOUT Mode
300727f2
300727e7
Auxiliary Output PSRR vs FRequency
MONO/AUX Input, MONO/AUX Gain = 0dB, EP Gain = 0dB
AVDD = 3.3V, VRIPPLE = 200mVPP, AUXOUT Mode
300727e8
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28
after START condition and free after STOP condition. During
data transmission, I2C master can generate repeated START
conditions. First START and repeated START conditions are
equivalent, function-wise.
12.0 System Control
Method 1. I2C Compatible Interface
12.1 I2C SIGNALS
In I2C mode the LM49352 pin SCL is used for the I2C clock
SCL and the pin SDA is used for the I2C data signal SDA. Both
these signals need a pull-up resistor according to I2C speci-
fication. The I2C slave address for LM49352 is 00110102.
12.2 I2C DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when SCL is LOW.
30072724
FIGURE 7. I2C Start and Stop Conditions
12.4 TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9th clock pulse, signifying an acknowledge. A
receiver which has been addressed must generate an ac-
knowledge after each byte has been received.
30072723
FIGURE 6. I2C Signals: Data Validity
After the START condition, the I2C master sends a chip ad-
dress. This address is seven bits long followed by an eight bit
which is a data direction bit (R/W). The LM49352 address is
00110102. For the eighth bit, a “0” indicates a WRITE and a
“1” indicates a READ. The second byte selects the register to
which the data will be written. The third byte contains data to
write to the selected register.
12.3 I2C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I2C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from LOW
to HIGH while SCL is HIGH. The I2C master always generates
START and STOP bits. The I2C bus is considered to be busy
30072725
FIGURE 8. I2C Chip Address
29
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Register changes take effect at the SCL rising edge during
the last ACK from slave.
30072726
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by slave)
rs = repeated start
FIGURE 9. Example I2C Write Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle
waveform.
30072727
FIGURE 10. Example I2C Read Cycle
30072728
FIGURE 11. I2C Timing Diagram
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30
12.5 I2C TIMING PARAMETERS
Symbol
Limit
Typ
Parameter
Units
Min
0.6
Max
1
2
3
4
Hold Time (repeated) START Condition
Clock Low Time
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
1.3
Clock High Time
600
600
Setup Time for a Repeated START Condition
Data Hold Time (Output direction, delay generated by LM49352)
Data Hold Time (Input direction, delay generated by the Master)
Data Setup Time
50
(Note 8)
5
50
6
7
100
Rise Time of SDA
300
300
8
Fall Time of SDA
9
Set-up Time for STOP condition
Bus Free Time between a STOP and a START Condition
600
1.3
10
Note 8: Data guaranteed by fall time.
31
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13.0 Device Register Map
TABLE 1. Device Register Map
Address
Register
7
6
5
4
3
2
1
0
BASIC SETUP
PMC
CHIP
PORT2
PORT1
MCLK
OVR
OSC
ENB
PLL
CHIP
PLL_P2
ENB
0x00h
0x01h
0x02h
SETUP
ACTIVE
CLK OVR CLK OVR
ENB
ENABLE
PMC
CLOCKS
PMC_CLK_SEL
PMC
CLK_DIV
PMC_CLK_DIV(R)
PLL
0x03h
0x04h
0x05h
PLL_CLK_SEL
PLL M
PLL N
PLL M
PLL N
PLL
N_MOD
0x06h
PLL P2[8] PLL P1[8]
PLL N_MOD
0x07h
0x08h
PLL P
PLL P1 [7:0]
PLL P2[7:0]
PLL P2
ANALOG MIXER
0x10h
0x11h
CLASSD
HEAD
AUX_LS
MONO_LS
DACL_LS DACR_LS
DACL_HPL DACR_HPL
MONO
_HPL
AUX_HPL
PHONESL
HEAD
MONO
_HPR
DACL
_HPR
DACR
_HPR
0x12h
0x13h
0x14h
0x15h
AUX_HPR
AUX_AUX
PHONESR
MONO
_AUX
DACR
_AUX
AUX_OUT
MIC_AUX DACL_AUX
OUTPUT
OPTIONS
AUX_LINE AUX_NEG
_OUT
LS_LEVEL
LR_HP_LEVEL
DACL
RSVD
_6dB
MONO
_ADCL
AUX
_ADCR
DACR
ADC
MIC_ADCL MIC_ADCR
_ADCL
MIC_LEVEL
_ADCR
0x16h
0x18h
MIC_LVL
MUTE
SE/DIFF
AUXL_LVL
SE/DIFF
SE/DIFF
AUX_LEVEL
AUXL_MO
NO_IN
0x19h
0x1Bh
MONO_LV
MONO_LEVEL
HP
_SENSE
HP SENSE HP SENSE
HP
SENSE_D
HP SENSE
MONO
_AUX_D
_AUX
ADC
0x20h
0x21h
ADC BASIC DSPONLY
ADC_CLK_SEL
MUTE_R
MUTE_L
ADC_OSR
ADC
CLOCK
ADC_CLK_DIV (T)
STEREO
ADC
_MIXER
0x23h
ADC_MIX_LEVEL_R
ADC_MIX_LEVEL_L
DAC_OSR
_LINK
DAC
DAC
0x30h
0x31h
DSPONLY
_BASIC
DAC_CLK_SEL
MUTE_R
DAC_CLK_DIV (S)
DIGITAL MIXER
MUTE_L
DAC
_CLOCK
0x40h
0x41h
0x42h
0x43h
IPLVL1
IPLVL2
PORT2_RX_R_LVL
INTERP_L_LVL
PORT2_RX_L_LVL
INTERP_R_LVL
PORT1_RX_R_LVL
ADC_R_LVL
R_SEL
PORT1_RX_L_LVL
ADC_L_LVL
L_SEL
OPPORT1
OPPORT2
MONO
MONO
SWAP
SWAP
R_SEL
L_SEL
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32
Address
0x44h
Register
OPDAC
OPDECI
7
6
5
4
3
2
1
0
SWAP
ADCR
PORT2R
PORT1R
ADCL
PORT2L
PORT1L
0x45h
MXRCLK_SEL
AUDIO PORT 1
R_SEL
L_SEL
STEREO
_SYNC
_MODE
STEREO
_SYNC
_PHASE
0x50h
BASIC
CLK_PH
SYNC_MS CLK_MS
TX_ENB
RX_ENB
STEREO
0x51h
0x52h
CLK_GEN1
CLK_GEN2
CLK_SEL
HALF_CYCLE_DIVDER
SYNTH
_DENOM
SYNTH_NUM
SYNC_RATE
RX_WIDTH
SYNC
_GEN
0x53h
0x54h
SYNC_WIDTH(MONO MODE)
TX_WIDTH
DATA
_WIDTH
TX_EXTRA_BITS
0x55h
0x56h
RX_MODE
TX_MODE
A/ULAW COMPAND
A/ULAW COMPAND
MSB_POSITION
MSB_POSITION
RX_MODE
TX_MODE
AUDIO PORT 2
STEREO
_SYNC
_MODE
STEREO
_SYNC
_PHASE
0x60h
BASIC
CLK_PH SYNC_MS CLK_MS
TX_ENB
RX_ENB
STEREO
0x61h
0x62h
CLK_GEN1
CLK_GEN2
CLK_SEL
HALF_CYCLE_DIVDER
SYNTH_D
ENOM
SYNTH_NUM
SYNC_RATE
RX_WIDTH
SYNC
_GEN
0x63h
0x64h
SYNC_WIDTH (MONO MODE)
TX_WIDTH
DATA
_WIDTH
TX_EXTRA_BITS
0x65h
0x66h
RX_MODE
TX_MODE
A/ULAW COMPAND
A/ULAW COMPAND
MSB_POSITION
RX_MODE
TX_MODE
MSB_POSITION
EFFECTS ENGINE
ADC
ADC
ADC
PK ENB
DAC
ADC
ADC
0x70h
0x71h
ADC FX
DAC FX
SCLP ENB
DAC
EQ ENB
ALC ENB HPF_ENB
DAC
DAC
RSVD
SCLP ENB
ADC EFFECTS
EQ ENB
PK ENB
ALC ENB
0x80h
0x81h
HPF
ADC
HPF MODE
SOURCE
OVR
SOURCE
RSEL
SOURCE
LSEL
STEREO
LINK
LIMITER
ADC_SAMPLE
ALC 1
ADC
0x82h
0x83h
0x84h
0x85h
0x86h
0x87h
0x88h
NG_ENB
NOISE_FLOOR
ALC 2
ADC
ALC_TARGET_LEVEL
ATTACK_RATE
ALC 3
ADC
ALC 4
ADC
PK_DECAY_RATE
DECAY_RATE/RELEASE_RATE
HOLDTIME
ALC 5
ADC
ALC 6
ADC
MAX_LEVEL
ALC 7
ADC
MIN_LEVEL
ALC 8
33
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Address
Register
ADC L
7
6
5
4
3
2
1
0
STEREO
LINK
0x89h
ADC_L_LEVEL
ADC_R_LEVEL
LEVEL
ADC R
0x8Ah
LEVEL
0x8Bh
0x8Ch
0x8Dh
0x8Eh
0x8Fh
EQ BAND 1
EQ BAND 2
EQ BAND 3
EQ BAND 4
EQ BAND 5
LEVEL
LEVEL
LEVEL
LEVEL
LEVEL
FREQ
FREQ
FREQ
FREQ
FREQ
Q
Q
Q
SOFTCLIP
1
SOFT
KNEE
0x90h
0x91h
0x92h
THRESHOLD
RATIO
SOFTCLIP
2
SOFTCLIP
3
LEVEL
ADC EFFECT MONITORS
ADC LEFT LEVEL MONITOR
ADC RIGHT LEVEL MONITOR
0x98h
0x99h
LVLMONL
LVLMONR
SCLP
_R CLIP
SCLP
_L CLIP
EQ
_R CLIP
EQ
_L CLIP
GAIN
_R CLIP
GAIN
_L CLIP
ADC
_R CLIP
ADC
_L CLIP
0x9Ah
0x9Bh
0x9Ch
FXCLIP
SCLP_R
DISTORT
SCLP_L
SCLP_L
DISTORT
SCLP_R
DISTORT
ALCMONL
ALCMONR
ADC LEFT ALC MONITOR
ADC RIGHT ALC MONITOR
DISTORT
DAC EFFECTS
DAC
ALC 1
STEREO
LINK
0xA0h
0xA1h
0xA2h
0xA3h
0xA4h
0xA5h
0xA6h
0xA7h
0xA8h
0xA9h
LIMITER
DAC_SAMPLE
NOISE_FLOOR
DAC
NG_ENB
ALC 2
DAC
AGC_TARGET_LEVEL
ATTACK_RATE
ALC 3
DAC
ALC 4
DAC
PK_DECAY_RATE
DECAY_RATE/RELEASE_RATE
HOLDTIME
ALC 5
DAC
ALC 6
DAC
MAX_LEVEL
ALC 7
DAC
MIN_LEVEL
ALC 8
DAC L
LEVEL
DAC R
LEVEL
EQ BAND 1
EQ BAND 2
EQ BAND 3
EQ BAND 4
EQ BAND 5
STEREO
LINK
DAC_L_LEVEL
DAC_R_LEVEL
0xABh
0xACh
0xADh
0xAEh
0xAFh
LEVEL
LEVEL
LEVEL
LEVEL
LEVEL
FREQ
Q
Q
Q
FREQ
FREQ
FREQ
FREQ
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34
Address
Register
7
6
5
4
3
2
1
0
SOFTCLIP
1
SOFT
KNEE
0xB0h
THRESHOLD
SOFTCLIP
2
0xB1h
0xB2h
RATIO
LEVEL
SOFTCLIP
3
DAC EFFECT MONITORS
0xB8h
0xB9h
LVLMONL
LVLMONR
DAC LEFT LEVEL MONITOR
DAC RIGHT LEVEL MONITOR
SCLP
_R CLIP
SCLP
_L CLIP
EQ
_R CLIP
EQ
GAIN
_R CLIP
GAIN
_L CLIP
0xBAh
0xBBh
0xBCh
FXCLIP
RSVD
_L CLIP
RSVD
SCLP_R
DISTORT
SCLP_L
SCLP_L
DISTORT
SCLP_R
DISTORT
ALCMONL
ALCMONR
DAC LEFT ALC MONITOR
DAC RIGHT ALC MONITOR
DISTORT
GPIO
0xE0h
0xE1h
GPIO1
GPIO2
GPIO_RX
GPIO_TX
GPIO_MODE
TEMP
SHORT
SPREAD SPECTRUM
SOFT
RSVD
0xF0h
RESET
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
_RESET
SS
_DISABLE
0xF1h
0xFEh
SS
FORCE
CPFORCE DACREF
RSVD
Unless otherwise specified, the default values of the I2C reg-
isters is 0x00h.
TABLE 2. Nonzero I2C Default Registers
Address
0x02h
0x30h
0x31h
0x84h
0x85h
0x86h
0x87h
0x89h
0x8Ah
0xA3h
0xA4h
0xA5h
0xA6h
0xA8h
0xA9h
0xF0h
Register
Default Data Value
0x50h
PMC_CLK_DIV
DAC_BASIC
DAC_CLOCK
ADC_ALC_4
ADC_ALC_5
ADC_ALC_6
ADC_ALC_7
ADC_L_LEVEL
ADC_R_LEVEL
DAC_ALC_4
DAC_ALC_5
DAC_ALC_6
DAC_ALC_7
DAC_L_LEVEL
DAC_R_LEVEL
RESET
0x02h
0x03h
0x0Ah
0x0Ah
0x0Ah
0x1Fh
0x33h
0x33h
0x0Ah
0x0Ah
0x0Ah
0x33h
0x33h
0x33h
0x02h
35
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14.0 Basic PMC Setup Register
This register is used to control the LM49352's Basic Power Management Setup:
TABLE 3. PMC_SETUP (0x00h)
Bits
Field
Description
When this bit is set the power management will enable the MCLK I/O or internal
oscillator1. It will then use this clock to sequence the enabling of the analog references and
bias points. When this bit is cleared the PMC will bring the analog down gently and disable
the MCLK or oscillator.
0
CHIP_ENABLE
CHIP _ENABLE
Chip Status
Turn Chip Off
Turn Chip On
0
1
This enables the PLL.
PLL_ENABLE
PLL Status
PLL Off
1
2
PLL_ENB
0
1
PLL On
This enables the P2 output of the PLL.
PLL_P2ENB
PLL P2 Status
PLL P2 Off
PLL_P2ENB
0
1
PLL P2 On
This enables the internal 300kHz Oscillator. For analog only chip modes, the oscillator can
be used instead of an external system clock to drive the chip's power management (PMC).
OSC_ENABLE
Oscillator Status
Oscillator Off
Oscillator On
3
OSC_ENB
0
1
This forces the MCLK input to enable, regardless of requirement. If set, the audio ports and
digital mixer can be activated even if the chip is in shutdown mode. This assumes that MCLK
is selected as the PMC clock source (reg 0x01h) and that there is an active clock signal
driving the MCLK pin. Setting this bit reduces power consumption, by allowing audio ports
and digital mixer to operate while the analog sections of the chip are powered down.
4
5
MCLK_OVR
MCLK_OVR
Comment
0
1
I/O control is automatic
MCLK input forced on.
This forces the clock input of Audio Port 1 input to enable, regardless of other port settings.
PORT1_CLK_OVR
Comment
PORT1_CLK_OVR
0
1
I/O control is automatic
PORT_CLK input forced on
This forces the clock input of Audio Port 2 input to enable, regardless of other port settings.
PORT2_CLK_OVR
Comment
6
7
PORT2_CLK_OVR
CHIP_ACTIVE
0
1
I/O control is automatic
PORT_CLK input forced on
This bit is used to readback the enable status of the chip.
1. If the PMC is set to operate from one of the audio ports then it will wait for the port to be enabled or the relevant override bit to
be set, forcing the port clock input to enable.
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36
15.0 PMC Clocks Register
This register is used to control the LM49352's Basic Power Management Clock:
TABLE 4. PMC_SETUP (0x01h)
Bits
Field
Description
This selects the source of the PMC input clock.
1:0
PMC_CLK_SEL
PMC_CLK_SEL
PMC Input Clock Source
MCLK (Default divide is 40.5)
Internal 300kHz Oscillator
DAC SOURCE CLOCK
00
01
10
11
ADC SOURCE CLOCK
16.0 PMC Clock Divide Register
This register is used to control the LM49352's Power Management Circuit Clock Divider:
TABLE 5. PMC_SETUP (0x02h)
Bits
Field
Description
7:0
PMC_CLK_DIV
This programs the half cycle divider that precedes the PMC. The PMC should run from a
300kHz clock. The default of this divider is 0x50h (divide by 40.5) to get a ≈300kHz PMC
clock from a 12MHz or 12.288MHz MCLK.
Program this divider with the required division, multiplied by 2, and subtract 1.
PMC_CLK_DIV
00000000
00000001
00000010
00000011
00000100
00000101
—
Divide by
1
1
1.5
2
2.5
3
—
11111101
11111110
11111111
126
127.5
128
37
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17.0 LM49352 Clock Network
(Refer to Figure 12)
The audio DAC and ADC operate at a clock frequency of 2*OSR*fS where OSR is the oversampling ratio and fS is the sampling
frequency of the DAC or ADC. The DAC can operate at three different OSR settings (128, 125, 64). The ADC can operate at two
different OSR settings (128, 125). For example, if the stereo DAC or ADC is set at OSR = 128, a 12.288MHz clock is required for
48kHz data. If a 12.288MHz clock is not available, then the internal PLL can be used to generate the desired clock frequency.
Otherwise, if a 12.288MHz is available, the PLL can be bypassed to reduce power consumption. The DAC clock divider or ADC
clock divider can also be used to generate the correct clock. If an 18.432 MHz clock is available, the DAC or ADC clock divider
could be set to 1.5 in order to generate a 12.288MHz clock from 18.432MHz without using a PLL.
The DAC path clock (DAC_SOURCE_CLK) and ADC path clock (ADC_SOURCE_CLK) can be driven directly by the MCLK input,
the PORT1_CLK input, the PORT2_CLK input, or PLL output.
For instances where a PLL must be used, the PLL input clock can come from three sources. The clock input to the PLL can come
from the MCLK input, the PORT1_CLK input, or the PORT2_CLK input.
The LM49352's Power Management Circuit (PMC) requires a clock that is independent from the DAC or ADC. It is recommended
to provide a ≈300kHz clock at Point C. The PMC clock divider is available to generate the correct clock to the PMC block. The
PMC clock path can be driven directly by the MCLK input, the internal 300kHz oscillator, the DAC_SOURCE_CLK, or the
ADC_SOURCE_CLK.
TABLE 6. DAC Clock Requirements
DAC Sample Rate
(kHz)
Clock Required at A
(OSR = 128)
Clock Required at A
(OSR = 125)
Clock Required at A
(OSR = 64)
Clock Required at A
(OSR = 32)
8
11.025
12
2.048 MHz
2.8224 MHz
3.072 MHz
4.096 MHz
5.6448 MHz
6.144 MHz
8.192 MHz
11.2896 MHz
12.288 MHz
24.576 MHz
2 MHz
2.75625 MHz
3 MHz
1.024 MHz
1.4112 MHz
1.536 MHz
2.048 MHz
2.8224 MHz
3.072 MHz
4.096 MHz
5.6448 MHz
6.144 MHz
12.288 MHz
0.512 MHz
0.7056 MHz
0.768 MHz
1.024 MHz
1.4112 MHz
1.536 MHz
2.048MHz
2.8224 MHz
3.072 MHz
6.144 MHz
16
4 MHz
22.05
24
5.5125 MHz
6 MHz
32
8 MHz
44.1
48
11.025 MHz
12 MHz
96
24 MHz
TABLE 7. ADC Clock Requirements
ADC Sample Rate
Clock Required at B
(OSR = 128)
Clock Required at B
(kHz)
(OSR = 125)
8
2.048 MHz
2.8224 MHz
3.072 MHz
4.096 MHz
5.6448 MHz
6.144 MHz
8.192 MHz
11.2896 MHz
12.288 MHz
2 MHz
11.025
12
2.75625 MHz
3 MHz
16
4 MHz
22.05
24
5.5125 MHz
6 MHz
32
8 MHz
44.1
48
11.025 MHz
12 MHz
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38
30072713
FIGURE 12. Internal Clock Network
39
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18.0 PLL Setup Registers
30072730
FIGURE 13. PLL Loop
The LM49352 contains a PLL for flexible operation of its dual audio ports. The PLL has a P1 and P2 output divider thereby allowing
the PLL to generate two distinct clock outputs. The equations for the PLL's generated output clocks are as follows:
fOUT1 = (fIN . N / M . P1)
fOUT2 = (fIN . N / M . P2)
where:
N = PLL_N + PLL_N_MOD
M = (PLL_M + 1) / 2
P1 = (PLL_P1 + 1) / 2
P2 = (PLL_P2 + 1) / 2
The VCO frequency and comparison frequencies are as follows:
fVCO = fOUT.P
fCOMP = fIN/M
Keep fVCO between 140MHz to 240MHz and keep fCOMP between 700KHz to 5MHz.
TABLE 8. PLL Settings for Common System Clock Frequencies
fIN (MHz)
12
fOUT (Hz)
12288000
12287970
12288000
12288000
12288000
12288000
12288000
12288000
12288000
12288000
11289600
11289600
11289603
11289600
M
N
N_MOD
P
Error (Hz)
2.5
32
0
26
0
12.5
12
0
–30
0
13
15.5
12.5
13.5
3.5
175
128
128
32
14.4
16.2
16.8
19.2
19.68
19.8
26
12
0
12.5
12.5
12
0
0
0
12.5
20.5
16.5
32.5
22.5
12.5
10
96
0
0
160
128
192
128
147
147
144
147
0
12.5
12.5
12.5
12.5
12.5
16
0
0
0
0
0
27
0
0
12
0
0
12.288
13
0
0
9
19
0
18.5
15
+3
0
14.4
12.5
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40
fIN (MHz)
16.2
16.8
19.2
19.68
19.8
26
fOUT (Hz)
11289600
11289600
11289600
11289600
11289600
11289602.1
12289600
12000000
12000000
12000000
12000000
12000000
12000000
12000000
12000000
12000000
12000000
12000000
11025000
11025000
11025000
11025000
11025000
11025000
11025000
11025000
11025000
11025000
11025000
1102500
M
22.5
12.5
20
N
N_MOD
P
12.5
15
Error (Hz)
196
126
147
147
196
144
196
195
125
102
68
0
0
0
0
0
0
0
2.1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
12.5
12.5
12.5
18
20.5
27.5
18.5
37.5
10.5
8
0
0
19
0
27
12.5
17.5
16
11.2896
12.288
13
0
0
6.5
4.5
6
0
17
13.5
14.4
16.2
16.8
19.2
19.68
19.8
26
0
17
85
0
17
13.5
7
170
85
0
17
0
17
8
85
0
17
20.5
16.5
6.5
8
200
170
36
0
16
0
17
0
12
11.2896
12
125
147
114
96
0
16
10
0
16
12.288
13
8
27
15
0
16
6.5
10
17.5
18
13.5
14.4
16.2
16.8
19.2
19.68
19.8
26
147
49
4
0
16
4
49
0
18
16
189
147
189
147
27
0
18
16
0
16
16
0
18
16
0
16.5
13
5
18
TABLE 9. PLL_CLOCK_SOURCE (0x03h)
Description
This selects the source of the input clock to the PLL.
Bits
Field
PLL_CLK_SEL
1:0
PLL_CLK_SEL
PLL Input Clock Source
00
01
10
11
MCLK
PORT1_CLK
PORT2_CLK
RESERVED
41
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TABLE 10. PLL_M (0x04h)
Description
Bits
Field
6:0
PLL_M
This programs the PLL's M divider to divide from 1 to 64.
PLL_M
000000
000001
000010
000011
000100
000101
—
PLL Input Divider Value
1
1
1.5
2
2.5
3
—
63
63.5
64
1111101
1111110
1111111
TABLE 11. PLL_N (0x05h)
Bits
Field
Description
7:0
PLL_N
This programs the PLL N divider to divide from 1 to 250.
PLL_N
00000000 to 00001010
00001011
Feedback Divider Value
10
11
00001100
12
00001101
13
00001110
14
00001111
15
—
—
11111000
248
249
250
11111001
11111010 to 11111111
TABLE 12. PLL_N_MOD (0x06h)
Bits
Field
Description
4:0
PLL_N_MOD
This programs the sigma-delta modulator in the PLL.
PLL_N_MOD
00000
00001
00010
00011
00100
00101
—
Fractional Part of N
0
1/32
2/32
3/32
4/32
5/32
—
11101
11110
11111
20/32
30/32
31/32
5
6
PLL_P1[8]
PLL_P2[8]
This sets the MSB of the 1st P Divider on the PLL which is part of a standard half-cycle divider
control.
This sets the MSB of the 2nd P Divider on PLL which is part of a standard half-cycle divider
control.
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42
TABLE 13. PLL_P1 (0x07h)
Description
Bits
Field
7:0
PLL_P1[7:0]
This programs the 8 LSBs of the PLL's P1 Divider. These LSBs combine with PL1_P1[8] which
allows the P1 divider to divide by up to 256.
PLL_P1 [8:0]
000000000
000000001
000000010
000000011
000000100
000000101
—
P1 Divider Value
1
1
1.5
2
2.5
3
—
111111101
111111110
111111111
255
255.5
256
TABLE 14. PLL_P2 (0x08h)
Bits
Field
Description
7:0
PLL_P2[7:0]
This programs 8 LSBs of the PLL's P2 Divider. These LSBs combine with PLL_P2[8] which
allows the P2 divider to divide by up to 256.
PLL_P2 [8:0]
000000000
000000001
000000010
000000011
000000100
000000101
—
P2 Divider Value
1
1
1.5
2
2.5
3
—
111111101
111111110
111111111
255
255.5
256
43
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19.0 Analog Mixer Control Registers
This register is used to control the LM49352's Analog Mixer:
TABLE 15. CLASS_D_OUTPUT (0x10h)
Description
Bits
0
Field
DACR_LS
DACL_LS
RSVD
The right DAC output is added to the loudspeaker output.
The left DAC output is added to the loudspeaker output.
Reserved
1
2
3
RSVD
Reserved
4
MONO_LS
AUX_LS
The MONO input is added to the loudspeaker output.
The AUX input is added to the loudspeaker output.
5
Class D Loudspeaker Amplifier
The LM49352 features a filterless modulation scheme. The differential outputs of the device switch at 300kHz from VDD to GND.
When there is no input signal applied, the two outputs (LS+ and LS-) switch with a 50% duty cycle, with both outputs in phase.
Because the outputs of the LM49352 are differential, the two signals cancel each other. This results in no net voltage across the
speaker, thus there is no load current during an idle state, conserving power.
With an input signal applied, the duty cycle (pulse width) of the LM49352 outputs changes. For increasing output voltages, the duty
cycle of LS+ increases, while the duty cycle of LS- decreases. For decreasing output voltages, the converse occurs, the duty cycle
of LS- increases while the duty cycle of LS+ decreases. The difference between the two pulse widths yields the differential output
voltage.
Spread Spectrum Modulation
The LM49352 features a fitlerless spread spectrum modulation scheme that eliminates the need for output filters, ferrite beads or
chokes. The switching frequency varies by ±30% about a 300kHz center frequency, reducing the wideband spectral content,
improving EMI emissions radiated by the speaker and associated cables and traces. Where a fixed frequency class D exhibits
large amounts of spectral energy at multiples of the switching frequency, the spread spectrum architecture of the LM49352 spreads
that energy over a larger bandwidth. The cycle-to-cycle variation of the switching period does not affect the audio reproduction or
efficiency.
Class D Power Dissipation and Efficiency
In general terms, efficiency is considered to be the ratio of useful work output divided by the total energy required to produce it
with the difference being the power dissipated, typically, in the IC. The key here is “useful” work. For audio systems, the energy
delivered in the audible bands is considered useful including the distortion products of the input signal. Sub-sonic (DC) and super-
sonic components (>22kHz) are not useful. The difference between the power flowing from the power supply and the audio band
power being transduced is dissipated in the LM49352 and in the transducer load. The amount of power dissipation in the LM49352's
class D amplifier is very low. This is because the ON resistance of the switches used to form the output waveforms is typically less
than 0.25Ω. This leaves only the transducer load as a potential "sink" for the small excess of input power over audio band output
power. The LM49352 dissipates only a fraction of the excess power requiring no additional PCB area or copper plane to act as a
heat sink.
EMI/RFI Filtering
If system level PCB layout constraints require the LM49352’s Class D output bumps to be placed far away from the speaker or the
Class D output traces to be routed near EMI/RFI sensitive components, an external EMI/RFI filter should be used. A series ferrite
bead placed close to the Class D output bumps along with a shunt capacitor to ground placed close to the ferrite bead will reduce
the EMI/RFI emissions of the Class D amplifier’s switching outputs. The ferrite bead must be rated with a current rating high enough
to properly drive the loudspeaker. The ferrite bead that is rated for 1A or greater is recommended. The DC resistance of the ferrite
bead is another important specification that must be taken into consideration. A low DC resistance will minimize any power losses
dissipated by the EMI/RFI filter thereby preserving the power efficiency advantages of the Class D amplifier. Selecting a ferrite
bead with high DC resistance will decrease output power delivered to speaker and reduce the Class D amplifier’s efficiency. The
shunt capacitor needs to have low ESR. A 10pF ceramic capacitor with a X7R dielectric is recommended as a starting point. Care
needs to be taken to ensure that the value of the shunt capacitor does not exceed 47pF when using a low resistance ferrite bead
in order to prevent permanent damage to the low side FETs of the Class D output stage.
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44
30072732
FIGURE 14. EMI/RFI Filter for the Class D Amplifier
TABLE 16. LEFT HEADPHONE_OUTPUT (0x11h)
Description
Bits
0
Field
DACR_HPL
DACL_HPL
RSVD
The right DAC output is added to the left headphone output.
The left DAC output is added to the left headphone output.
Reserved
1
2
3
RSVD
Reserved
4
MONO_HPL
AUX_HPL
The MONO input is added to the left headphone output.
The AUX input is added to the left headphone output.
5
TABLE 17. RIGHT HEADPHONE_OUTPUT (0x12h)
Bits
0
Field
DACR_HPR
DACL_HPR
RSVD
Description
The right DAC output is added to the right headphone output.
The left DAC output is added to the right headphone output.
Reserved
1
2
3
RSVD
Reserved
4
MONO_HPR
AUX _HPR
The MONO input is added to the right headphone output.
The AUX input is added to the right headphone output.
5
Headphone Amplifier Function
The LM49352 headphone amplifier features National’s ground referenced architecture that eliminates the large DC-blocking ca-
pacitors required at the outputs of traditional headphone amplifiers. A low-noise inverting charge pump creates a negative supply
(HP_VSS) from the positive supply voltage (LS_VDD). The headphone amplifiers operate from these bipolar supplies, with the
amplifier outputs biased about GND, instead of a nominal DC voltage (typically VDD/2), like traditional amplifiers. Because there is
no DC component to the headphone output signals, the large DC-blocking capacitors (typically 220μF) are not necessary, con-
serving board space and system cost, while improving frequency response.
Charge Pump Capacitor Selection
Use low ESR ceramic capacitors (less than 100mΩ) for optimum performance.
Charge Pump Flying Capacitor (C6)
The flying capacitor (C6) affects the load regulation and output impedance of the charge pump. A C6 value that is too low results
in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C6 improves load regulation and lowers charge
pump output impedance to an extent. Above 2.2μF, the RDS(ON) of the charge pump switches and the ESR of C6 and C5 dominate
the output impedance. A lower value capacitor can be used in systems with low maximum output power requirements. Please refer
to the demonstration board schematic shown in Figure 27.
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Charge Pump Flying Capacitor (C5)
The value and ESR of the hold capacitor (C5) directly affects the ripple on CPVSS. Increasing the value of C5 reduces output ripple.
Decreasing the ESR of C5 reduces both output ripple and charge pump output impedance. A lower value capacitor can be used
in systems with low maximum output power requirements. Please refer to the demonstration board schematic shown in Figure 27.
TABLE 18. AUX_OUTPUT (0x13h)
Bits
0
Field
Description
The right DAC output is added to the AUX output.
The left DAC output is added to the AUX output.
The MIC input is added to the AUX output.
Reserved
DACR_AUX
DACL_AUX
MIC_AUX
RSVD
1
2
3
4
MONO_AUX
AUX_AUX
The MONO input is added to the AUX output.
The AUX input is added to the AUX output.
5
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46
Auxiliary Output Amplifier
The LM49352’s auxiliary output (AUXOUT) amplifier provides differential drive capability to loads that are connected across its
outputs. This results in output signals at the AUX_OUT+ and AUX_OUT- pins that are 180 degrees out of phase with respect to
each other. This effectively doubles the maximum possible output swing for a specific supply voltage when compared to single-
ended output configurations. The differential output configuration also allows the load to be isolated from ground since both the
AUX_OUT+ and AUX_OUT- pins are biased at the same DC potential. This eliminates the need for any large and expensive DC
blocking capacitors at the AUXOUT amplifier outputs. The load can then be directly connected to the positive and negative outputs
of the AUXOUT amplifier which then isolates it from any ground noise, thereby improving signal to noise ratio (SNR) and power
supply rejection ratio (PSRR).
The AUXOUT amplifier has two modes of operation. The primary mode of operation is high current drive mode (Earpiece Mode)
where the AUXOUT amplifier can be used to differentially drive a mono earpiece speaker. The secondary mode of operation is
low current drive mode where the AUXOUT amplifier operates in a power saving mode (AUX_LINE_OUT Mode) to provide a
differential output that is used as a mono differential line level input to a standalone mono differential input class D amplifier
(LM4675) for stereo loudspeaker applications.
TABLE 19. OUTPUT_OPTIONS (0x14h)
Bits
Field
Description
0
RSVD
Reserved
This sets the gain of the left and right headphone amplifiers. The gain of the left and right headphone
amplifiers are always set to the same level.
LR_HP_LEVEL
Gain (dB)
0
000
001
–1.5
–3
010
3:1
LR_HP_LEVEL
011
–6
100
–9
101
–12
–15
–18
110
111
This sets the gain of the Auxiliary output amplifier.
AUX_NEG_6dB
Gain (dB)
4
5
AUX_NEG_6dB
AUX_LINE_OUT
0
0
1
–6
This sets the Auxiliary output amplifier mode of operation.
AUX_LINE_OUT
Auxiliary Output Mode
Earpiece Amplifier
AUX_LINE_OUT
0
1
This sets the gain of the Class D loudspeaker amplifier.
LS_LEVEL
Gain (dB)
00
01
10
11
0
4
7:6
LS_LEVEL
8
12
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TABLE 20. ADC_INPUT (0x15h)
Description
Bits
0
Field
DACR_ADCR
DACL_ADCL
MIC_ADCR
MIC_ADCL
AUX_ADCR
MONO_ADCL
The right DAC output is added to the ADC right input.
The left DAC output is added to the ADC left input.
The MIC input is added to the ADC right input.
The MIC input is added to the ADC left input.
The AUX input is added to the ADC right input.
The MONO input is added to the ADC left input.
1
2
3
4
5
TABLE 21. MIC_INPUT (0x16h)
Bits
Field
Description
3:0
MIC_LEVEL
This sets the gain of the microphone preamp.
MIC_LEVEL
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Gain
6dB
8dB
10dB
12dB
14dB
16dB
18dB
20dB
22dB
24dB
26dB
28dB
30dB
32dB
34dB
36dB
4
5
SE_DIFF
MUTE
If set, the MIC negative input is ignored. In single-ended mode, the MIC negative input pin should
left floating.
If set, the microphone preamp is muted.
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TABLE 22. AUX_LEVEL (0x18h)
Description
Bits
Field
5:0
AUX_LEVEL This programs the AUX input level. All gain changes are performed at zero crossings.
AUX_LEVEL
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011000
011001
011010
011100
011101
011110
011111
Level
–46.5dB
–45dB
–43.5dB
–42dB
–40.5dB
–39dB
–37.5dB
–36dB
–34.5dB
–33dB
–31.5dB
–30dB
–28.5dB
–27dB
–25.5dB
–24dB
–22.5dB
–21dB
–19.5dB
–18dB
–16.5dB
–15dB
–13.5dB
–12dB
–10.5dB
–9dB
AUX_LEVEL
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
Level
1.5dB
3dB
4.5dB
6dB
7.5dB
9dB
10.5dB
12dB
13.5dB
15dB
16.5dB
18dB
–7.5dB
–6dB
–4.5dB
–3dB
–1.5dB
0dB
6
SE/DIFF
If set, the AUXL input is ignored. In single-ended mode, the AUXL input pin should be left
floating.
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TABLE 23. MONO_LEVEL (0x19h)
Description
Bits
Field
5:0
MONO_LEVEL This programs the MONO input level. All gain changes are performed at zero crossings.
MONO_LEVEL
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011000
011001
011010
011100
011101
011110
011111
Level
–46.5dB
–45dB
–43.5dB
–42dB
–40.5dB
–39dB
–37.5dB
–36dB
–34.5dB
–33dB
–31.5dB
–30dB
–28.5dB
–27dB
–25.5dB
–24dB
–22.5dB
–21dB
–19.5dB
–18dB
–16.5dB
–15dB
–13.5dB
–12dB
–10.5dB
–9dB
MONO_LEVEL
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
Level
1.5dB
3dB
4.5dB
6dB
7.5dB
9dB
10.5dB
12dB
13.5dB
15dB
16.5dB
18dB
–7.5dB
–6dB
–4.5dB
–3dB
–1.5dB
0dB
6
7
SE/DIFF
If set, the MONO– input is ignored. In single-ended mode, the MONO- input pin should
be left floating.
AUXL_MONO If set, AUXL is routed to the MONO Input Amplifier.
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Headphone Detection Circuit
The LM49352 features a headphone detection circuit (HDC) that automatically enables the headphone amplifier whenever the
insertion of a headphone plug is detected and disables the headphone amplifier during the removal of a headphone plug. The HDC
optimizes power management by automatically disabling any output amplifier that is not in use. The HDC eliminates the necessity
of polling the I2C bus for status changes. However, since the HDC requires the use of the GPIO pin, the PORT2_SDO functionality
sensing is required.
The HDC requires a headphone jack with a normally closed mechanical switch and a pullup resistor, RPU, tied between the me-
chanical switch and I/O_VDD (Refer to Figure 14). Choosing a RPU value of at least 500kΩ ensures minimal current draw through
the pullup resistor. When the headphone amplifier is disabled, an internal 50kΩ pulldown, RPD, is connected to each headphone
amplifier output. Without the presence of a headphone plug, the headphone jack’s mechanical switch is closed thereby connecting
the right headphone amplifier output to RPU. The GPIO pin detects a logic low level due to the voltage division between RPU and
RPD. When the GPIO pin is set to HPSENSE mode, a logic low voltage reading causes the HDC to disable the headphone amplifier.
When a headphone plug is inserted, the mechanical connection between RPU and RPD is broken, resulting in a logic high level
detected by the GPIO pin. A logic high voltage reading causes the HDC to enable the headphone amplifier.
The HDC has four modes of operation that automatically enable/disable different combinations of the audio output amplifiers
contained within the LM49352. Having the choice of four different HDC settings maximizes power management flexibility to suit a
particular application. Please refer to the HP_SENSE (reg 0x1Bh) register table for a detailed discussion on the different HDC
modes of operation.
30072793
FIGURE 15. Application Circuit for Headphone Detection
51
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TABLE 24. HP_SENSE (0x1Bh)
Description
Bits
Field
0
HP SENSE
This bit enables the headphone sense circuit. If enabled, the headphone amplifier will automatically
turn on/off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone
sense input. If the presence of a headphone insertion is detected, the headphone amplifier will
automatically turn on. If a headphone removal is detected the headphone amplifier will automatically
turn off.
HPSENSE
Headphone Sense Status
0
1
Off
On
1
2
3
HPSENSE_D
This bit enables the headphone sense circuit. If enabled, the headphone amplifier will automatically
turn on/off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone
sense input. If the presence of a headphone insertion is detected, the headphone amplifier will
automatically turn on and the Class D loudspeaker amplifier will turn off. If a headphone removal is
detected the headphone amplifier will automatically turn off and the Class D loudspeaker amplifier
will turn on. This bit overrides bit 0 of this register.
HPSENSE_D
Headphone Sense Status
0
1
Off
On
HPSENSE_AUX
This bit enables the headphone sense circuit. If enabled, the headphone amplifier will automatically
turn on/off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone
sense input. If the presence of a headphone insertion is detected, the headphone amplifier will
automatically turn on and the Earpiece / Auxout amplifier will turn off. If a headphone removal is
detected the headphone amplifier will automatically turn off and the Earpiece / Auxout amplifier will
turn on. This bit overrides bit 0 and bit 1 of this register.
HPSENSE_AUX
Headphone Sense Status
0
1
Off
On
HPSENSE_AUX_D This bit enables the headphone sense circuit. If enabled, the headphone amplifier will automatically
turn on/off based on the logic level of the GPIO pin whenever GPIO is selected as a headphone
sense input. If the presence of a headphone insertion is detected, the headphone amplifier will
automatically turn on and the Class D loudspeaker amplifier along with the Earpiece / Auxout
amplifier will turn off. If a headphone removal is detected the headphone amplifier will automatically
turn off and the Class D loudspeaker amplifier along with the Earpiece / Auxout amplifier will turn
on. This bit overrides bit 0, bit 1, and bit 2 of this register.
HPSENSE_AUX_D
Headphone Sense Status
0
1
Off
On
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20.0 ADC Control Registers
This register is used to control the LM49352's ADC:
TABLE 25. ADC Basic (0x20h)
Description
Bits
Field
0
MONO
This sets mono or stereo operation of the ADC.
MONO
0
ADC Operation
Stereo Audio
1
Mono Voice (Right ADC channel disabled, Left ADC channel active)
This sets the oversampling ratio of the ADC.
1
OSR
OSR
Stereo Audio ADC
Oversampling Ratio
Mono Voice ADC Oversampling Ratio
0
1
128
128
125
128
2
3
MUTE_L
MUTE_R
If set, a digital mute is applied to the Left (or mono) ADC output.
If set, a digital mute is applied to the Right ADC output.
6:4
ADC_CLK_SEL
This selects the source of the ADC clock domain, ADC_SOURCE_CLK.
ADC_CLK_SEL
Source
000
001
010
011
100
MCLK
PORT1_RX_CLK
PORT2_RX_CLK
PLL_OUTPUT1
PLL_OUTPUT2
7
ADC_DSP_ONLY
If set, the ADC's analog circuitry is disabled to reduce power consumption, however, ADC DSP
functionality is maintained. This can be used to perform asynchronous resampling between audio
rates of a common family. Setting this bit is also useful whenever applying Automatic Level Control
(ALC) to an analog only audio path.
TABLE 26. ADC_CLK_DIV (0x21h)
Description
Bits
Field
7:0
ADC_CLK_DIV
This programs the half cycle divider that preceeds the ADC. The input of this divider should be
around 12MHz. The default of this divider is 0x00.
Program this divider with the division you want, multiplied by 2, and subtract 1.
ADC_CLK_DIV
00000000
00000001
00000010
00000011
—
Divides by
1
1
1.5
2
—
11111101
11111110
11111111
127
127.5
128
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TABLE 27. ADC_MIXER (0x23h)
Description
Bits
Field
1:0
ADC_MIX_LEVEL_L This sets the input level to the left ADC channel.
ADC_MIX_LEVEL_L
Level
0dB
00
01
1.35dB
3.5dB
6dB
10
11
3.2
ADC_MIX_LEVEL_R This sets the input level to the right ADC channel.
ADC_MIX_LEVEL_R
Level
0dB
00
01
10
11
1.35dB
3.5dB
6dB
4
STEREO_LINK
If set, this links ADC_MIX_LEVEL_R with ADC_MIX_LEVEL_L.
STEREO_LINK
Status
Off
0
1
On
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21.0 DAC Control Registers
This register is used to control the LM49352's DAC:
TABLE 28. DAC Basic (0x30h)
Description
Bits
Field
1:0
MODE
This programs the over sampling ratio of the stereo DAC.
MODE
DAC Oversampling Ratio
00
125
128
01
10
11
64 (Default)
RSVD
2
3
MUTE_L
MUTE_R
This digitally mutes the Left DAC output.
This digitally mutes the Right DAC output.
6:4
DAC_CLK_SEL
This selects the source of the DAC clock domain, DAC_SOURCE_CLK.
DAC_CLK_SEL
Source
000
001
010
011
100
MCLK
PORT1_RX_CLK
PORT2_RX_CLK
PLL_OUTPUT1
PLL_OUTPUT2
7
DSP_ONLY
If set, the DAC's analog circuitry is disabled to reduce power consumption, however DAC DSP
functionality is maintained. This can be used to perform asyncronous resampling between audio rates
of a common family.
TABLE 29. DAC_CLK_DIV (0x31h)
Description
Bits
Field
7:0
DAC_CLK_DIV
This programs the half cycle divider that precedes the DAC. The input of this divider should be
around 12MHz. The default of this divider is 0x03 which gives a division by 2.
Program this divider with the division you want, multiplied by 2, and subtract 1.
DAC_CLK_DIV
00000000
00000001
00000010
00000011
—
Divides by
1
1
1.5
2 (Default)
—
11111101
11111110
11111111
127
127.5
128
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22.0 Digital Mixer Control Registers
Digital Mixer
The LM49352’s digital mixer allows for flexible routing of digital audio signals between both audio ports, DAC, and ADC. This mixer
handles which digital data path (Port1 RX data, Port2 RX data, or ADC output) is routed to the DAC input. The digital mixer also
selects the appropriate digital data path (Port1 RX data, Port2 RX data, ADC output, or DAC DSP (Interpolator) output) that is used
for data transmission on Audio Port 1 and 2. Audio inputs to the digital mixer can be attenuated down to -18dB to avoid clipping
conditions. The digital mixer also allows direct routing from the DAC interpolator output to the ADC decimator input which allows
the DAC and ADC DSP blocks to be cascaded witjhout having to enable the analog of the DAC and ADC in order to save power.
Another key feature of the digital mixer is sample rate conversion (SRC) between audio ports. This allows simultaneous operation
of the dual audio ports even if each port is operating at a different sample rate. The LM49352 can be used as an audio port bridge
with SRC capability. The digital mixer allows either straight pass through between audio ports or, if desired, DSP effects can be
added to the digital audio signal during audio port bridge operation. The digital mixer automatically handles stereo I2S to mono
PCM conversion between audio ports and vice versa.
30072701
FIGURE 16. Digital Mixer
The LM49352 includes two separate and independent DSP blocks, one for the DAC and the other for the ADC. The digital mixer
also allows both DSP blocks to be cascaded together in either order so that the DSP effects from both blocks can be combined
into the same signal path. For example, the 5 band parametric EQ of each DSP block can be combined together to form a 10 band
parametric EQ for added flexibility.
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This register is used to control the LM49352's digital mixer:
TABLE 30. Input Levels 1 (0x40h)
Bits
Field
Description
1:0
PORT1_RX_L
_LVL
This programs the input level of the data arriving from the left receive channel of Audio Port 1.
PORT1_RX_L_LVL
Level
0dB
00
01
10
11
–6dB
–12dB
–18dB
3:2
5:4
7:6
PORT1_RX_R
_LVL
This programs the input level of the data arriving from the right receive channel of Audio Port 1.
PORT1_RX_R_LVL
Level
0dB
00
01
10
11
–6dB
–12dB
–18dB
PORT2_RX_L
_LVL
This programs the input level of the data arriving from the left receive channel of Audio Port 2.
PORT2_RX_L_LVL
Level
0dB
00
01
10
11
–6dB
–12dB
–18dB
PORT2_RX_R
_LVL
This programs the input level of the data arriving from the right receive channel of Audio Port 2.
PORT2_RX_R_LVL
Level
0dB
00
01
10
11
–6dB
–12dB
–18dB
TABLE 31. Input Levels 2 (0x41h)
Bits
Field
Description
1:0
3:2
5:4
ADC_L_LVL
This programs the input level of the data arriving from the left ADC channel.
ADC_L_LVL
Level
0dB
00
01
–6dB
–12dB
–18dB
10
11
ADC_R_LVL
This programs the input level of the data arriving from the right ADC channel.
ADC_R_LVL
Level
0dB
00
01
10
11
–6dB
–12dB
–18dB
INTERP_L_LVL This programs the input level of the data arriving from the left DAC's interpolator output.
INTERP_L_LVL
Level
0dB
00
01
10
11
–6dB
–12dB
–18dB
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Bits
Field
Description
7:6
INTERP_R_LVL This programs the input level of the data arriving from the right DAC's interpolator output.
INTERP_R_LVL
Level
0dB
00
01
10
11
–6dB
–12dB
–18dB
TABLE 32. Audio Port 1 Input (0x42h)
Bits
Field
Description
1:0
L_SEL
This selects which input is fed to the Left TX Channel of Audio Port 1.
L_SEL
Selected Input
None
00
01
ADC_L
10
PORT2_RX_L
DAC_INTERP_L
11
3:2
R_SEL
This selects which input is fed to the Right TX Channel of Audio Port 1.
R_SEL
Selected Input
None
00
01
ADC_R
10
PORT2_RX_R
DAC_INTERP_R
11
4
5
SWAP
MONO
If set, this swaps the Left and Right outputs to Audio Port 1.
If set, the right channel is ignored and the left channel becomes (left+right)/2.
TABLE 33. Audio Port 2 Input (0x43h)
Bits
Field
Description
1:0
L_SEL
This selects which input is fed to Audio Port 2's Left TX Channel.
L_SEL
Selected Input
None
00
01
ADC_L
10
PORT1_RX_L
DAC_INTERP_L
11
3:2
R_SEL
This selects which input is fed to Audio Port 2's Right TX Channel.
R_SEL
00
Selected Input
None
01
ADC_R
10
PORT1_RX_R
11
DAC_INTERP_R
4
5
SWAP
MONO
If set, this swaps the Left and Right outputs to Audio Port 2.
If set, the right channel is ignored and the left channel becomes (left+right)/2.
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TABLE 34. DAC Input Select (0x44h)
Bits
0
Field
Description
This adds Audio Port 1's left RX channel to the DAC's left input.
This adds Audio Port 2's left RX channel to the DAC's left input.
This adds the ADC's left output to the DAC's left input.
PORT1_L
PORT2_L
ADC_L
1
2
3
PORT1_R
PORT2_R
ADC_R
This adds Audio Port 1's right RX channel to the DAC's right input.
This adds Audio Port 2's right RX channel to the DAC's right input.
This adds the ADC's right output to the DAC's right input.
If set, this swaps the Left and Right inputs to the DAC.
4
5
6
SWAP
TABLE 35. Decimator Input Select (0x45h)
Bits
Field
Description
1:0
L_SEL
This selects which input is fed to the left ADC's decimator input.
L_SEL
Selected Input
None
00
01
PORT1_RX_L
PORT2_RX_L
DAC_INTERP_L
10
11
3:2
5:4
R_SEL
This selects which input is fed to the right ADC's decimator input.
R_SEL
00
Selected Input
None
01
PORT1_RX_R
PORT2_RX_R
DAC_INTERP_R
10
11
MXR_CLK_SEL This selects sets the source of the Digital Mixer Clock. The 'Auto' setting will automatically select the source
with the highest clock frequency. If the DAC interpolator output (DAC_OSR_L or DAC_OSR_R) is
selected, then MXR_CLK_SEL should be set to '10'.
MXR_CLK_SEL
Selected Input
Auto
00
01
10
11
MCLK
DAC
ADC
59
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23.0 Audio Port Control Registers
30072771
FIGURE 17. I2S Serial Data Format (24 bit example)
30072772
FIGURE 18. Left Justified Data Format (24 bit example)
30072770
FIGURE 19. Right Justified Data Format (24 bit example)
30072734
FIGURE 20. PCM Serial Data Format (16 bit example)
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The following registers are used to control the LM49352's audio ports. Audio Port 1 and Audio Port 2 are identical. Port 1 is
programmed through the (0x5Xh) registers. Port 2 is programmed through the (0x6Xh) registers.
TABLE 36. BASIC_SETUP (0x50h/0x60h)
Bits
0
Field
Description
STEREO
If set, the audio port will receive and transmit stereo data.
1
RX_ENABLE
If set, the input is enabled (enables the SDI port and input shift register and any clock
generation required).
2
TX_ENABLE
If set, the output is enabled (enables the SDO port and output shift register and any clock
generation required).
3
4
5
CLOCK_MS
SYNC_MS
If set, the audio port will transmit the clock when either the RX or TX is enabled.
If set, the audio port will transmit the sync signal when either the RX or TX is enabled.
This sets how data is clocked by the Audio Port.
CLOCK_PHASE
CLOCK_PHASE
Audio Data Mode
I2S (TX on falling edge, RX on rising edge)
0
1
PCM (TX on rising edge, RX on falling edge)
6
7
STEREO_SYNC_PHASE
If set, this reverses the left and right channel data of the Audio Port.
STEREO_SYNC_PHASE
Audio Port Data Orientation
Left channel data goes to left channel output.
Right channel data goes to right channel output.
0
Right channel data goes to left channel output.
Left channel data goes to right channel output.
1
SYNC_INVERT
If this bit is set the SYNC is inverted before the receiver and transmitter.
SYNC_INVERT
SYNC ORIENTATION
0
1
SYNC Low = Left, SYNC High = Right
SYNC Low = Right, SYNC High = Left
TABLE 37. CLK_GEN_1 (0x51h/0x61h)
Bits
Field
Description
5:0
HALF_CYCLE_CLK_ This programs the half-cycle divider that generates the master clocks in the audio port. The default
DIV
of this divider is 0x00, i.e. bypassed.
Program this divider with the required division multiplied by 2, and subtract 1.
HALF_CYCLE_CLK_DIV
Divides By
000000
000001
000010
000011
—
BYPASS
1
1.5
2
—
111101
111110
11111
31
31.5
32
6
CLOCK_SEL
This selects the clock source of the master mode Audio Port Clock generator's half-cycle divider.
0 = DAC_SOURCE_CLK
1 = ADC_SOURCE_CLK
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TABLE 38. CLK_GEN_1 (0x52h/62h)
Description
Bits
Field
2:0
SYNTH_NUM
Along with SYNTH_DENOM, this sets the clock divider that generates the Port 1 or Port 2 clock in
master mode.
SYNTH_NUM
Numerator
000
001
010
011
100
101
110
111
SYNTH_DENOM (1/1)
100/SYNTH_DENOM
96/SYNTH_DENOM
80/SYNTH_DENOM
72/SYNTH_DENOM
64/SYNTH_DENOM
48/SYNTH_DENOM
0/SYNTH_DENOM
3
SYNTH_DENOM
Along with SYNTH_NUM, this sets the clock divider that generates the Port 1 or Port 2 clock in master
mode.
SYNTH_DENOM
Denominator
128
0
1
125
TABLE 39. CLK_GEN_1 (0x53h/63h)
Description
Bits
Field
2:0
SYNC_RATE
This sets the number of clock cycles before the sync pattern repeats. This depends if the audio port
data is mono or stereo.
In MONO mode:
SYNC_RATE
Number of Clock Cycles
000
8
001
12
16
18
20
24
25
32
010
011
100
101
110
111
In STEREO mode:
SYNC_RATE
000
Number of Clock Cycles
16
24
32
36
40
48
50
64
001
010
011
100
101
110
111
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62
Bits
Field
Description
5:3
SYNC_WIDTH
In MONO mode, this programs the width (in number of bits) of the SYNC signal.
SYNC_WIDTH
Width of SYNC (in bits)
000
001
010
011
100
101
110
111
1
2
4
7
8
11
15
16
TABLE 40. DATA_WIDTHS (0x54h/64h)
Bits
Field
Description
2:0
RX_WIDTH
This programs the expected bits per word of the serial data input SDI.
RX_WIDTH
Bits
24
20
18
16
14
13
12
8
000
001
010
011
100
101
110
111
5:3
TX_WIDTH
This programs the bits per word of the serial data output SDO.
TX_WIDTH
000
Description
24
20
18
16
14
13
12
8
001
010
011
100
101
110
111
7:6
TX_EXTRA_BITS This programs the TX data output padding.
TX_EXTRA_BITS
Description
00
01
10
11
0
1
High-Z
High-Z
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TABLE 41. RX_MODE (0x55h/x65h)
Bits
Field
Description
0
RX_MODE
This sets the RX data input justification with respect to the SYNC signal.
RX_MODE
Description
MSB Justified
LSB Justified
0
1
5:1
MSB_POSITION This specifies the bit location of the MSB from the start of the frame (MSB Justified) or from the end of
the frame (LSB Justified).
MSB_POSITION
Description
00000
0(Left Justified/PCM Long)
00001
1(I2S/PCM Short)
00010
2
00011
3
00100
4
00101
5
00110
6
00111
7
01000
8
01001
9
01010
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
6
7
COMPAND
If set, audio data will be companded.
This sets the audio companding mode.
μLaw/A-Law
Compand Mode
μLaw/A-Law
0
μLaw
1
A-Law
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TABLE 42. TX_MODE (0x56h/x66h)
Bits
Field
Description
0
TX_MODE
This sets the TX data output justification with respect to the SYNC signal.
TX_MODE
Description
MSB Justified
LSB Justified
0
1
5:1
MSB_POSITION This specifies the bit location of the MSB from the start of the frame (MSB Justified) or from the end of
the frame (LSB Justified).
MSB_POSITION
Description
00000
0(Left Justified/PCM Long)
00001
1(I2S/PCM Short)
00010
2
00011
3
00100
4
00101
5
00110
6
00111
7
01000
8
01001
9
01010
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
6
7
COMPAND
If set, audio data will be companded.
This sets the audio companding mode.
μLaw/A-Law
Compand Mode
μLaw/A-Law
0
μLaw
1
A-Law
65
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24.0 Digital Effects Engine
Digital Signal Processor (DSP)
The LM49352 is designed to handle the entire audio signal conditioning and processing within the audio system, thereby freeing
up the workload of any other applications processor contained within the system. The LM49352 features two independent DSPs,
one for the DAC and the other for the ADC. Each DSP is fully featured and performs as a professional quality digital audio effects
engine. Both DSP engines feature digital volume control, automatic level control (ALC), digital soft clip compression, and a 5-band
parametric EQ. The effects chain of each DSP engine is shown by the diagrams below.
30072735
FIGURE 21. ADC DSP Effects Chain
30072736
FIGURE 22. DAC DSP Effects Chain
The ADC and DAC DSP engines can be cascaded together in any order via the digital mixer to combine different audio effects to
the same signal path. For example, a signal can be processed with high-pass filtering from the ADC effects engine with ALC from
the DAC effects engine. The 5-band parametric EQs from each DSP engine can be combined to form a single 10-band parametric
EQ or a single 5-band parametric EQ with ±30dB (instead of ±15dB) gain control for each band.
TABLE 43. ADC EFFECTS (0x70h)
Bits
0
Field
Description
ADC_HPF_ENB
ADC_ALC_ENB
ADC_PK_ENB
ADC_EQ_ENB
ADC_SCLP_ENB
This enables the ADC's High Pass Filter.
1
This enables the ADC's Automatic Level Control.
This enables the ADC's Peak Detector.
2
3
This enables the ADC's 5-band Parametric EQ.
This enables the ADC's Soft Clip Feature.
4
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TABLE 44. DAC EFFECTS (0x71h)
Description
Bits
0
Field
DAC_ALC_ENB
DAC_PK_ENB
DAC_EQ_ENB
RSVD
This enables the DAC's Automatic Level Control.
This enables the DAC's Peak Detector.
This enables the DAC's 5-band Parametric EQ.
Reserved
1
2
3
4
ADC_SCLP_ENB
This enables the DAC's Soft Clip Feature.
TABLE 45. HPF MODE (0x80h)
Bits
Field
Description
2:0
HPF_MODE
This configures the ADC's High Pass Filter (HPF). To calculate the –3dB cutoff frequency, multiply
the coefficient by the sample rate (Hz): fC = Xn.fS(Hz)
HPF_MODE
Coefficient
Filter Characteristics
fC = 220Hz for:
000
001
010
011
100
X0 = 0.0275
X1 = 0.01833
X2 = 0.01375
X3 = 0.009166
X4 = 0.006875
8kHz Voice
12kHz Voice
16kHz Voice
24kHz Voice
32kHz Voice
fC = 100Hz for:
fC = 150Hz for:
101
110
X5 = 0.003125
X6 = 0.0020833
32kHz Audio
48kHz Audio
111
X7 = 0.0015625
96kHz Audio
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ALC Overview
The Automatic Level Control (ALC) system can be used to regulate the audio output level to a user defined target level. The ALC
feature is especially useful whenever the level of the audio input is unknown, unpredictable, or has a large dynamic range. The
main purpose of the ALC is to optimize the dynamic range of the audio input to audio output path.
There are two separate and independent ALC circuits in the LM49352. One of the ALC circuits is located within the DAC DSP
effects block. The other ALC circuit is integrated into the ADC DSP effects block. The DAC ALC controls the DAC digital gain. The
ADC ALC controls the mono/auxiliary input amplifier gain or microphone preamplifier gain. The dual ALCs can be used to regulate
the level of the analog (AUX, MONO, MIC) and digital (Port1 Data In, Port2 Data In) audio inputs. The ALC regulated output can
be routed to any of the LM49352’s amplifier outputs for playback. The ALC regulated output can also be routed to Audio Port1 or
Audio Port2 for digital data transmission via I2S or PCM.
Only audio inputs that are considered signals (rather than noise) are sent to the ALC’s peak detector block. The peak detector
compares the level of the audio input versus the ALC target level (TARGET_LEVEL). Signals lower than the target level will be
amplified and signals higher than the target level will be attenuated. Any audio input that is lower than the level specified by the
noise floor level (NOISE_FLOOR) will be considered as noise and will be gated from the ALC’s peak detector in order to avoid
noise pumping. So it is important to set NOISE_FLOOR to correlate with the signal to noise ratio of the corresponding audio path.
In some instances (ie. Conference calls), it may be desirable to mute audio input signals that consist solely of background noise
from the audio output. This is accomplished by enabling the ALC’s noise gate (NG_ENB). When the noise gate is enabled, signals
lower than the noise floor level will be muted from the audio output.
If the audio input signal is below the target level, the ALC will increase the gain of the corresponding volume control until the signal
reaches the target level. The rate at which the ALC performs gain increases is known as decay rate (DECAY RATE). But before
each ALC gain increase the ALC must wait a predetermined amount of time (HOLD TIME). If the audio input signal is above the
target level, the ALC will decrease the gain of the corresponding volume control until the signal reaches the target level. The rate
at which the ALC performs attenuation is known as attack rate (ATTACK RATE). The ALC’s peak detector tracks increases in
audio input signal amplitude instantaneously, but tracks decreases in audio input signal amplitude at programmable rate (PEAK
DECAY TIME). ATTACK RATE, DECAY RATE, HOLD TIME, and PEAK DECAY TIME are fully adjustable which allows flexible
operation of the ALC circuit. The ALC’s timers are based on the sample rate of the DAC or ADC, so the closest corresponding
sample rate must be programmed into the DAC SAMPLE setting (for DAC ALC) or the ADC SAMPLE (for ADC ALC).
30072791
FIGURE 23. ALC Example
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Limiter
The LM49352’s ALC features a limiter function. The purpose of the limiter is to limit the maximum level of the audio signal to the
specified ALC target level. When the limiter is enabled, the ALC will decrease the gain of the volume control whenever the audio
signal is higher than the specified target level. The programmed I2C gain setting when the limiter is first enabled is the maximum
gain setting that the ALC limiter will apply to the audio signal. Gain increases beyond the original I2C gain setting are disabled.
This is in contrast to ALC operation with the limiter disabled, where the ALC may increase gain of audio signals below target level
using gain settings beyond the original I2C gain setting. Therefore, it is important to set the gain of the audio path to the desired
setting before enabling the ALC limiter function.
The limiter’s target level can be set just below the clipping level of the output amplifier or ADC in order to prevent harsh distortions
delivered to the loudspeaker or headphone on the receiving end. This method of ALC limiter operation is also known as “no clip”
mode. Operating the ALC limiter in “no clip” mode maximizes the dynamic range of the audio amplifier or ADC while ensuring that
the audio signal will never clip. Utilizing the ALC limiter in “no clip” mode also protects the loudspeaker from damage due to harmful
overdriven conditions.
The ALC limiter’s target level can also be set for a predetermined maximum output power or voltage level. This method of ALC
limiter operation is known as “power limit” mode. Operating the ALC limiter in “power limit” mode prevents the speaker or headphone
from playing at unsafe hearing levels that can permanently damage the end user’s ears. “Power limit” operation is especially useful
for applications such as listening to music through a set of headphones. Another benefit of using the ALC limit in “power limit” mode
is to extend battery life by reducing power consumption of the output amplifiers during audio playback.
30072792
FIGURE 24. ALC Limiter
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TABLE 46. ADC_ALC_1 (0x81h)
Description
This programs the timers on the ALC with the closest sample rate of the ADC.
Bits
Field
2:0
ADC_SAMPLE
ADC_SAMPLE
Expected ADC fS
000
001
010
011
100
101
110
111
8kHz
12kHz
16kHz
24kHz
32kHz
48kHz
96kHz
192kHz
3
4
LIMITER
If set, the circuit will never apply gain to the signal, no matter how small, but it will attenuate the
signal as soon as it reaches target and release it at the decay rate, once signal level reduces below
target. The I2C gain setting (at the time the LIMITER is enabled) is the maximum gain that the ALC
will apply. Care should be taken when choosing the optimum I2C gain setting whenever enabling
the Limiter.
STEREO LINK
If set, the ALC circuit uses the stereo average of the input signals to control the gain of the stereo
output. This maintains stereo imaging. If this bit is cleared, then both channels operate as dual
mono.
5
6
7
SOURCE_RSEL
SOURCE_LSEL
SOURCE_OVR
If both SOURCE_OVR and this bit is set, the right ADC ALC channel will be active.
If both SOURCE_OVR and this bit is set, the left ADC ALC channel will be active.
If set, the active channel of the ADC ALC is determined by SOURCE_RSEL and SOURCE_LSEL.
If cleared, the active channel of the ADC ALC is determined by the selected input to the ADC.
MONO enables left ALC, AUX enables right ALC, MIC enables left and / or right ALC depending
on which ADC channel MIC is selected to.
TABLE 47. ADC_ALC_2 (0x82h)
Description
Bits
Field
3:0
NOISE_FLOOR
This sets the anticipated noise floor. Signals lower than the noise floor specified will be gated from
the ALC to avoid noise pumping.
NOISE_FLOOR
0000
Noise Floor (dB)
–39
–42
–45
–48
–51
–54
–57
–60
–63
–66
–69
–72
–75
–78
–81
–84
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4
NG_ENB
This enables the Noise Gate.
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TABLE 48. ADC_ALC_3 (0x83h)
Description
Bits
Field
4:0
TARGET_LEVEL
This sets the desired target output level. Signals lower than this will be amplified and signals larger
than this will be attenuated.
TARGET_LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Target Level (dB)
–1.5
–3
–4.5
–6
–7.5
–9
–10.5
–12
–13.5
–15
–16.5
–18
–19.5
–21
–22.5
–24
–25.5
–27
–28.5
–30
–31.5
–33
–34.5
–36
–37.5
–39
–40.5
–42
–43.5
–45
–46.5
–48
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TABLE 49. ADC_ALC_4 (0x84h)
Description
This sets the rate at which the ALC will reduce gain if it detects the input signal is large.
Bits
Field
4:0
ATTACK_RATE
ATTACK_RATE
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Time between gain steps (μs)
21
42
83
167
250
333
417
542
729
958
1250 (Default)
1604
1896
2208
2792
3708
4792
5688
6563
8396
11000
14167
17083
20000
25000
32000
45000
60000
75000
87500
100000
114583
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72
TABLE 50. ADC_ALC_5 (0x85h)
Description
Bits
Field
4:0
DECAY_RATE
This sets the rate at which the ALC will increase gain if it detects the input signal is too
small.
DECAY_RATE
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
PK_DECAY_RATE
000
Time between gain steps (μs)
104
125
167
250
292
396
500
708
896
1250
1396 (Default)
2000
2708
3500
4750
6250
8000
11000
14000
18500
25000
32000
42000
55000
72500
100000
125000
160000
225000
300000
375000
500000 (0.5s)
Max Time to track decay
1.3ms (Default)
2.6ms
7:5
PK_DECAY_RATE
001
010
5.3ms
011
10.6ms
21.3ms
42.6.3ms
85.5ms
2.73 secs
100
101
110
111
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TABLE 51. ADC_ALC_6 (0x86h)
Description
HOLD_TIME This sets how long the ALC circuit waits before increasing the gain.
Bits
Field
4:0
HOLD_TIME
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Time (ms)
1
1.25
1.6
2
2.5
3.2
4
5
6.25
8
10 (Default)
12.5
16
20
25
32
40
50
64
80
100
125
160
200
250
320
400
500
640
800
1000
1250
TABLE 52. ADC_ALC_7 (0x87h)
Description
Bits
Field
5:0
MAX_LEVEL
This sets the maximum allowed gain of the volume control to the output
amplifier whenever the ALC is use. If the volume control is less than 6 bits
the relevant LSBs are used as the limit and the MSBs are ignored.
TABLE 53. ADC_ALC_8 (0x88h)
Description
Bits
Field
5:0
MIN_LEVEL
This sets the minimum allowed gain of the volume control to the output
amplifier whenever the ALC is use. If the volume control is less than 6 bits the
relevant LSBs are used as the limit and the MSBs are ignored.
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TABLE 54. ADC_L_LEVEL (0x89h)
Description
ADC_L_LEVEL This sets the post ADC digital gain of the left channel.
Bits
Field
5:0
ADC_L_LEVEL
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
Level
-76.5dB
-75dB
ADC_L_LEVEL
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Level
-28.5dB
-27dB
-25.5dB
-24dB
-22.5dB
-21dB
-20.5dB
-18dB
-16.5dB
-15dB
-13.5dB
-12dB
-10.5dB
-9dB
-73.5dB
-72dB
-70.5dB
-69dB
-67.5dB
-66dB
-64.5dB
-63dB
-61.5dB
-60dB
-58.5dB
-57dB
-55.5dB
-54dB
-7.5dB
-6dB
-52.5dB
-51dB
-4.5dB
-3dB
-49.5dB
-48dB
-1.5dB
0dB
-46.5dB
-45dB
1.5dB
3dB
-43.5dB
-42dB
4.5dB
6dB
-40.5dB
-39dB
7.5dB
9dB
-37.5dB
-36dB
10.5dB
12dB
-34.5dB
-33dB
13.5dB
15dB
-31.5dB
-30dB
16.5dB
18dB
6
STEREO_LINK
If set, this links the ADC_R_LEVEL with ADC_L_LEVEL.
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TABLE 55. ADC_R_LEVEL (0x8Ah)
Description
ADC_R_LEVEL This sets the post ADC digital gain of the right channel.
Bits
Field
5:0
ADC_R_LEVEL
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
Level
-76.5dB
-75dB
ADC_R_LEVEL
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Level
-28.5dB
-27dB
-25.5dB
-24dB
-22.5dB
-21dB
-20.5dB
-18dB
-16.5dB
-15dB
-13.5dB
-12dB
-10.5dB
-9dB
-73.5dB
-72dB
-70.5dB
-69dB
-67.5dB
-66dB
-64.5dB
-63dB
-61.5dB
-60dB
-58.5dB
-57dB
-55.5dB
-54dB
-7.5dB
-6dB
-52.5dB
-51dB
-4.5dB
-3dB
-49.5dB
-48dB
-1.5dB
0dB
-46.5dB
-45dB
1.5dB
3dB
-43.5dB
-42dB
4.5dB
6dB
-40.5dB
-39dB
7.5dB
9dB
-37.5dB
-36dB
10.5dB
12dB
-34.5dB
-33dB
13.5dB
15dB
-31.5dB
-30dB
16.5dB
18dB
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76
TABLE 56. EQ_BAND_1 (0x8Bh)
Description
Bits
Field
1:0
FREQ
This sets the Sub-bass shelving filter's cut-off frequency. The cut-off
frequencies shown are based on a 48kHz sample rate. Using lower sample
rates will scale down the cut-off frequencies proportionately.
FREQ
00
Frequency (Hz)
60
80
01
10
100
120
11
6:2
LEVEL
This sets the gain at fC.
LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
1dB
2dB
3dB
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
13dB
14dB
15dB
77
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TABLE 57. EQ_BAND_2 (0x8Ch)
Description
Bits
Field
1:0
FREQ
This sets the Bass peak filter's center frequency. The cut-off frequencies
shown are based on a 48kHz sample rate. Using lower sample rates will scale
down the cut-off frequencies proportionately.
FREQ
Frequency (Hz)
00
150
200
250
300
01
10
11
6:2
LEVEL
This sets the gain at fC.
LEVEL
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
1dB
10010
2dB
10011
3dB
10100
4dB
10101
5dB
10110
6dB
10111
7dB
11000
8dB
11001
9dB
11010
10dB
11dB
12dB
13dB
14dB
15dB
11011
11100
11101
11110
11111
7
Q
Programs the width of the peak filter.
Q
0
Bandwidth
2/3 Octave
4/3 Octave
1
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78
TABLE 58. EQ_BAND_3 (0x8Dh)
Description
Bits
Field
1:0
FREQ
This sets the Mid peak filter's center frequency. The cut-off frequencies shown
are based on a 48kHz sample rate. Using lower sample rates will scale down
the cut-off frequencies proportionately.
FREQ
00
Frequency (Hz)
600
800
1k
01
10
11
1.2k
6:2
LEVEL
This sets the gain at fC.
LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
1dB
2dB
3dB
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
13dB
14dB
15dB
7
Q
This programs the width of the peak filter.
Q
0
Bandwidth
2/3 Octave
4/3 Octave
1
79
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TABLE 59. EQ_BAND_4 (0x8Eh)
Description
Bits
Field
1:0
FREQ
This sets the Treble peak filter's center frequency. The cut-off frequencies
shown are based on a 48kHz sample rate. Using lower sample rates will scale
down the cut-off frequencies proportionately.
FREQ
00
Frequency (Hz)
2k
01
2.7k
3.4k
4.1k
10
11
6:2
LEVEL
This sets the gain at fC.
LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
1dB
2dB
3dB
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
13dB
14dB
15dB
7
Q
This programs the width of the peak filter.
Q
0
Bandwidth
2/3 Octave
4/3 Octave
1
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80
TABLE 60. EQ_BAND_5 (0x8Fh)
Description
Bits
Field
1:0
FREQ
This sets the presence shelving filter's cut-off frequency. The cut-off
frequencies shown are based on a 48kHz sample rate. Using lower sample
rates will scale down the cut-off frequencies proportionately.
FREQ
00
Frequency (Hz)
7k
9k
01
10
11k
13k
11
6:2
LEVEL
This sets the gain at fC.
LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
1dB
2dB
3dB
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
13dB
14dB
15dB
81
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Digital Audio Compressor
The LM49352 features a digital audio compressor on both the DAC and ADC paths. The compressor works by reducing the level
of the audio signal that is higher than the level set by the audio compressor threshold level (THRESHOLD) by a fixed ratio (com-
pressor output / compressor input) that is set by a predetermined audio compression ratio (RATIO). Higher compression ratios
result in more compression as shown in Figure 24. The audio compressor can be used in conjunction with the ALC to limit audio
peaks that the ALC may not be fast enough to react to.
30072789
FIGURE 25. Audio Compressor Effect
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82
Soft Knee Function
The LM49352’s audio compressor also features a soft knee function that smoothes the harsh edges found during clipping of an
audio signal. For audio signals higher than the compressor threshold level, the soft knee function gradually increases the com-
pression ratio for increasing levels of audio signal beyond the compressor threshold. To achieve the smoothing effect to prevent
hard clipping, the soft knee function initially compresses the audio signal at the smallest ratio and then incrementally increases the
compression ratio if required. The highest level of compression applied by the soft knee function is set by the compressor ratio.
The effect of the soft knee function is shown in Figure 26.
30072790
FIGURE 26. Soft Knee Example with Compression Ratio Setting of 1:3.4
83
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TABLE 61. SOFTCLIP1 (0x90h)
Description
Bits
Field
3:0
THRESHOLD
This sets the threshold level of the audio compressor. Audio signals above
the threshold will be compressed.
THRESHOLD
0000
Threshold Level (dB)
-36dB
0001
-30dB
0010
-24dB
0011
-20dB
0100
-18dB
0101
-17dB
0110
-16dB
0111
-15dB
1000
-14dB
1001
-12dB
1010
-10dB
1011
-8dB
1100
-6dB
1101
-4dB
1110
-2.5dB
-1dB
1111
4
SOFT_KNEE
If set, the audio compressor will automatically apply higher compression ratios
to audio signals higher than the threshold level. As the audio signal
approaches levels higher than the threshold, SOFT_KNEE will increase the
compression RATIO. The highest compression that the SOFT_KNEE
algorithm will apply is the compression that is set by RATIO.
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84
TABLE 62. SOFTCLIP2 (0x91h)
Description
Bits
Field
4:0
RATIO
This sets the ratio at which the audio is compressed to when it passes beyond
the threshold. In SOFT_KNEE mode this is the final level of compression.
RATIO
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Ratio
1:1 (Bypass)
1:1.2
1:1.4
1:1.7
1:2.0
1:2.4
1:2.8
1:3.4
1:4.0
1:4.7
1:5.7
1:6.7
1:8.0
1:9.5
1:11.3
1:13.5
1:16.0
1:19.0
1:22.8
1:27.0
1:32.0
1:37.9
1:45.5
1:53.9
1:64.0
1:75.0
1:91.0
1:108
1:128
1:152
1:182
1:215
85
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TABLE 63. SOFTCLIP3 (0x92h)
Description
Bits
Field
3:0
LEVEL
This sets the post compressor gain level.
LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Level (dB)
-22.5dB
-21dB
-19.5dB
-18dB
-16.5dB
-15dB
-13.5dB
-12dB
-10.5dB
-9dB
-7.5dB
-6dB
-4.5dB
-3dB
-1.5dB
0dB
1.5dB
3dB
4.5dB
6dB
7.5dB
9dB
10.5dB
12dB
13.5dB
15dB
16.5dB
18dB
19.5dB
21dB
22.5dB
24dB
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86
25.0 DAC Effects Registers
TABLE 64. DAC_ALC_1 (0xA0h)
Description
DAC_SAMPLE This programs the timers on the ALC with the closest DAC sample rate.
Bits
Field
2:0
DAC_SAMPLE
Expected DAC fS
8kHz
000
001
010
011
100
101
110
111
12kHz
16kHz
24kHz
32kHz
48kHz
96kHz
192kHz
3
4
LIMITER
If set, the circuit will never apply gain to the signal, no matter how small, but
it will attenuate the signal as soon as it reaches target and release it at the
decay rate, once signal level reduces below target. The I2C gain setting (at
the time the LIMITER is enabled) is the maximum gain that the ALC will apply.
Care should be taken when choosing the optimum I2C gain setting whenever
enabling the Limiter.
STEREO LINK If set, the ALC circuit uses the stereo average of the input signals to control
the gain of the stereo output. This maintains stereo imaging. If this bit is
cleared, then both channels operate as dual mono.
TABLE 65. DAC_ALC_2 (0xA1h)
Bits
Field
Description
3:0
NOISE_FLOOR This sets the anticipated noise floor. Signals lower than the specified noise
floor will be gated from the ALC to avoid noise pumping.
NOISE_FLOOR
Noise Floor (dB)
0000
-39
-42
-45
-48
-51
-54
-57
-60
-63
-66
-69
-72
-75
-78
-81
-84
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4
NG_ENB
This enables the Noise Gate
87
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TABLE 66. DAC_ALC_3 (0xA2h)
Description
Bits
Field
4:0
TARGET_LEVEL This sets the desired output level. Signals lower than this will be amplified
and signals larger than this will be attenuated.
TARGET_LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Target Level (dB)
-1.5
-3
-4.5
-6
-7.5
-9
-10.5
-12
-13.5
-15
-16.5
-18
-19.5
-21
-22.5
-24
-25.5
-27
-28.5
-30
-31.5
-33
-34.5
-36
-37.5
-39
-40.5
-42
-43.5
-45
-46.5
-48
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88
TABLE 67. DAC_ALC_4 (0xA3h)
Description
Bits
Field
4:0
ATTACK_RATE This sets the rate at which the ALC will reduce gain if it detects the input
signal is too large.
ATTACK_RATE
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Time between gain steps (μs)
21
42
83
167
250
333
417
542
729
958
1250 (Default)
1604
1896
2208
2792
3708
4792
5688
6563
8396
11000
14167
17083
20000
25000
32000
45000
60000
75000
87500
100000
114583
89
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TABLE 68. DAC_ALC_5 (0xA4h)
Description
Bits
Field
4:0
DECAY_RATE
This sets the rate at which the ALC will increase gain if it detects the input
signal is too small.
DECAY_RATE
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Time between gain steps(us)
104
125
167
250
292
396
500
708
896
1250
1396 (Default)
2000
2708
3500
4750
6250
8000
11000
14000
18500
25000
32000
42000
55000
72500
100000
125000
160000
225000
300000
375000
500000 (0.5s)
7:5
PK_DECAY_RATE This sets how precise the ALC will track amplitude reductions of the audio
input. The shorter the length of time for PK_DECAY_RATE, the more
responsive the ALC will be when applying gain increases whenever the audio
falls below target level.
PK_DECAY_RATE
Time
1.3ms (Default)
2.6ms
000
001
010
011
100
101
110
111
5.3ms
10.6ms
21.3ms
42.6ms
85.5ms
2.73secs
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90
TABLE 69. DAC_ALC_6 (0xA5h)
Description
This sets how long the ALC circuit waits before increasing the gain.
Bits
Field
4:0
HOLD_TIME
HOLDTIME
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Time (ms)
1
1.25
1.6
2
2.5
3.2
4
5
6.25
8
10 (Default)
12.5
16
20
25
32
40
50
64
80
100
125
160
200
250
320
400
500
640
800
1000
1250
TABLE 70. DAC_ALC_7 (0xA6h)
Bits
Field
Description
5:0
MAX_LEVEL
This sets the maximum allowed gain to the digital level control when the
ALC is used.
TABLE 71. DAC_ALC_8 (0xA7h)
Description
Bits
Field
5:0
MIN_LEVEL
This sets the minimum allowed gain to the digital level control when the ALC
is used.
91
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TABLE 72. DAC_L_LEVEL (0xA8h)
Description
DAC_L_LEVEL This sets the pre DAC digital gain.
Bits
Field
5:0
DAC_L_LEVEL
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
Level
-76.5dB
-75dB
DAC_L_LEVEL
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Level
-28.5dB
-27dB
-25.5dB
-24dB
-22.5dB
-21dB
-20.5dB
-18dB
-16.5dB
-15dB
-13.5dB
-12dB
-10.5dB
-9dB
-73.5dB
-72dB
-70.5dB
-69dB
-67.5dB
-66dB
-64.5dB
-63dB
-61.5dB
-60dB
-58.5dB
-57dB
-55.5dB
-54dB
-7.5dB
-6dB
-52.5dB
-51dB
-4.5dB
-3dB
-49.5dB
-48dB
-1.5dB
0dB
-46.5dB
-45dB
1.5dB
3dB
-43.5dB
-42dB
4.5dB
6dB
-40.5dB
-39dB
7.5dB
9dB
-37.5dB
-36dB
10.5dB
12dB
-34.5dB
-33dB
13.5dB
15dB
-31.5dB
-30dB
16.5dB
18dB
6
STEREO_LINK If set, this links DAC_R_LEVEL with DAC_L_LEVEL.
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92
TABLE 73. DAC_R_LEVEL (0xA9h)
Description
DAC_R_LEVEL This sets the pre DAC digital gain.
Bits
Field
5:0
DAC_R_LEVEL
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
Level
-76.5dB
-75dB
DAC_R_LEVEL
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Level
-28.5dB
-27dB
-25.5dB
-24dB
-22.5dB
-21dB
-20.5dB
-18dB
-16.5dB
-15dB
-13.5dB
-12dB
-10.5dB
-9dB
-73.5dB
-72dB
-70.5dB
-69dB
-67.5dB
-66dB
-64.5dB
-63dB
-61.5dB
-60dB
-58.5dB
-57dB
-55.5dB
-54dB
-7.5dB
-6dB
-52.5dB
-51dB
-4.5dB
-3dB
-49.5dB
-48dB
-1.5dB
0dB
-46.5dB
-45dB
1.5dB
3dB
-43.5dB
-42dB
4.5dB
6dB
-40.5dB
-39dB
7.5dB
9dB
-37.5dB
-36dB
10.5dB
12dB
-34.5dB
-33dB
13.5dB
15dB
-31.5dB
-30dB
16.5dB
18dB
93
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TABLE 74. EQ_BAND_1 (0xABh)
Description
Bits
Field
1:0
FREQ
This sets the Sub-bass shelving filter's cut-off frequency. The cut-off
frequencies shown are based on a 48kHz sample rate. Using lower sample
rates will scale down the cut-off frequencies proportionately.
FREQ
00
Frequency (Hz)
60
80
01
10
100
120
11
6:2
LEVEL
This sets the gain at fC.
LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
1dB
2dB
3dB
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
13dB
14dB
15dB
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94
TABLE 75. EQ_BAND_2 (0xACh)
Description
Bits
Field
1:0
FREQ
This sets the Bass peak filter's center frequency. The cut-off frequencies shown
are based on a 48kHz sample rate. Using lower sample rates will scale down
the cut-off frequencies proportionately.
FREQ
00
Frequency (Hz)
150
200
250
300
01
10
11
6:2
LEVEL
This sets the gain at fC.
LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
1dB
2dB
3dB
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
13dB
14dB
15dB
7
Q
This programs the width of the peak filter.
Q
0
Bandwidth
2/3 Octave
4/3 Octave
1
95
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TABLE 76. EQ_BAND_3 (0xADh)
Description
Bits
Field
1:0
FREQ
This sets the Mid peak filter's center frequency. The cut-off frequencies shown
are based on a 48kHz sample rate. Using lower sample rates will scale down
the cut-off frequencies proportionately.
FREQ
00
Frequency (Hz)
600
800
1k
01
10
11
1.2k
6:2
LEVEL
This sets the gain at fC.
LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
1dB
2dB
3dB
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
13dB
14dB
15dB
7
Q
This programs the width of the peak filter.
Q
0
Bandwidth
2/3 Octave
4/3 Octave
1
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96
TABLE 77. EQ_BAND_4 (0xAEh)
Description
Bits
Field
1:0
FREQ
This sets the Treble peak filter's center frequency. The cut-off frequencies
shown are based on a 48kHz sample rate. Using lower sample rates will scale
down the cut-off frequencies proportionately.
FREQ
00
Frequency (Hz)
2k
01
2.7k
3.4k
4.1k
10
11
6:2
LEVEL
This sets the gain at fC.
LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
1dB
2dB
3dB
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
13dB
14dB
15dB
7
Q
This programs the width of the peak filter.
Q
0
Bandwidth
2/3 Octave
4/3 Octave
1
97
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TABLE 78. EQ_BAND_5 (0xAFh)
Description
Bits
Field
1:0
FREQ
This sets the presence shelving filter's cut-off frequency. The cut-off
frequencies shown are based on a 48kHz sample rate. Using lower sample
rates will scale down the cut-off frequencies proportionately.
FREQ
00
Frequency (Hz)
7k
9k
01
10
11k
13k
11
6:2
LEVEL
This sets the gain at fC.
LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Effect
Off (0dB)
-15dB
-14dB
-13dB
-12dB
-11dB
-10dB
-9dB
-8dB
-7dB
-6dB
-5dB
-4dB
-3dB
-2dB
-1dB
0dB
1dB
2dB
3dB
4dB
5dB
6dB
7dB
8dB
9dB
10dB
11dB
12dB
13dB
14dB
15dB
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98
TABLE 79. SOFTCLIP1 (0xB0h)
Description
Bits
Field
3:0
TRESHOLD
This sets the threshold level of the audio compressor. Audio signals above the
threshold will be compressed.
THRESHOLD
0000
Threshold Level (dB)
-36dB
0001
-30dB
0010
-24dB
0011
-20dB
0100
-18dB
0101
-17dB
0110
-16dB
0111
-15dB
1000
-14dB
1001
-12dB
1010
-10dB
1011
-8dB
1100
-6dB
1101
-4dB
1110
-2.5dB
-1dB
1111
4
SOFT_KNEE
If set, the audio compressor will automatically apply higher compression ratios
to audio signals higher than the threshold level. As the audio signal approaches
levels higher than the threshold, SOFT_KNEE will increase the compression
RATIO. The highest compression that the SOFT_KNEE algorithm will apply is
the compression that is set by RATIO.
99
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TABLE 80. SOFTCLIP2 (0xB1h)
Description
Bits
Field
4:0
RATIO
This sets the ratio at which the audio is compressed to when it passes beyond
the threshold. In soft clip mode this is the final level of compression.
RATIO
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Ratio
1:1 (Bypass)
1:1.2
1:1.4
1:1.7
1:2.0
1:2.4
1:2.8
1:3.4
1:4.0
1:4.7
1:5.7
1:6.7
1:8.0
1:9.5
1:11.3
1:13.5
1:16.0
1:19.0
1:22.8
1:27.0
1:32.0
1:37.9
1:45.5
1:53.9
1:64
1:75.9
1:91.0
1:108
1:128
1:152
1:182
1:215
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100
TABLE 81. SOFTCLIP3 (0xB2h)
Description
Bits
Field
4:0
LEVEL
This sets the post compressor gain level.
LEVEL
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Level (dB)
-22.5dB
-21dB
-19.5dB
-18dB
-16.5dB
-15dB
-13.5dB
-12dB
-10.5dB
-9dB
-7.5dB
-6dB
-4.5dB
-3dB
-1.5dB
0dB
1.5dB
3dB
4.5dB
6dB
7.5dB
9dB
10.5dB
12dB
13.5dB
15dB
16.5dB
18dB
19.5dB
21dB
22.5dB
24dB
101
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26.0 GPIO Registers
TABLE 82. GPIO1 (0xE0h)
Description
Bits
Field
5:0
GPIO_MODE This sets the mode of the GPIO Pin.
GPIO_MODE
GPIO STATUS
000000
GPIO Mode is disabled .PORT2_SDO is controlled by the Port2
serial interface configuration. In all the other modes
PORT2_SDO is configured as the GPIO pin.
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
GPIO_RX (in)
CHIP ENABLE (in)
CHIP ENABLE (in)
ADC MUTE (in)
ADC MUTE (in)
HP SENSE (in)
HP SENSE (in)
SPARE (in)
SPARE (in)
GPIO TX (out)
CHIP ACTIVE (out)
CHIP ACTIVE (out)
HP ENABLE (out)
HP ENABLE (out)
LS ENABLE (out)
LS ENABLE (out)
EP ENABLE (out)
EP ENABLE (out)
ADC CLIPPED (out)
ADC CLIPPED (out)
DAC CLIPPED (out)
DAC CLIPPED (out)
SOMETHING CLIPPED (out)
SOMETHING CLIPPED (out)
ADC NG ACTIVE (out)
ADC NG ACTIVE (out)
DAC NG ACTIVE (out)
DAC NG ACTIVE (out)
THERMAL (out)
THERMAL (out)
LS SHORT CCT (out)
LS SHORT CCT (out)
5:0
GPIO_MODE
ANALOG ERROR
Thermal or LS CCT condition (out)
100001
100010
100011
ANALOG ERROR (out)
ERROR (out)
Thermal or LS CCT or Clipping
100100
ERROR (out)
RESERVED
100101 – 111111
6
7
GPIO_TX
GPIO_RX
Whenever GPIO_MODE is set to '001010', the GPIO pin will output a logic level
based on this bit setting. Setting this bit high will result in a logic high GPIO output.
This bit reports the logic level is present on the GPIO pin.
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102
TABLE 83. GPIO2 (0xE1h)
Description
Bits
Field
0
SHORT
This bit will go high whenever a short circuit condition occurs on the Class D
loudspeaker amplifier outputs. Once triggered by a short circuit event, an I2C write
of 1 to this bit clear this bit.
1
TEMP
This bit will go high whenever the temperature of the LM49352 reaches a critical
temperature. Once triggered by a thermal event, an I2C write of 1 to this bit clear
this bit.
TABLE 84. RESET (0xF0h)
Bits
4:0
5
Field
RSVD
Description
Reserved.
SOFT_RESET
Setting this bit resets the digital core of LM49352. SOFT_RESET does not affect
the current I2C register settings.
TABLE 85. Spread Spectrum (0xF1h)
Bits
1:0
2
Field
RSVD
Description
Reserved
SS_DISABLE
If this bit is set, Spread Spectrum mode will be disabled from the Class D amplifier.
TABLE 86. FORCE (0xFE)
Bits
0
Field
RSVD
Description
Reserved
1
DACREF
This bit determines whether the DAC reference voltage is internally generated or
externally driven.
DACREF
STATUS
0
1
DACREF uses an internal bandgap reference.
DACREF is driven by an external voltage reference.
2
CP_FORCE
If set, a -LS_VDD rail will be generated on HP_VSS, even if the headphone output
stage is not required.
103
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27.0 Schematic Diagram
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104
28.0 Demonstration Board Layout
30072721
FIGURE 28. Top Silkscreen
30072782
FIGURE 29. Top Layer
105
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30072780
FIGURE 30. Inner Layer 2
30072781
FIGURE 31. Inner Layer 3
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106
30072779
FIGURE 32. Bottom Layer
30072778
FIGURE 33. Bottom Silkscreen
107
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29.0 Revision History
Rev
1.0
Date
Description
05/03/10
06/30/10
Initial released.
Fixed a typo in the I2C Timing Parameters table.
1.01
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108
30.0 Physical Dimensions inches (millimeters) unless otherwise noted
micro SMD–36 Package
Order Number LM49352RL
NS Package Number RLA36MMA
X1 = 3.281±.03mm, X2 = 3.281±.03mm, X3 = 0.65±.075mm
109
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Notes
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