LM4935WLX_技术文档

October 2005

LM4935

Audio Sub-System with Dual-Mode Stereo Headphone &

Mono High Efficiency Loudspeaker Amplifiers and

Multi-Purpose ADC

j

1.0 General Description

Supply Voltage Range

BB_V_DD= 1.8V to 4.5V,

The LM4935 is an integrated audio subsystem that supports

both analog and digital audio functions. The LM4935 in-

cludes a high quality stereo DAC, a mono ADC, a multi-

purpose SAR ADC, a stereo headphone amplifier, which

supports output cap-less (OCL) or AC-coupled (SE)modes of

operation, a mono earpiece amplifier and a mono high effi-

ciency loudspeaker amplifier. It is designed for demanding

applications in mobile phones and other portable devices.

D_V_DD& PLL_V_DD= 2.7V to 4.5V

LS_V_DD& A_V_DD= 2.7V to 5.5V

n Shutdown Current

n PSRR 217 Hz, A_V_DD= 3.3V, (Headphone)

n SNR (Stereo DAC to AUXOUT)

n SNR (Mono ADC from Cell Phone In)

n SNR (Aux In to Headphones)

1.1 µA

60 dB

88 dB (typ)

90 dB (typ)

98 dB (typ)

@

The LM4935 features a bi-directional I²S serial interface for

full range audio and an I²C or SPI compatible interface for

control. The stereo DAC path features an SNR of 88 dB with

an 18-bit 48 kHz input. In SE mode the headphone amplifier

delivers at least 33 mW_RMSto a 32Ω single-ended stereo

4.0 Features

n 18-bit stereo DAC

n 16-bit mono ADC

load with less than 1% distortion (THD+N) when A_V_DD

=

n 12-bit 4 input multipurpose SAR ADC

n 8 kHz to 48 kHz stereo audio playback

n 8 kHz to 48 kHz mono recording

n 1 Hz to 13.888 kHz sample rate on all 4 SAR channels

n Bidirectional PCM/I²S compatible audio interface

n Sigma-Delta PLL for operation from any clock at any

sample rate

3.3V. The mono earpiece amplifier delivers at least 115

mW_RMSto a 32Ω bridged-tied load with less than 1% distor-

tion (THD+N) when A_V_DD= 3.3V. The mono speaker am-

plifier delivers up to 600 mW into an 8Ω load with less than

1% distortion when LS_V_DD= 3.3V and up to 1.3W when

LS_V_DD= 5.0V. The LM4935 also contains a general pur-

pose SAR ADC for housekeeping duties such as battery and

temperature monitoring. This can also be used for analog

volume control of the output stages and can trigger interrupt

events.

n Low power clock network operation if 12 MHz system

clock is available

n Read/write I²C or SPI compatible control interface

n 33mW stereo headphone amplifier at 3.3V

n OCL or AC-coupled headphone operation

n Automatic headphone & microphone detection

n Support for internal and external microphones

n Automatic gain control for microphone input

The LM4935 employs advanced techniques to reduce power

consumption, to reduce controller overhead to speed devel-

opment time and to eliminate click and pop. Boomer audio

power amplifiers were designed specifically to provide high

quality output power with a minimal amount of external com-

ponents. It is therefore ideally suited for mobile phone and

other low voltage applications where minimal power con-

sumption, PCB area and cost are primary requirements.

@

n High efficiency BTL 8Ω amplifier, 600 mW 3.3V

n 115 mW earpiece amplifier at 3.3V

n Differential audio I/O for external cellphone module

n Mono differential auxiliary output

n Stereo auxiliary inputs

2.0 Applications

n Smartphones

n Mobile Phones and Multimedia Terminals

n PDAs, Internet Appliances and Portable Gaming

n Portable DVD/CD/AAC/MP3 Players

n Digital Cameras/Camcorders

n Differential microphone input for internal microphone

n Flexible audio routing from input to output

n 32 Step volume control for mixers with 1.5 dB steps

n 16 Step volume control for microphone in 2 dB steps

n Programmable sidetone attenuation in 3 dB steps

n DC Volume Control

n Two configurable GPIO ports

n Programmable voltage triggers on SAR channels

n Multi-function IRQ output

3.0 Key Specifications

@

n P_{HP (AC-COUP)}A_V_DD= 3.3V, 32Ω, 1% THD

33 mW

31 mW

1.3 W

900 mW

600 mW

@

n P_{HP (OCL)}A_V_DD= 3.3V, 32Ω, 1% THD

@

n P_LSLS_V_DD= 5V, 8Ω, 1% THD

n Micro-power shutdown mode

n Available in the 4 x 4 mm 49 bump microfil package

@

n P_LSLS_V_DD= 4.2V, 8Ω, 1% THD

@

n P_LSLS_V_DD= 3.3V, 8Ω, 1% THD

Boomer^®is a registered trademark of National Semiconductor Corporation.

DS201341

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5.0 LM4935 Overview

20134101

FIGURE 1. Conceptual Schematic

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6.0 Typical Application

20134102

FIGURE 2. Example Application in Multimedia Mobile Phone

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Table of Contents

1.0 General Description ..................................................................................................................................... 1

2.0 Applications .................................................................................................................................................. 1

3.0 Key Specifications ........................................................................................................................................ 1

4.0 Features ....................................................................................................................................................... 1

5.0 LM4935 Overview ........................................................................................................................................ 2

6.0 Typical Application ........................................................................................................................................ 3

7.0 Connection Diagrams ................................................................................................................................... 6

7.1 PIN TYPE DEFINITIONS .......................................................................................................................... 7

8.0 Absolute Maximum Ratings ........................................................................................................................ 8

9.0 Operating Ratings ........................................................................................................................................ 8

10.0 Electrical Characteristics ........................................................................................................................... 8

11.0 System Control ......................................................................................................................................... 16

11.1 I²C SIGNALS ......................................................................................................................................... 16

11.2 I²C DATA VALIDITY ............................................................................................................................... 16

11.3 I²C START AND STOP CONDITIONS .................................................................................................. 16

11.4 TRANSFERRING DATA ........................................................................................................................ 16

11.5 I²C TIMING PARAMETERS ................................................................................................................. 18

12.0 Status & Control Registers ...................................................................................................................... 20

12.1 BASIC CONFIGURATION REGISTER ................................................................................................. 21

12.2 CLOCKS CONFIGURATION REGISTER ............................................................................................. 22

12.3 LM4935 CLOCK NETWORK ................................................................................................................ 23

12.4 COMMON CLOCK SETTINGS FOR THE DAC & ADC ....................................................................... 24

12.5 PLL M DIVIDER CONFIGURATION REGISTER .................................................................................. 25

12.6 PLL N DIVIDER CONFIGURATION REGISTER .................................................................................. 26

12.7 PLL P DIVIDER CONFIGURATION REGISTER .................................................................................. 27

12.8 PLL N MODULUS CONFIGURATION REGISTER ............................................................................... 28

12.9 FURTHER NOTES ON PLL PROGRAMMING ..................................................................................... 29

12.10 ADC_1 CONFIGURATION REGISTER ............................................................................................... 31

12.11 ADC_2 CONFIGURATION REGISTER ............................................................................................... 32

12.12 AGC_1 CONFIGURATION REGISTER ............................................................................................. 33

12.13 AGC_2 CONFIGURATION REGISTER ............................................................................................. 34

12.14 AGC_3 CONFIGURATION REGISTER ............................................................................................. 35

12.15 AGC OVERVIEW ................................................................................................................................. 36

12.16 MIC_1 CONFIGURATION REGISTER ............................................................................................... 37

12.17 MIC_2 CONFIGURATION REGISTER ............................................................................................... 38

12.18 SIDETONE ATTENUATION REGISTER ............................................................................................. 39

12.19 CP_INPUT CONFIGURATION REGISTER ........................................................................................ 40

12.20 AUX_LEFT CONFIGURATION REGISTER ........................................................................................ 41

12.21 AUX_RIGHT CONFIGURATION REGISTER ...................................................................................... 42

12.22 DAC CONFIGURATION REGISTER .................................................................................................. 43

12.23 CP_OUTPUT CONFIGURATION REGISTER .................................................................................... 44

12.24 AUX_OUTPUT CONFIGURATION REGISTER .................................................................................. 45

12.25 LS_OUTPUT CONFIGURATION REGISTER ..................................................................................... 46

12.26 HP_OUTPUT CONFIGURATION REGISTER .................................................................................... 47

12.27 EP_OUTPUT CONFIGURATION REGISTER .................................................................................... 48

12.28 DETECT CONFIGURATION REGISTER ............................................................................................ 49

12.29 HEADSET DETECT OVERVIEW ........................................................................................................ 50

12.30 STATUS REGISTER ........................................................................................................................... 53

12.31 AUDIO INTERFACE CONFIGURATION REGISTER ......................................................................... 54

12.32 DIGITAL AUDIO DATA FORMATS ...................................................................................................... 55

12.33 GPIO CONFIGURATION REGISTER ................................................................................................. 56

12.34 SAR CHANNELS 0 & 1 CONFIGURATION REGISTER .................................................................... 57

12.35 SAR CHANNELS 2 & 3 CONFIGURATION REGISTER .................................................................... 58

12.36 SAR DATA 0 TO 3 REGISTERS ......................................................................................................... 59

12.37 SAR OVERVIEW ................................................................................................................................. 60

12.38 DC VOLUME CONFIGURATION REGISTER .................................................................................... 62

12.39 SAR TRIGGER 1 CONFIGURATION REGISTER .............................................................................. 63

12.40 SAR TRIGGER 1 MSBs CONFIGURATION REGISTER ................................................................... 64

12.41 SAR TRIGGER 2 CONFIGURATION REGISTER .............................................................................. 65

12.42 SAR TRIGGER 2 MSBs CONFIGURATION REGISTER ................................................................... 66

12.43 DEBUG REGISTER ........................................................................................................................... 67

13.0 Typical Performance Characteristics ....................................................................................................... 68

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Table of Contents (Continued)

14.0 LM4935 Demonstration Board Schematic Diagram .............................................................................. 104

15.0 Demoboard PCB Layout ........................................................................................................................ 105

16.0 Product Status Definitions ...................................................................................................................... 110

17.0 Revision History ...................................................................................................................................... 111

18.0 Physical Dimensions .............................................................................................................................. 112

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7.0 Connection Diagrams

49 Bump Microfil

49 Bump Microfil Marking

201341P5

Top View

XY — Date Code

TT — Die Traceability

G — Boomer

F4 — LM4935WL/WLX

201341P3

Top View (Bump Side Down)

Order Number LM4935

See NS Package Number WLA49VVA

Pin Descriptions

A1

A2

A3

A4

A5

A6

A7

B1

B2

B3

B4

Pin Name

EP_NEG

A_V_DD

Type Direction

Description

Analog

Supply

Output

Input

Output

Input

Inout

Input

Earpiece negative output

Headphone and mixer V_DD

Internal microphone positive input

External microphone input

Input to SAR channel 2

Input to SAR channel 1

PLL V_SS

INT_MIC_POS Analog

EXT_MIC

VSAR2

Analog

Supply

Analog

VSAR1

PLL_V_SS

A_V_SS

Headphone and mixer V_SS

Earpiece positive output

Internal microphone negative input

A_V_DD/2 filter point

EP_POS

INT_MIC_NEG Analog

BYPASS Analog

B5 TEST_MODE/CS Digital

If SPI_MODE = 1, then this pin becomes CS. If SPI_MODE = 0,

and TEST_MODE/CS = 1, then this places the LM4935 into test mode.

Filter point for PLL VCO input

B6

B7

C1

C2

C3

C4

C5

C6

C7

D1

D2

D3

D4

D5

D6

D7

E1

PLL_FILT

PLL_V_DD

HP_R

Analog

Supply

Analog

Digital

Analog

Digital

Supply

Analog

Inout

Input

Output

Input

Inout

Input

Output

Inout

Input

Inout

Input

Inout

PLL V_DD

Headphone Right Output

EXT_BIAS

INT_BIAS

AUX_R

External microphone supply (2.0/2.5/2.8/3.3V)

2.0V/2.5V ultra-clean supply for internal microphone

Right Analog Input

GPIO_2

SDA

General Purpose I/O 2

Control Data, I2C_SDA or SPI_SDI

Control Clock, I2C_SCL or SPI_SCK

Headphone Left Output

SCL

HP_L

VREF_FLT

AUX_L

Filter point for the microphone power supply

Left Analog Input

SPI_MODE

GPIO_1

BB_V_DD

D_V_DD

Control mode select 1 = SPI, 0 = I2C (or test)

General Purpose I/O 1

Baseband V_DDfor the digital I/Os

Digital V_DD

HP_VMID

Virtual Ground for Headphones in OCL mode, otherwise 1st headset detection input

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7.0 Connection Diagrams (Continued)

Pin Descriptions (Continued)

E2

E3

E4

E5

E6

E7

F1

F2

F3

F4

Pin Name

HP_VMID_FB

MIC_DET

CPI_NEG

IRQ

Type Direction

Description

VMID Feedback in OCL mode, otherwise a 2nd headset detection input

Headset insertion/removal and Microphone presence detection input

Cell Phone analog input negative

Interrupt request signal (NOT open drain)

I2S Serial Data Out

Analog

Digital

Supply

Analog

Inout

Input

Output

Input

I2S_SDO

I2S_SDI

I2S Serial Data Input

LS_V_DD

Input

Loudspeaker V_DD

LS_V_DD

Input

Loudspeaker V_DD

CPI_POS

CPO_NEG

Input

Cell Phone analog input positive

Cell Phone analog output negative

Auxiliary analog output negative

I2S Word Select Signal (can be master or slave)

I2S Clock Signal (can be master or slave)

Loudspeaker positive output

Output

Inout

F5 AUX_OUT_NEG Analog

F6

F7

I2S_WS

I2S_CLK

LS_POS

LS_V_SS

Digital

Analog

Supply

Analog

Inout

G1

G2

G3

G4

Output

Input

Loudspeaker V_SS

LS_NEG

CPO_POS

Output

Input

Loudspeaker negative output

Cell Phone analog output positive

Auxiliary analog output positive

Digital V_SS

G5 AUX_OUT_POS Analog

G6

G7

D_V_SS

MCLK

Supply

Digital

Input

Input clock from 0.5 MHz to 30 MHz

never driven.

7.1 PIN TYPE DEFINITIONS

Analog Input— A pin that is used by the analog and is

never driven by the device. Supplies are

part of this classification.

Digital Output— A pin that is driven by the device and

should not be driven by another device to

avoid contention.

Analog Output— A pin that is driven by the device and

should not be driven by external sources.

Digital Inout—

A pin that is either open drain (I2C_SDA)

or a bidirectional CMOS in/out. In the

later case the direction is selected by a

control register within the LM4935.

Analog Inout— A pin that is typically used for filtering a

DC signal within the device, Passive com-

ponents can be connected to these pins.

Digital Input—

A pin that is used by the digital but is

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8.0 Absolute Maximum Ratings

Thermal Resistance

θ_JA– WLA49 (soldered down

to PCB with 2in²1oz. copper

plane)

(Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

60˚C/W

Soldering Information

See AN-1279 for Microfil^TMpackage information. Peak

Analog Supply Voltage

reflow temperature should not exceed 235˚C.

(A_V_DD& LS_V_DD

)

6.0V

Digital Supply Voltage

(BB_V_DD& D_V_DD& PLL_V_DD

Storage Temperature

)

6.0V

−65˚C to +150˚C

Internally Limited

9.0 Operating Ratings

Temperature Range

Supply Voltage

D_V_DD/PLL_V_DD

BB_V_DD

−40˚C to +85˚C

Power Dissipation (Note 3)

ESD Susceptibility

2.7V to 4.5V

1.8V to 4.5V

2.7V to 5.5V

Human Body Model (Note 4)

Machine Model (Note 5)

Junction Temperature

2500V

200V

LS_V_DD/A_V_DD

150˚C

10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_V_DD= 3.3V, D_V_DD= 3.3V,

BB_V_DD= 1.8V, A_V_DD= 3.3V, LS_V_DD= 3.3V. The following specifications apply for the circuit shown in Figure 2 unless

otherwise stated. Limits apply for 25˚C.

LM4935

Symbol

DC CURRENT CONSUMPTION

DI_SDDigital Shutdown Current

Parameter

Conditions

Units

Typical

(Note 6)

Limit

(Note 7)

Chip Mode ’00’, f_MCLK= 13MHz

Chip Mode ’00’, f_MCLK= 19.2MHz

0.7

µA

5

3

(max)

mA

Chip Mode ’01’, f_MCLK= 13MHz

Chip Mode ’01’, f_MCLK= 19.2MHz

1.5

2.2

DI_ST

Digital Standby Current

mA

(max)

Chip Mode ’10’, f_MCLK= 13MHz,

DAC, ADC, SAR OFF

1.5

2.2

mA

Chip Mode ’10’, f_MCLK= 19.2MHz,

DAC, ADC, SAR OFF

DI_DD

Digital Active Current

Chip Mode ’10’, f_MCLK= 13MHz

DAC, ADC, SAR ON

11.2

16.2

0.2

Chip Mode ’10’, f_MCLK= 19.2MHz,

DAC, ADC, SAR ON

mA

(max)

µA

20

3

AI_SD

AI_ST

Analog Shutdown Current

Analog Standby Current

Chip Mode ’00’

(max)

µA

Chip Mode ’01’,

0.2

3

No headset inserted

(max)

mA

All Outputs OFF, SE MODE

All Outputs OFF, OCL MODE

All Outputs ON, SE MODE

All Outputs ON, OCL MODE

6.1

5.7

mA

AI_DD

Analog Active Current

18.3

mA

18.7

4.2

28

(max)

f_MCLK= 13 MHz

mA

f_PLLOUT= 12 MHz, PLL ON only

f_MCLK= 19.2 MHz

PLLI_DD

PLL Active Current

ADC Active Current

6.2

f_PLLOUT= 12 MHz, PLL ON only

f_MCLK= 13MHz, ADC ON only

f_MCLK= 19.2MHz, ADC ON only

ADCI_DD

2.5

3.6

mA

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10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_V_DD= 3.3V, D_V_DD= 3.3V,

BB_V_DD= 1.8V, A_V_DD= 3.3V, LS_V_DD= 3.3V. The following specifications apply for the circuit shown in Figure 2 unless

otherwise stated. Limits apply for 25˚C. (Continued)

LM4935

Symbol

Parameter

Conditions

Units

Typical

Limit

(Note 6)

(Note 7)

DC CURRENT CONSUMPTION

f_MCLK= 13MHz, DAC ON only;

PLL OFF, f_S= 48kHz

f_MCLK= 19.2MHz, DAC ON only

PLL OFF; f_S= 48kHz

f_MCLK= 13MHz, SAR ON only

f_MCLK= 19.2MHz, SAR ON only

LS ON only

7.4

mA

DACI_DD

DAC Active Current

10.7

1.6

2.3

8.8

3.5

3.9

4.4

4.8

mA

SARI_DD

LSI_DD

SAR Active Current

Loudspeaker Quiescent Current

Headphone Quiescent Current

HP ON only, SE MODE

HP ON only, OCL MODE

EP ON only

HPI_DD

EPI_DD

Earpiece Quiescent Current

AUXOUT Quiescent Current

CPOUT Quiescent Current

AUXI_DD

CPOUTI_DD

AUXOUT ON only

CPOUT ON only

LOUDSPEAKER AMPLIFIER

P_LS

Max Loudspeaker Power

8Ω load, LS_V_DD= 5V

8Ω load, LS_V_DD= 4.2V

8Ω load, LS_V_DD= 3.3V

8Ω load, LS_V_DD= 3.3V,

P_O= 400mW

1.3

0.9

0.6

W

0.44

W (min)

LS_THD+N

LS_EFF

Loudspeaker Harmonic Distortion

Efficiency

0.4

84

%

0 dB Input

MCLK = 12.000 MHz

AUX inputs terminated

C_BYPASS= 1.0 µF

PSRR_LS

Power Supply Rejection Ration

(Loudspeaker)

54

dB

V_RIPPLE= 200 mV_P-P

f_RIPPLE= 217 Hz

SNR_LS

Signal to Noise Ratio

From 0 dB Analog AUX input at

1 kHz, A-weighted

A-weighted

76

e_N

Output Noise

Offset Voltage

350

7

µV

V_OS

mV

HEADPHONE AMPLIFIER

P_HP

Headphone Power

32Ω load, 3.3V, SE

mW

(min)

mW

33

20

16Ω load, 3.3V, SE

32Ω load, 3.3V, OCL, VCM = 1.5V

32Ω load, 3.3V, OCL, VCM = 1.2V

16Ω load, 3.3V, OCL, VCM = 1.5V

16Ω load, 3.3V, OCL, VCM = 1.2V

AUX inputs terminated

C_BYPASS= 1.0 µF

52

31

20

50

32

V_RIPPLE= 200 mV_P-P

f_RIPPLE= 217 Hz

Power Supply Rejection Ratio

(Headphones)

SE Mode

60

68

dB

PSRR_HP

OCL Mode

VCM = 1.2V

OCL Mode

65

dB

VCM = 1.5V

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10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_V_DD= 3.3V, D_V_DD= 3.3V,

BB_V_DD= 1.8V, A_V_DD= 3.3V, LS_V_DD= 3.3V. The following specifications apply for the circuit shown in Figure 2 unless

otherwise stated. Limits apply for 25˚C. (Continued)

LM4935

Symbol

Parameter

Conditions

Units

Typical

Limit

(Note 6)

(Note 7)

HEADPHONE AMPLIFIER

From 0dB Analog AUX input

A-weighted

SE Mode

98

97

dB

SNR_HP

Signal to Noise Ratio

OCL Mode

VCM = 1.2V

OCL Mode

96

dB

VCM = 1.5V

HP_THD+N

e_N

Headphone Harmonic Distortion

Output Noise

32Ω load, 3.3V, P_O= 7.5mW

A-weighted

0.05

12

%

µV

∆A_CH-CH

Stereo Channel-to-Channel Gain

Mismatch

0.3

dB

SE Mode

61

63

dB

X_TALK

Stereo Crosstalk

OCL Mode

EARPIECE AMPLIFIER

P_EP

Earpiece Power

32Ω load, 3.3V

mW

(min)

mW

115

150

100

16Ω load, 3.3V

PSRR_EP

Power Supply Rejection Ratio

(Earpiece)

AUX inputs terminated

C_BYPASS= 1.0 µF

V_RIPPLE= 200 mV_P-P

F_RIPPLE= 217 Hz

65

dB

SNR_EP

Signal to Noise Ratio

From 0dB Analog AUX input,

A-weighted

98

dB

EP_THD+N

e_N

Earpiece Harmonic Distortion

Output Noise

32Ω load, 3.3V, P_O= 50mW

A-weighted

0.04

24

%

µV

mV

V_OS

Offset Voltage

15

AUXOUT AMPLIFIER

THD+N

PSRR

Total Harmonic Distortion + Noise

Power Supply Rejection Ratio

V_O= 1V_RMS, 5kΩ load

AUX inputs terminated

C_BYPASS= 1.0µF

0.02

70

%

dB

V_RIPPLE= 200mVPP

f_RIPPLE= 217Hz

CP_OUT AMPLIFIER

THD+N

PSRR

Total Harmonic Distortion + Noise

V_O= 1V_RMS, 5kΩ load

C_BYPASS= 1.0µF

0.02

68

%

Power SUpply Rejection Ratio

V_RIPPLE= 200mVPP

f_RIPPLE= 217Hz

dB

MONO ADC

R_ADC

ADC Ripple

0.25

300

dB

Hz

dB

PB_ADC

ADC Passband

Lower (HPF Mode 1), f_S= 8 kHz

Upper

3470

60

SBA_ADC

ADC Stopband Attenuation

Above Passband

HPF Notch, 50 Hz/60 Hz (worst

case)

58

dB

SNR_ADC

ADC Signal to Noise Ratio

ADC Full Scale Input Level

From CPI, A-weighted

90

1

dB

ADC_LEVEL

V_RMS

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10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_V_DD= 3.3V, D_V_DD= 3.3V,

BB_V_DD= 1.8V, A_V_DD= 3.3V, LS_V_DD= 3.3V. The following specifications apply for the circuit shown in Figure 2 unless

otherwise stated. Limits apply for 25˚C. (Continued)

LM4935

Symbol

Parameter

Conditions

Units

Typical

Limit

(Note 6)

(Note 7)

STEREO DAC

R_DAC

DAC Ripple

0.1

20

70

88

96

1

dB

kHz

dB

PB_DAC

DAC Passband

SBA_DAC

SNR_DAC

DR_DAC

DAC_LEVEL

PLL

DAC Stopband Attenuation

DAC Signal to Noise Ratio

DAC Dynamic Range

A-weighted, AUXOUT

dB

DAC Full Scale Output Level

V_RMS

F_IN

Input Frequency Range

Min

0.5

30

MHz

Max

I2S/PCM

f_S= 48kHz; 16 bit mode

f_S= 48kHz; 25 bit mode

f_S= 8kHz; 16 bit mode

f_S= 8kHz; 25 bit mode

f_S= 48kHz; 16 bit mode

f_S= 48kHz; 25 bit mode

f_S= 8kHz; 16 bit mode

f_S= 8kHz; 25 bit mode

Min

1.536

2.4

MHz

% (min)

%

f_I2SCLK

I2S CLK Frequency

0.256

0.4

0.768

1.2

f_PCMCLK

PCM CLK Frequency

I2S_CLK Duty Cycle

0.128

0.2

DC_{I2S_CLK}

40

60

Max

(max)

%

DC_{I2S_WS}

I2C

I2S_WS Duty Cycle

50

T_I2CSET

T_I2CHOLD

SPI

I2C Data Setup Time

I2C Data Hold Time

Refer to Pg. 18 for more details

100

300

ns (min)

T_SPISETENB

Enable Setup Time

100

500

ns (min)

T_SPIHOLD-ENBEnable Hold Time

T_SPISETD

T_SPIHOLDD

T_SPICL

Data Setup Time

Data Hold Time

Clock Low Time

Clock High Time

T_SPICH

VOLUME CONTROL

Minimum Gain w/ AUX_BOOST OFF

Maximum Gain w/ AUX_BOOST

OFF

–46.5

0

dB

VCR_AUX

AUX Volume Control Range

Minimum Gain w/ AUX_BOOST ON

Maximum Gain w/ AUX_BOOST ON

Minimum Gain w/ DAC_BOOST OFF

Maximum Gain w/ DAC_BOOST

OFF

–34.5

12

dB

–46.5

0

VCR_DAC

DAC Volume Control Range

CPIN Volume Control Range

Minimum Gain w/ DAC_BOOST ON

Maximum Gain w/ DAC_BOOST ON

Minimum Gain

–34.5

12

dB

–34.5

12

VCR_CPIN

Maximum Gain

11

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10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_V_DD= 3.3V, D_V_DD= 3.3V,

BB_V_DD= 1.8V, A_V_DD= 3.3V, LS_V_DD= 3.3V. The following specifications apply for the circuit shown in Figure 2 unless

otherwise stated. Limits apply for 25˚C. (Continued)

LM4935

Symbol

Parameter

Conditions

Units

Typical

Limit

(Note 6)

(Note 7)

VOLUME CONTROL

Minimum Gain

6

36

–30

0

dB

VCR_MIC

MIC Volume Control Range

Maximum Gain

Minimum Gain

Maximum Gain

VCR_SIDE

SIDETONE Volume Control Range

SS_AUX

SS_DAC

SS_CPIN

SS_MIC

SS_SIDE

AUX VCR Stepsize

DAC VCR Stepsize

CPIN VCR Stepsize

MIC VCR Stepsize

1.5

2

SIDETONE VCR Stepsize

3

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12

10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_V_DD= 3.3V, D_V_DD= 3.3V,

BB_V_DD= 1.8V, A_V_DD= 3.3V, LS_V_DD= 3.3V. The following specifications apply for the circuit shown in Figure 2 unless

otherwise stated. Limits apply for 25˚C. (Continued)

LM4935

Symbol

Parameter

Conditions

Units

Typical

Limit

(Note 6)

(Note 7)

AUDIO PATH GAIN W/ STEREO (bit 6 of 0x00h) ENABLED (AUX_L & AUX_R signals identical and selected onto mixer)

Minimum Gain from AUX input,

BOOST OFF

–34.5

dB

Maximum Gain from AUX input,

BOOST OFF

12

dB

Loudspeaker Audio Path Gain

Minimum Gain from CPI input

Maximum Gain from CPI input

Minimum Gain from AUX input,

BOOST OFF

–22.5

24

dB

–52.5

Maximum Gain from AUX input,

BOOST OFF

–6

dB

Minimum Gain from CPI input

Maximum Gain from CPI input

Minimum Gain from MIC input using

SIDETONE path w/ VCR_MICgain =

6dB

–40.5

6

dB

Headphone Audio Path Gain

–30

Maximum Gain from MIC input using

SIDETONE path w/ VCR_MICgain =

6dB

0

dB

Minimum Gain from AUX input,

BOOST OFF

–40.5

6

dB

Maximum Gain from AUX input,

BOOST OFF

Minimum Gain from CPI input

Maximum Gain from CPI input

Minimum Gain from MIC input using

SIDETONE path w/ VCR_MICgain =

6dB

–28.5

18

dB

Earpiece Audio Path Gain

–18

Maximum Gain from MIC input using

SIDETONE path w/ VCR_MICgain =

6dB

12

dB

Minimum Gain from AUX input,

BOOST OFF

–46.5

0

dB

Maximum Gain from AUX input,

BOOST OFF

AUXOUT Audio Path Gain

Minimum Gain from CPI input

Maximum Gain from CPI input

Minimum Gain from AUX input,

BOOST OFF

–34.5

12

dB

–46.5

Maximum Gain from AUX input,

BOOST OFF

0

dB

CPOUT Audio Path Gain

Minimum Gain from MIC input

Maximum Gain from MIC input

6

dB

36

13

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10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_V_DD= 3.3V, D_V_DD= 3.3V,

BB_V_DD= 1.8V, A_V_DD= 3.3V, LS_V_DD= 3.3V. The following specifications apply for the circuit shown in Figure 2 unless

otherwise stated. Limits apply for 25˚C. (Continued)

LM4935

Symbol

Parameter

Conditions

Units

Typical

Limit

(Note 6)

(Note 7)

Total DC Power Dissipation

DAC (f_S= 48kHz) and HP ON

f_MCLK= 12MHz, PLL OFF

f_MCLK= 13MHz, PLL ON

f_PLLOUT= 12MHz

57

63

mW

MP3 Mode Power Dissipation

f_MCLK= 19.2MHz, PLL ON

f_PLLOUT= 12MHz

64

mW

AUX Inputs selected and HP ON

f_MCLK= 12MHz, PLL OFF

f_MCLK= 13MHz, PLL OFF

f_MCLK= 19.2MHz, PLL OFF

PCM DAC (f_S= 8kHz) + ADC (f_S

8kHz) and EP ON

24

25

27

mW

FM Mode Power Dissipation

=

f_MCLK= 12MHz, PLL OFF

f_MCLK= 13MHz, PLL OFF

f_MCLK= 19.2MHz, PLL ON

f_PLLOUT= 12MHz

49

50

56

mW

VOICE CODEC Mode Power

Dissipation

CP IN selected. EP and CPOUT ON

f_MCLK= 12MHz, PLL OFF

30

31

33

mW

VOICE Module Mode Power

Dissipation

f_MCLK= 13MHz, PLL OFF

f_MCLK= 19.2MHz, PLL OFF

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14

10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_V_DD= 3.3V, D_V_DD= 3.3V,

BB_V_DD= 1.8V, A_V_DD= 3.3V, LS_V_DD= 3.3V. The following specifications apply for the circuit shown in Figure 2 unless

otherwise stated. Limits apply for 25˚C. (Continued)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional but do not guarantee specific performance limits.

Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device

is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device

performance.

Note 2: All voltages are measured with respect to the relevant V pin unless otherwise specified. All grounds should be coupled as close as possible to the device.

SS

Note 3: The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJ

, θ , and the ambient temperature, T . The maximum

A

MAX JA

allowable power dissipation is P

= (T

– T )/ θ or the number given in Absolute Maximum Ratings, whichever is lower.

DMAX

JMAX A JA

Note 4: Human body model: 100pF discharged through a 1.5kΩ resistor.

Note 5: Machine model: 220pF – 240pF discharged through all pins.

Note 6: Typical values are measured at 25˚C and represent the parametric norm.

Note 7: Limits are guaranteed to Nationals AOQL (Average Outgoing Quality Level).

<

>

D_V

DD

Note 8: Best operation is achieved by maintaining 3.0V A_V

5.0 and 3.0V D_V

3.6V and A_V

.

DD

Note 9: Digital shutdown current is measured with system clock set for PLL output while the PLL is disabled.

Note 10: Disabling or bypassing the PLL will usually result in an improvement in noise measurements.

15

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11.0 System Control

Method 1. I²C Compatible Interface

11.1 I²C SIGNALS

In I²C mode the LM4935 pin SCL is used for the I²C clock SCL and the pin SDA is used for the I²C data signal SDA. Both these

signals need a pull-up resistor according to I²C specification. The I²C slave address for LM4935 is 0011010₂.

11.2 I²C DATA VALIDITY

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can

only be changed when SCL is LOW.

201341Q1

I²C Signals: Data Validity

11.3 I²C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of the I²C session. START condition is defined as SDA signal

transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH

while SCL is HIGH. The I²C master always generates START and STOP bits. The I²C bus is considered to be busy after START

condition and free after STOP condition. During data transmission, I²C master can generate repeated START conditions. First

START and repeated START conditions are equivalent, function-wise.

201341Q2

11.4 TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data

has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter

releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9^thclock

pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been

received.

After the START condition, the I²C master sends a chip address. This address is seven bits long followed by an eighth bit which

is a data direction bit (R/W). The LM4935 address is 0011010₂. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a

READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected

register.

201341Q3

I²C Chip Address

Register changes take an effect at the SCL rising edge during the last ACK from slave.

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16

11.0 System Control (Continued)

201341Q5

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by slave)

rs = repeated start

Example I²C Write Cycle

17

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11.0 System Control (Continued)

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read

Cycle waveform.

201341Q6

Example I²C Read Cycle

201341P9

I²C Timing Diagram

11.5 I²C TIMING PARAMETERS

Symbol

Parameter

Limit

Units

Min

0.6

1.3

600

300

0

Max

1

2

Hold Time (repeated) START Condition

Clock Low Time

µs

ns

µs

pF

3

Clock High Time

4

Setup Time for a Repeated START Condition

Data Hold Time (Output direction, delay generated by LM4935)

Data Hold Time (Input direction, delay generated by the Master)

Data Setup Time

5

900

5

6

100

7

Rise Time of SDA and SCL

20+0.1C_b

15+0.1C_b

600

300

8

Fall Time of SDA and SCL

9

Set-up Time for STOP condition

10

C_b

Bus Free Time between a STOP and a START Condition

1.3

Capacitive Load for Each Bus Line

10

200

NOTE: Data guaranteed by design

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18

11.0 System Control (Continued)

Method 2. SPI/Microwire Control/3–wire Control

The LM4935 can be controlled via a three wire interface consisting of a clock, data and an active low chip_select. To use this

control method connect SPI_MODE to BB_V_DDand use TEST_MODE/CS as the chip_select as follows:

20134106

FIGURE 3. SPI Write Transaction

If the application requires read access to the register set; for example to determine the cause of an interrupt request or to read

back a SAR data field, the GPIO2 pin can be configured as an SPI format serial data output by setting the GPIO_SEL in the GPIO

configuration register (0x1Ah) to SPI_SDO. To perform a read rather than a write to a particular address the MSB of the register

address field is set to a 1, this effectively mirrors the contents of the register field to read-only locations above 0x80h:

20134107

FIGURE 4. SPI Read Transaction

Three Wire Mode Write Bus Timing

20134109

FIGURE 5. SPI Timing

19

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12.0 Status & Control Registers

TABLE 1. Register Map

Address

0x00h

0x01h

0x02h

0x03h

0x04h

0x05h

0x06h

0x07h

0x08h

0x09h

0x0Ah

0x0Bh

0x0Ch

0x0Dh

0x0Eh

0x0Fh

0x10h

0x11h

0x12h

Register

BASIC

7

6

5

4

3

2

1

0

OCL

STEREO

CAP_SIZE

R_DIV

USE_OSC PLL_ENB

CHP_MODE

ADCLK DACCLK

CLOCKS

PLL_M

PLLINPUT

PLL_M

PLL_N

RSVD

MIC

PLL_N

PLL_P

RSVD

Q_DIV

PLL_P

PLL_MOD

ADC_1

DITHER_LEVEL

SAMPLE_RATE

PLL_N_MOD

HPF_MODE

IF216 ADC_I2SM

NOISE_GATE_THRESHOLD

AGC_TIGHT

RIGHT

LEFT

CPI

ADC_2

AGC_FRAME_TIME

NG_ON

ADCMUTE COMPND U/ALAW

AGC_TARGET AGC_ENB

AGC_MAX_GAIN

AGC_HOLD_TIME

PREAMP_GAIN

AGC_1

AGC_2

AGC_DECAY

AGC_3

AGC_ATTACK

INT_EXT

MIC_1

SE_DIFF

MUTE

MIC_2

BTN_DEBOUNCE_TIME BTNTYPE MIC_BIAS_VOLTAGE VCMVOLT

SIDETONE_ATTEN

SIDETONE

CP_INPUT

AUX_LEFT

AUX_RIGHT

DAC

MUTE

BOOST

USAXLVL

CPI_LEVEL

AUX_LEFT_LEVEL

AUX_RIGHT_LEVEL

DAC_LEVEL

AUX_DAC

DACMUTE

MUTE

BOOST

CP_OUTPUT

MICGATE

MUTE

LEFT

RIGHT

MIC

CPI

0x13h AUX OUTPUT

MUTE

LEFT

RIGHT

CPI

0x14h

0x15h

0x16h

0x17h

0x18h

0x19h

0x1Ah

0x1Bh

0x1Ch

LS_OUTPUT

HP_OUTPUT

EP_OUTPUT

DETECT

LEFT

CPI

MUTE

RIGHT

SIDE

CPI

HS_DBNC_TIME

SARTRG2 SARTRG1

TEMP_INT BTN_INT DET_INT

STATUS

GPIN

TEMP

BTN

MIC

STEREO HEADSET

AUDIO_IF_MODE

GPIO_SEL

AUDIO_IF

GPIO

I2S_SDO_DATA

GPIODATA PCM_LNG I2S_MODE

PCMCLMS PCMSYMS I2SCLKMS I2SWSMS

SAR_CH_SEL

SLT0ENB

SLT2ENB

SAR_SLT0/1

SAR_SLT2/3

SLT1ENB

SLOT1_FS

SLT2VBB

SLOT0_FS

SLT3ENB

SLOT2_FS

0x1Dh SAR_DATA_0

0x1Eh SAR_DATA_1

SLOT0_DATA

SLOT1_DATA

SLOT2_DATA

SLOT3_DATA

0x1Fh

0x20h

0x21h

0x22h

0x23h

0x24h

0x25h

0x26h

SAR_DATA_2

SAR_DATA_3

DC_VOL

MAX_LVL

SOURCE

EFFECT DCVLENB

TRIG_1

TRIG_1 [3:0]

TRIG_2 [3:0]

RSVD RSVD

DIR

ENB

TRIG_1_MSB

TRIG_2

TRIG_1 [11:4]

TRIG_2 [11:4]

SOURCE

DIR

ENB

TRIG_2_MSB

DEBUG

GPIO_TEST

_MODE

RSVD

SOFT

RESET

RSVD

For all registers, the default setting of data bits 7 through 0 are all set to zero.

RESERVED bits should always be set to zero.

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20

12.0 Status & Control Registers (Continued)

12.1 BASIC CONFIGURATION REGISTER

This register is used to control the basic function of the chip.

TABLE 2. BASIC (0x00h)

Description

Bits

Field

1:0

CHIP_MODE

The LM4935 can be placed in one of four modes which dictate its basic operation. When a new

mode is selected the LM4935 will change operation silently and will re-configure the power

management profile automatically. The modes are described as follows:

CHIP MODE

Audio System

Detection System

Typical Application

Power-down Mode

00₂

01₂

Off

On

Stand-by mode with headset event

detection

10₂

11₂

On

Off

On

Active without headset event detection

Active with headset event detection

2

3

PLL_ENABLE

USE_OSC

If set the PLL can be used.

If set the power management and control circuits will assume that no external clock is available and

will resort to using an on-chip oscillator for SAR, headset detection and analog power management

functions such as click and pop.

5:4

CAP_SIZE

Programs the extra delays required to stabilize once charge/discharge is complete, based on the size

of the bypass capacitor.

CAP_SIZE

00₂

Bypass Capacitor Size

Turn-off/on time

45 ms/75 ms

45 ms/140 ms

45 ms/260 ms

45 ms/500 ms

0.1 µF

1 µF

01₂

10₂

2.2 µF

4.7 µF

11₂

6

7

STEREO

If set, the mixers assume that the signals on the left and right internal busses are highly correlated

and when these signals are combined their levels are reduced by 6 dB to allow enough headroom for

them to be summed at the Loudspeaker, Earpiece, CPOUT, and AUXOUT amplifiers. For the

Headphone amplifier, if this bit is set, the left and right signal levels are routed to the corresponding

left or right headphone output; if this bit is cleared, the left and the right signals are added and routed

to both headphone outputs and their levels are reduced by 6dB to allow enough headroom.

If set the part is placed in OCL (Output Capacitor Less) mode.

OCL

For reliable headset / push button detection the following bits should be defined before enabling the headset detection system by

setting bit 0 of CHIP_MODE:

The OCL-bit (Cap / Capless headphone interface; bit 7 of this register)

The headset insert/removal debounce settings (bits 6:3 of DETECT (0x17h))

The BTN_TYPE-bit (Parallel / Series push button type; bit 3 MIC_2 register (0x0Ch))

The parallel push button debounce settings (bits 5:4 of MIC_2 register (0x0Ch))

All register fields controlling the audio system should be defined before setting bit 1 of CHIP_MODE and should not be altered

while the audio sub-system is active.

If the analog or digital levels are below −12 dB then it is not necessary to set the stereo bit allowing greater output levels to be

obtained for such signals.

21

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12.0 Status & Control Registers (Continued)

12.2 CLOCKS CONFIGURATION REGISTER

This register is used to control the clocks throughout the chip.

TABLE 3. CLOCKS (0x01h)

Description

Bits

Field

0

DAC_CLK

Selects the clock to be used by the audio DAC system.

DAC_CLK

DAC Input Source

PLL Input (MCLK or I2S_CLK)

PLL Output

0

1

ADC_CLK

R_DIV

Selects the clock to be used by the audio ADC system.

ADC_CLK

Audio ADC Input Source

MCLK

0

1

PLL Output

7:2

Programs the R divider (divides from an expected 12.000 MHz input).

R_DIV

Divide Value

0

Bypass

1.5

2

1

2

3

4

2.5

3

5

6

3.5

4

7

8

9

4.5

5

10

5.5

6

11

12

6.5

7 to 31

31.5

32

13 to 61

62

63

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22

12.0 Status & Control Registers (Continued)

12.3 LM4935 CLOCK NETWORK

The audio ADC operates at 125*fs, so it requires a 1.000 MHz clock to sample at 8 kHz (at point C as marked on the following

diagram). The stereo DAC operates at 250*fs, i.e. 12.000 MHz (at point B) for 48 kHz data. It is expected that the PLL is used

to drive the audio system unless a 12.000 MHz master clock is supplied and the sample rate is always a multiple of 8 kHz, in

which case the PLL can be bypassed to reduce power, clock division instead being performed by the Q and R dividers. The PLL

can also use the I2S clock input as a source. In this case, the audio DAC uses the clock from the output of the PLL and the audio

ADC either uses the PLL output divided by 2*FSDAC/FSADC or a system clock divided by Q, this allows n*8 kHz recording and

44.1 kHz playback.

MCLK must be less than or equal to 30 MHz, the I2S clock should be an integer multiple of the DAC’s sampling frequency and

should be below 6 MHz.

When using the Class D amplifier with the DAC the Class D clock generator will assume 12 MHz at point A, if this is not the case

then the DAC and power stage may become unsynchronized and SNR performance may be reduced.

The LM4935 is designed to work from a 12.000 MHz or 11.025 MHz clock at point A. This is used to drive the power management

and control logic. Performance may not meet the electrical specifications if the frequency at this point deviates significantly

beyond this range.

20134110

FIGURE 6. LM4935 Clock Network

23

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12.0 Status & Control Registers (Continued)

12.4 COMMON CLOCK SETTINGS FOR THE DAC & ADC

The DAC has an over sampling rate of 125 but requires a 250*fs clock at point B. This allows a simple clocking solution as it will

work from 12.000 MHz (common in most systems with Bluetooth or USB) at 48 kHz exactly, the following table describes the clock

required at point B for various clock sample rates in the different DAC modes:

TABLE 4. Common DAC Clock Frequencies

DAC Sample Rate (kHz)

Clock Required at B (MHz)

8

11.025

12

2

2.75625

3

16

4

5.5125

6

22.05

24

32

8

44.1

48

11.025

12

The ADC has an over sampling ratio of 125 so the table below shows the required clock frequency at point C.

TABLE 5. Common ADC Clock Frequencies

ADC Sample Rate (kHz)

Clock Required at C (MHz)

8

11.025

12

1

1.378125

1.5

16

2

2.75625

3

22.05

24

Methods for producing these clock frequencies are described in the PLL Section.

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24

12.0 Status & Control Registers (Continued)

12.5 PLL M DIVIDER CONFIGURATION REGISTER

This register is used to control the input section of the PLL.

TABLE 6. PLL_M (0x02h)

Description

Bits

0

Field

RSVD

PLL_M

RESERVED

6:1

PLL_M

Input Divider Value

0

1

2

3

4

4...62

63

5...63

64

7

PLL_INPUT

Programs the PLL input multiplexer to select between:

PLL_INPUT

PLL Input Source

MCLK

0

1

I2S_CLK

The M divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz.

The division of the M divider is derived from PLL_M such that:

M = PLL_M + 1

Note 11: See Further Notes on PLL Programming for more detail.

25

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12.0 Status & Control Registers (Continued)

12.6 PLL N DIVIDER CONFIGURATION REGISTER

This register is used to control the feedback divider of the PLL.

TABLE 7. PLL_N (0x03h)

Description

Bits

Field

7:0

PLL_N

Programs the PLL feedback divider as follows:

PLL_N

Feedback Divider Value

0 to 10

10

11

12

13

14

13

14

…

249

250

250 to 255

The N divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz. (Fin/M)*N will be the target resting

<

VCO frequency, F_VCO. The N divider should be set such that 40 MHz (Fin/M)*N 60 MHz. Fin/M is often referred to as F_comp

(comparison frequency) or F_ref(reference frequency), in this document F_compis used.

The integer division of the N divider is derived from PLL_N such that:

<

For 9 PLL_N 251: N = PLL_N

Note 12: See Further Notes on PLL Programming for further details.

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26

12.0 Status & Control Registers (Continued)

12.7 PLL P DIVIDER CONFIGURATION REGISTER

This register is used to control the output divider of the PLL.

TABLE 8. PLL_P (0x04h)

Description

Bits

0

Field

RSVD

PLL_P

RESERVED

3:1

PLL_P

000₂

001₂

010₂

011₂

100₂

101₂

110₂

111₂

Output Divider Value

1

2

3

4

5

6

7

8

6:4

Q_DIV

Programs the Q Divider (divides from an expected 12.000 MHz input).

Q_DIV

000₂

001₂

010₂

011₂

100₂

101₂

110₂

111₂

Divide Value

2

3

4

6

8

10

12

13

7

RSVD

RESERVED

The division of the P divider is derived from PLL_P such that:

P = PLL_P + 1

Note 13: See Further Notes on PLL Programming for more details.

27

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12.0 Status & Control Registers (Continued)

12.8 PLL N MODULUS CONFIGURATION REGISTER

This register is used to control the modulation applied to the feedback divider of the PLL.

TABLE 9. PLL_N_MOD (0x05h)

Bits

Field

Description

Programs the PLL N divider’s fractional component:

4:0

PLL_N_MOD

Fractional Addition

0/32

0

1

1/32

2 to 30

2/32 to 30/32

31/32

31

6:5

DITHER_LEVEL

Allows control over the dither used by the N divider:

DITHER_LEVEL

Value

Medium

Small

Large

Off

00₂

01₂

10₂

11₂

7

RSVD

RESERVED

The complete N divider is a fractional divider as such:

N = PLL_N + PLL_N_MOD/32

If the modulus input is zero then the N divider is simply an integer N divider. The output from the PLL is determined by the

following formula:

F_out= (F_in*N)/(M*P)

Note 14: See Further Notes on PLL Programming for more details.

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28

12.0 Status & Control Registers (Continued)

12.9 FURTHER NOTES ON PLL PROGRAMMING

The sigma-delta PLL is designed to drive audio circuits requiring accurate clock frequencies of up to 30 MHz with frequency errors

noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48 kHz and 44.1 kHz

sample rates from any common system clock. In systems where an isochronous I2S data stream is the source of data to the DAC

a clock synchronous to the sample rate should be used as input to the PLL (typically the I2S clock). If no isochronous source is

available then the PLL can be used to obtain a clock that is accurate to within 1 Hz of the correct sample rate although this is

highly unlikely to be a problem.

20134111

FIGURE 7. PLL Overview

TABLE 10. Example PLL Settings for 48 kHz and 44.1 kHz Sample Rates

F_in(MHz)

11

F_s(kHz)

48

M

11

4

N

P

5

6

5

4

5

PLL_M

10

3

PLL_N

60

PLL_N_MOD

PLL_P

F_out(MHz)

12

60

0

17

0

4

5

4

3

4

12.288

13

48

19.53125

60

19

12

48

13

9

12

8

60

12

14.4

16.2

16.8

19.2

19.44

19.68

19.8

11

48

37.5

37

16

0

12

48

27

14

13

27

21

17

11

8

100

26

13

12

26

20

16

10

7

100

50

12

48

50

0

12

48

40.625

100

40

20

0

12

48

100

64

12

48

64.03125

51.5

1

12

48

51

16

4

12

44.1

55.125

39.0625

22.96875

55.125

45.9375

30.625

55.78125

45.9375

39.6875

47.0625

30.625

55

11.025

11.2896

12

39

2

5

4

22

31

4

13

12

9

12

11

8

55

14.4

16.2

16.8

19.2

19.44

19.68

19.8

45

30

20

25

30

22

2

9

17

16

14

21

11

16

15

13

20

10

30

45

39

47

30

204

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12.0 Status & Control Registers (Continued)

These tables cover the most common applications, obtaining clocks for derivative sample rates such as 22.05 kHz should be

done by increasing the P divider value or using the R/Q dividers.

If the user needs to obtain a clock unrelated to those described above, the following method is advised. An example of obtaining

12.000 MHz from 1.536 MHz is shown below (this is typical for deriving DAC clocks from I2S datastreams).

Choose a small range of P so that the VCO frequency is swept between 40 MHz and 60 MHz. So for P = 3 to 5, sweep the M

inputs from 1 to 3. The most accurate N and N_MOD can be calculated by:

N = FLOOR(((Fout/Fin)*(P*M)),1)

N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0)

This shows that setting M = 1, N = 39+1/16, P = 5 (i.e. PLL_M = 0, PLL_N = 39, PLL_N_MOD = 2, & PLL_P = 4) gives a

comparison frequency of 1.5 MHz, a VCO frequency of 60 MHz and an output frequency of 12.000 MHz. The same settings can

be used to get 11.025 from 1.4112 MHz for 44.1 kHz sample rates.

Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used but an exact

frequency match cannot be found. The I2S should be master on the LM4935 so that the data source can support appropriate SRC

as required. This method should only be used with data being read on demand to eliminate sample rate mismatch problems.

Where a system clock exists at an integer multiple of the required ADC or DAC clock rate it is preferable to use this rather than

the PLL. The LM4935 is designed to work in 8, 12, 16, 24, 48 kHz modes from a 12 MHz clock and 8, 13, 26, 52 kHz modes from

a 13 MHz clock without the use of the PLL. This saves power and reduces clock jitter which can affect SNR.

The actual ADC and DAC sample rates are set up by the PLL and internal clock dividers.

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12.0 Status & Control Registers (Continued)

12.10 ADC_1 CONFIGURATION REGISTER

This register is used to control the LM4935’s audio ADC.

TABLE 11. ADC_1 (0x06h)

Description

Bits

0

Field

MIC_SELECT

CPI_SELECT

LEFT_SELECT

If set the microphone preamp output is added to the ADC input signal.

If set the cell phone input is added to the ADC input signal.

If set the left stereo bus is added to the ADC input signal.

1

2

3

RIGHT_SELECT If set the right stereo bus is added to the ADC input signal.

5:4

ADC_SAMPLE_

RATE

Programs the closest expected sample rate of the mono ADC, which is a variable required by the

AGC algorithm whenever the AGC is in use. This does not set the sample rate of the mono ADC.

ADC_SAMPLE_RATE

Sample Rate

8 kHz

00₂

01₂

10₂

11₂

12 kHz

16 kHz

24 kHz

7:6

HPF_MODE

Sets the HPF of the ADC

HPF-MODE

00₂

HPF Response

No HPF

@ @

F_S= 8 kHz, −0.5 dB 300 Hz, Notch 55 Hz

01₂

@

F_S= 12 kHz, −0.5 dB 450 Hz, Notch 82 Hz

@

F_S= 16 kHz, −0.5 dB 600 Hz, Notch 110 Hz

@ @

F_S= 8 kHz, −0.5 dB 150 Hz, Notch 27 Hz

10₂

11₂

@

F_S= 12 kHz, −0.5 dB 225 Hz, Notch 41 Hz

@

F_S= 16 kHz, −0.5 dB 300 Hz, Notch 55 Hz

No HPF

31

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12.0 Status & Control Registers (Continued)

12.11 ADC_2 CONFIGURATION REGISTER

This register is used to control the LM4935’s audio ADC.

TABLE 12. ADC_2 (0x07h)

Description

Bits

Field

0

ULAW/ALAW

If COMPAND is set then the data across the PCM interface to the DAC and from the ADC is

companded as follows:

ULAW/ALAW

Commanding Type

µ-law

0

1

A-law

1

2

COMPAND

ADC_MUTE

If set the 16 bit PCM data from the ADC is companded before the PCM interface and the PCM

data to the DAC is treated as companded data.

If set the analog inputs to the ADC are muted.

5:3 AGC_FRAME_TIME This sets the frame time to be used by the AGC algorithm. In a given frame, the AGC’s peak

detector determines the peak value of the incoming microphone audio signal and compares this

value to the target value of the AGC defined by AGC_TARGET (bits [3:1] of register (0x08h)) in

order to adjust the microphone preamplifiers gain accordingly. AGC_FRAME_TIME basically sets

the sample rate of the AGC to adjust for a wide variety of speech patterns. (Note 15)

AGC_FRAME_TIME

Time (ms)

96

000₂

001₂

010₂

011₂

100₂

101₂

110₂

111₂

128

192

256

384

512

768

1000

6

7

ADC_I2S_M

If set the DAC clock system is enabled to drive the I2S in master mode. The Point B frequency

should be double that at Point C. This bit should be set when using the I2S interface in master

mode to read SAR information whenever both the audio ADC and DAC are inactive.

AUDIO_IF_2_16BIT If set the PCM and I2S interfaces are 16 bits per word in master mode. The 2 last clock cycles per

word are 25% shorter to allow generation.

Note 15: Refer to the AGC overview for further detail.

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12.0 Status & Control Registers (Continued)

12.12 AGC_1 CONFIGURATION REGISTER

This register is used to control the LM4935’s Automatic Gain Control. (Note 16)

TABLE 13. AGC_1 (0x08h)

Bits

Field

Description

0

AGC_ENABLE

If set the AGC controls the analog microphone preamplifier gain into the system. The microphone

input must be passed to the ADC.

3:1

AGC_TARGET

Programs the target level of the AGC. This will depend on the expected transients and desired

headroom. Refer to AGC_TIGHT (bit 7 of 0x09h) for more detail.

AGC_TARGET

000₂

Target Level

−6 dB

001₂

−8 dB

010₂

−10 dB

−12 dB

−14 dB

−16 dB

−18 dB

−20 dB

011₂

100₂

101₂

110₂

111₂

4

NOISE_GATE_ON If set, signals below the noise gate threshold are muted.The noise gate is only activated after a set

period of signal absence.

7:5

NOISE_

GATE_

THRES

This field sets the expected background noise level relative to the peak signal level. The sole

presence of signals below this level will not result in an AGC gain change of the input and will be

gated from the ADC output if the NOISE_GATE_ON is set. This level must be set even if the noise

gate is not in use as it is required by the AGC algorithm.

NOISE_GATE_THRES

Level

000₂

001₂

010₂

011₂

100₂

101₂

110₂

111₂

−72 dB

−66 dB

−60 dB

−54 dB

−48 dB

−42 dB

−36 dB

−30 dB

Note 16: See the AGC overview.

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12.0 Status & Control Registers (Continued)

12.13 AGC_2 CONFIGURATION REGISTER

This register is used to control the LM4935’s Automatic Gain Control.

TABLE 14. AGC_2 (0x09h)

Description

AGC_MAX_GAIN This programs the maximum gain that the AGC algorithm can apply to the microphone preamplifier.

Bits

Field

3:0

AGC_MAX_GAIN

0000₂

Max Preamplifier Gain

6 dB

8 dB

0001₂

0010₂

10 dB

0011₂

12 dB

0100₂to 1100₂

1101₂

14 dB to 30 dB

32 dB

1110₂

34 dB

1111₂

36 dB

6:4

AGC_DECAY

Programs the speed at which the AGC will increase gains if it detects the input level is a quiet

signal.

AGC_DECAY

000₂

Step Time (ms)

32

64

001₂

010₂

128

256

512

1024

2048

4096

011₂

100₂

101₂

110₂

111₂

7

AGC_TIGHT

If set the AGC algorithm controls the microphone preamplifier more exactly. (Note 17)

AGC_TIGHT = 0

AGC_TARGET

000₂

Min Level

−6 dB

Max Level

−3 dB

001₂

−8 dB

−4 dB

010₂

−10 dB

−12 dB

−14 dB

−16 dB

−18 dB

−20 dB

−6 dB

−5 dB

011₂

−6 dB

100₂

−7 dB

101₂

−8 dB

110₂

−9 dB

111₂

−10 dB

−3 dB

AGC_TIGHT = 1

000₂

001₂

−8 dB

−5 dB

010₂

−10 dB

−12 dB

−14 dB

−16 dB

−18 dB

−20 dB

−7 dB

011₂

−9 dB

100₂

−11 dB

−13 dB

−15 dB

−17 dB

101₂

110₂

111₂

Note 17: The AGC can be used to control the analog path of the microphone to the output stages or to optimize the microphone path for recording on the ADC.

When the analog path is used this bit should be set to ensure the target is tightly adhered to. If the ADC is the only destination of the microphone or the desired analog

mixer level is line level then AGC_TIGHT should be cleared, allowing greater dynamic rage of the recorded signal. For further details see the AGC overview.

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34

12.0 Status & Control Registers (Continued)

12.14 AGC_3 CONFIGURATION REGISTER

This register is used to control the LM4935’s Automatic Gain Control. (Note 18)

TABLE 15. AGC_3 (0x0Ah)

Bits

Field

Description

4:0

AGC_HOLDTIME Programs the amount of delay before the AGC algorithm begins to adjust the gain of the

microphone preamplifier.

AGC_HOLDTIME

00000₂

No. of speech segments

0

00001₂

1

2

00010₂

00011₂

3

00100₂to 11100₂

11101₂

4 to 28

29

11110₂

30

11111₂

31

7:5

AGC_ATTACK

Programs the speed at which the AGC will reduce gains if it detects the input level is too large.

AGC_ATTACK

000₂

Step Time (ms)

32

64

001₂

010₂

128

256

512

1024

2048

4096

011₂

100₂

101₂

110₂

111₂

Note 18: See the AGC overview.

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12.0 Status & Control Registers (Continued)

12.15 AGC OVERVIEW

The Automatic Gain Control (AGC) system can be used to optimize the dynamic range of the ADC for voice data when the level

of the source is unknown. A target level for the output is set so that any transients on the input won’t clip during normal operation.

The AGC circuit then compares the output of the ADC to this level and increases or decreases the gain of the microphone

preamplifier to compensate. If the audio from the microphone is to be output digitally through the ADC then the full dynamic range

of the ADC can be used automatically. If the output is through the analog mixer then the ADC is used to monitor the microphone

level. In this case, the analog dynamic range is less important than the absolute level, so AGC_TIGHT should be set to tie

transients closely to the target level.

To ensure that the system doesn’t reduce the quality of the speech by constantly modulating the microphone preamplifier gain,

the ADC output is passed through an envelope detector. This frames the output of the ADC into time segments roughly equal to

the phonemes found in speech (AGC_FRAME_TIME). To calculate this, the circuit must also know the sample rate of the data

from the ADC (ADC_SAMPLERATE). If after a programmable number of these segments (AGC_HOLDTIME), the level is

consistently below target, the gain will be increased at a programmable rate (AGC_DECAY). If the signal ever exceeds the target

level (AGC_TARGET) then the gain of the microphone is reduced immediately at a programmable rate (AGC_ATTACK). This is

demonstrated below:

20134112

AGC Operation Example

The signal in the above example starts with a small analog input which, after the hold time has timed out, triggers a rise in the

→

gain ((1)

(2)). After some time the real analog input increases and it reaches the threshold for a gain reduction which decreases

→

the gain at a faster rate ((2)

(3)) to allow the elimination of typical popping noises.

Only ADC outputs that are considered signal (rather than noise) are used to adjust the microphone preamplifier gain. The signal

to noise ratio of the expected input signal is set by NOISE_GATE_THRESHOLD. In some situations it is preferable to remove

audio considered to be consisting solely of background noise from the audio output; for example conference calls. This can be

done by setting NOISE_GATE_ON. This does not affect the performance of the AGC algorithm.

The AGC algorithm should not be used where very large background noise is present. If the type of input data, application and

microphone is known then the AGC will typically not be required for good performance, it is intended for use with inputs with a

large dynamic range or unknown nominal level. When setting NOISE_GATE_THRESHOLD be aware that in some mobile phone

scenarios the ADC SNR will be dictated by the microphone performance rather than the ADC or the signal. Gain changes to the

microphone are performed on zero crossings. To eliminate DC offsets, wind noise, and pop sounds from the output of the ADC,

the ADC’s HPF should always be enabled.

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36

12.0 Status & Control Registers (Continued)

12.16 MIC_1 CONFIGURATION REGISTER

This register is used to control the microphone configuration.

TABLE 16. MIC_1 (0x0Bh)

Description

Programs the gain applied to the microphone preamplifier if the AGC is not in use.

Bits

Field

3:0

PREAMP_GAIN

Gain

6 dB

0000₂

0001₂

8 dB

0010₂

10 dB

0011₂

12 dB

0100₂to 1100₂

14 dB to 30 dB

32 dB

1101₂

1110₂

1111₂

34 dB

36 dB

4

5

MIC_MUTE

If set the microphone preamplifier is muted.

INT_SE_DIFF

If set the internal microphone is assumed to be single ended and the negative connection is

connected to the ADC common mode point internally. This allows a single-ended internal

microphone to be used.

6

INT_EXT

If set the single ended external microphone is used and the negative microphone input is grounded

internally, otherwise internal microphone operation is assumed. (Note 19)

Note 19: On changing INT_EXT from internal to external note that the dc blocking cap will not be charged so some time should be taken (300 ms for a 1 µF cap)

between the detection of an external headset and the switching of the output stages and ADC to that input to allow the DC points on either side of this cap to stabilize.

This can be accomplished by deselecting the microphone input from the audio outputs and ADC until the DC points stabilize.

An active MIC path to CPOUT or the ADC may result in the microphone DC blocking caps causing audio pops under the following situations:

1) Switching between internal and external microphone operation while in chip modes ’10’ or ’11’.

2) Toggling in and out of powerdown/standby modes.

3) Toggling between chip modes ’10’ and ’11’ whenever external microphone operation is selected.

4) The insertion/removal of a headset while in chip modes ’10’ or ’11’ whenever external microphone operation is selected.

To avoid these potential pop issues, it is recommended to deselect the microphone input from CPOUT and ADC until the DC points stabilize.

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12.0 Status & Control Registers (Continued)

12.17 MIC_2 CONFIGURATION REGISTER

This register is used to control the microphone configuration.

TABLE 17. MIC_2 (0x0Ch)

Description

Bits

Field

OCL_

0

Selects the voltage used as virtual ground (HP_VMID pin) in OCL mode. This will depend on the

available supply and the power output requirements of the headphone amplifiers.

VCM_

VOLTAGE

OCL_VCM_VOLTAGE

Voltage

1.2V

0

1

1.5V

2:1

MIC_

BIAS_

Selects the voltage as a reference to the internal and external microphones. Only one bias pin is

driven at once depending on the INT_EXT bit setting found in the MIC_1 (0x0Bh) register.

>

VOLTAGE

MIC_BIAS_VOLTAGE should be set to ’11’ only if A_V_DD3.4V. In OCL mode,

MIC_BIAS_VOLTAGE = ’00’ (EXT_BIAS = 2.0V) should not be used to generate the EXT_BIAS

supply for a cellular headset external microphone. Please refer to Table 18 for more detail.

MIC_BIAS_VOLTAGE

EXT_BIAS

2.0V

INT_BIAS

2.0V

00₂

01₂

10₂

11₂

2.5V

2.8V

3.3V

3

BUTTON_TYPE If set the LM4935 assumes that the button (if used) in the headset is in series (series push button)

with the microphone, opening the circuit when pressed. The default is for the button to be in parallel

(parallel push button), shorting out the microphone when pressed.

5:4

BUTTON_

DEBOUNCE_

TIME

Sets the time used for debouncing the pushing of the button on a headset with a parallel push

button.

BUTTON_DEBOUNCE_TIME

Time (ms)

00₂

01₂

10₂

11₂

0

8

16

32

In OCL mode there is a trade-off between the external microphone supply voltage (EXT_MIC_BIAS - OCL_VCM_ VOLTAGE) and

the maximum output power possible from the headphones. A lower OCL_VCM_VOLTAGE gives a higher microphone supply

voltage but a lower maximum output power from the headphone amplifiers due to the lower OCL_VCM_VOLTAGE - A_V_SS

.

TABLE 18. External MIC Supply Voltages in OCL Mode

Available

A_V_DD

Recommended

EXT_MIC_BIAS

Supply to Microphone

OCL_VCM_VOLT = 1.5V

OCL_VCM_VOLT = 1.2V

>

3.4V

3.3V

2.8V

2.5V

1.8V

1.3V

1.0V

-

2.1V

1.6V

1.3V

2.9V to 3.4V

2.8V to 2.9V

2.7V to 2.8V

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12.0 Status & Control Registers (Continued)

12.18 SIDETONE ATTENUATION REGISTER

This register is used to control the analog sidetone attenuation. (Note 20)

TABLE 19. SIDETONE (0x0Dh)

Bits

Field

SIDETONE_

ATTEN

Description

3:0

Programs the attenuation applied to the microphone preamp output to produce a sidetone signal.

SIDETONE_ATTEN

0000₂

Attenuation

-Inf

0001₂

−30 dB

0010₂

−27 dB

0011₂

−24 dB

0100₂

−21 dB

0101₂to 1010₂

1011₂to 1111₂

−18 dB to −3 dB

0 dB

Note 20: An active SIDETONE path to an audio output may result in the microphone DC blocking caps causing audio pops under the following situations:

1) Switching between internal and external microphone operation while in chip modes ’10’ or ’11’.

2) Toggling in and out of powerdown/standby modes.

3) Toggling between chip modes ’10’ and ’11’ whenever external microphone operation is selected.

4) The insertion/removal of a headset while in chip modes ’10’ or ’11’ whenever external microphone operation is selected.

To avoid potential pop noises, it is recommended to set SIDETONE_ATTEN to ’0000’ until DC points have stabilized whenever the SIDETONE path is used.

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12.0 Status & Control Registers (Continued)

12.19 CP_INPUT CONFIGURATION REGISTER

This register is used to control the differential cell phone input.

TABLE 20. CP_INPUT (0x0Eh)

Description

Bits

Field

4:0

CPI_LEVEL

Programs the gain/attenuation applied to the cell phone input.

CPI_LEVEL

Level

−34.5 dB

−33 dB

00000₂

00001₂

00010₂

−31.5 dB

−30 dB

00011₂

00100 to 11100₂

−28.5 dB to +7.5 dB

+9 dB

11101₂

11110₂

11111₂

+10.5 dB

+12 dB

5

CPI_MUTE

If set the CPI input is muted at source.

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40

12.0 Status & Control Registers (Continued)

12.20 AUX_LEFT CONFIGURATION REGISTER

This register is used to control the left aux analog input.

TABLE 21. AUX_LEFT (0x0Fh)

Description

Programs the gain/attenuation applied to the AUX LEFT analog input to the mixer. (Note 21)

Bits

Field

AUX_

LEFT_

LEVEL

4:0

AUX_LEFT_LEVEL

00000₂

Level (With Boost)

−34.5 dB

Level (Without Boost)

−46.5 dB

00001₂

−33 dB

−45 dB

00010₂

−31.5 dB

−43.5 dB

00011₂

−30 dB

−42 dB

00100 to 11100₂

11101₂

−28.5 dB to +7.5 dB

+9 dB

−40.5 dB to −4.5 dB

−3 dB

11110₂

+10.5 dB

−1.5 dB

11111₂

+12 dB

0 dB

5

AUX_

LEFT_

If set the gain of the AUX_LEFT input to the mixer is increased by 12 dB (see above).

BOOST

6

7

AUX_L_MUTE

If set the AUX LEFT input is muted.

AUX_OR_DAC_L If set the AUX LEFT input is passed to the mixer, the default is for the DAC LEFT output to be

passed to the mixer.

Note 21: The recommended mixer level is 1V RMS. The auxiliary analog inputs can be boosted by 12 dB if enough headroom is available. Clipping may occur if

the analog power supply is insufficient to cater for the required gain.

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12.0 Status & Control Registers (Continued)

12.21 AUX_RIGHT CONFIGURATION REGISTER

This register is used to control the right aux analog input.

TABLE 22. AUX_RIGHT (0x10h)

Description

Programs the gain/attenuation applied to the AUX RIGHT analog input to the mixer. (Note 22)

Bits

Field

AUX_

4:0

RIGHT_

LEVEL

AUX_RIGHT_LEVEL

00000₂

Level (With Boost)

−34.5 dB

Level (Without Boost)

−46.5 dB

00001₂

−33 dB

−45 dB

00010₂

−31.5 dB

−43.5 dB

00011₂

−30 dB

−42 dB

00100 to 11100₂

11101₂

−28.5 dB to +7.5 dB

+9 dB

−40.5 dB to −4.5 dB

−3 dB

11110₂

+10.5 dB

−1.5 dB

11111₂

+12 dB

0 dB

5

AUX_

If set the gain of the AUX_RIGHT input to the mixer is increased by 12 dB (see above).

RIGHT_BOOST

AUX_R_MUTE

6

7

If set the AUX RIGHT input is muted.

AUX_OR_DAC_R If set the AUX RIGHT input is passed to the mixer, the default is for the DAC RIGHT output to be

passed to the mixer.

Note 22: The recommended mixer level is 1V RMS. The auxiliary analog inputs can be boosted by 12 dB if enough headroom is available. Clipping may occur if

the analog power supply is insufficient to cater for the required gain.

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12.0 Status & Control Registers (Continued)

12.22 DAC CONFIGURATION REGISTER

This register is used to control the DAC levels to the mixer.

TABLE 23. DAC (0x11h)

Description

Programs the gain/attenuation applied to the DAC input to the mixer. (Note 23)

Bits

Field

4:0

DAC_LEVEL

00000₂

Level (With Boost)

−34.5 dB

Level (Without Boost)

−46.5 dB

00001₂

−33 dB

−45 dB

00010₂

−31.5 dB

−43.5 dB

00011₂

−30 dB

−42 dB

00100 to 11100₂

11101₂

−28.5 dB to +7.5 dB

+9 dB

−40.5 dB to −4.5 dB

−3 dB

11110₂

+10.5 dB

−1.5 dB

11111₂

+12 dB

0 dB

5

USE_AUX_

LEVELS

If set the gain of the DAC inputs is controlled by the AUX_LEFT and AUX_RIGHT registers, allowing

a stereo balance to be applied.

6

7

BOOST

If set the gain of the DAC inputs to the mixer is increased by 12 dB (see above).

If set the stereo DAC input is muted on the next zero crossing.

DAC_MUTE

Note 23: The output from the DAC is 1V RMS for a full scale digital input. This can be boosted by 12 dB if enough headroom is available. Clipping may occur if the

analog power supply is insufficient to cater for the required gain.

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12.0 Status & Control Registers (Continued)

12.23 CP_OUTPUT CONFIGURATION REGISTER

This register is used to control the differential cell phone output. (Note 24)

TABLE 24. CP_OUTPUT (0x12h)

Bits

0

Field

Description

MIC_SELECT

RIGHT_SELECT

LEFT_SELECT

CPO_MUTE

If set the microphone channel of the mixer is added to the cellphone output signal.

If set the right channel of the mixer is added to the cellphone output signal.

If set the left channel of the mixer is added to the cellphone output signal.

If set the CPOUT output is muted.

1

2

3

4

MIC_NOISE_GATE If this is set and NOISE_GATE_ON (register 0x08h) is enabled, the MIC to CPO path will be

gated if the signal is determined to be noise by the AGC (that is, if the signal is below the set

noise threshold).

Note 24: The gain of cell phone output amplifier is 0 dB.

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12.0 Status & Control Registers (Continued)

12.24 AUX_OUTPUT CONFIGURATION REGISTER

This register is used to control the differential auxiliary output. (Note 25)

TABLE 25. AUX_OUTPUT (0x13h)

Description

Bits

0

Field

CPI_SELECT

RIGHT_SELECT

LEFT_SELECT

AUX_MUTE

If set the cell phone input channel of the mixer is added to the aux output signal.

If set the right channel of the mixer is added to the aux output signal.

If set the left channel of the mixer is added to the aux output signal.

If set the aux output is muted.

1

2

3

Note 25: The gain of the auxiliary output amplifier is 0 dB. If a second (external) loudspeaker amplifier is to be used its gain should be set to 12 dB to match the

onboard loudspeaker amplifier gain.

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12.0 Status & Control Registers (Continued)

12.25 LS_OUTPUT CONFIGURATION REGISTER

This register is used to control the loudspeaker output. (Note 26)

TABLE 26. LS_OUTPUT (0x14h)

Description

Bits

0

Field

CPI_SELECT

RIGHT_SELECT

LEFT_SELECT

LS_MUTE

If set the cell phone input channel of the mixer is added to the loudspeaker output signal.

If set the right channel of the mixer is added to the loudspeaker output signal.

If set the left channel of the mixer is added to the loudspeaker output signal.

If set the loudspeaker output is muted.

1

2

3

Note 26: The gain of the loudspeaker output amplifier is 12 dB.

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12.0 Status & Control Registers (Continued)

12.26 HP_OUTPUT CONFIGURATION REGISTER

This register is used to control the stereo headphone output. (Note 27)

TABLE 27. HP_OUTPUT (0x15h)

Description

Bits

0

Field

SIDETONE_SELECT

CPI_SELECT

If set the sidetone channel of the mixer is added to both of the headphone output signals.

If set the cell phone input channel of the mixer is added to both of the headphone output

signals.

1

2

3

4

RIGHT_SELECT

LEFT_SELECT

HP_MUTE

If set the right channel of the mixer is added to the headphone output. If the STEREO bit

(0x00h) is set, the right channel is added to the right headphone output signal only. If the

STEREO bit (0x00h) is cleared, it is added to both the right and left headphone output

signals.

If set the left channel of the mixer is added to the headphone output. If the STEREO bit

(0x00h) is set, the left channel is added to the left headphone output signal only. If the

STEREO bit (0x00h) is cleared, it is added to both the right and left headphone output

signals.

If set the headphone output is muted.

Note 27: The gain of the headphone output amplifier is –6 dB for the cell phone input channel and sidetone channel of the mixer. When the STEREO bit (0x00h)

is set, headphone output amplifier gain is –6 dB for the left and right channel. When the STEREO bit (0x00h) is cleared, the headphone output amplifier gain is –12

dB for the left and right channel (to allow enough headroom for adding them and routing them to both headphone amplifiers).

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12.0 Status & Control Registers (Continued)

12.27 EP_OUTPUT CONFIGURATION REGISTER

This register is used to control the mono earpiece output. (Note 28)

TABLE 28. EP_OUTPUT (0x16h)

Description

Bits

0

Field

SIDETONE_SELECT

CPI_SELECT

If set the sidetone channel of the mixer is added to the earpiece output signal.

If set the cell phone input channel of the mixer is added to the earpiece output signal.

If set the right channel of the mixer is added to the earpiece output signal.

If set the left channel of the mixer is added to the earpiece output signal.

If set the earpiece output is muted.

1

2

RIGHT_SELECT

LEFT_SELECT

EP_MUTE

3

4

Note 28: The gain of the earpiece output amplifier is 6 dB.

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12.0 Status & Control Registers (Continued)

12.28 DETECT CONFIGURATION REGISTER

This register is used to control the headset detection system.

TABLE 29. DETECT (0x17h)

Description

Bits

Field

0

DET_INT

If set an IRQ is raised when a change is detected in the headset status. Clearing this bit will clear

an IRQ that has been triggered by the headset detect.

1

2

BTN_INT

If set an IRQ is raised when the headset button is pressed. Clearing this bit will clear an IRQ that

has been triggered by a button event.

TEMP_INT

If set an IRQ is raised during a temperature event. If cleared, the LM4935 will still automatically

cycle the power amplifiers off if the internal temperature is too high. This bit should not be set

whenever the loudspeaker amplifier is turned on. Clearing this bit will clear an IRQ that has been

triggered by a temperature event.

6:3

HS_

Sets the time used for debouncing the analog signals from the detection inputs used to sense the

insertion/removal of a headset.

DBNC_TIME

HS_DBNC_TIME

0000₂

0001₂

0010₂

0011₂

Time (ms)

0

8

16

32

0100₂

0101₂

0110₂

48

64

96

0111₂

128

192

256

384

512

768

1024

1536

2048

1000₂

1001₂

1010₂

1011₂

1100₂

1101₂

1110₂

1111₂

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12.0 Status & Control Registers (Continued)

12.29 HEADSET DETECT OVERVIEW

The LM4935 has built in monitors to automatically detect headset insertion or removal. The detection scheme can differentiate

between mono, stereo, mono-cellular and stereo-cellular headsets. Upon detection of headset insertion or removal, the LM4935

updates read-only bit 0 - headset absence/presence, bit 1- mono/stereo headset and bit 2 - headset without mic / with mic, of the

STATUS register (0x18h). Headset insertion/removal and headset type can also be detected in standby mode; this consumes no

analog supply current when the headset is absent.

The LM4935 can be programmed to raise an interrupt (set the IRQ pin high) when headset insert/removal is sensed by setting

bit 0 of DETECT (0x17h). When headset detection is enabled in active mode and a headset is not detected, the HPL_OUT and

HPR_OUT amplifiers will be disabled (switched off for capless mode and muted for AC-coupled mode) and the EXT_BIAS pin will

be disconnected from the MIC_BIAS amplifier, irrespective of control register settings.

The LM4935 also has the capability to detect button press, when a button is present on the headset microphone. Both parallel

button-type (in parallel with the headset microphone, default value) and series button-type (in series with the headset micro-

phone) can be detected; the button type used needs to be defined in bit 3 of MIC_2 (0x0Ch). Button press can also be detected

in stand-by mode; this consumes 10 µA of analog supply current for a series type push button and 100 µA for a parallel type push

button. Upon button press, the LM4935 updates bit 3 of STATUS (0x18h). In active OCL mode, with internal microphone selected

(INT_EXT = 0; (reg 0x0Bh)), if a parallel pushbutton headset is inserted into the system, INT_EXT must be set high before BTN

(bit 3 of STATUS (0x18h)) can be read. The LM4935 can also be programmed to raise an interrupt on the IRQ pin when button

press is sensed by setting bit 1 of DETECT.

The LM4935 provides debounce programmability for headset and button detect. Debounce programmability can be used to reject

glitches generated, and hence avoid false detection, while inserting/removing a headset or pressing a button.

Headset insert/removal debounce time is defined by HS_DBNC_TIME; bits 6:3 of DETECT (0x17h). Parallel button press

debounce time is defined by BTN_DBNC_TIME; bits 5:4 of MIC_2 (0x0Ch).

Note that since the first effect of a series button press (microphone disconnected) is indistinguishable from headset removal, the

debounce time for series button press in defined by HS_DBNC_TIME.

Headset and push button detection can be enabled by setting CHIP_MODE 0; bit 0 of BASIC (0x00h). For reliable headset / push

button detection all following bits should be defined before enabling the headset detection system:

1) the OCL-bit (AC-Coupled / Capless headphone interface (bit 7 of BASIC (0x00h))

2) the headset insert/removal debounce settings (bit 6:3 of DETECT (0x17h))

3) the BTN_TYPE-bit (Parallel / Series push button type (bit 3 of MIC_2 (0x0Ch))

4) the parallel push button debounce settings (bit 5:4 of MIC_2 (0x0Ch))

Figure 8 shows terminal connections and jack configuration for various headsets. Care should be taken to avoid any DC path from

the MIC_DET pin to ground when a headset is not inserted.

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12.0 Status & Control Registers (Continued)

20134113

FIGURE 8. Headset Configurations Supported by the LM4935

The wiring of the headset jack to the LM4935 will depend on the intended mode of the headphone amplifier:

51

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12.0 Status & Control Registers (Continued)

20134114

FIGURE 9. Connection of Headset Jack to LM4935 Depends on the Mode of the Headphone Amplifier.

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12.0 Status & Control Registers (Continued)

12.30 STATUS REGISTER

This register is used to report the status of the device.

TABLE 30. STATUS (0x18h)

Description

Bits

Field

0

HEADSET

This field is high when headset presence is detected (only valid if the detection system is

enabled). (Note 29)

1

2

3

STEREO_

HEADSET

MIC

This field is high when a headset with stereo speakers is detected (only valid if the detection

system is enabled). (Note 29)

This field is high when a headset with a microphone is detected (only valid if the detection system

is enabled). (Note 29)

BTN

This field is high when the button on the headset is pressed (only valid if the detection system is

enabled). IRQ is cleared when the button has been released and this register has been written

to.

4

5

6

SAR TRIG 1

SAR TRIG 2

TEMP

If this field is high then an event has happened on SAR trigger 1 (write to this register to clear

IRQ).

If this field is high then an event has happened on SAR trigger 2 (write to this register to clear

IRQ).

If this field is high then a temperature event has occurred (write to this register to clear IRQ). This

field will stay high even when the IRQ is cleared so long as the event occurs. This bit is only valid

whenever the loudspeaker amplifier is turned off.

7

GPIN

When GPIO_SEL is set to a readable configuration a digital input on GPIO1 can be read back

here.

Note 29: The detection IRQ is cleared when this register has been written to.

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12.0 Status & Control Registers (Continued)

12.31 AUDIO INTERFACE CONFIGURATION REGISTER

This register is used to control the configuration of the audio data interfaces.

TABLE 31. AUDIO_IF (0x19h)

Bits

Field

Description

1:0

AUDIO_IF_MODE Selects the function of the 6 audio interface IOs.

AUDIO_IF_MODE

I2S_

CLK pin

I²S

I2S_

WS pin

I²S

I2S_

SDI pin

I²S

I2S_

SDO pin

I²S

GPIO_1

GPIO_2

00₂

01₂

10₂

11₂

GPIO

1

GPIO

2

CLK

WS

SDI

SDO

PCM

SDO

PCM

SDO

PCM

SDO

PCM

CLK

PCM

SYNC

PCM

SYNC

I²S

-

GPIO

1

GPIO

2

PCM

CLK

I²S

PCM

SDI

I²S

GPIO

1

GPIO

2

PCM

CLK

PCM

SYNC

CLK

WS

SDI

2

3

I2S_WS_MS

I2S_CLK_MS

If set the I²S_WS is produced by the LM4935 and the I²S_WS pin will be an output.

If set the I²S_CLK is produced by the LM4935 and the I²S_CLK pin will be an output.

If set the PCM_SYNC is produced by the LM4935 and the relevant pin will be an output.

If set the PCM_CLK is produced by the LM4935 and the relevant pin will be an output.

4

PCM_SYNC_MS

PCM_CLK_MS

I2S_SDO_DATA

5

7:6

The two ADCs on the LM4935 can both be read via the isochronous I2S interface. The most recent

valid sample is output from the following source: (Please refer to the GPIO configuration register

(0x1Ah) for more information on SAR_CH_SEL)

I2S_SDO_DATA

LEFT

RIGHT

00₂

01₂

10₂

11₂

AUDIO ADC

SAR VSAR 1

SAR VSAR 2

A_V_DD/2

SAR_CH_SEL

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12.0 Status & Control Registers (Continued)

12.32 DIGITAL AUDIO DATA FORMATS

I2S master mode can only be used when the DAC is enabled unless the ADC_I2S_M bit is set. PCM Master mode can only be

used when the ADC is enabled. If the PCM receiver interface is operated in slave mode the clock and sync should be enabled

at the same time as the PCM receiver uses the first PCM frame to calculate the PCM interface format. This format can not be

changed unless a soft reset is issued. It is strongly recommended that the LM4935 is operated in master mode as this eliminates

the risk of sample rate mismatch between the data converters and the audio interfaces.

In master mode the I2S_CLK has a 60/40 duty cycle and a frequency of 50*fs. In slave mode the PCM and I2S receivers only

record the 1st 16 and 18 bits of the serial words respectively. The I2S format is as follows:

20134115

FIGURE 10. I²S Serial Data Format (Default Mode)

20134116

FIGURE 11. PCM Serial Data Format (16 bit Slave Example)

When SAR SDO data is passed to the I2S, it is left aligned (MSB aligned) to allow lower I2S resolutions to be used.

If the DAC is driven from the PCM interface then the left channel of the DAC is used and the right channel is inactive.

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12.0 Status & Control Registers (Continued)

12.33 GPIO CONFIGURATION REGISTER

This register is used to control the GPIO system.

TABLE 32. GPIO (0x1Ah)

Description

This sets the function of the GPIOs when the Audio Interface is not using them.

Bits

Field

2:0

GPIO_SEL

000₂

GPIO 1

0

GPIO 2

0

001₂

READABLE

LS_AMP_ENABLE

GPIO_DATA

0

SPI_SDO

SAR_SDO

010₂

011₂

100₂

101₂

READABLE

LS_AMP_ENABLE

GPIO_DATA

110₂

111₂

Setting GPIO_SEL = “010” with the GPIO_TEST_MODE bit (register 0X26h) set configures the

GPIOs for digital mic operation. With this setting, GPI01 will output VADC_CLK_OUT to provide a

clock for the digital mic. GPIO2 will accept digital mic data. GPIO1’s LS_AMP_ENABLE setting will

be logic high whenever the loudspeaker amplifier is enabled. This is useful for enabling an external

amplifier for stereo loudspeaker applications.

4:3

SAR_CH_SEL

This field selects the SAR output channel for the 2nd (Right) I²S channel or for SAR_SDO via

GPIO2.

SAR_CH_SEL

Selected Channel

VSAR_1

00₂

01₂

10₂

11₂

VSAR_2

D_V_DD/2 or BB_V_DD

A_V_DD/2

5

I2S_MODE

If set the I2S operates in left justified mode (sometimes referred to as DSP mode). See example

below. (Note 30)

6

7

PCM_LONG

GPIO_DATA

2

If set the PCM interface uses LONG frame sync which is essentially an inverted short frame sync.

If GPIO_SEL is set to GPIO_DATA then the content of this field is passed to GPIO1 as an output.

2

Note 30: The left justified I S mode is similar to normal I S other than there is no delay between a change in WS to the MSB:

20134117

FIGURE 12. I²S Serial Data Format (Left Justified Mode)

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56

12.0 Status & Control Registers (Continued)

12.34 SAR CHANNELS 0 & 1 CONFIGURATION REGISTER

This register is used to control channel 0 and 1 of the SAR system. (Note 31)

TABLE 33. SAR_SLOT01 (0x1Bh)

Bits

Field

Description

2:0

SLOT_0_FS

Programs the sampling frequency of SAR channel 0:

@

SLOT_0_FS

Sample Rate 12.000 MHz

(point A)

13.888 kHz

3.472 kHz

0.868 kHz

217 Hz

54 Hz

000₂

001₂

010₂

011₂

100₂

101₂

110₂

111₂

14 Hz

4 Hz

1 Hz

3

SLOT_0_ENB

SLOT_1_FS

If set then VSAR 1 is sampled into SAR slot 0 which also activates the

SAR ADC.

6:4

Programs the sampling frequency of SAR channel 1:

@

SLOT_1_FS

Sample Rate 12.000 MHz

(point A)

13.888 kHz

3.472 kHz

0.868 kHz

217 Hz

54 Hz

000₂

001₂

010₂

011₂

100₂

101₂

110₂

111₂

14 Hz

4 Hz

1 Hz

7

SLOT_1_ENB

If set then VSAR 2 is sampled into SAR slot 1 which also activates the

SAR ADC.

Note 31: See the section SAR Overview for more details on this register.

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12.0 Status & Control Registers (Continued)

12.35 SAR CHANNELS 2 & 3 CONFIGURATION REGISTER

This register is used to control channel 2 and 3 of the SAR system. (Note 31)

TABLE 34. SAR_SLOT23 (0x1Ch)

Bits

Field

Description

2:0

SLOT_2_FS

Programs the sampling frequency of SAR channels 2 and 3:

@

SLOT_2_FS

Sample Rate 12.000 MHz

(point A)

13.888 kHz

3.472 kHz

0.868 kHz

217 Hz

54 Hz

000₂

001₂

010₂

011₂

100₂

101₂

110₂

111₂

14 Hz

4 Hz

1 Hz

3

4

5

SLOT_2_ENB

SLOT_3_ENB

SLOT_2_VBB

If set then D_V_DD/ 2 or BB_V_DD(depending on SLOT2_V_BB) is sampled

into SAR slot 2 which also activates the SAR ADC.

If set then A_V_DD/ 2 is sampled into SAR slot 3 which also activates the

SAR ADC.

If set then BB_V_DDinput is used as input to SAR slot 2 rather than the

D_V_DD

.

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58

12.0 Status & Control Registers (Continued)

12.36 SAR DATA 0 TO 3 REGISTERS

These registers are used to read the 8 MSBs from the 4 SAR channels.

TABLE 35. SAR_DATA_0 Register (0x1Dh)

Description

Bits

Field

7:0

SLOT_0_DATA

Latest slot 0 sample bits 11:4.

TABLE 36. SAR_DATA_1 Register (0x1Eh)

Description

Bits

Field

7:0

SLOT_1_DATA

Latest slot 1 sample bits 11:4.

TABLE 37. SAR_DATA_2 Register (0x1Fh)

Description

Bits

Field

7:0

SLOT_2_DATA

Latest slot 2 sample bits 11:4.

TABLE 38. SAR_DATA_3 Register (0x20h)

Description

Bits

Field

7:0

SLOT_3_DATA

Latest slot 3 sample bits 11:4.

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12.0 Status & Control Registers (Continued)

12.37 SAR OVERVIEW

The SAR controller works via a scheduler that allocates time slots for each of the four channels. All four channels can operate up

to the same maximum frequency. When the sampling frequency of a channel is to be reduced the time slot allocated to that

channel is simply enabled less often. For example if one slot is to work at a quarter of the frequency of the others then only one

in four of its allocated slot triggers the SAR to activate:

20134118

FIGURE 13. Internal SAR Control Signals to SAR Module

Each time slot is used to sample a single fixed input, slot 0 is used for VSAR 1, slot 1 for VSAR 2, slot 2 for either D_V_DDor

BB_V_DD* and slot 3 for the A_V_DD. When a particular time slot is activated the correct mux, clock and enable controls to the ADC

module are produced and the output sampled when ready. If the D_V_DDor the A_V_DDare being sampled then a voltage divider

is used to half the input to below the full scale reference of 2.5V. As this results in a current path to ground it is only inserted while

the ADC is settling to reduce power consumption.

Using this method, samples can be taken using as little power as possible while allowing sample rates as low as 1 Hz. The data

can either be read directly or used to trigger interrupts when set voltages are passed. This reduces the baseband controllers

software overhead and IO bandwidth, further reducing system power.

The full scale digital output from the SAR is equal to 2.5V. The A_V_DDand D_V_DDinputs are divided by two during sampling. The

SAR ADC can be activated at any time, even while the chip is in shutdown mode (chip mode ’00’). This allows the LM4935 to

perform housekeeping duties such as voltage monitoring with minimal power consumption.

*Depending on SLOT_2_VBB in SAR_SLOT23 (0x1Ch).

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12.0 Status & Control Registers (Continued)

Only the 8 MSBS [11:4] from the 12 bits of SAR output data can be read back using the I²C interface.

The SPI interface can be used to access all 12 bits of the SAR output data. In this case, GPIO2 should be set to SAR_SDO by

setting GPIO_SEL in register (0x1Ah). The SAR channel selected by SAR_CH_SEL in the GPIO register is then output onto

GPIO2 as follows:

20134108

FIGURE 14. SPI SAR Read Transaction (GPIO2 set to SAR_SDO)

In applications where the 8 MSBS [11:4] from the SAR output data is enough resolution, GPIO2 should be set to SPI_SDO by

setting GPIO_SEL in register (0x1Ah). The SAR data is then output on GPIO2 as follows:

20134107

FIGURE 15. SPI SAR Read Transaction (GPIO2 set to SPI_SDO)

If the user performs a write to the GPIO register the changes will not take effect until the next SPI operation so SAR data can be

read while the next channel is being selected. The SAR data is sampled at the start of the SPI transaction to ensure that the data

is stable during the read operation.

All 12 bits of the SAR output data for up to 2 SAR channels can be read back simultaneously through the bi-directional I²S

interface. This is accomplished by setting I2S_SDO_DATA (bit [7:6] of (0x19h)) to the desired SAR channel(s).

As mentioned previously in the Digital Audio Data Formats section, when SAR SDO is passed to the I²S bus, the SAR SDO’s

MSB is aligned with the MSB of I2S_SDO.

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12.0 Status & Control Registers (Continued)

12.38 DC VOLUME CONFIGURATION REGISTER

This register is used to control the DC volume control system.

TABLE 39. DC_VOLUME (0x21h)

Bits

Field

Description

0

DC_VOL_ENB

Enables the DC volume control system to use the voltage applied on the

VSAR 1 pin to set the gain of the DC volume control. (Note 32)

Selects which volume is altered:

1

DC_VOL_EFFECT

MAX_LEVEL

DC_VOL_EFFECT

Source

AUX/DAC

CPI

0

1

3:2

Programs the maximum level that can be applied by the system

MAX_LEVEL

LEVEL

0 dB

00₂

01₂

10₂

11₂

−3 dB

−6 dB

−12 dB

Note 32: The correlation between the voltage on VSAR1 to the attenuation on the AUX/DAC channel is as follows:

201341P4

FIGURE 16. DC Volume Transfer Function For AUX/DAC

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62

12.0 Status & Control Registers (Continued)

12.39 SAR TRIGGER 1 CONFIGURATION REGISTER

This register is used to setup a voltage trigger on one of the SAR outputs.

TABLE 40. TRIG_1 (0x22h)

Bits

0

Field

Description

TRIG_1_ENB

TRIG_1_DIR

Enables the 1st SAR trigger interrupt, if cleared will clear the IRQ.

Selects the direction the voltage should be moving:

1

TRIG_1_DIR

Trigger if signal passes:

Above Threshold

0

1

Below Threshold

3:2

7:4

TRIG_1_SOURCE

Programs the channel used by the trigger.

TRIG_1_SOURCE

Source

VSAR_1

00₂

01₂

10₂

11₂

VSAR_2

D_V_DD/2 or BB_V_DD

A_V_DD/2

TRIG_1_LSB

Sets bits 3:0 of the threshold used by the trigger.

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12.0 Status & Control Registers (Continued)

12.40 SAR TRIGGER 1 MSBs CONFIGURATION REGISTER

This register is used to setup the threshold of a voltage trigger on one of the SAR outputs.

TABLE 41. TRIG_1_MSB (0x23h)

Bits

Field

Description

Sets bits 11:4 of the threshold used by the trigger.

7:0

TRIG_1_MSB

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12.0 Status & Control Registers (Continued)

12.41 SAR TRIGGER 2 CONFIGURATION REGISTER

This register is used to setup a voltage trigger on one of the SAR outputs.

TABLE 42. TRIG_2 (0x24h)

Bits

0

Field

Description

TRIG_2_ENB

TRIG_2_DIR

Enables the 2nd SAR trigger interrupt, if cleared will clear the IRQ.

Selects the direction the voltage should be moving:

1

TRIG_2_DIR

Trigger if signal passes:

Above Threshold

0

1

Below Threshold

3:2

7:4

TRIG_2_SOURCE

Programs the channel used by the trigger

TRIG_2_SOURCE

Source

VSAR_1

00₂

01₂

10₂

11₂

VSAR_2

D_V_DD/2 or BB_V_DD

A_V_DD/2

TRIG_2_LSB

Sets bits 3:0 of the threshold used by the trigger.

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12.0 Status & Control Registers (Continued)

12.42 SAR TRIGGER 2 MSBs CONFIGURATION REGISTER

This register is used to setup the threshold of a voltage trigger on one of the SAR outputs.

TABLE 43. TRIG_2_MSB (0x25h)

Bits

Field

Description

Sets bits 11:4 of the threshold used by the trigger.

7:0

TRIG_2_MSB

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12.0 Status & Control Registers (Continued)

12.43 DEBUG REGISTER

This register is used to set test modes within the device.

TABLE 44. DEBUG (0x26h)

Description

Bits

0

Field

RSVD

Reserved

1

RSVD

2

RSVD

3

SOFT_RESET

RSVD

This field can be used to reset the chip without a power cycle.

4

Reserved

5

RSVD

6

RSVD

7

GPIO_TEST_MODE If set and GPIO_SEL = ’010’, then the GPIOs are configured to interface with the LMV1026

digital microphone as long as AUDIO_IF_MODE (0x19h) is not set to ’11’.

GPIO_SEL

000₂

GPIO 1

RSVD

GPIO 2

RSVD

001₂

RSVD

010₂

VADC_CLOCK_OUT

RSVD

DIG_MIC_IN

RSVD

011₂

100₂

RSVD

101₂

RSVD

110₂

RSVD

111₂

RSVD

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13.0 Typical Performance Characteristics

(For all performance curves AV_DDrefers to the voltage applied to the A_V_DDand LS_V_DDpins. DV_DDrefers to the voltage applied

to the D_V_DDand PLL_V_DDpins; AV_DD= 3.3V and DV_DD= 3.3V unless otherwise specified.

Stereo DAC Frequency Response

f_S= 8kHz

Stereo DAC Frequency Response Zoom

f_S= 8kHz

20134136

20134137

Stereo DAC Frequency Response

f_S= 16kHz

Stereo DAC Frequency Response Zoom

f_S= 16kHz

20134138

20134139

Stereo DAC Frequency Response

f_S= 24kHz

Stereo DAC Frequency Response Zoom

f_S= 24kHz

20134140

20134141

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68

13.0 Typical Performance Characteristics (Continued)

Stereo DAC Frequency Response

f_S= 32kHz

Stereo DAC Frequency Response Zoom

f_S= 32kHz

20134142

20134143

Stereo DAC Frequency Response

f_S= 48kHz

Stereo DAC Frequency Response Zoom

f_S= 48kHz

20134145

20134144

THD+N vs

Stereo DAC Input Voltage

(0dB DAC, AUXOUT)

Stereo DAC Crosstalk

(0dB DAC, HP SE)

20134147

20134146

69

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13.0 Typical Performance Characteristics (Continued)

MONO ADC Frequency Response

f_S= 8kHz, 6dB MIC

MONO ADC Frequency Response Zoom

f_S= 8kHz, 6dB MIC

20134148

20134149

MONO ADC Frequency Response

f_S= 8kHz, 36dB MIC

MONO ADC Frequency Response Zoom

f_S= 8kHz, 36dB MIC

20134150

20134151

MONO ADC Frequency Response

f_S= 16kHz, 6dB MIC

MONO ADC Frequency Response Zoom

f_S= 16kHz, 6dB MIC

20134152

20134153

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70

13.0 Typical Performance Characteristics (Continued)

MONO ADC Frequency Response

f_S= 16kHz, 36dB MIC

MONO ADC Frequency Response Zoom

f_S= 16kHz, 36dB MIC

20134154

20134155

MONO ADC Frequency Response

f_S= 24kHz, 6dB MIC

MONO ADC Frequency Response Zoom

f_S= 24kHz, 6dB MIC

20134156

20134157

MONO ADC Frequency Response

f_S= 24kHz, 36dB MIC

MONO ADC Frequency Response Zoom

f_S= 24kHz, 36dB MIC

20134158

20134169

71

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13.0 Typical Performance Characteristics (Continued)

MONO ADC Frequency Response

f_S= 32kHz, 6dB MIC

MONO ADC Frequency Response Zoom

f_S= 32kHz, 6dB MIC

20134159

20134160

MONO ADC Frequency Response

f_S= 32kHz, 36dB MIC

MONO ADC Frequency Response Zoom

f_S= 32kHz, 36dB MIC

20134161

20134162

MONO ADC HPF Frequency Response

f_S= 8kHz, 36dB MIC

MONO ADC HPF Frequency Response

f_S= 16kHz, 36dB MIC

(from left to right: HPF_MODE ’00’, ’10’, ’01’)

20134163

20134164

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72

13.0 Typical Performance Characteristics (Continued)

MONO ADC HPF Frequency Response

f_S= 24kHz, 36dB MIC

MONO ADC HPF Frequency Response

f_S= 32kHz, 36dB MIC

(from left to right: HPF_MODE ’00’, ’10’, ’01’)

20134165

20134166

MONO ADC THD+N

vs MIC Input Voltage

(f_S= 8kHz, 6dB MIC)

MONO ADC THD+N

vs MIC Input Voltage

(f_S= 8kHz, 36dB MIC)

20134168

20134167

MONO ADC PSRR vs Frequency

AV_DD= 3.3V, 6dB MIC

MONO ADC PSRR vs Frequency

AV_DD= 5V, 6dB MIC

20134170

20134171

73

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13.0 Typical Performance Characteristics (Continued)

MONO ADC PSRR vs Frequency

AV_DD= 3.3V, 36dB MIC

MONO ADC PSRR vs Frequency

AV_DD= 5V, 36dB MIC

20134172

20134173

20134175

20134177

AUXOUT PSRR vs Frequency

AV_DD= 3.3V, 0dB AUX

AUXOUT PSRR vs Frequency

AV_DD= 5V, 0dB AUX

(AUX inputs terminated)

20134174

AUXOUT PSRR vs Frequency

AV_DD= 3.3V, 0dB CPI

AUXOUT PSRR vs Frequency

AV_DD= 5V, 0dB CPI

(CPI inputs terminated)

20134176

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74

13.0 Typical Performance Characteristics (Continued)

AUXOUT PSRR vs Frequency

AV_DD= 3.3V, 0dB DAC

(DAC inputs selected)

AUXOUT PSRR vs Frequency

AV_DD= 5V, 0dB DAC

(DAC inputs selected)

20134178

20134180

20134182

20134179

20134181

20134183

CPOUT PSRR vs Frequency

AV_DD= 3.3V, 0dB AUX

(AUX inputs terminated)

CPOUT PSRR vs Frequency

AV_DD= 5V, 0dB AUX

(AUX inputs terminated)

CPOUT PSRR vs Frequency

AV_DD= 3.3V, 0dB DAC

(DAC inputs selected)

CPOUT PSRR vs Frequency

AV_DD= 5V, 0dB DAC

(DAC inputs selected)

75

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13.0 Typical Performance Characteristics (Continued)

CPOUT PSRR vs Frequency

AV_DD= 3.3V, 36dB MIC

CPOUT PSRR vs Frequency

AV_DD= 5V, 36dB MIC

(EXTMIC inputs terminated, AGC on)

20134185

20134187

CPOUT PSRR vs Frequency

AV_DD= 3.3V, 36dB MIC, MICBIAS = 2.0V

(INTMIC DIFF inputs terminated, AGC off)

AV_DD= 3.3V, 36dB MIC, MICBIAS = 2.0V

(INTMIC DIFF inputs terminated, AGC on)

20134188

20134189

CPOUT PSRR vs Frequency

AV_DD= 3.3V, 36dB MIC, MICBIAS = 2.5V

(INTMIC DIFF inputs terminated, AGC off)

AV_DD= 3.3V, 36dB MIC, MICBIAS = 2.5V

(INTMIC DIFF inputs terminated, AGC on)

20134190

20134191

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76

13.0 Typical Performance Characteristics (Continued)

CPOUT PSRR vs Frequency

AV_DD= 3.3V, 36dB MIC, MICBIAS = 2.8V

(INTMIC DIFF inputs terminated, AGC off)

AV_DD= 3.3V, 36dB MIC, MICBIAS = 2.8V

(INTMIC DIFF inputs terminated, AGC on)

20134192

20134193

CPOUT PSRR vs Frequency

AV_DD= 5V, 36dB MIC, MICBIAS = 2.0V

(INTMIC DIFF inputs terminated, AGC off)

CPOUT PSRR vs Frequency

AV_DD= 5V, 36dB MIC, MICBIAS = 2.0V

(INTMIC DIFF inputs terminated, AGC on)

20134196

20134197

CPOUT PSRR vs Frequency

AV_DD= 5V, 36dB MIC, MICBIAS = 2.5V

(INTMIC DIFF inputs terminated, AGC off)

CPOUT PSRR vs Frequency

AV_DD= 5V, 36dB MIC, MICBIAS = 2.5V

(INTMIC DIFF inputs terminated, AGC on)

20134198

20134199

77

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13.0 Typical Performance Characteristics (Continued)

CPOUT PSRR vs Frequency

AV_DD= 5V, 36dB MIC, MICBIAS = 2.8V

(INTMIC DIFF inputs terminated, AGC off)

CPOUT PSRR vs Frequency

AV_DD= 5V, 36dB MIC, MICBIAS = 2.8V

(INTMIC DIFF inputs terminated, AGC on)

201341A0

201341A1

CPOUT PSRR vs Frequency

AV_DD= 5V, 36dB MIC, MICBIAS = 3.3V

(INTMIC DIFF inputs terminated, AGC off)

CPOUT PSRR vs Frequency

AV_DD= 5V, 36dB MIC, MICBIAS = 3.3V

(INTMIC DIFF inputs terminated, AGC on)

201341A2

201341A3

CPOUT PSRR vs Frequency

AV_DD= 3.3V, 36dB MIC

CPOUT PSRR vs Frequency

AV_DD= 5V, 36dB MIC

(INTMIC SE input terminated, AGC on)

201341A5

201341A7

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78

13.0 Typical Performance Characteristics (Continued)

Earpiece PSRR vs Frequency

AV_DD= 3.3V, 0dB AUX

Earpiece PSRR vs Frequency

AV_DD= 5V, 0dB AUX

(AUX inputs terminated)

201341A8

201341B0

201341B2

201341A9

201341B1

201341B3

Earpiece PSRR vs Frequency

AV_DD= 3.3V, 0dB CPI

Earpiece PSRR vs Frequency

AV_DD= 5V, 0dB CPI

(CPI input terminated)

Earpiece PSRR vs Frequency

AV_DD= 3.3V, 0dB DAC

(DAC input selected)

Earpiece PSRR vs Frequency

AV_DD= 5V, 0dB DAC

(DAC input selected)

79

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13.0 Typical Performance Characteristics (Continued)

Headphone PSRR vs Frequency

AV_DD= 3.3V, 0dB AUX, OCL 1.2V

(AUX inputs terminated)

Headphone PSRR vs Frequency

AV_DD= 5V, 0dB AUX, OCL 1.2V

(AUX inputs terminated)

201341B4

201341B5

Headphone PSRR vs Frequency

AV_DD= 3.3V, 0dB CPI, OCL 1.2V

(CPI input terminated)

Headphone PSRR vs Frequency

AV_DD= 5V, 0dB CPI, OCL 1.2V

(CPI input terminated)

201341B6

201341B7

Headphone PSRR vs Frequency

AV_DD= 3.3V, 0dB ADC, OCL 1.2V

(DAC input selected)

Headphone PSRR vs Frequency

AV_DD= 5V, 0dB ADC, OCL 1.2V

(DAC input selected)

201341B8

201341B9

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80

13.0 Typical Performance Characteristics (Continued)

Headphone PSRR vs Frequency

AV_DD= 3.3V, 0dB AUX, OCL 1.5V

(AUX inputs terminated)

Headphone PSRR vs Frequency

AV_DD= 5V, 0dB AUX, OCL 1.5V

(AUX inputs terminated)

201341C0

201341C1

Headphone PSRR vs Frequency

AV_DD= 3.3V, 0dB CPI, OCL 1.5V

(CPI input terminated)

Headphone PSRR vs Frequency

AV_DD= 5V, 0dB CPI, OCL 1.5V

(CPI input terminated)

201341C2

201341C3

Headphone PSRR vs Frequency

AV_DD= 3.3V, 0dB DAC, OCL 1.5V

(DAC input selected)

Headphone PSRR vs Frequency

AV_DD= 5V, 0dB DAC, OCL 1.5V

(DAC input selected)

201341C4

201341C5

81

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13.0 Typical Performance Characteristics (Continued)

Headphone PSRR vs Frequency

AV_DD= 3.3V, 0dB AUX, SE

(AUX inputs terminated)

Headphone PSRR vs Frequency

AV_DD= 5V, 0dB AUX, SE

(AUX inputs terminated)

201341C6

201341C7

Headphone PSRR vs Frequency

AV_DD= 3.3V, 0dB CPI, SE

(CPI input terminated)

Headphone PSRR vs Frequency

AV_DD= 5V, 0dB CPI, SE

(CPI input terminated)

201341C8

201341C9

Headphone PSRR vs Frequency

AV_DD= 3.3V, 0dB DAC, SE

(DAC input selected)

Headphone PSRR vs Frequency

AV_DD= 5V, 0dB DAC, SE

(DAC input selected)

201341D0

201341D1

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82

13.0 Typical Performance Characteristics (Continued)

Loudspeaker PSRR vs Frequency

AV_DD= 3.3V, 0dB AUX

Loudspeaker PSRR vs Frequency

AV_DD= 5V, 0dB AUX

(AUX inputs terminated)

201341N6

201341N7

Loudspeaker PSRR vs Frequency

AV_DD= 3.3V, 0dB CPI

Loudspeaker PSRR vs Frequency

AV_DD= 5V, 0dB CPI

(CPI input terminated)

201341N8

201341N9

Loudspeaker PSRR vs Frequency

AV_DD= 3.3V, 0dB DAC

Loudspeaker PSRR vs Frequency

AV_DD= 5V, 0dB DAC

(DAC input selected)

201341O0

201341O1

83

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13.0 Typical Performance Characteristics (Continued)

INT/EXT MICBIAS PSRR vs Frequency

AV_DD= 3.3V, MICBIAS = 2.0V

INT/EXT MICBIAS PSRR vs Frequency

AV_DD= 5V, MICBIAS = 2.0V

201341D2

201341D3

INT/EXT MICBIAS PSRR vs Frequency

AV_DD= 3.3V, MICBIAS = 2.5V

INT/EXT MICBIAS PSRR vs Frequency

AV_DD= 5V, MICBIAS = 2.5V

201341D4

201341D5

INT/EXT MICBIAS PSRR vs Frequency

AV_DD= 3.3V, MICBIAS = 2.8V

INT/EXT MICBIAS PSRR vs Frequency

AV_DD= 5V, MICBIAS = 2.8V

201341D6

201341D7

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84

13.0 Typical Performance Characteristics (Continued)

INT/EXT MICBIAS PSRR vs Frequency

AV_DD= 5V, MICBIAS = 3.3V

AUXOUT THD+N vs Frequency

AV_DD= 3.3V, 0dB, V_OUT= 1V_RMS, 5kΩ

201341D9

201341D8

AUXOUT THD+N vs Frequency

CPOUT THD+N vs Frequency

AV_DD= 5V, 0dB, V_OUT= 1V_RMS, 5kΩ

AV_DD= 3.3V, 0dB, V_OUT= 1V_RMS, 5kΩ

201341E0

201341E1

CPOUT THD+N vs Frequency

Earpiece THD+N vs Frequency

AV_DD= 5V, 0dB, V_OUT= 1V_RMS, 5kΩ

AV_DD= 3.3V, 0dB, P_OUT= 500mW, 32Ω

201341E2

201341E3

85

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13.0 Typical Performance Characteristics (Continued)

Headphone THD+N vs Frequency

Earpiece THD+N vs Frequency

AV_DD= 3.3V, OCL 1.5V, 0dB

AV_DD= 5V, 0dB, P_OUT= 50mW, 32Ω

P_OUT= 7.5mW, 32Ω

201341E4

201341E5

Headphone THD+N vs Frequency

AV_DD= 5V, OCL 1.5V, 0dB

P_OUT= 10mW, 32Ω

Headphone THD+N vs Frequency

AV_DD= 3.3V, OCL 1.2V, 0dB

P_OUT= 7.5mW, 32Ω

201341E6

201341N1

Headphone THD+N vs Frequency

AV_DD= 5V, OCL 1.2V, 0dB

P_OUT= 10mW, 32Ω

Headphone THD+N vs Frequency

AV_DD= 3.3V, SE, 0dB

P_OUT= 7.5mW, 32Ω

201341E7

201341E8

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86

13.0 Typical Performance Characteristics (Continued)

Headphone THD+N vs Frequency

AV_DD= 5V, SE, 0dB

Loudspeaker THD+N vs Frequency

AV_DD= 3.3V, P_OUT= 400mW

P_OUT= 10mW, 32Ω

15µH+8Ω+15µH

201341E9

201341O2

Loudspeaker THD+N vs Frequency

AV_DD= 5V, P_OUT= 400mW

15µH+8Ω+15µH

Earpiece THD+N vs Output Power

AV_DD= 3.3V, 0dB AUX

f_OUT= 1kHz, 16Ω

201341F0

201341O3

Earpiece THD+N vs Output Power

AV_DD= 5V, 0dB AUX

Earpiece THD+N vs Output Power

AV_DD= 3.3V, 0dB AUX

f_OUT= 1kHz, 32Ω

f_OUT= 1kHz, 16Ω

201341F1

201341F2

87

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13.0 Typical Performance Characteristics (Continued)

Earpiece THD+N vs Output Power

AV_DD= 5V, 0dB AUX

Earpiece THD+N vs Output Power

AV_DD= 3.3V, 0dB CPI

f_OUT= 1kHz, 32Ω

f_OUT= 1kHz, 16Ω

201341F3

201341F4

Earpiece THD+N vs Output Power

AV_DD= 5V, 0dB CPI

Earpiece THD+N vs Output Power

AV_DD= 3.3V, 0dB CPI

f_OUT= 1kHz, 16Ω

f_OUT= 1kHz, 32Ω

201341F5

201341F6

Earpiece THD+N vs Output Power

AV_DD= 5V, 0dB CPI

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.2V, 0dB DAC

f_OUT= 1kHz, 16Ω

f_OUT= 1kHz, 32Ω

201341F7

201341F8

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88

13.0 Typical Performance Characteristics (Continued)

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.2V, 0dB DAC

f_OUT= 1kHz, 16Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.2V, 0dB DAC

f_OUT= 1kHz, 32Ω

201341F9

201341G0

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.2V, 0dB DAC

f_OUT= 1kHz, 32Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.2V, 12dB DAC

f_OUT= 1kHz, 16Ω

201341G1

201341G2

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.2V, 12dB DAC

f_OUT= 1kHz, 16Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.2V, 12dB DAC

f_OUT= 1kHz, 32Ω

201341G3

201341G4

89

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13.0 Typical Performance Characteristics (Continued)

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.2V, 12dB DAC

f_OUT= 1kHz, 32Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.5V, 0dB DAC

f_OUT= 1kHz, 16Ω

201341G5

201341G6

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.5V, 0dB DAC

f_OUT= 1kHz, 16Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.5V, 0dB DAC

f_OUT= 1kHz, 32Ω

201341G7

201341G8

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.5V, 0dB DAC

f_OUT= 1kHz, 32Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.5V, 12dB DAC

f_OUT= 1kHz, 16Ω

201341G9

201341H0

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90

13.0 Typical Performance Characteristics (Continued)

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.5V, 12dB DAC

f_OUT= 1kHz, 16Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.5V, 12dB DAC

f_OUT= 1kHz, 32Ω

201341H1

201341H2

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.5V, 12dB DAC

f_OUT= 1kHz, 32Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, SE, 0dB DAC

f_OUT= 1kHz, 16Ω

201341H3

201341H4

Headphone THD+N vs Output Power

AV_DD= 5V, SE, 0dB DAC

f_OUT= 1kHz, 16Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, SE, 0dB DAC

f_OUT= 1kHz, 32Ω

201341H5

201341H6

91

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13.0 Typical Performance Characteristics (Continued)

Headphone THD+N vs Output Power

AV_DD= 5V, SE, 0dB DAC

f_OUT= 1kHz, 32Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, SE, 12dB DAC

f_OUT= 1kHz, 16Ω

201341H7

201341H8

Headphone THD+N vs Output Power

AV_DD= 5V, SE, 12dB DAC

f_OUT= 1kHz, 16Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, SE, 12dB DAC

f_OUT= 1kHz, 32Ω

201341H9

201341I0

Headphone THD+N vs Output Power

AV_DD= 5V, SE, 12dB DAC

f_OUT= 1kHz, 32Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.2V, 0dB AUX

f_OUT= 1kHz, 16Ω

201341I1

201341I2

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92

13.0 Typical Performance Characteristics (Continued)

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.2V, 12dB AUX

f_OUT= 1kHz, 16Ω

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.2V, 0dB AUX

f_OUT= 1kHz, 16Ω

201341I3

201341I4

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.2V, 12dB AUX

f_OUT= 1kHz, 16Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.2V, 0dB AUX

f_OUT= 1kHz, 32Ω

201341I5

201341I6

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.2V, 12dB AUX

f_OUT= 1kHz, 32Ω

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.2V, 0dB AUX

f_OUT= 1kHz, 32Ω

201341I7

201341I8

93

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13.0 Typical Performance Characteristics (Continued)

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.2V, 12dB AUX

f_OUT= 1kHz, 32Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.2V, 0dB CPI

f_OUT= 1kHz, 16Ω

201341I9

201341J0

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.2V, 0dB CPI

f_OUT= 1kHz, 16Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.2V, 0dB CPI

f_OUT= 1kHz, 32Ω

201341J1

201341J2

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.2V, 0dB CPI

f_OUT= 1kHz, 32Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.5V, 0dB AUX

f_OUT= 1kHz, 16Ω

201341J3

201341J4

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94

13.0 Typical Performance Characteristics (Continued)

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.5V, 12dB AUX

f_OUT= 1kHz, 16Ω

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.5V, 0dB AUX

f_OUT= 1kHz, 16Ω

201341J5

201341J6

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.5V, 12dB AUX

f_OUT= 1kHz, 16Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.5V, 0dB AUX

f_OUT= 1kHz, 32Ω

201341J7

201341J8

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.5V, 12dB AUX

f_OUT= 1kHz, 32Ω

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.5V, 0dB AUX

f_OUT= 1kHz, 32Ω

201341J9

201341K0

95

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13.0 Typical Performance Characteristics (Continued)

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.5V, 12dB AUX

f_OUT= 1kHz, 32Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.5V, 0dB CPI

f_OUT= 1kHz, 16Ω

201341K1

201341K2

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.5V, 0dB CPI

f_OUT= 1kHz, 16Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, OCL 1.5V, 0dB CPI

f_OUT= 1kHz, 32Ω

201341K3

201341N2

Headphone THD+N vs Output Power

AV_DD= 5V, OCL 1.5V, 0dB CPI

f_OUT= 1kHz, 32Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, SE, 0dB AUX

f_OUT= 1kHz, 16Ω

201341N3

201341N4

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96

13.0 Typical Performance Characteristics (Continued)

Headphone THD+N vs Output Power

AV_DD= 5V, SE, 0dB AUX

f_OUT= 1kHz, 16Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, SE, 0dB AUX

f_OUT= 1kHz, 32Ω

201341K4

201341N5

Headphone THD+N vs Output Power

AV_DD= 5V, SE, 0dB AUX

f_OUT= 1kHz, 32Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, SE, 0dB CPI

f_OUT= 1kHz, 16Ω

201341K5

201341K6

Headphone THD+N vs Output Power

AV_DD= 5V, SE, 0dB CPI

f_OUT= 1kHz, 16Ω

Headphone THD+N vs Output Power

AV_DD= 3.3V, SE, 0dB CPI

f_OUT= 1kHz, 32Ω

201341K7

201341K8

97

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13.0 Typical Performance Characteristics (Continued)

Headphone THD+N vs Output Power

AV_DD= 5V, SE, 0dB CPI

f_OUT= 1kHz, 32Ω

Loudspeaker THD+N vs Output Power

AV_DD= 3.3V, 0dB AUX

f_OUT= 1kHz, 15µH+8Ω+15µH

201341K9

201341O4

Loudspeaker THD+N vs Output Power

AV_DD= 4.2V, 0dB AUX

Loudspeaker THD+N vs Output Power

AV_DD= 5V, 0dB AUX

f_OUT= 1kHz, 15µH+8Ω+15µH

201341O5

201341O6

Loudspeaker THD+N vs Output Power

AV_DD= 3.3V, 0dB CPI

Loudspeaker THD+N vs Output Power

AV_DD= 4.2V, 0dB CPI

f_OUT= 1kHz, 15µH+8Ω+15µH

201341O7

201341O8

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98

13.0 Typical Performance Characteristics (Continued)

Loudspeaker THD+N vs Output Power

AV_DD= 5V, 0dB CPI

Loudspeaker THD+N vs Output Power

AV_DD= 3.3V, 0dB DAC

f_OUT= 1kHz, 15µH+8Ω+15µH

201341O9

201341P0

Loudspeaker THD+N vs Output Power

AV_DD= 4.2V, 0dB DAC

Loudspeaker THD+N vs Output Power

AV_DD= 5V, 0dB DAC

f_OUT= 1kHz, 15µH+8Ω+15µH

201341P1

201341P2

AUXOUT THD+N vs Output Voltage

AV_DD= 3.3V, 0dB AUX

AUXOUT THD+N vs Output Voltage

AV_DD= 5V, 0dB AUX

f_OUT= 1kHz, 5kΩ

201341L0

201341L1

99

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13.0 Typical Performance Characteristics (Continued)

AUXOUT THD+N vs Output Voltage

AV_DD= 3.3V, 0dB CPI

AUXOUT THD+N vs Output Voltage

AV_DD= 5V, 0dB CPI

f_OUT= 1kHz, 5kΩ

201341L2

201341L3

AUXOUT THD+N vs Output Voltage

AV_DD= 3.3V, 0dB DAC

AUXOUT THD+N vs Output Voltage

AV_DD= 5V, 0dB DAC

f_OUT= 1kHz, 5kΩ

201341L4

201341L5

AUXOUT THD+N vs Output Voltage

AV_DD= 3.3V, 12dB DAC

f_OUT= 1kHz, 5kΩ

AUXOUT THD+N vs Output Voltage

AV_DD= 5V, 12dB DAC

f_OUT= 1kHz, 5kΩ

201341L6

201341L7

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100

13.0 Typical Performance Characteristics (Continued)

CPOUT THD+N vs Output Voltage

AV_DD= 3.3V, 0dB AUX

f_OUT= 1kHz, 5kΩ

CPOUT THD+N vs Output Voltage

AV_DD= 5V, 0dB AUX

f_OUT= 1kHz, 5kΩ

201341L8

201341L9

CPOUT THD+N vs Output Voltage

AV_DD= 3.3V, 0dB DAC

f_OUT= 1kHz, 5kΩ

CPOUT THD+N vs Output Voltage

AV_DD= 5V, 0dB DAC

f_OUT= 1kHz, 5kΩ

201341M1

201341M0

CPOUT THD+N vs Output Voltage

AV_DD= 3.3V, 6dB MIC

CPOUT THD+N vs Output Voltage

AV_DD= 5V, 6dB MIC

f_OUT= 1kHz, 5kΩ

201341M2

201341M3

101

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13.0 Typical Performance Characteristics (Continued)

CPOUT THD+N vs Output Voltage

AV_DD= 3.3V, 12dB DAC

f_OUT= 1kHz, 5kΩ

CPOUT THD+N vs Output Voltage

AV_DD= 5V, 12dB DAC

f_OUT= 1kHz, 5kΩ

201341M4

201341M5

CPOUT THD+N vs Output Voltage

AV_DD= 3.3V, 36dB MIC

f_OUT= 1kHz, 5kΩ

CPOUT THD+N vs Output Voltage

AV_DD= 5V, 36dB MIC

f_OUT= 1kHz, 5kΩ

201341M6

201341M7

Headphone Crosstalk vs Frequency

OCL 1.2V, 0dB AUX, 32Ω

OCL 1.5V, 0dB AUX, 32Ω

201341M8

201341M9

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102

13.0 Typical Performance Characteristics (Continued)

Headphone Crosstalk vs Frequency

SE, 0dB AUX, 32Ω

201341N0

103

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104

15.0 Demoboard PCB Layout

20134132

Top Silkscreen

105

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15.0 Demoboard PCB Layout (Continued)

20134131

Top Layer

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106

15.0 Demoboard PCB Layout (Continued)

20134129

Mid Layer 1

107

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15.0 Demoboard PCB Layout (Continued)

20134130

Mid Layer 2

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108

15.0 Demoboard PCB Layout (Continued)

20134128

Bottom Layer

109

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16.0 Product Status Definitions

Datasheet Status

Advance

Product Status

Formative or in

Design

Definition

This data sheet contains the design specifications for product development.

Specifications may change in any manner without notice.

Information

Preliminary

First Production

This data sheet contains preliminary data. Supplementary data will be published

at a later date. National Semiconductor Corporation reserves the right to make

changes at any time without notice in order to improve design and supply the

best possible product.

No Identification

Noted

Full Production

This data sheet contains final specifications. National Semiconductor Corporation

reserves the right to make changes at any time without notice in order to improve

design and supply the best possible product.

Obsolete

Not in Production

This data sheet contains specifications on a product that has been discontinued

by National Semiconductor Corporation. The datasheet is printed for reference

information only.

National Semiconductor B.V reserves the right to make changes without notice to any products herein to improve reliability, function or design. National does not

assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the

right of others.

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110

17.0 Revision History

Rev

1.0

Date

Description

Filled in the actual limits (for TBDs) under

Limit and edited few Typical values, all

under the EC table. Edits from Alvin F.

Input more edits. Replaced the correct

boards. Replaced the Schematic Diagram

(pg 60).

5/11/05

1.1

7/29/05

1.2

1.3

1.4

1.5

1.6

1.7

1.8

9/8/05

9/21/05

9/30/05

10/5/05

10/11/05

10/12/05

10/14/5

Added the 1st set of Typ Perf curves.

Added a couple of tables.

Input text edits.

Input more edits.

More edits.

First D/S WEB release.

Input more text edits after the 1st

released.

1.9

2.0

10/17/05

10/18/05

Input some text edits, then re-released

D/S to the WEB.

More text edits. Also used graphic

20134107 back.

111

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18.0 Physical Dimensions inches (millimeters) unless otherwise noted

49 Bump Microfil Package

Order Number LM4935

Dimensions: X1 = 3.925 mm, X2 = 3.925 mm, X3 = 0.6 mm

NS Package Number WLA49VVA

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves

the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS

WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR

CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or

(b) support or sustain life, and whose failure to perform when

properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result

in a significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be reasonably

expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

BANNED SUBSTANCE COMPLIANCE

National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products

Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain

no ‘‘Banned Substances’’ as defined in CSP-9-111S2.

Leadfree products are RoHS compliant.

National Semiconductor

Americas Customer

Support Center

National Semiconductor

Europe Customer Support Center

Fax: +49 (0) 180-530 85 86

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Support Center

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Fax: 81-3-5639-7507

Email: new.feedback@nsc.com

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Email: ap.support@nsc.com

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Tel: 81-3-5639-7560

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型号：	LM4935WLX
厂家：	National Semiconductor
描述：	Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC 音频子系统具有双模立体声耳机和单声道高效扬声器放大器和多用途ADC 放大器
文件：	总112页 (文件大小：4995K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM4935WLX [NSC]

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