LM5041SDX [NSC]
Cascaded PWM Controller; 级联型PWM控制器
| 型号： | LM5041SDX |
| 厂家： | 
National Semiconductor |
| 描述： | Cascaded PWM Controller |
| 文件： | 总16页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 2003
LM5041
Cascaded PWM Controller
General Description
Features
n Internal Start-up Bias Regulator
The LM5041 PWM controller contains all of the features
necessary to implement either current-fed or voltage-fed
push-pull or bridge power converters. These “Cascaded”
topologies are well suited for multiple output and higher
power applications. The LM5041’s four control outputs in-
clude: the buck stage controls (HD and LD) and the push-
pull control outputs (PUSH and PULL). Push-pull outputs are
driven at 50% nominal duty cycle at one half of the switching
frequency of the buck stage and can be configured for either
a guaranteed overlap time (for current-fed applications) or a
guaranteed both-off time (for voltage-fed applications).
Push-pull stage MOSFETs can be driven directly from the
internal gate drivers while the buck stage requires an exter-
nal driver such as the LM5102. The LM5041 includes a
high-voltage start-up regulator that operates over a wide
input range of 15V to 100V. The PWM controller is designed
for high-speed capability including an oscillator frequency
range up to 1 MHz and total propagation delays of less than
100ns. Additional features include: line Under-Voltage Lock-
out (UVLO), soft-start, an error amplifier, precision voltage
reference, and thermal shutdown.
n Programmable Line Under-Voltage Lockout (UVLO) with
Adjustable Hysteresis
n Current Mode Control
n Internal Error Amplifier with Reference
n Dual Mode Over-Current Protection
n Leading Edge Blanking
n Programmable Push-Pull Overlap or Dead Time
n Internal 1.5A Push-Pull Gate Drivers
n Programmable Soft-start
n Programmable Oscillator with Sync Capability
n Precision Reference
n Thermal Shutdown
Applications
n Telecommunication Power Converters
n Industrial Power Converters
n Multi-Output Power Converters
n +42V Automotive Systems
Packages
n TSSOP-16
n LLP-16 (5x5 mm) Thermally Enhanced
Typical Application Circuit
20074901
Simplified Cascaded Push-Pull Power Converter
© 2003 National Semiconductor Corporation
DS200749
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Connection Diagram
20074902
16-Lead TSSOP, LLP
Ordering Information
Order Number
LM5041MTC
LM5041MTCX
LM5041SD
Package Type
NSC Package Drawing
MTC-16
Supplied As
TSSOP-16
TSSOP-16
LLP-16
92 Units per anti-static tube
2500 Units on Tape and Reel
Available Soon
MTC-16
SDA-16A
LM5041SDX
LLP-16
SDA-16A
Available Soon
Pin Description
PIN
1
NAME
VIN
DESCRIPTION
APPLICATION INFORMATION
Source Input Voltage
Feedback Signal
Input to start-up regulator. Input range 15V to 100V.
Inverting input for the internal error amplifier. The
non-inverting input is connected to a 0.75V
reference.
2
FB
3
4
COMP
REF
Output of the Internal Error Amplifier
Precision 5 volt reference output
There is an internal 5kΩ resistor pull-up on this pin.
The error amplifier provides an active sink.
Maximum output current: 10mA. Locally decouple
with a 0.1µF capacitor. Reference stays low until the
line UV and the VCC UV are satisfied.
5
HD
Main Buck PWM control output
Sync Switch control output
Buck switch PWM control output. The maximum duty
cycle clamp for this output corresponds to an off time
of typically 240ns per cycle. The LM5101 or LM5102
Buck stage gate driver can be used to level shift and
drive the Buck switch.
6
7
LD
Sync Switch control output. Inversion of HD output.
The LM5101 or LM5102 lower drive can be used to
drive the synchronous rectifier switch.
VCC
Output from the internal high voltage start-up If an auxiliary winding raises the voltage on this pin
regulator. Regulated to 9 volts.
above the regulation setpoint, the internal start-up
regulator will shutdown, reducing the IC power
dissipation.
8
PUSH
Output of the push-pull drivers
Output of the push-pull gate driver. Output capability
of 1.5A peak .
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2
Pin Description (Continued)
PIN
NAME
DESCRIPTION
APPLICATION INFORMATION
Output of the push-pull gate driver. Output capability
of 1.5A peak.
9
PULL
Output of the push-pull drivers
10
11
12
PGND
AGND
CS
Power ground
Connect directly to analog ground.
Analog ground
Connect directly to power ground.
Current sense input
Current sense input to the PWM comparator (CM
control). There is a 50ns leading edge blanking on
this pin. Using separate dedicated comparators, if
CS exceeds 0.5V the outputs will go into cycle by
cycle current limit. If CS exceeds 0.6V the outputs
will be disabled and a soft-start commenced.
An external capacitor and an internal 10uA current
source, set the soft-start ramp. The controller will
enter a low power state if the SS pin is below the
shutdown threshold of 0.45V
13
14
SS
Soft-start control
TIME
Push-Pull overlap and dead time control
An external resistor sets the overlap time or dead
time for the push-pull outputs. A resistor connected
between TIME and GND produces overlap. A
resistor connected between TIME and REF produces
dead time.
15
16
RT / SYNC Oscillator timing resistor pin and sync
UVLO Line Under-Voltage Shutdown
An external resistor sets the oscillator frequency.
This pin will also accept an external oscillator.
An external divider from the power converter source
sets the shutdown levels. Threshold of operation
equals 2.5V. Hysteresis is set by a switched internal
current source (20µA).
3
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Block Diagram
Simplified Block Diagram
20074903
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4
Absolute Maximum Ratings (Note 1)
ESD Rating
Lead temperature (Note 2)
Wave
2 kV
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
4 seconds
10 seconds
75 seconds
260˚C
240˚C
219˚C
Infrared
VIN to GND
100V
Vapor Phase
VCC to GND
16V
All Other Inputs to GND
Junction Temperature
Storage Temperature
Range
-0.3 to 7V
150˚C
Operating Ratings (Note 1)
VIN
15 to 90V
-65˚C to +150˚C
Junction Temperature
-40˚C to +105˚C
Electrical Characteristics
Specifications with standard typeface are for TJ = 25˚C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 26.7kΩ, RSET = 20kΩ) unless otherwise stated (Note 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Startup Regulator
VCC Reg
I-VIN
VCC Regulation
VCC Current Limit
Startup Regulator
Leakage (external Vcc
Supply)
open circuit
8.7
15
9
9.3
V
(Note 4)
25
mA
µA
VIN = 100V
145
500
Shutdown Current (Iin) UVLO = 0V, VCC = open
350
450
µA
V
VCC Supply
VCC Under-voltage
Lockout Voltage
VCC Reg
- 400mV
VCC Reg -
275mV
(positive going Vcc
)
VCC Under-voltage
Hysteresis
1.7
2.1
3
2.6
4
V
Supply Current (ICC
)
CL = 0
mA
Error Amplifier
GBW Gain Bandwidth
3
80
0.75
8
MHz
dB
DC Gain
Input Voltage
VFB = COMP
0.735
4
0.765
V
COMP Sink Capability
Reference Supply
VREF Ref Voltage
VFB = 1.5V, COMP= 1V
mA
IREF = 0 mA
4.85
15
5
5.15
50
V
Ref Voltage
IREF = 0 to 10mA
25
mV
Regulation
Ref Current Limit
20
40
mA
ns
Current Limit
ILIM Delay to Output
CS Step from 0 to 0.6V
Time to Onset of OUT
Transition (90%)
CL = 0
Cycle by Cycle
Threshold Voltage
Cycle Skip Threshold
Voltage
0.45
0.55
0.5
0.6
50
5
0.55
0.65
V
V
Resets SS capacitor;
auto restart
Leading Edge
Blanking Time
CS Sink Current
(clocked)
ns
mA
CS = 0.3V
2
5
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Electrical Characteristics (Continued)
Specifications with standard typeface are for TJ = 25˚C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 26.7kΩ, RSET = 20kΩ) unless otherwise stated (Note 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
µA
V
Soft-Start
Soft-start Current
Source
7
10
13
Soft-start to COMP
Offset
0.35
0.25
0.55
0.5
200
600
3
0.75
0.75
Shutdown Threshold
V
Oscillator
Frequency1 (RT =
26.7KΩ)
TJ = 25˚C
180
175
515
220
225
685
kHz
kHz
V
Frequency2 (RT =
7.87KΩ)
Sync threshold
3.5
PWM Comparator
Delay to Output
COMP set to 2V
CS stepped 0 to 0.4V,
Time to onset of OUT
transition low
25
ns
Max Duty Cycle
Min Duty Cycle
COMP to PWM
Comparator Gain
COMP Open Circuit
Voltage
TS = Oscillator Period
COMP = 0V
(Ts-240ns)/Ts)
%
%
0
0.32
4.8
1
FB = 0V
4.1
0.6
5.5
1.4
V
COMP Short Circuit
Current
FB = 0V, COMP = 0V
mA
Slope Compensation
Slope Comp Amplitude Delta increase at PWM
Comparator to CS
110
mV
UVLO Shutdown
Under-voltage
Shutdown
2.44
16
2.5
20
2.56
24
V
Under-voltage
Shutdown
µA
Hysteresis Current
Source
Buck Stage Outputs
Output High level
5 (VREF
)
V
V
Output High Saturation IOUT = 10mA
REF = VOUT
0.5
1
1
Output Low Saturation
Rise Time
IOUT = −10mA
CL = 100pF
CL = 100pF
0.5
10
10
V
ns
ns
Fall Time
Push-Pull Outputs
Overlap Time
RSET = 20kΩ Connected
to GND, 50% to 50%
Transitions
60
65
90
95
120
125
ns
ns
Dead Time
RSET = 20kΩ Connected
to GND, 50% to 50%
Transitions
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6
Electrical Characteristics (Continued)
Specifications with standard typeface are for TJ = 25˚C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 26.7kΩ, RSET = 20kΩ) unless otherwise stated (Note 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Output High Saturation IOUT = 50mA
VCC - VOUT
0.25
0.5
V
Output Low Saturation
Rise Time
IOUT = 100mA
CL = 1nF
0.5
20
20
1
V
ns
ns
Fall Time
CL = 1nF
Thermal Shutdown
TSD Thermal Shutdown
165
25
˚C
˚C
Temp.
Thermal Shutdown
Hysteresis
Thermal Resistance
θJA Junction to Ambient
MTC Package
SDA Package
125
32
˚C/W
˚C/W
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: For detailed information on soldering plastic TSSOP and LLP packages, refer to the Packaging Data Book available from National Semiconductor
Corporation.
Note 3: All limits are guaranteed. All electrical characteristics having room temperature limits are tested during production with T = T = 25˚C. All hot and cold limits
A
J
are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
Note 4: Device thermal limitations may limit usable range.
7
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Typical Performance Characteristics
VCC and VIN vs VIN
VCC vs ICC
20074909
20074908
SS Pin Current vs Temp
Frequency vs RT
20074910
20074915
Overlap Time vs RSET
Dead Time vs RSET
20074912
20074911
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8
Typical Performance Characteristics (Continued)
Overlap Time vs Temp
Dead Time vs Temp
20074913
20074914
Error Amplifier Gain Phase
20074916
9
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ground sets the operational range of the converter. The
divider must be designed such that the voltage at the UVLO
pin will be greater than 2.5V when VIN is in the desired
operating range. If the Under-Voltage threshold is not met,
all functions of the controller are disabled and the controller
Detailed Operating Description
The LM5041 PWM controller contains all of the features
necessary to implement either current-fed or voltage-fed
push-pull or bridge power converters. These “Cascaded”
topologies are well suited for multiple output and higher
power applications. The LM5041’s four control outputs in-
clude: the buck stage controls (HD and LD) and the push-
pull control outputs (PUSH and PULL). Push-pull outputs are
driven at 50% nominal duty cycle at one half of the switching
frequency of the buck stage and can be configured for either
a guaranteed overlap time (for current-fed applications) or a
guaranteed both-off time (for voltage-fed applications).
Push-pull stage MOSFETs can be driven directly from the
internal gate drivers while the buck stage requires an exter-
nal driver such as the LM5102. The LM5041 includes a
high-voltage start-up regulator that operates over a wide
input range of 15V to 100V. The PWM controller is designed
for high-speed capability including an oscillator frequency
range up to 1 MHz and total propagation delays of less than
100ns. Additional features include: line Under-Voltage Lock-
out (UVLO), soft-start, an error amplifier, precision voltage
reference, and thermal shutdown.
<
will enter a low-power state with input current 300µA.
ULVO hysteresis is accomplished with an internal 20µA cur-
rent source that is switched on or off into the impedance of
the set-point divider. When the UVLO threshold is exceeded,
the current source is activated to instantly raise the voltage
at the UVLO pin. When the UVLO pin falls below the 2.5V
threshold, the current source is turned off causing the volt-
age at the UVLO pin to fall. The UVLO pin can also be used
to implement a remote enable / disable function. By shorting
the UVLO pin to ground, the converter can be disabled. The
controller can also be disabled through the soft-start pin
(SS). The controller will enter a low-power off state if the SS
pin is forced below the 0.45V shutdown threshold.
Buck Stage Control Outputs
The LM5041 Buck switch maximum duty cycle clamp en-
sures that there will be sufficient off time each cycle to
recharge the bootstrap capacitor used in the high side gate
driver. The Buck switch is guaranteed to be off, and the sync
switch on, for at least 250ns per switching cycle. The Buck
stage control outputs (LD and HD) are CMOS buffers with
logic levels of 0 to 5V.
High Voltage Start-Up Regulator
The LM5041 contains an internal high-voltage start-up regu-
lator, thus the input pin (Vin) can be connected directly to the
line voltage. The regulator output is internally current limited
to 15mA. When power is applied, the regulator is enabled
and sources current into an external capacitor connected to
the Vcc pin. The recommended capacitance range for the
Vcc regulator is 0.1uF to 100uF. When the voltage on the
Vcc pin reaches the regulation point of 9V and the internal
voltage reference (REF) reaches its regulation point of 5V,
the controller outputs are enabled. The Buck stage outputs
will remain enabled until Vcc falls below 7V or the line
Under-Voltage Lockout detector indicates that Vin is out of
range. The push-pull outputs continue switching until the
REF pin voltage falls below approximately 3V. In typical
applications, an auxiliary transformer winding is connected
through a diode to the Vcc pin. This winding must raise the
Vcc voltage above 9.3V to shut off the internal start-up
regulator. Powering VCC from an auxiliary winding improves
efficiency while reducing the controller’s power dissipation.
The recommended capacitance range for the Vref regulator
output is 0.1uF to 10uF.
During any fault state or Under-Voltage off state, the buck
stage control outputs will default to HD low and LD high.
Push-Pull Outputs
The push pull outputs operate continuously at a nominal
50% duty cycle. A distinguishing feature of the LM5041 is the
ability to accurately configure either dead time (both-off) or
overlap time (both-on) on the complementary push-pull out-
puts. The overlap/dead time magnitude is controlled by a
resistor connected to the TIME pin on the controller. The
TIME pin holds one end of the resistor at 2.5V and the other
end of the resistor should be connected to either REF for
dead time control setting or to GND for overlap control. The
polarity of the current in the TIME is detected by the LM5041
The magnitude of the overlap/dead time can be calculated
as follows:
Overlap Time (ns) = (3.66 x RSET) + 7
Overlap Time in ns, RSET connected to GND, RSET in kΩ
Dead Time (ns) = (3.69 x RSET) + 21
The external VCC capacitor must be sized such that the
capacitor maintains a VCC voltage greater than 7V during the
initial start-up. During a fault mode when the converter aux-
iliary winding is inactive, external current draw on the VCC
line should be limited so the power dissipated in the start-up
regulator does not exceed the maximum power dissipation
of the controller.
Dead Time in ns, RSET connected to REF, RSET in kΩ
Recommended RSET programming range: 10kΩ to 100kΩ
Current-fed designs require a period of overlap to insure
there is a continuous path for the buck inductor current.
Voltage-fed designs require a period of dead time to insure
there is no time when the push-pull transformer acts as a
shorted turn to the low impedance sourcing node. The push-
pull outputs alternate continuously under all conditions pro-
vided REF the voltage is greater than 3V.
An external start-up or other bias rail can be used instead of
the internal start-up regulator by connecting the VCC and the
VIN pins together and feeding the external bias voltage into
the two pins.
Line Under-Voltage Detector
The LM5041 contains a line Under-Voltage Lockout (UVLO)
circuit. An external set-point resistor divider from VIN to
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10
Push-Pull Outputs (Continued)
20074904
must be placed close to the device and connected directly to
the pins of the controller (CS and GND). If a current sense
transformer is used, both leads of the transformer secondary
should be routed to the sense resistor, which should also be
located close to the IC. A resistor may be used for current
sensing instead of a transformer, located in the push-pull
transistor sources, but a low inductance type of resistor is
required. When designing with a sense resistor, all of the
noise sensitive low power grounds should be connected
together around the IC and a single connection should be
made to the high current power ground (sense resistor
ground point).
PWM Comparator
The PWM comparator compares the slope compensated
current ramp signal to the loop error voltage from the internal
error amplifier (COMP pin). This comparator is optimized for
speed in order to achieve minimum controllable duty cycles.
The comparator polarity is such that 0V on the COMP pin will
produce zero duty cycle in the buck stage.
Error Amplifier
An internal high gain wide-bandwidth error amplifier is pro-
vided within the LM5041. The amplifier’s non-inverting input
is tied to a 0.75V reference. The inverting input is connected
to the FB pin. In non-isolated applications the power con-
verter output is connected to the FB pin via the voltage
setting resistors. Loop compensation components are con-
nected between the COMP and FB pins. For most isolated
applications the error amplifier function is implemented on
the secondary side of the converter and the internal error
amp is not used. The internal error amplifier is configured as
an open drain output and can be disabled by connecting the
FB pin to ground. An internal 5kΩ pull-up resistor between
the 5V reference and COMP can be used as the pull-up for
an opto-coupler in isolated applications.
The second level current sense threshold is intended to
protect the power converter by initiating a low duty cycle
hick-up mode when abnormally high currents are sensed. If
the second level threshold is reached, the soft-start capaci-
tor will be discharged and a start-up sequence will com-
mence when the soft-start capacitor is determined to be fully
discharged. The second level threshold will only be reached
when a high dV/dt is present at the current sense pin. The
current sense transient must be fast enough to reach the
second level threshold before the first threshold detector
turns off the buck stage driver. Very high current sense dV/dt
can occur with a saturated power inductor or shorted load.
Excessive filtering on the CS pin such as an extremely low
value current sense resistor or an inductor that does not
saturate with excessive loading, may prevent the second
level threshold from being reached. If the second level
threshold is never exceeded during an overload condition,
the first level current sense will continue cycle by cycle
limiting and the output characteristic of the converter will be
that of a current source. However, a sustained overload
current level can cause excessive temperatures in the power
train especially the output rectifiers.
Current Limit/Current Sense
The LM5041 contains two levels of over-current protection. If
the voltage at the CS pin exceeds 0.5V the present buck
stage duty cycle is terminated (cycle by cycle current limit). If
the voltage at the CS pin overshoots the 0.5V threshold and
exceeds 0.6V, then the controller will terminate the present
cycle and fully discharge the soft-start capacitor. A small RC
filter located near the controller is recommended to filter
current sense signals at the CS pin. An internal MOSFET
discharges the external CS pin for an additional 50ns at the
beginning of each cycle to reduce the leading edge spike
that occurs when the buck stage MOSFET is turned on.
Oscillator and Sync Capability
The LM5041 oscillator is set by a single external resistor
connected between the RT pin and GND. To set a desired
oscillator frequency (F), the necessary RT resistor can be
calculated from:
The LM5041 current sense and PWM comparators are very
fast, and may respond to short duration noise pulses. Layout
considerations are critical for the current sense filter and
sense resistor. The capacitor associated with the CS filter
11
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ramp and summing a current ramp generated by the oscil-
lator internally with the current sense signal. Additional slope
compensation may be provided by increasing the source
impedance of the current sense signal.
Oscillator and Sync Capability
(Continued)
Soft-start and Shutdown
The soft-start feature allows the power converter to gradually
reach the initial steady state operating point, thereby reduc-
ing start-up stresses and surges. At power on, a 10uA cur-
rent is sourced out of the soft-start pin (SS) to charge an
external capacitor. The capacitor voltage will ramp up slowly
and will limit the maximum duty cycle of the buck stage. In
the event of a fault as indicated by VCC Under-voltage, line
Under-voltage or second level current limit, the output driv-
ers are disabled and the soft-start capacitor is discharged to
ground. When the fault condition is no longer present, a
soft-start sequence will begin again and buck stage duty
cycle will gradually increase as the soft-start capacitor is
charged. The SS pin also serves as an enable input. The
controller will enter a low power state if the SS pin is forced
below the 0.45V threshold.
The buck stage will switch at the oscillator frequency and
each push-pull output will switch at half the oscillator fre-
quency in a push-pull configuration. The LM5041 can also
be synchronized to an external clock. The external clock
must have a higher frequency than the free running fre-
quency set by the RT resistor. The clock signal should be
capacitively coupled into the RT pin with a 100pF capacitor.
A peak voltage level greater than 3V is required for detection
of the sync pulse. The sync pulse width should be set in the
15 to 150ns range by the external components. The RT
resistor is always required, whether the oscillator is free
running or externally synchronized. The voltage at the RT pin
is internally regulated to 2V. The RT resistor should be
located very close to the device and connected directly to the
pins of the IC (RT and GND).
Thermal Protection
Slope Compensation
Internal Thermal Shutdown circuitry is provided to protect the
integrated circuit in the event that the maximum junction
temperature is exceeded. When activated, typically at 165
degrees Celsius, the controller is forced into a low-power
standby state, disabling the output drivers and the bias
regulator. This feature is provided to prevent catastrophic
failures from accidental device overheating.
The PWM comparator compares the current sense signal to
the voltage at the COMP pin. The output stage of the internal
error amplifier generally drives the COMP pin. At duty cycles
greater than 50 percent, current mode control circuits are
subject to sub-harmonic oscillation. By adding an additional
fixed ramp signal (slope compensation) to the current sense
ramp, oscillations can be avoided. The LM5041 integrates
this slope compensation by buffering the internal oscillator
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12
Thermal Protection (Continued)
20074906
FIGURE 1. Simplified Cascaded Half-Bridge
13
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14
Physical Dimensions inches (millimeters)
unless otherwise noted
Molded TSSOP-16
NS Package Number MTC16
Molded TSSOP-16
NS Package Number SDA16A
15
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Notes
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