LMH7324SQ [NSC]
Quad 700 PS High Speed Comparator with RSPECL Outputs; 四路700 ps的高速比较器与RSPECL输出
| 型号： | LMH7324SQ |
| 厂家： | 
National Semiconductor |
| 描述： | Quad 700 PS High Speed Comparator with RSPECL Outputs |
| 文件： | 总20页 (文件大小：489K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2007
LMH7324
Quad 700 PS High Speed Comparator with RSPECL
Outputs
General Description
The LMH7324 is a quad comparator with 700 ps propagation
delay and low dispersion of less then 20 ps for a supply volt-
age of 5V. The input voltage range extends from VCC−2V to
VEE−200 mV The devices can be operated from a wide supply
voltage range of 5V to 12V.
Features
(VCCI = VCCO = +5V, VEE = 0V.)
Propagation delay
Overdrive dispersion
Fast rise and fall times
Supply range
700 ps
20 ps
150 ps
■
■
■
5V to 12V
■
The outputs of the LMH7324 are RSPECL compatible. The
LMH7324 is available in a 32-Pin LLP package.
Input common mode range extends 200 mV below neg-
■
ative rail
RSPECL outputs
■
Applications
Digital receivers
■
■
■
■
■
■
High speed signal restoration
Zero-crossing detectors
High speed sampling
Window comparators
High speed signal triggering
Typical Application
30017401
© 2007 National Semiconductor Corporation
300174
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Soldering Information
Absolute Maximum Ratings (Note 1)
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
Storage Temperature Range
Junction Temperature (Note 3)
235°C
260°C
−65°C to +150°C
+150°C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Tolerance (Note 2)
Human Body Model
Machine Model
Output Short Circuit Duration
Supply Voltages (V+ –V−)
Voltage at Input/Output Pins
2.5 kV
250V
(Notes 3, 4)
13.2V
Operating Ratings (Note 1)
Supply Voltage (V+ –V−)
Temperature Range
Package Thermal Resistance
32-Pin LLP
5V to 12V
−40°C to +125°C
±13V
36°C/W
12V DC Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TJ = 25°C. VCCI = VCCO = 12V, VEE = 0V, RL = 50Ω to VCCO-2V,
VCM = 300 mV. (Note 7)
Symbol Parameter
Conditions
Min
Typ
Max
Units
(Note 6)
(Note 5)
(Note 6)
Input Characteristics
IB
Input Bias Current (Note 11)
VIN Differential = 0V
VIN Differential = 0V
VIN Differential = 0V
VCM = 0V
−5
−2.5
40
µA
nA
IOS
Input Offset Current
−250
250
TC IOS
VOS
Input Offset Current TC (Note 10)
Input Offset Voltage
0.15
nA/°C
mV
−9.5
+9.5
TC VOS
VRI
Input Offset Voltage TC (Note 10)
Input Voltage Range
VCM = 0V
7
μV/°C
V
CMRR > 50 dB
VEE
−12
VCCI−2
+12
VRID
Input Differential Voltage Range
V
VEE ≤ INP or INM ≤ VCCI
0V ≤ VCM ≤ VCC−2V
CMRR
PSRR
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
83
75
dB
dB
VCM = 0V, 5V ≤ VCC ≤ 12V
AV
Active Gain
Hysteresis
54
dB
Hyst
Fixed Internal Value
20.8
mV
Output Characteristics
VOH
VOL
VOD
Output Voltage High
VIN Differential = 25 mV
VIN Differential = 25 mV
VIN Differential = 25 mV
10.78
10.43
300
10.85
10.50
345
10.93
10.58
400
V
V
Output Voltage Low
Output Voltage Differential
mV
Power Supplies
IVCCI
VCCI Supply Current
VIN Differential = 25 mV Load Current
Excluded
5.6
8
mA
IVCCO
VCCO Supply Current
VIN Differential = 25 mV Load Current
Excluded
11.6
17
12V AC Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TJ = 25°C. VCCI = VCCO = 12V, VEE = 0V, RL = 50Ω to VCCO-2V,
VCM = 300 mV. (Note 7)
Symbol
TR
Parameter
Maximum Toggle Rate
Minimum Pulse Width
Jitter
Conditions
Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)
Units
Gb/s
ps
Overdrive = ±50 mV, CL = 2 pF
@ 50% Output Swing
3.84
280
<1
Overdrive = ±50 mV, CL = 2 pF
@ 50% Output Swing
Overdrive = ±50 mV, CL = 2 pF
@ freq = 140 MHz
ps
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2
Symbol
tPDH
Parameter
Propagation Delay
Conditions
Overdrive 20 mV
Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)
Units
737
720
706
731
31
(see Figure 3 application note)
Overdrive 50 mV
Overdrive 100 mV
Overdrive 1V
ps
Input SR = Constant
VIN Startvalue = VREF −100 mV
tOD-disp
Input Overdrive Dispersion
tPDH @ Overdrive 20 mV ↔ 100 mV
tPDH @ Overdrive 100 mV ↔ 1V
0.1 V/ns to 1 V/ns
Overdrive 100 mV
ps
ps
25
40
tSR-disp
tCM-disp
Input Slew Rate Dispersion
Input Common Mode Dispersion
SR = 1 V/ns, Overdrive 100 mV,
0V ≤ VCM ≤ VCCI – 2V
28
ps
Q to Q Time Skew
| tPDH - tPDL | (Note 8)
Overdrive = 50 mV, CL = 2 pF
55
40
ps
ps
ps
ps
ΔtPDLH
Q to Q Time Skew
| tPDL - tPDH | (Note 8)
Overdrive = 50 mV, CL = 2 pF
Overdrive = 50 mV, CL = 2 pF
Overdrive = 50 mV, CL = 2 pF
ΔtPDHL
tr
tf
Output Rise Time (20% - 80%)
(Note 9)
140
140
Output Fall Time (20% - 80%
(Note 9)
5V DC Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TJ = 25°C. VCCI = VCCO = 5V, VEE = 0V, RL = 50Ω to VCCO-2V,
VCM = 300 mV. (Note 7)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 6) (Note 5) (Note 6)
IB
Input Bias Current (Note 11)
Input Offset Current
VIN Differential = 0V
−5
−2.2
30
µA
nA
IOS
VIN Differential = 0V
VIN Differential = 0V
VCM = 0V
−250
+250
+9.5
TC IOS
VOS
Input Offset Current TC (Note 10)
Input Offset Voltage
0.1
nA/°C
mV
−9.5
TC VOS
VRI
Input Offset Voltage TC (Note 10)
Input Voltage Range
VCM = 0V
7
μV/°C
V
CMRR > 50 dB
VEE
−5
VCCI−2
+5
VRID
Input Differential Voltage Range
V
VEE ≤ INP or INM ≤ VCCI
0V ≤ VCM ≤ VCC−2V
CMRR
PSRR
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
80
75
dB
dB
VCM = 0V, 5V ≤ VCC ≤ 12V
AV
Active Gain
Hysteresis
54
dB
Hyst
Fixed Internal Value
22.5
mV
Output Characteristics
VOH
VOL
VOD
Output Voltage High
VIN Differential = 25 mV
VIN Differential = 25 mV
VIN Differential = 25 mV
3.8
3.45
300
3.87
3.52
345
3.95
3.60
400
V
V
Output Voltage Low
Output Voltage Differential
mV
Power Supplies
IVCCI
VCCI Supply Current
VIN Differential = 25 mV, Load Current
Excluded
5.4
11
7.5
15
mA
mA
IVCCO
VCCO Supply Current
VIN Differential = 25 mV, Load Current
Excluded
3
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5V AC Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TJ = 25°C. VCCI = VCCO = 5V, VEE = 0V, RL = 50Ω to VCCO-2V,
VCM = 300 mV. (Note 7)
Symbol
TR
Parameter
Maximum Toggle Rate
Minimum Pulse Width
Jitter
Conditions
Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)
Units
Gb/s
ps
Overdrive = ±50 mV, CL = 2 pF
@ 50% Output Swing
Overdrive = ±50 mV, CL = 2 pF
@ 50% Output Swing
Overdrive = ±50 mV, CL = 2 pF
@ freq = 140 MHz
3.72
290
<1
ps
tPDH
Propagation Delay
(see Figure 3 application note)
Overdrive 20 mV
740
731
722
740
18
Overdrive 50 mV
ps
Input SR = Constant
VIN Startvalue = VREF −100 mV
Overdrive 100 mV
Overdrive 1V
tOD-disp
Input Overdrive Dispersion
TPDH @ Overdrive 20 mV ↔ 100 mV
TPDH @ Overdrive 100 mV ↔ 1V
0.1 V/ns to 1 V/ns,
Overdrive = 100 mV
ps
ps
19
40
tSR-disp
tCM-disp
Input Slew Rate Dispersion
Input Common Mode Dispersion
SR = 1 V/ns, Overdrive 100 mV,
0V ≤ VCM ≤ VCCI – 2V
24
ps
Q to Q Time Skew
| tPDH - tPDL | (Note 8)
Overdrive = 50 mV, CL = 2 pF
60
40
ps
ps
ps
ps
ΔtPDLH-disp
Q to Q Time Skew
| tPDL - tPDH | (Note 8)
Overdrive = 50 mV, CL = 2 pF
Overdrive = 50 mV, CL = 2 pF
Overdrive = 50 mV, CL = 2 pF
ΔtPDHL
tr
tf
Output Rise Time (20% - 80%)
(Note 9)
145
145
Output Fall Time (20% - 80%)
(Note 9)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Conditions indicate specifications for which the
device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical
Characteristics.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)
Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC)
Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Note 4: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150°C.
Note 5: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will
also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 6: All limits are guaranteed by testing or statistical analysis.
Note 7: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating
of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self heating where
TJ > TA.
Note 8: Propagation Delay Skew, ΔtPD, is defined as the average of ΔtPDLH and ΔtPDHL
Note 9: The rise or fall time is the average of the Q and Q rise or fall time.
.
Note 10: Average Temperature Coefficient is determined by dividing the change in a parameter at temperature extremes by the total temperature change.
Note 11: Positive current corresponds to current flowing into the device.
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4
Connection Diagram
32-Pin LLP
30017402
30017403
Top View
Ordering Information
Package
Part Number
LMH7324SQ
LMH7324SQX
Package Marking
L7324SQ
Transport Media
NSC Drawing
1k Units Tape and Reel
4.5k Units Tape and Reel
32-Pin LLP
SQA32A
5
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Typical Performance Characteristics At TJ = 25°C, V+ = +5V, V− = 0V, unless otherwise specified.
Propagation Delay vs. Supply Voltage
Propagation Delay vs. Temperature
30017425
30017424
Propagation Delay vs. Overdrive Voltage
Propagation Delay vs. Supply Voltage for Different Overdrive
30017426
30017427
Propagation Delay vs. Common Mode Voltage
Propagation Delay vs. Slew Rate
30017429
30017428
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Pulse Response and Maximum Toggle Rate
Bias Current vs. Temperature
30017430
30017431
Input Current vs. Differential Input Voltage
Output Voltage vs. Input Voltage
30017432
30017433
Hysteresis Voltage vs. Temperature
30017434
7
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The output stage of the LMH7324 is built using two emitter
followers, which are referenced to the VCCO. (See Figure 2.)
Each of the output transistors is active when a current is flow-
ing through any external output resistor connected to a lower
supply rail. Activating the outputs is done by connecting the
emitters to a termination voltage which lies 2V below the
VCCO. In this case a termination resistor of 50Ω can be used
and a transmission line of 50Ω can be driven. Another method
is to connect the emitters through a resistor to the most neg-
ative supply by calculating the right value for the emitter
current in accordance with the datasheet tables. Both meth-
ods are useful, but they each have good and bad aspects.
Application Information
INTRODUCTION
The LMH7324 is a high speed comparator with RS(P)ECL
(Reduced Swing Positive Emitter Coupled Logic) outputs,
and is compatible with LVDS (Low Voltage Differential Sig-
naling) if VCCO is set to 2.5V. The use of complementary
outputs gives a high level of suppression for common mode
noise. The very fast rise and fall times of the LMH7324 enable
data transmission rates up to several Gigabits per second
(Gbps). The LMH7324 inputs have a common mode voltage
range that extends 200 mV below the negative supply voltage
thus allowing ground sensing when used with a single supply.
The rise and fall times of the LMH7324 are about 150 ps, while
the propagation delay time is about 700 ps. The LMH7324
can operate over the supply voltage range of 5V to 12V, while
using single or dual supply voltages. This is a flexible way to
interface between several high speed logic families. Several
configurations are described in the section INTERFACE BE-
TWEEN LOGIC FAMILIES. The outputs are referenced to the
positive VCCO supply rail. The supply current is 17 mA at 5V
(per comparator, load current excluded.) The LMH7324 is of-
fered in a 32-Pin LLP package. This small package is ideal
where space is an important issue.
INPUT & OUTPUT TOPOLOGY
All input and output pins are protected against excessive volt-
ages by ESD diodes. These diodes are conducting from the
negative supply to the positive supply. As can be seen in
Figure 1, both inputs are connected to these diodes. Protec-
tion against excessive supply voltages is provided by two
power clamps per comparator; one between the VCCI and the
30017405
FIGURE 2. Equivalent Output Circuitry
VEE and one between the VCCO and the VEE
.
The output voltages for ‘1’ and ‘0’ have a difference of ap-
proximately 400 mV and are respectively 1.1V (for the ‘1’) and
1.5V (for the ‘0’) below the VCCO. This swing of 400 mV is
enough to drive any LVDS input but can also be used to drive
any ECL or PECL input, when the right supply voltage is cho-
sen, especially the right level for the VCCO
.
30017404
FIGURE 1. Equivalent Input Circuitry
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8
DEFINITIONS
This table provides a short description of the parameters used in the datasheet and in the timing diagram of Figure 3.
Symbol
Text
Input Bias Current
Description
IB
Current flowing in or out of the input pins, when both are biased at the
VCM voltage as specified in the tables.
IOS
Input Offset Current
Difference between the input bias current of the inverting and non-inverting
inputs.
TC IOS
VOS
Average Input Offset Current Drift Temperature coefficient of IOS.
Input Offset Voltage
Voltage difference needed between IN+ and IN− to make the outputs
change state, averaged for H to L and L to H transitions.
TC VOS
VRI
Average Input Offset Voltage Drift Temperature coefficient of VOS.
Input Voltage Range
Voltage which can be applied to the input pin maintaining normal operation.
VRID
Input Differential Voltage Range
Differential voltage between positive and negative input at which the input
clamp is not working. The difference can be as high as the supply voltage
but excessive input currents are flowing through the clamp diodes and
protection resistors.
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Ratio of input offset voltage change and input common mode voltage
change.
Ratio of input offset voltage change and supply voltage change from VS-
MIN to VS-MAX
.
AV
Active Gain
Overall gain of the circuit.
Hyst
VOH
VOL
Hysteresis
Difference between the switching point ‘0’ to ‘1’ and vice versa.
High state single ended output voltage (Q or Q) (see Figure 16)
Low state single ended output voltage (Q or Q) (see Figure 16)
(VODH + VODL)/2
Output Voltage High
Output Voltage Low
Average of VODH and VODL
Supply Current Input Stage
Supply Current Output Stage
VOD
IVCCI
IVCCO
Supply current into the input stage.
Supply current into the output stage while current through the load resistors
is excluded.
IVEE
TR
Supply Current VEE Pin
Maximum Toggle Rate
Current flowing out of the negative supply pin.
Maximum frequency at which the outputs can toggle at 50% of the nominal
VOH and VOL
.
PW
Pulse Width
Time from 50% of the rising edge of a signal to 50% of the falling edge.
tPDH resp tPDL
Propagation Delay
Delay time between the moment the input signal crosses the switching level
L to H and the moment the output signal crosses 50% of the rising edge of
Q output (tPDH), or delay time between the moment the input signal crosses
the switching level H to L and the moment the output signal crosses 50% of
the falling edge of Q output (tPDL).
tPDL resp tPDH
Delay time between the moment the input signal crosses the switching level
L to H and the moment the output signal crosses 50% of the falling edge of
Q output (tPDL), or delay time between the moment the input signal crosses
the switching level H to L and the moment the output signal crosses 50% of
the rising edge of Q output (tPDH).
tPDLH
Average of tPDH and tPDL
Average of tPDL and tPDH
Average of tPDLH and tPDHL
tPDHL
tPD
tPDHd resp tPDLd
Delay time between the moment the input signal crosses the switching level
L to H and the zero crossing of the rising edge of the differential output signal
(tPDHd), or delay time between the moment the input signal crosses the
switching level H to L and the zero crossing of the falling edge of the
differential output signal (tPDLd).
tOD-disp
tSR-disp
Input Overdrive Dispersion
Input Slew Rate Dispersion
Change in tPD for different overdrive voltages at the input pins.
Change in tPD for different slew rates at the input pins.
9
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Symbol
tCM-disp
Text
Description
Input Common Mode Dispersion Change in tPD for different common mode voltages at the input pins.
Q to Q Time Skew
Time skew between 50% levels of the rising edge of Q output and the falling
edge of Q output (ΔtPDLH), or time skew between 50% levels of falling edge
of Q output and rising edge of Q output (ΔtPDHL).
ΔtPDLH resp
ΔtPDHL
Average Q to Q Time Skew
Average Diff. Time Skew
Average of tPDLH and tPDHL for L to H and H to L transients.
Average of tPDHd and tPDLd for L to H and H to L transients.
ΔtPD
ΔtPDd
tr/trd
Output Rise Time (20% - 80%)
Time needed for the (single ended or differential) output voltage to change
from 20% of its nominal value to 80%.
tf/tfd
Output Fall Time (20% - 80%)
Time needed for the (single ended or differential) output voltage to change
from 80% of its nominal value to 20%.
30017406
FIGURE 3. Timing Definitions
PIN DESCRIPTIONS
Pin Name
Description
Part
Comment
1.
VCCO
Positive Supply Output Stage
A
This supply pin is independent of the supply for the input stage. This
allows output levels of different logic families.
2.
3.
4.
Q
Inverted Output
Output
A
A
A
Output levels are determined by the choice of VCCOA
Output levels are determined by the choice of VCCOA
.
.
Q
VEE
Negative Supply
All four VEE pins are circular connected together via two antiparallel
diodes. (see Figure 4)
5.
VEE
Negative Supply
B
All four VEE pins are circular connected together via two antiparallel
diodes. (see Figure 4)
6.
7.
8.
Q
Output
B
B
B
Output levels are determined by the choice of VCCOB
Output levels are determined by the choice of VCCOB
.
.
Q
Inverted Output
VCCO
Positive Supply Output Stage
This supply pin is independent of the supply for the input stage. This
allows output levels of different logic families.
9.
VCCI
Positive Supply for Input Stage
Negative Input
B
B
This supply pin is independent of the supply for the output stage.
VCCIand VCCO share the same ground pin VEE
Input for analog voltages between 200 mV below VEE and 2V below
VCCI
.
10. IN−
.
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10
Pin Name
Description
Positive Input
Part
Comment
11. IN+
B
Input for analog voltages between 200 mV below VEE and 2V below
VCCI
.
12. VEE
13. VEE
14. IN+
15. IN−
16. VCCI
17. VCCO
Negative Supply
B
C
C
C
C
C
All four VEE pins are circular connected together via two antiparallel
diodes. (see Figure 4)
Negative Supply
All four VEE pins are circular connected together via two antiparallel
diodes. (see Figure 4)
Positive Input
Input for analog voltages between 200 mV below VEE and 2V below
VCCI
Input for analog voltages between 200 mV below VEE and 2V below
VCCI
This supply pin is independent of the supply for the output stage.
VCCI and VCCO share the same ground pin VEE
.
Negative Input
.
Positive Supply for Input Stage
Positive Supply Output Stage
.
This supply pin is independent of the supply for the input stage. This
allows output levels of different logic families.
18.
19.
Q
Q
Inverted Output
Output
C
C
C
Output levels are determined by the choice of VCCOC
Output levels are determined by the choice of VCCOC
.
.
20. VEE
Negative Supply
All four VEE pins are circular connected together via two antiparallel
diodes. (see Figure 4)
21. VEE
Negative Supply
D
All four VEE pins are circular connected together via two antiparallel
diodes. (see Figure 4)
22.
23.
Q
Q
Output
D
D
D
Output levels are determined by the choice of VCCOD
Output levels are determined by the choice of VCCOD
.
.
Inverted Output
24. VCCO
25. VCCI
26. IN−
Positive Supply Output Stage
This supply pin is independent of the supply for the input stage. This
allows output levels of different logic families.
Positive Supply for Input Stage
Negative Input
D
D
D
D
A
This supply pin is independent of the supply for the output stage.
VCCI and VCCO share the same ground pin VEE
Input for analog voltages between 200 mV below VEE and 2V below
VCCI
Input for analog voltages between 200 mV below VEE and 2V below
VCCI
.
.
27. IN+
28. VEE
29. VEE
30. IN+
31. IN−
32. VCCI
33. DAP
Positive Input
.
Negative Supply
All four VEE pins are circular connected together via two antiparallel
diodes. (see Figure 4)
Negative Supply
All four VEE pins are circular connected together via two antiparallel
diodes. (see Figure 4)
Positive Input
A
Input for analog voltages between 200 mV below VEE and 2V below
VCCI
Input for analog voltages between 200 mV below VEE and 2V below
VCCI
This supply pin is independent of the supply for the output stage.
VCCI and VCCO share the same ground pin VEE
The purpose of this pad is to transfer heat outside the part.
.
Negative Input
A
.
Positive Supply for Input Stage
A
.
Central Pad at the Bottom of the
Package
All
11
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TIPS & TRICKS USING THE LMH7324
This section discusses several aspects concerning special
applications using the LMH7324.Topics include the connec-
tion of the DAP in conjunction to the VEE pins and the use of
this part as an interface between several logic families. Other
sections discuss several widely used definitions and terms for
comparators. The final sections explain some aspects of
transmission lines and the choice for the most suitable com-
ponents handling very fast pulses.
THE DAP AND THE VEE PINS
To protect the device against damage during handling and
production, two antiparallel connected diodes are placed be-
tween the VEE pins. Under normal operating conditions (all
VEE pins have the same voltage level) these diodes are not
functioning, as can be seen in Figure 4.
30017408
FIGURE 5. ECL TO RSPECL
Interface from PECL to (RS) ECL
The DAP (Die Attach Paddle) functions as a heat sink which
means that heat can be transferred, using vias below this pad,
to any appropriate copper plane.
This setup needs the VCCI pin at +5V because the input logic
levels are positive. To obtain the ECL levels at the output it is
necessary to connect the VCCO to the ground while the VEE
has to be connected to the −5.2V. The reason for this is that
the minimum requirement for the supply is 5V. The high level
of the output of the LMH7324 is normally 1.1V below the
VCCO supply voltage, and the low level is 1.5V below this sup-
ply. The output levels are now −1100 mV for the logic ‘1’ and
−1500 mV for the logic ‘0’ (see Figure 6.)
30017407
FIGURE 4. DAP and VEE Configuration
INTERFACE BETWEEN LOGIC FAMILIES
The LMH7324 can be used to interface between different log-
ic families. The feature that facilitates this is the fact that the
input stage and the output stage use different positive power
supply pins which can be used at different voltages. The only
restriction is that the minimum supply voltage between VEE
and one of the positive supplies must be 5V. The negative
supply pins are connected together for all four parts. Using
the power pins at different supply voltages makes it possible
to create several translations for logic families. It is possible
to translate from logic at negative voltage levels such as ECL
to logic at positive levels such as RSPECL and LVDS and vice
versa.
30017409
FIGURE 6. PECL TO RSECL
Interface from Analog to LVDS
As seen in Figure 7, the LMH7324 can be configured to create
LVDS levels. This is done by connecting the VCCO to 2.5V. As
discussed before, the output levels are now at VCCO −1.1V for
the logic ‘1’ and at VCCO -1.5V for the logic ‘0’. These levels
of 1000 mV and 1400 mV comply with the LVDS levels. As
can be seen in this setup, an AC coupled signal via a trans-
mission line is used. This signal is terminated with 50Ω to the
ground. The input stage has its supply from +5V to −5V, which
means that the input common mode level is midway between
the input stage supply voltages.
Interface from ECL to RSPECL
The supply pin VCCI can be connected to ground because the
input levels are negative and VEE is at −5.2V. With this setup
the minimum requirements for the supply voltage of 5V are
obtained. The VCCO pin must operate at +5V to create the
RSPECL levels (See Figure 5).
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12
DELAY AND DISPERSION
Comparators are widely used to connect the analog world to
the digital one. The accuracy of a comparator is dictated by
its DC properties, such as offset voltage and hysteresis, and
by its timing aspects, such as rise and fall times and delay.
For low frequency applications most comparators are much
faster than the analog input signals they handle. The timing
aspects are less important here than the accuracy of the input
switching levels. The higher the frequencies, the more impor-
tant the timing properties of the comparator become, because
the response of the comparator can make a noticeable
change in critical parameters such as time frame or duty cy-
cle. A designer has to know these effects and has to deal with
them. In order to predict what the output signal will do, several
parameters are defined which describe the behavior of the
comparator. For a good understanding of the timing parame-
ters discussed in the following section, a brief explanation is
given and several timing diagrams are shown for clarification.
30017410
FIGURE 7. ANALOG TO LVDS
Standard Comparator Setup
Figure 8 shows a standard comparator setup which creates
RSPECL levels because the VCCO supply voltage is +5V. In
this setup the VEE pin is connected to the ground level. The
VCCI pin is connected to the VCCO pin because there is no
need to use different positive supply voltages. The input sig-
nal is AC coupled to the positive input. To maintain reliable
results, even for signals with larger amplitudes, the input pins
IN+ and IN− are biased at 1.4V through a resistive divider
using a resistor of 1 kΩ to ground and a resistor of 2.5 kΩ to
the VCC and by adding two decoupling capacitors. Both inputs
are connected to the bias level by the use of a 10 kΩ resistor.
With this input configuration the input stage can work in a lin-
ear area with signals of approximately 3 VPP (See input level
restrictions in the data tables.)
PROPAGATION DELAY
The propagation delay parameter is described in the definition
section. Two delay parameters can be distinguished, tPDH and
tPDL. (Figure 9) Both parameters do not necessarily have the
same value. It is possible that differences will occur due to a
different response of the internal circuitry. As a derivative of
this effect another parameter is defined: ΔtPD. This parameter
is defined as the absolute value of the difference between
tPDH and tPDL
.
30017412
FIGURE 9. Propagation Delay
30017411
FIGURE 8. Standard Setup
13
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If ΔtPD is not zero, duty cycle distortion will occur. For example
when applying a symmetrical waveform (e.g. a sinewave) at
the input, it is expected that the comparator will produce a
symmetrical square wave at the output with a duty cycle of
50%. When tPDH and tPDL are different, the duty cycle of the
output signal will not remain at 50%, but will be increased or
decreased. In addition to the propagation delay parameters
for single ended outputs discussed before, there are other
parameters in the case of complementary outputs. These pa-
rameters describe the delay from input to each of the outputs
and the difference between both delay times. (See Figure
10.) When the differential input signal crosses the reference
level from L to H, both outputs will switch to their new state
with some delay. This is defined as tPDH for the Q output and
tPDL for the Q output, while the difference between both sig-
nals is defined as ΔtPDLH. Similar definitions for the falling
slope of the input signal can be seen in Figure 3.
30017414
FIGURE 11. Overdrive Dispersion
The overdrive dispersion is caused by the switching currents
in the input stage which are dependent on the level of the
differential input signal.
Slew Rate Dispersion
The slew rate is another parameter that affects propagation
delay. The higher the input slew rate, the faster the input stage
switches. (See Figure 12.)
30017413
FIGURE 10. tPD with Complementary Outputs
Both output circuits should be symmetrical. At the moment
one output is switching ‘on’ the other is switching ‘off’ with
ideally no skew between both outputs. The design of the
LMH7324 is optimized so that this timing difference is mini-
mized. The propagation delay, tPD, is defined as the average
delay of both outputs at both slopes: (tPDLH + tPDHL)/2. Both
overdrive and starting point should be equally divided around
the VREF (absolute values).
DISPERSION
There are several circumstances that will produce a variation
of the propagation delay time. This effect is called dispersion.
Amplitude Overdrive Dispersion
30017415
One of the parameters that causes dispersion is the amplitude
variation of the input signal. Figure 11 shows the dispersion
due to a variation of the input overdrive voltage. The overdrive
is defined as the ‘go to’ differential voltage applied to the in-
puts. Figure 11 shows the impact it has on the propagation
delay time if the overdrive is varied from 10 mV to 100 mV.
This parameter is measured with a constant slew rate of the
input signal.
FIGURE 12. Slew Rate Dispersion
A combination of overdrive and slew rate dispersion occurs
when applying signals with different amplitudes at constant
frequency. A small amplitude will produce a small voltage
change per time unit (dV/dt) but also a small maximum switch-
ing current (overdrive) in the input transistors. High ampli-
tudes produce a high dV/dt and a bigger overdrive.
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14
Common Mode Dispersion
Dispersion will also occur when changing the common mode
level of the input signal. (See Figure 13.) When VREF is swept
through the CMVR (Common Mode Voltage Range), it results
in a variation of the propagation delay time. This variation is
called Common Mode Dispersion.
30017417
FIGURE 14. Oscillations on Output Signal
In most circumstances this is not an option because the slew
rate of the input signal will vary.
Using Hysteresis
A good way to avoid oscillations and noise during slow slopes
is the use of hysteresis. With hysteresis the switching level is
forced to a new level at the moment the input signal crosses
this level. This can be seen in Figure 15.
30017416
FIGURE 13. Common Mode Dispersion
All of the dispersion effects described previously influence the
propagation delay. In practice the dispersion is often caused
by a combination of more than one varied parameter.
HYSTERESIS & OSCILLATIONS
In contrast to an op amp, the output of a comparator has only
two defined states ‘0’ or ‘1.’ Due to finite comparator gain
however, there will be a small band of input differential voltage
where the output is in an undefined state. An input signal with
fast slopes will pass this band very quickly without problems.
During slow slopes however, passing the band of uncertainty
can take a relatively long time. This enables the comparators
output to switch back and forth several times between ‘0’ and
‘1’ on a single slope. The comparator will switch on its input
noise, ground bounce (possible oscillations), ringing etc.
Noise in the input signal will also contribute to these undesired
switching actions.
30017418
FIGURE 15. Hysteresis
The next sections explain these phenomena in situations
where no hysteresis is applied, and discuss the possible im-
provement hysteresis can give.
In this picture there are two dotted lines A and B, both indi-
cating the resulting level at which the comparator output will
switch over. Assume that for this situation the input signal is
connected to the negative input and the switching level
(VREF) to the positive input. The LMH7324 has a built-in hys-
teresis voltage that is fixed at approximately 20 mVPP. The
input level of Figure 15 starts much lower than the reference
level and this means that the state of the input stage is well
defined with the inverting input much lower than the non-in-
verting input. As a result the output will be in the high state.
Internally the switching level is at A, with the input signal slop-
ing up, this situation remains until VIN crosses level A at t = 1.
Now the output toggles, and the internal switching level is
lowered to level B. So before the output has the possibility to
toggle again, the difference between the inputs is made suf-
ficient to have a stable situation again. When the input signal
Using No Hysteresis
Figure 14 shows what happens when the input signal rises
from just under the threshold VREF to a level just above it.
From the moment the input reaches the lowest dotted line
around VREF at t = 0, the output toggles on noise etc. Toggling
ends when the input signal leaves the undefined area at t =
1. In this example the output was fast enough to toggle three
times. Due to this behavior digital circuitry connected to the
output will count a wrong number of pulses. One way to pre-
vent this is to choose a very slow comparator with an output
that is not able to switch more than once between ‘0’ and ‘1’
during the time the input state is undefined.
15
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comes down from high to low, the situation is stable until level
B is reached at t = 0. At this moment the output will toggle
back, and the circuit is back in the starting situation with the
inverting input at a much lower level than the non-inverting
input. In the situation without hysteresis, the output will toggle
exactly at VREF. With hysteresis this happens at the internally
introduced levels A and B, as can be seen in Figure 15. If by
design the levels A and B which are due to a change in the
built-in hysteresis voltage are changed then the timing of t =
0 and t = 1 will also vary. When designing a circuit be aware
of this effect. Introducing hysteresis will cause some time shift
between output and input (e.g. duty cycle variations), but will
eliminate undesired switching of the output.
Another parasitic capacity that can affect the output signal is
the capacity directly between both outputs, called CPAR. (See
Figure 17.) The LMH7324 has two complementary outputs so
there is the possibility that the output signal will be transported
by a symmetrical transmission line. In this case both output
tracks form a coupled line with their own parasitics and both
receiver inputs are connected to the transmission line. Actu-
ally the line termination looks like 100Ω and the input capac-
ities, which are in series, are parallel to the 100Ω termination.
The best way to measure the input signal is to use a differ-
ential probe directly across both inputs. Such a probe is very
suitable for measuring these fast signals because it has good
high frequency characteristics and low parasitic capacitance.
The Output
OUTPUT SWING PROPERTIES
The LMH7324 has differential outputs, which means that both
outputs have the same swing but in opposite directions. (see
Figure 16.) Both outputs swing around the common mode
output voltage (VO). This voltage can be measured at the
midpoint between two equal resistors connected to each out-
put. The absolute value of the difference between both volt-
ages is called VOD. The outputs cannot be held at the VO level
because of their digital nature. They only cross this level dur-
ing a transition. Due to the symmetrical structure of the circuit,
both output voltages cross at VO regardless of whether the
output changes from ‘0’ to ‘1’ or vise versa.
30017420
FIGURE 17. Parasitic Capacities
TRANSMISSION LINES & TERMINATION
TECHNOLOGIES
The LMH7324 uses complementary RSPECL outputs and
emitter followers, which means high output current capability
and low sensitivity to parasitic capacitance. The use of Re-
duced Swing Positive Emitter Coupled Logic gives advan-
tages concerning speed and supply. Data rates are growing,
which requires increasing speed. Data is not only connected
to other IC’s on a single PCB board but, in many cases, there
are interconnections from board to board or from equipment
to equipment. Distances can be short or long but it is always
necessary to have a reliable connection, which consumes low
power and is able to handle high data rates. The complemen-
tary outputs of the LMH7324 make it possible to use sym-
metrical transmission lines. The advantage over single ended
signal transmission is that the LMH7324 has higher immunity
to common mode noise. Common mode signals are signals
that are equally apparent on both lines and because the re-
ceiver only looks at the difference between both lines, this
noise is canceled.
30017419
FIGURE 16. Output Swing
LOADING THE OUTPUT
Both outputs are activated when current is flowing through a
resistor that is externally connected to VT. The termination
voltage should be set 2V below the VCCO. This makes it pos-
sible to terminate each of the outputs directly with 50Ω, and
if needed to connect through a transmission line with the
same impedance (see Figure 17.) Due to the low ohmic na-
ture of the output emitter followers and the 50Ω load resistor,
a capacitive load of several pF does not dramatically affect
the speed and shape of the signal. When transmitting the sig-
nal from one output to any input the termination resistor
should match the transmission line. The capacitive load (CP)
will distort the received signal. When measuring this input with
a probe, a certain amount of capacitance from the probe is
parallel to the termination resistor. The total capacitance can
be as large as 10 pF. In this case there is a pole at:
Maximum Bit Rates
The maximum toggle rate is defined at an amplitude of 50%
of the nominal output signal. This toggle rate is a number for
the maximum transfer rate of the part and can be given in Hz
or in Bps. When transmitting signals in a NRZ (Non Return to
Zero) format the bitrate is double this frequency number, be-
cause during one period two bits can be transmitted. (See
Figure 18.) The rise and fall times are very important specifi-
cations in high speed circuits. In fact these times determine
the maximum toggle rate of the part. Rise and fall times are
f = 1/(2*π*C*R)
f = 1e9/ π
f = 318 MHz
For this frequency the current IP has the same value as the
current through the termination resistor. This means that the
voltage drops at the input and the rise and fall times are dra-
matically different from the specified numbers for this part.
www.national.com
16
normally specified at 20% and 80% of the signal amplitude
(60% difference). Assuming that the edges at 50% amplitude
are coming up and down like a sawtooth it is possible to cal-
culate the maximum toggle rate but this number is too opti-
mistic. In practice the edges are not linear while the pulse
shape is more or less a sinewave.
30017421
FIGURE 18. Bit Rates
Need for Terminated Transmission Lines
During the 1980’s and 90’s, National fabricated the 100K ECL
logic family. The rise and fall time specifications were 0.75 ns,
which were considered very fast. If sufficient care has not
been given in designing the transmission lines and choosing
the correct terminations, then errors in digital circuits are in-
troduced. To be helpful to designers that use ECL with “old”
PCB-techniques, the 10K ECL family was introduced with rise
and fall time specifications of 2 ns. This is much slower and
easier to use. The RSPECL output signals of the LMH7324
have transition times that extend the fastest ECL family. A
careful PCB design is needed using RF techniques for trans-
mission and termination.
30017423
FIGURE 20. PCB Lines
Differential Microstrip Line
The transmission line which is ideally suited for complemen-
tary signals is the differential microstrip line. This is a double
microstrip line with a narrow space in between. This means
both lines have strong coupling and this determines the char-
acteristic impedance. The fact that they are routed above a
copper plane does not affect differential impedance, only CM-
capacitance is added. Each of the structures above has its
own geometric parameters, so for each structure there is a
different formula to calculate the right impedance. For calcu-
lations on these transmission lines visit the National website
or order RAPIDESIGNER. At the end of the transmission line
there must be a termination having the same impedance as
that of the transmission line itself. It does not matter what
impedance the line has, if the load has the same value no
reflections will occur. When designing a PCB board with
transmission lines on it, space becomes an important item
especially on high density boards. With a single microstrip
line, line width is fixed for a given impedance and for a specific
board material. Other line widths will result in different
impedances.
Transmission lines can be formed in several ways. The most
commonly used types are the coaxial cable and the twisted
pair telephony cable (Figure 19.)
30017422
FIGURE 19. Cable Types
Advantages of Differential Microstrip Lines
These cables have a characteristic impedance determined by
their geometric parameters. Widely used impedances for the
coaxial cable are 50Ω and 75Ω. Twisted pair cables have
impedances of about 120Ω to 150Ω.
Other types of transmission lines are the strip line and the
microstrip line. These last types are used on PCB boards.
They have the characteristic impedance dictated by the phys-
ical dimensions of a track placed over a metal ground plane.
(See Figure 20.)
Impedances of transmission lines are always dictated by their
geometric parameters. This is also true for differential mi-
crostrip lines. Using this type of transmission line, the distance
of the track determines the resulting impedance. So, if the
PCB manufacturer can produce reliable boards with low track
spacing the track width for a given impedance is also small.
The wider the spacing, the wider tracks are needed for a spe-
cific impedance. For example two tracks of 0.2 mm width and
0.1 mm spacing have the same impedance as two tracks of
0.8 mm width and 0.4 mm spacing. With high-end PCB pro-
cesses, it is possible to design very narrow differential mi-
crostrip transmission lines. It is desirable to use these to
create optimal connections to the receiving part or the termi-
17
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nating resistor, in accordance to their physical dimensions.
Seen from the comparator, the termination resistor must be
connected at the far end of the line. Open connections after
the termination resistor (e.g. to the input of a receiver) must
be as short as possible. The allowed length of such connec-
tions varies with the received transients. The faster the tran-
sients, the shorter the open lines must be to prevent signal
degradation.
plane, providing a low impedance path for all decoupling ca-
pacitors and other ground connections. Care should be given
especially that on-board transmission lines have the same
impedance as the cables to which they are connected. Most
single ended applications have 50Ω impedance (75Ω for
video and cable TV applications). Such low impedance, single
ended microstrip transmission lines usually require much
wider traces (2 to 3 mm) on a standard double sided PCB
board than needed for a ‘normal’ trace. Another important is-
sue is that inputs and outputs should not ‘see’ each other. This
occurs if input and output tracks are routed in parallel over the
PCB with only a small amount of physical separation, partic-
ularly when the difference in signal level is high. Furthermore
components should be placed as flat and low as possible on
the surface of the PCB. For higher frequencies a long lead
can act as a coil, a capacitor or an antenna. A pair of leads
can even form a transformer. Careful design of the PCB min-
imizes oscillations, ringing and other unwanted behavior. For
ultra high frequency designs only surface mount components
will give acceptable results. (For more information see
OA-15).
PCB LAYOUT CONSIDERATIONS AND COMPONENT
VALUE SELECTION
High frequency designs require that both active and passive
components be selected from those that are specially de-
signed for this purpose. The LMH7324 is fabricated in a 32-
pin LLP package intended for surface mount design. For
reliable high speed design it is highly recommended to use
small surface mount passive components because these
packages have low parasitic capacitance and low inductance
simply because they have no leads to connect them to the
PCB. It is possible to amplify signals at frequencies of several
hundreds of MHz using standard through-hole resistors. Sur-
face mount devices however, are better suited for this pur-
pose. Another important issue is the PCB itself, which is no
longer a simple carrier for all the parts and a medium to in-
terconnect them. The PCB becomes a real component itself
and consequently contributes its own high frequency proper-
ties to the overall performance of the circuit. Good practice
dictates that a high frequency design have at least one ground
National suggests the following evaluation board as a guide
for high frequency layout and as an aid in device testing: #
013272 LMH7324 SQA32A eval board. To order on line an
eval board follow next link:
http://www.national.com/store
www.national.com
18
Physical Dimensions inches (millimeters) unless otherwise noted
32-Pin LLP
NS Package Number SQA32A
19
www.national.com
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Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
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