M36L0R7050T0ZAQT [NUMONYX]
Memory Circuit, 8MX16, CMOS, PBGA88, 8 X 10 MM, 0.80 MM PITCH, TFBGA-88;
| 型号： | M36L0R7050T0ZAQT |
| 厂家： | 
NUMONYX B.V |
| 描述： | Memory Circuit, 8MX16, CMOS, PBGA88, 8 X 10 MM, 0.80 MM PITCH, TFBGA-88 静态存储器 内存集成电路 |
| 文件： | 总18页 (文件大小：406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M36L0R7050T0
M36L0R7050B0
128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
32 Mbit (2M x16) PSRAM, 1.8V Supply Multi-Chip Package
FEATURES SUMMARY
■
MULTI-CHIP PACKAGE
Figure 1. Package
–
–
1 die of 128 Mbit (8Mb x16, Multiple Bank,
Multi-level, Burst) Flash Memory
1 die of 32 Mbit (2Mb x16) Asynchronous
Pseudo SRAM
■
■
SUPPLY VOLTAGE
FBGA
–
–
VDDF = VDDP = VDDQ = 1.7 to 1.95V
VPPF = 9V for fast program (12V tolerant)
ELECTRONIC SIGNATURE
–
–
Manufacturer Code: 20h
Device Code (Top Flash Configuration)
M36L0R7050T0: 88C4h
TFBGA88 (ZAQ)
8 x 10mm
–
Device Code (Bottom Flash
Configuration) M36L0R7050B0: 88C5h
■
PACKAGE
–
Compliant with Lead-Free Soldering
Processes
–
Lead-Free Versions
■
BLOCK LOCKING
FLASH MEMORY
–
–
All blocks locked at power-up
Any combination of blocks can be locked
with zero latency
WPF for Block Lock-Down
Absolute Write Protection with VPPF = VSS
■
SYNCHRONOUS / ASYNCHRONOUS READ
–
–
–
Synchronous Burst Read mode: 54MHz
Asynchronous Page Read mode
Random Access: 85ns
–
–
■
■
SYNCHRONOUS BURST READ SUSPEND
PROGRAMMING TIME
■
■
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
–
10µs typical Word program time using
Buffer Program
PSRAM
■
■
■
MEMORY ORGANIZATION
■
■
■
■
■
■
■
ACCESS TIME: 85ns
–
Multiple Bank Memory Array: 8 Mbit
Banks
LOW STANDBY CURRENT: 100µA
DEEP POWER-DOWN CURRENT: 10µA
BYTE CONTROL: UBP/LBP
PROGRAMMABLE PARTIAL ARRAY
8 WORD PAGE ACCESS CAPABILITY: 25ns
PARTIAL POWER-DOWN MODES
–
–
–
–
–
Parameter Blocks (Top or Bottom
location)
DUAL OPERATIONS
–
program/erase in one Bank while read in
others
–
No delay between read and write
operations
Deep Power-Down
4 Mbit Partial Power-Down
8 Mbit Partial Power-Down
16 Mbit Partial Power-Down
SECURITY
–
–
64 bit unique device number
2112 bit user programmable OTP Cells
December 2004
1/18
M36L0R7050T0, M36L0R7050B0
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Chip Enable (EF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Output Enable (GF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Write Enable (WF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Latch Enable (LF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Clock (KF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Wait (WAITF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PSRAM Chip Enable (E1P).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PSRAM Chip Enable (E2P).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PSRAM Output Enable (GP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Write Enable (WP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Upper Byte Enable (UBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Lower Byte Enable (LBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
V
V
DDF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DDP Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PPF Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
V
VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PSRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Power-Down Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/18
M36L0R7050T0, M36L0R7050B0
Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Bottom View Outline15
Table 10. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data. . . . . 15
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3/18
M36L0R7050T0, M36L0R7050B0
SUMMARY DESCRIPTION
The M36L0R7050T0 and M36L0R7050B0 com-
bine two memory devices in a Multi-Chip Package:
a 128-Mbit, Multiple Bank Flash memory, the
M30L0R7000T0 or M30L0R7000B0, and a 32-
Mbit PseudoSRAM, the M69AR048B. Recom-
mended operating conditions do not allow more
than one memory to be active at the same time.
Table 1. Signal Names
(1)
Address Inputs
A0-A22
DQ0-DQ15
Common Data Input/Output
V
DDF
Power Supply for Flash Memory
Flash Memory Power Supply for I/O
Buffers
The memory is offered in a Stacked TFBGA88
(8x10mm, 8x10 ball array, 0.8mm pitch) package.
In addition to the standard version, the packages
are also available in Lead-free version, in compli-
ance with JEDEC Std J-STD-020B, the ST ECO-
PACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free solder-
ing processes.
The memory is supplied with all the bits erased
(set to ‘1’).
V
V
DDQ
Flash Optional Supply Voltage for Fast
Program and Erase
PPF
V
V
Ground
SS
PSRAM Power Supply
Not Connected Internally
Do Not Use as Internally Connected
DDP
NC
DU
Flash Memory
Figure 2. Logic Diagram
L
Latch Enable Input
Chip Enable Input
Output Enable Input
Write Enable Input
Reset Input
F
V
V
PPF
DDQ
E
F
V
V
DDF
DDP
G
F
23
16
W
F
A0-A22
RP
F
DQ0-DQ15
E
G
F
F
F
WP
Write Protect Input
Burst Clock
F
WAIT
F
K
F
W
WAIT
Wait Data in Burst Mode
F
RP
F
PSRAM
WP
M36L0R7050T0
M36L0R7050B0
F
E1
Chip Enable Input
P
L
F
G
Output Enable Input
Write Enable Input
P
K
F
P
P
W
P
E1
E2
Power-down Input
P
G
UB
Upper Byte Enable Input
Lower Byte Enable Input
P
W
P
LB
P
E2
P
Note: 1. A22-A21 are not connected to the PSRAM component.
UB
P
P
LB
V
SS
AI08731
4/18
M36L0R7050T0, M36L0R7050B0
Figure 3. TFBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
DU
A4
A5
A3
A2
A1
A0
DU
A21
A22
A9
DU
DU
A11
A12
A13
A15
A16
NC
A18
A19
NC
NC
NC
V
V
NC
V
SS
SS
DDF
LB
P
NC
K
F
A17
A7
V
W
P
E
P
PPF
WP
L
F
A20
A8
A10
A14
WAIT
F
A6
UB
P
RP
W
F
F
G
H
J
DQ8
DQ0
DQ2
DQ1
DQ9
DU
DQ10
DQ3
DQ11
NC
DQ5
DQ12
DQ4
DQ13
DQ14
DQ6
NC
F
G
P
DQ7
NC
NC
G
F
DQ15
V
DDQ
E
F
K
L
DU
V
V
E2
P
DDP
DDQ
V
V
V
V
V
V
V
V
SS
SS
DDQ
DDF
SS
SS
SS
SS
DU
DU
M
DU
DU
AI08732
5/18
M36L0R7050T0, M36L0R7050B0
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A22). Addresses A0-A20
are common inputs for the Flash Memory and the
PSRAM components. The other lines (A21-A22)
are inputs for the Flash Memory components only.
The Address Inputs select the cells in the memory
array to access during Bus Read operations. Dur-
ing Bus Write operations they control the com-
mands sent to the Command Interface of the Flash
memory Program/Erase Controller or they select
the cells to access in the PSRAM.
The Flash memory component is accessed
through the Chip Enable signal (EF) and through
the Write Enable (WF) signal, while the PSRAM is
accessed through two Chip Enable signals (E1P
and E2P) and the Write Enable signal (WP).
Data Input/Output (DQ0-DQ15). In the Flash
memory the Data I/O outputs the data stored at the
selected address during a Bus Read operation or
inputs a command or the data to be programmed
during a Write Bus operation.
In the PSRAM the Lower Byte Data Inputs/Out-
puts, DQ0-DQ7, carry the data to or from the lower
part of the selected address during a Write or
Read operation, when Lower Byte Enable (LBP) is
driven Low.
The Upper Byte Data Inputs/Outputs, DQ8-DQ15,
carry the data to or from the upper part of the se-
lected address during a Write or Read operation,
when Upper Byte Enable (UBP) is driven Low.
locked or unlocked. (See the Lock Status Table in
the M30L0R7000T0 datasheet).
Flash Reset (RPF). The Reset input provides a
hardware reset of the memory. When Reset is at
VIL, the memory is in Reset mode: the outputs are
high impedance and the current consumption is
reduced to the Reset Supply Current IDD2. Refer to
Table 7., Flash Memory DC Characteristics - Cur-
rents, for the value of IDD2. After Reset all blocks
are in the Locked state and the Configuration Reg-
ister is reset. When Reset is at VIH, the device is in
normal operation. Exiting Reset mode the device
enters Asynchronous Read mode, but a negative
transition of Chip Enable or Latch Enable is re-
quired to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to VRPH
(refer to Table 8., Flash Memory DC Characteris-
tics - Voltages).
Flash Latch Enable (LF). Latch Enable latches
the address bits on its rising edge. The address
latch is transparent when Latch Enable is Low, VIL,
and it is inhibited when Latch Enable is High, VIH.
Latch Enable can be kept Low (also at board level)
when the Latch Enable function is not required or
supported.
Flash Clock (KF). The Clock input synchronizes
the Flash memory to the microcontroller during
synchronous read operations; the address is
latched on a Clock edge (rising or falling, accord-
ing to the configuration settings) when Latch En-
able is at VIL. Clock is don't care during
Asynchronous Read and in write operations.
Flash Wait (WAITF). WAIT is a Flash output sig-
nal used during Synchronous Read to indicate
whether the data on the output bus are valid. This
output is high impedance when Flash Chip Enable
is at VIH or Flash Reset is at VIL. It can be config-
ured to be active during the wait cycle or one clock
cycle in advance. The WAITF signal is not gated
by Output Enable.
Flash Chip Enable (EF). The Chip Enable input
activates the memory control logic, input buffers,
decoders and sense amplifiers. When Chip En-
able is Low, VIL, and Reset is High, VIH, the device
is in active mode. When Chip Enable is at VIH the
Flash memory is deselected, the outputs are high
impedance and the power consumption is reduced
to the standby level.
Flash Output Enable (GF). The Output Enable
input controls data output during Flash memory
Bus Read operations.
PSRAM Chip Enable (E1P). When
asserted
(Low), the Chip Enable, E1P, activates the memo-
ry state machine, address buffers and decoders,
allowing Read and Write operations to be per-
formed. When de-asserted (High), all other pins
are ignored, and the device is put, automatically, in
low-power Standby mode.
Flash Write Enable (W ). The Write Enable
F
controls the Bus Write operation of the Flash
memories’ Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WPF). Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is Low, VIL,
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is at High, VIH, Lock-Down is
disabled and the Locked-Down blocks can be
It is not allowed to set EF at VIL, E1P at VIL and E2P
at VIH at the same time.
PSRAM Chip Enable (E2P). The Chip Enable,
E2P, puts the device in Power-down mode (Deep
Power-Down or a Partial Power-Down mode)
when it is driven Low. Deep Power-down mode is
the lowest power mode.
6/18
M36L0R7050T0, M36L0R7050B0
It is not allowed to set EF at VIL, E1P at VIL and E2P
at VIH at the same time.
PSRAM Output Enable (GP). The Output En-
able, GP, provides a high speed tri-state control,
allowing fast read/write cycles to be achieved with
the common I/O data bus.
VPPF Program Supply Voltage. VPPF is both a
Flash control input and a Flash power supply pin.
The two functions are selected by the voltage
range applied to the pin.
If VPPF is kept in a low voltage range (0V to VDDQ
)
VPPF is seen as a control input. In this case a volt-
age lower than VPPLKF gives an absolute protec-
tion against Program or Erase, while VPPF > VPP1F
enables these functions (see Tables 7 and 8, DC
Characteristics for the relevant values). VPPF is
only sampled at the beginning of a Program or
Erase; a change in its value after the operation has
started does not have any effect and Program or
Erase operations continue.
If VPPF is in the range of VPPHF it acts as a power
supply pin. In this condition VPPF must be stable
until the Program/Erase algorithm is completed.
VSS Ground. VSS is the common ground refer-
ence for all voltage measurements in the Flash
(core and I/O Buffers) and PSRAM chips.
Note: Each Flash memory device in a system
should have their supply voltage (VDDF) and
the program supply voltage VPPF decoupled
with a 0.1µF ceramic capacitor close to the pin
(high frequency, inherently low inductance ca-
pacitors should be as close as possible to the
package). See Figure 6., AC Measurement
Load Circuit. The PCB track widths should be
sufficient to carry the required VPPF program
and erase currents.
PSRAM Write Enable (WP). The Write Enable,
WP, controls the Bus Write operation of the device.
PSRAM Upper Byte Enable (UBP). The Upper
Byte Enable, UBP, gates the data on the Upper
Byte Data Inputs/Outputs (DQ8-DQ15) to or from
the upper part of the selected address during a
Write or Read operation.
PSRAM Lower Byte Enable (LBP). The Lower
Byte Enable, LBP, gates the data on the Lower
Byte Data Inputs/Outputs (DQ0-DQ7) to or from
the lower part of the selected address during a
Write or Read operation.
VDDF Supply Voltage. VDDF provides the power
supply to the internal cores of the Flash memory
component. It is the main power supply for all
Flash operations (Read, Program and Erase).
VDDP Supply Voltage. The VDDP Supply Volt-
age supplies the power for all PSRAM operations
(Read, Write, etc.) and for driving the refresh logic,
even when the device is not being accessed.
V
DDQ Supply Voltage. VDDQ provides the power
supply for the Flash Memory I/O pins. This allows
all Outputs to be powered independently of the
Flash Memory core power supply, VDDF
.
7/18
M36L0R7050T0, M36L0R7050B0
FUNCTIONAL DESCRIPTION
The PSRAM and Flash memory components have
separate power supplies but share the same
grounds. They are distinguished by three Chip En-
able inputs: EF for the Flash memory and E1P and
E2P for the PSRAM.
most common example is simultaneous read oper-
ations in the Flash memory and the PSRAM which
would result in a data bus contention. Therefore it
is recommended to put the other device in the high
impedance state when reading the selected de-
vice.
Recommended operating conditions do not allow
more than one device to be active at a time. The
Figure 4. Functional Block Diagram
V
V
V
DDF
PPF DDQ
E
F
G
F
A21-A22
A0-A20
W
128 Mbit
Flash
DQ0-DQ15
F
F
RP
Memory
WAIT
WP
F
F
L
K
F
F
V
DDP
E1
P
G
P
W
32 Mbit
PSRAM
P
E2
P
UB
P
LB
P
V
SS
AI08733
8/18
M36L0R7050T0, M36L0R7050B0
Table 2. Main Operating Modes
(4)
E
F
GF WF
L
RP
E1
E2
G
W
LB
UB
P
Operation
DQ15-DQ0
F
F
WAIT
P
P
P
P
P
F
(2
V
IL
)
V
V
V
V
Flash Read
Flash Data Out
IL
IL
IL
IL
IL
IH
IH
(2
V
IL
)
V
V
V
IH
V
V
V
V
Flash Write
Flash Data In
PSRAM must be disabled
IL
IH
Flash Data Out
Flash Address
Latch
V
X
IH
IL
IH
(3)
or Hi-Z
Flash Output
Disable
V
V
V
IH
V
V
V
X
Hi-Z
IH
IH
Any PSRAM mode is allowed
Flash Standby
Flash Reset
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
IH
IH
V
X
X
X
IL
Upper Byte
data out
V
IL
V
V
IL
V
V
V
IL
IH
IH
IH
Lower Byte
data out
PSRAM Read
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IL
IL
IH
IH
IH
IL
IH
IH
IL
IL
V
V
Word Read
IL
IL
IL
Flash Memory must be disabled
Upper Byte
data in
V
IH
V
V
IL
IL
IH
Lower Byte
data in
PSRAM Write
Output Disable
V
IL
V
V
V
V
V
V
V
V
IH
IH
IH
IL
V
IL
V
IL
V
IL
V
V
V
V
Word Write
IH
IH
IH
IH
IL
IL
IH
IH
IL
IH
IH
V
IL
V
V
V
V
V
IH
Hi-Z
V
IH
V
IL
PSRAM
Standby
Any Flash mode is allowed
V
IH
V
X
X
X
X
Hi-Z
Hi-Z
IH
(Deselected)
PSRAM Power-
Down
V
X
X
X
X
X
IL
Note: 1. X = Don't care.
2. L can be tied to V if the valid address has been previously latched.
F
IH
3. Depends on G .
F
4. WAIT signal polarity is configured using the Set Configuration Register command. See the M30L0R7000T0 datasheet for details.
9/18
M36L0R7050T0, M36L0R7050B0
FLASH MEMORY DEVICE
The M36L0R7050T0 and M36L0R7050B0 contain
a 128 Mbit Flash memory. For detailed information
on how to use the devices, see the
M30L0R7000(T/B)0 datasheet which is available
from the internet site http://www.st.com or from
your local STMicroelectronics distributor.
PSRAM DEVICE
The M36L0R7050T0 and M36L0R7050B0 contain
a 32 Mbit PSRAM. This device can be placed in a
number of sleep and partial sleep modes (see Ta-
ble 3.). For detailed information on how to use the
device, see the M69AR048B datasheet which is
available from the internet site http://www.st.com
or from your local STMicroelectronics distributor.
Table 3. Power-Down Configuration Data
Power-Down Configuration Data
Mode
DQ15–DQ9
DQ8-DQ2
DQ1
DQ0
Deep Power-Down (default)
4Mb Partial Power-Down
8Mb Partial Power-Down
16Mb Partial Power-Down
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
10/18
M36L0R7050T0, M36L0R7050B0
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 4. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
–25
–25
–55
Max
85
T
Ambient Operating Temperature
Temperature Under Bias
°C
°C
°C
°C
V
A
T
85
BIAS
T
Storage Temperature
125
(1)
STG
T
Lead Temperature during Soldering
Input or Output Voltage
LEAD
V
IO
–0.5
–0.2
–0.2
3.6
2.5
V
, V
,
DDF DDQ
Core and Input/Output Supply Voltages
V
V
DDP
V
Flash Program Voltage
14
V
PPF
I
Output Short Circuit Current
100
100
mA
O
t
Time for V
at V
PPF PPFH
hours
VPPFH
®
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
11/18
M36L0R7050T0, M36L0R7050B0
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 5., Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 5. Operating and AC Measurement Conditions
Flash Memory
PSRAM
Parameter
Min
Unit
Max
1.95
–
Min
–
Max
–
V
DDF
V
DDP
V
DDQ
Supply Voltage
Supply Voltage
Supply Voltage
1.7
–
V
V
V
1.7
–
1.95
–
1.7
1.95
VPPF Supply Voltage (Factory
environment)
8.5
12.6
–
–
V
V
VPPF Supply Voltage (Application
environment)
V
+0.4
–0.4
–25
–
–
DDQ
Ambient Operating Temperature
85
–30
85
°C
pF
kΩ
ns
V
Load Capacitance (C )
30
50
L
Output Circuit Resistors (R , R )
16.7
16.7
1
2
Input Rise and Fall Times
Input Pulse Voltages
5
5
0 to V
V
0 to V
DDQ
DDQ
/2
V
/2
DDQ
Input and Output Timing Ref. Voltages
V
DDQ
Figure 5. AC Measurement I/O Waveform
Figure 6. AC Measurement Load Circuit
VDDQ
V
DDQ
VDDF
VDDQ
V
/2
DDQ
R1
0V
DEVICE
UNDER
TEST
AI06161
Note: V
= V
.
DDP
DDQ
CL
0.1µF
R2
0.1µF
CL includes JIG capacitance
AI08364B
Table 6. Device Capacitance
Symbol
Parameter
Test Condition
Min
Max
12
Unit
C
V
IN
= 0V
= 0V
Input Capacitance
Output Capacitance
pF
pF
IN
C
V
OUT
15
OUT
Note: Sampled only, not 100% tested.
12/18
M36L0R7050T0, M36L0R7050B0
Table 7. Flash Memory DC Characteristics - Currents
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Typ
Max
±1
Unit
µA
I
LI
0V ≤ V ≤ V
IN
DDQ
I
LO
0V ≤ V ≤ V
OUT DDQ
±1
µA
Supply Current
Asynchronous Read (f=6MHz)
E = V , G = V
IH
10
15
mA
F
IL
F
4 Word
8 Word
7
16
18
20
25
18
20
25
27
mA
mA
mA
mA
mA
mA
mA
mA
10
13
18
16
18
21
22
Supply Current
Synchronous Read (f=40MHz)
16 Word
Continuous
4 Word
I
DD1
8 Word
Supply Current
Synchronous Read (f=54MHz)
16 Word
Continuous
Supply Current
(Reset)
I
I
I
RP = V ± 0.2V
25
25
25
70
70
70
µA
µA
µA
DD2
DD3
DD4
F
SS
E = V
F
± 0.2V
Supply Current (Standby)
DDF
Supply Current (Automatic
Standby)
E = V , G = V
IH
F
IL
F
V
V
V
V
= V
8
10
8
15
20
15
20
mA
mA
mA
mA
PPF
PPH
DDF
PPH
DDF
Supply Current (Program)
Supply Current (Erase)
= V
= V
= V
PPF
PPF
PPF
(1)
I
DD5
10
Program/Erase in one
Bank, Asynchronous
Read in another Bank
20
35
mA
Supply Current
(Dual Operations)
(1,2)
(1)
I
DD6
Program/Erase in one
Bank, Synchronous
Read in another Bank
32
25
47
70
mA
µA
Supply Current Program/ Erase
Suspended (Standby)
E = V
F
± 0.2V
I
I
DDF
DD7
V
= V
2
5
5
5
5
5
mA
µA
mA
µA
µA
PPF
PPF
PPF
PPF
PPF
PPH
DDF
PPH
DDF
DDF
V
Supply Current (Program)
Supply Current (Erase)
PPF
PPF
V
V
V
V
= V
= V
= V
≤ V
0.2
2
(1)
PP1
V
0.2
0.2
I
V
V
Supply Current (Read)
PP2
PPF
(1)
Supply Current (Standby)
V
≤ V
0.2
5
µA
I
PPF
PPF
DDF
PP3
Note: 1. Sampled only, not 100% tested.
2. V Dual Operation current is the sum of read and program or erase currents.
DDF
13/18
M36L0R7050T0, M36L0R7050B0
Table 8. Flash Memory DC Characteristics - Voltages
Symbol
Parameter
Input Low Voltage
Test Condition
Min
Typ
Max
Unit
V
V
IL
–0.5
0.4
V
V
V
–0.4
V
+ 0.4
DDQ
Input High Voltage
Output Low Voltage
Output High Voltage
V
IH
DDQ
V
I
= 100µA
0.1
V
OL
OL
V
I
= –100µA
–0.1
V
OH
OH
DDQ
V
V
Program Voltage-Logic
Program, Erase
Program, Erase
1.1
1.8
9.0
3.3
12.6
0.4
V
PP1
PPF
V
V
Program Voltage Factory
PPF
8.5
V
PPH
V
Program or Erase Lockout
V Lock Voltage
DDF
V
PPLK
V
LKO
1
V
V
RP pin Extended High Voltage
F
3.3
V
RPH
Table 9. PSRAM DC Characteristics
Symbol
Parameter
Test Condition
Min
Max
Unit
t
/ t
=
RC WC
V
= 1.95V,
= V or V ,
IH IL
DDP
I
25
3
mA
CC1
minimum
V
IN
V
Active Current
DDP
DDP
E1 = V and E2 = V ,
P
IL
P
IH
t
/ t
1 µs
=
RC WC
I
mA
mA
µA
CC2
I
= 0mA
OUT
V
= 1.95V,
DDP
V
= V or V ,
IH IL
E1 = V and E2 = V ,
IN
I
V
Page Read Current
Power-Down Current
10
10
CC3
P
IL
P
IH
I
= 0mA, t
= min.
PRC
OUT
Deep Power-
Down
I
CCPD
V
= 1.95V,
= V or V ,
E2 ≤ 0.2V
DDP
(3)
I
40
50
µA
µA
CCP4
4Mb Partial
V
DDP
V
IN IH IL
(3)
P
I
CCP8
8Mb Partial
(3)
I
65
1
µA
µA
µA
CCP16
16Mb Partial
I
LI
0V ≤ V ≤ V
IN DDP
Input Leakage Current
Output Leakage Current
–1
–1
I
LO
0V ≤ V
≤ V
1
OUT
DDP
V
= 1.95V,
DDP
I
SB
V
≤ 0.2V or V ≥ V
–0.2V,
Standby Supply Current CMOS
100
µA
IN
IN
DDP
E1 = E2 ≥ V
–0.2V
P
P
DDP
(1)
0.8V
V + 0.2
DDP
Input High Voltage
V
V
IH
DDP
(2)
0.2V
Input Low Voltage
Output High Voltage
Output Low Voltage
–0.3
1.4
V
V
V
V
DDP
IL
V
V
DDP
= 1.65V, I
= –0.5mA
OH
OH
V
I
OL
= 1mA
0.4
OL
Note: 1. Maximum DC voltage on input and I/O pins is V
+ 0.2V.
DDP
During voltage transitions, input may positive overshoot to V
2. Minimum DC voltage on input or I/O pins is –0.3V.
+ 1.0V for a period of up to 5ns.
+ 1.0V for a period of up to 5ns.
DDP
During voltage transitions, input may positive overshoot to V
SSP
14/18
M36L0R7050T0, M36L0R7050B0
PACKAGE MECHANICAL
Figure 7. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Bottom View Outline
D
D1
e
SE
E
E2 E1
b
BALL "A1"
ddd
FE FE1
FD
SD
A
A2
A1
BGA-Z42
Note: Drawing is not to scale.
Table 10. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.0472
0.200
0.0079
0.850
0.350
8.000
5.600
0.0335
0.0138
0.3150
0.2205
0.300
7.900
0.400
8.100
0.0118
0.3110
0.0157
0.3189
D
D1
ddd
E
0.100
0.0039
0.3976
10.000
7.200
8.800
0.800
1.200
1.400
0.600
0.400
0.400
9.900
–
10.100
0.3937
0.2835
0.3465
0.0315
0.0472
0.0551
0.0236
0.0157
0.0157
0.3898
E1
E2
e
–
–
–
FD
FE
FE1
SD
SE
15/18
M36L0R7050T0, M36L0R7050B0
PART NUMBERING
Table 11. Ordering Information Scheme
Example:
M36 L 0 R 7 0 5 0 T 0 ZAQ T
Device Type
M36 = Multi-Chip Package (Multiple Flash + RAM)
Flash 1 Architecture
L = Multilevel, Multiple Bank, Burst mode
Flash 2 Architecture
0 = No Die
Operating Voltage
R = V
= V
= V
= 1.7 to 1.95V
DDQ
DDF1
DDP
Flash 1 Density
7 = 128 Mbit
Flash 2 Density
0 = No Die
RAM 1 Density
5 = 32 Mbit
RAM 0 Density
0 = No Die
Parameter Blocks Location
T = Top Boot Block Flash
B = Bottom Boot Block Flash
Product Version
0 = 0.13µm Flash technology, 85ns speeds;
0.18µm RAM, 85ns speed
Package
ZAQ = Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch
Option
Blank = Standard Packing
T = Tape & Reel Packing
E= Lead-free and RoHS package, standard packing
F= Lead-free and RoHS package, tape and reel packing
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available op-
tions (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST-
Microelectronics Sales Office nearest to you.
16/18
M36L0R7050T0, M36L0R7050B0
REVISION HISTORY
Table 12. Document Revision History
Date
Version
Revision Details
29-Jul-2003
0.1
First Issue
Package specifications updated. PSRAM component updated in accordance with
M69AR048B datasheet. Flash memory component updated in accordance with
M30L0R7000(T/B)0 datasheet.
03-Jun-2004
04-Dec-2004
0.2
1.0
Document status changed from Target Specification to Preliminary Data.
TFBGA88 package fully compliant with the ST ECOPACK specification.
Document status promoted from Preliminary Data to full Datasheet.
Flash memory and PSRAM data updated to the version 1.0 of the M30L0R7000x0
datasheet and to the version 4.0 of the M69AR048B datasheet.
17/18
M36L0R7050T0, M36L0R7050B0
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
ECOPACK is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
18/18
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