74HCT7273N [NXP]
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs; 八路D型触发器与复位;正边沿触发;漏极开路输出
| 型号： | 74HCT7273N |
| 厂家： | 
NXP |
| 描述： | Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs |
| 文件： | 总20页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74HCT7273
Octal D-type flip-flop with reset;
positive edge-trigger; open drain
outputs
Product specification
1999 Oct 01
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
FEATURES
DESCRIPTION
• ESD protection:
HBM EIA/JESD22-A114-A
Exceeds 2000 V
The 74HCT7273 is a high-speed SI-gate CMOS device and is pin compatible
with Low power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard no 7A.
MM EIA/JESD22-A115-A
Exceeds 200 V
The 74HCT7273 has eight edge-triggered D-type flip-flops with individual D
inputs and Q outputs. The common Clock (CP) and Master Reset (MR) inputs
load and reset (clear) all flip-flops simultaneously.
• Ideal buffer for MOS
microprocessor or memory
The state of each D input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding output (Qn) of the flip-flop.
• Eight positive edge-triggered
D-type flip-flops
A LOW level on the MR input forces all outputs LOW, independently of the clock
or data inputs.
• Common clock and master reset
• Output capability: standard (open
The device is useful for applications requiring true outputs only and clock and
master reset inputs that are common to all storage elements.
drain)
• ICC category: MSI.
The 74HCT7273 has open-drain N-outputs, which are clamped by a diode
connected to VCC. When a HIGH is clocked in the flip-flop, the output comes in
the high-impedance OFF-state. The output may now be pulled to any voltage
between GND and VOmax. This allows the device to be used as a LOW-to-HIGH
or HIGH-to-LOW level shifter. For digital operation and OR-tied output
applications, the device must have a pull-up resistor to establish a logic HIGH
level.
QUICK REFERENCE DATA
Ground = 0 V; Tamb = 25 °C; tr = tf = 6.0 ns.
SYMBOL PARAMETER
propagation delay
CONDITIONS
CL = 50 pF; VCC = 4.5 V
TYPICAL
UNIT
tPZL/tPLZ
CP to Qn
16
23
56
3.5
37
ns
ns
MR to Qn
fmax
CI
maximum clock frequency
input capacitance
power dissipation capacitance
MHz
pF
CPD
CL = 50 pF; f = 1 MHz; notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
2
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) + ∑(V0 /RL) × duty factor LOW where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
RL = pull-up resistor in MΩ;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC − 1.5 V.
1999 Oct 01
2
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
FUNCTION TABLE
See note 1.
INPUTS
CP
OUTPUTS
Qn
OPERATING MODES
MR
Dn
Reset (clear)
Load ‘1’
L
H
H
X
↑
X
h
l
L
Z
L
Load ‘0’
↑
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level.
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
Z = high-impedance OFF-state;
X = don’t care;
↑ = LOW-to-HIGH CP transition.
ORDERING INFORMATION
PACKAGE
OUTSIDENORTH
AMERICA
NORTH AMERICA
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
74HCT7273D
74HCT7273N
74HCT7273D
74HCT7273N
−40 to +125 °C
20
20
SO
plastic
plastic
SOT163-1
SOT146-1
DIP
1999 Oct 01
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
PINNING
PIN
SYMBOL
DESCRIPTION
1
MR
asynchronous master reset (active LOW)
flip-flop outputs
2, 5, 6, 9, 12, 15, 16, 19
Q0 to Q7
D0 to D7
GND
CP
3, 4, 7, 8, 13, 14, 17, 18
data inputs
10
11
20
ground (0 V)
clock input (LOW-to-HIGH, edge triggered)
DC supply voltage
VCC
handbook, halfpage
V
MR
1
2
20
19
18
17
16
CC
Q
0
Q
D
7
D
0
3
4
7
8
13 14 17 18
3
handbook, halfpage
7
6
D
D
1
4
D
D
D
D
D
D
D
D
7
0
1
2
3
4
5
6
Q
Q
D
Q
1
11
5
CP
6
5
7273
1
Q
2
15
14
13
12
11
MR
6
Q
Q
Q
Q
Q
Q
Q
Q
7
0
1
2
3
4
5
6
D
2
7
5
4
D
2
5
6
9
12 15 16 19
D
3
8
MNA381
Q
Q
3
9
4
GND
CP
10
MNA380
Fig.1 Pin configuration.
Fig.2 Logic symbol.
1999 Oct 01
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
handbook, halfpage
11
C1
1
R
3
2
1D
4
7
8
5
6
9
13
14
17
18
12
15
16
19
MNA382
Fig.3 IEC logic symbol.
3
4
7
8
13
14
17
18
D
0
D
D
D
D
D
D
6
D
7
1
2
3
4
5
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
FF1
CP
FF2
CP
FF3
CP
FF4
CP
FF5
CP
FF6
CP
FF7
CP
FF8
CP
R
R
R
R
R
R
R
R
D
D
D
D
D
D
D
D
CP
11
1
MR
Q
Q
Q
Q
Q
Q
Q
Q
7
0
1
2
3
4
5
6
2
5
6
9
12
15
16
19
MNA383
Fig.4 Functional diagram.
5
1999 Oct 01
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D
D
D
D
D
D
D
D
7
0
1
2
3
4
5
6
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
FF1
CP
FF2
CP
FF3
CP
FF4
CP
FF5
CP
FF6
CP
FF7
CP
FF8
CP
R
D
R
R
R
R
R
R
R
D
D
D
D
D
D
D
CP
MR
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
Q
Q
Q
Q
Q
Q
Q
Q
7
0
1
2
3
4
5
6
MNA384
Fig.5 Logic diagram.
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
RECOMMENDED OPERATING CONDITIONS
TYPE
TYP.
5.0
SYMBOL
VCC
PARAMETER
CONDITIONS
UNIT
MIN.
4.5
MAX.
5.5
DC supply voltage
input voltage
V
VI
0
−
VCC
VCC
+85
+125
500
500
500
V
VO
output voltage
0
−
V
Tamb
operating ambient
temperature
see DC and AC characteristics
per device
−40
−40
−
−
°C
°C
ns/V
−
tr,tf (∆t/∆f)
input rise and fall times
except for Schmitt-trigger
inputs
VCC = 2.0 V
6.0
6.0
6.0
V
CC = 4.5 V
CC = 6.0 V
−
V
−
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN.
−0.5
−0.5
−
MAX. UNIT
VCC
VO
IIK
+7.0
V
output voltage
+7.0
20
V
DC input diode current
DC output diode current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
mA
mA
mA
mA
°C
IOK
IO
−
±20
25
DC output source or sink current −0.5V < VO < VCC + 0.5 V
DC VCC or GND current
−
ICC
Tstg
PD
−
±50
+150
storage temperature
−65
power dissipation per package
plastic DIP
for temperature range: −40 to +125 °C
note 1
note 2
−
−
750
500
mW
mW
plastic mini-pack (SO)
Note
1. For DIP package: above 70 °C the value of PD derates linearly with 12 mW/K.
2. For SO package: above 70 °C the value of PD derates linearly with 8 mW/K.
1999 Oct 01
7
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
Tamb (°C)
−40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
SYMBOL PARAMETER
25
OTHER
VCC (V)
4.5 to 5.5 2.0
VIH
VIL
HIGH-level input
voltage
1.6
1.2 0.8
0.1
0.15 0.26
−
2.0
−
2.0
−
V
LOW-level input
voltage
4.5 to 5.5
4.5
−
−
−
−
−
−
0.8
0.1
0.33
1.0
±5.0
−
0.8
0.1
0.4
1.0
V
VOL
LOW-level
VI = VIH or VIL;
0
−
−
V
output voltage
IO = 20 µA
VI = VIH or VIL;
IO = 4.0 mA
4.5
−
−
V
II
input leakage
current
VI = VIH or VIL
5.5
−
−
0.1
−
−
µA
IOZ
HIGH level
output leakage
current
VI = VIL;
4.5 to 5.5
±0.5
−
−
±10.0 µA
VO = VCC or GND
ICC
quiescentsupply VI = VCC or GND; 5.5
−
−
−
8.0
−
−
80
−
−
160
490
µA
µA
current
IO = 0
∆ICC
additional
VI = VCC − 2.1 V
4.5 to 5.5
100 360
450
quiescentsupply other inputs at
current per input VCC or GND;
pin
IO = 0; note 1
Note
1. The value off additional quiescent supply current (∆ICC) for a unit load of 1 is given in the specifications. To determine
∆ICC per input, multiply this value by the unit load coefficient shown in Table 1.
Table 1
INPUT
UNIT LOAD COEFFICIENT
MR
CP
Dn
1.50
1.50
0.40
1999 Oct 01
8
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
AC CHARACTERISTICS
Ground = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF.
TEST CONDITIONS
T
amb (°C)
−40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
SYMBOL
PARAMETER
25
WAVEFORMS
VCC (V)
t
PZL/tPLZ
propagation delay see Figs 6 and 9 4.5
CP to Qn
−
16
23
7
30
34
15
110
−
−
38
43
19
110
−
−
45
51
22
110
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
tPZL
tTHL
tTLH
tW
propagation delay see Figs 6 and 9 4.5
MR to Qn
−
−
−
output transition
time
see Figs 6 and 9 4.5
−
−
−
output transition
time
see Figs 7 and 9 4.5
−
−
−
−
clock pulse width see Figs 6 and 9 4.5
HIGH or LOW
16
16
10
12
3
9
20
20
13
15
3
24
24
15
18
3
tW
master reset
pulse width; LOW
see Figs 7 and 9 4.5
see Figs 7 and 9 4.5
see Figs 8 and 9 4.5
see Figs 8 and 9 4.5
see Figs 6 and 9 4.5
8
−
−
−
trem
tsu
removal time
MR to CP
−2
5
−
−
−
set-up time
Dn to CP
−
−
−
th
hold time
Dn to CP
−4
56
−
−
−
fmax
maximum clock
pulse frequency
30
−
24
−
20
−
1999 Oct 01
9
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
AC WAVEFORMS
1/f
h
max
V
I
CP input
V
M
t
GND
t
W
t
PZL
90%
PLZ
V
OH
V
Q
output
M
n
10%
10%
V
OL
MNA385
t
THL
VM = 1.3 V; VI = GND to 3 V.
Fig.6 The clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and
maximum clock pulse frequency.
V
CC
V
MR input
CP input
M
GND
t
t
rem
W
V
CC
V
M
GND
t
t
PHL
TLH
V
OH
90%
V
Q
output
M
n
10%
V
OL
MNA386
VM = 1.3 V; VI = GND to 3 V.
Fig.7 Master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset
to clock (CP).
1999 Oct 01
10
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
V
I
V
CP input
M
GND
t
t
su
su
t
t
h
h
V
I
D
input
V
M
n
GND
V
OH
Q
output
n
V
OL
MNA387
VM = 1.3 V; VI = GND to 3 V.
The shaded areas indicate when the input is permitted to change for predicable output performance.
Fig.8 Data set-up and hold times for the data input (Dn).
S1
V
CC
open
V
CC
GND
1000 Ω
V
V
O
I
PULSE
D.U.T.
GENERATOR
C
R
L
T
MNA219
TEST
S1
open
t
PLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Definitions for test circuit.
VCC
CL = load capacitance including jig and probe capacitance (See Chapter “AC characteristics”).
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
GND
Fig.9 Load circuit for switching times.
11
1999 Oct 01
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
PACKAGE OUTLINES
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-24
97-05-22
SOT163-1
075E04
MS-013AC
1999 Oct 01
12
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
20
11
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
UNIT
mm
b
b
c
D
E
e
e
1
L
M
M
H
w
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.10
7.62
0.30
0.254
0.01
2.0
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.020
0.13
0.078
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-05-24
SOT146-1
SC603
1999 Oct 01
13
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Oct 01
14
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
not suitable(2)
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, SMS
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
Introduction to soldering through-hole mount packages
This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found
in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011).
Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board.
Soldering by dipping or by solder wave
The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the
joints for more than 5 seconds.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may
be necessary immediately after soldering to keep the temperature within the permissible limit.
Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm
above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If
the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.
1999 Oct 01
15
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
Suitability of through-hole mount IC packages for dipping and wave soldering methods
SOLDERING METHOD
PACKAGE
DIPPING
WAVE
DBS, DIP, HDIP, SDIP, SIL
suitable
suitable(1)
Note
1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Oct 01
16
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
NOTES
1999 Oct 01
17
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
NOTES
1999 Oct 01
18
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive
edge-trigger; open drain outputs
74HCT7273
NOTES
1999 Oct 01
19
Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
68
SCA
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245002/01/pp20
Date of release: 1999 Oct 01
Document order number: 9397 750 05733
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