74HCT73DB-T [NXP]
IC HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, SSOP-14, FF/Latch;
| 型号： | 74HCT73DB-T |
| 厂家： | 
NXP |
| 描述： | IC HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, SSOP-14, FF/Latch 光电二极管 输出元件 |
| 文件： | 总7页 (文件大小：50K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT73
Dual JK flip-flop with reset;
negative-edge trigger
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT73
The 74HC/HCT73 are dual negative-edge triggered
FEATURES
JK-type flip-flops featuring individual J, K, clock (nCP) and
reset (nR) inputs; also complementary Q and Q outputs.
• Output capability: standard
• ICC category: flip-flops
The J and K inputs must be stable one set-up time prior to
the HIGH-to-LOW clock transition for predictable
operation.
GENERAL DESCRIPTION
The 74HC/HCT73 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing
the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
HCT
tPHL/ tPLH
CL = 15 pF; VCC = 5 V
nCP to nQ
16
15
ns
nCP to nQ
16
15
77
3.5
30
18
15
79
3.5
30
ns
nR to nQ, nQ
ns
fmax
CI
maximum clock frequency
input capacitance
MHz
pF
CPD
power dissipation capacitance per flip-flop
notes 1 and 2
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT73
PIN DESCRIPTION
PIN NO.
1, 5
SYMBOL
1CP, 2CP
1R, 2R
NAME AND FUNCTION
clock input (HIGH-to-LOW, edge-triggered)
asynchronous reset inputs (active LOW)
positive supply voltage
2, 6
4
VCC
11
GND
ground (0 V)
12, 9
13, 8
14, 7, 3, 10
1Q, 2Q
1Q, 2Q
1J, 2J, 1K, 2K
true flip-flop outputs
complement flip-flop outputs
synchronous inputs; flip-flops 1 and 2
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT73
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
MODE
nR
nCP
J
K
Q
Q
asynchronous reset
L
X
X
X
L
H
toggle
H
H
H
H
↓
↓
↓
↓
h
l
h
l
h
h
l
q
L
H
q
q
H
L
load “0” (reset)
load “1” (set)
hold “no change”
l
q
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP
transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP
transition
q = lower case letters indicate the state of the referenced output one
set-up time prior to the HIGH-to-LOW CP transition
X = don’t care
↓
= HIGH-to-LOW CP transition
Fig.4 Functional diagram.
Fig.5 Logic diagram (one flip-flop).
December 1990
4
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT73
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
VCC
+25
−40 to +85 −40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nCP to nQ
52
19
15
160
32
27
200
40
34
240
48
41
ns
2.0
4.5
6.0
Fig.6
Fig.6
Fig.7
Fig.6
Fig.6
Fig.7
Fig.7
Fig.6
Fig.6
Fig.6
t
t
t
PHL/ tPLH propagation delay
nCP to nQ
52
19
15
160
32
27
200
40
34
240
48
41
ns
2.0
4.5
6.0
PHL/ tPLH propagation delay
nR to nQ, nQ
50
18
14
145
29
25
180
36
31
220
44
38
ns
2.0
4.5
6.0
THL/ tTLH output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
tW
clock pulse width
HIGH or LOW
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
tW
reset pulse width
HIGH or LOW
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
trem
tsu
th
removal time
nR to nCP
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
set-up time
nJ, nK to nCP
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
hold time
3
3
3
−8
−3
−2
3
3
3
3
3
3
ns
2.0
4.5
6.0
nJ, nK to nCP
fmax
maximum clock pulse
frequency
6.0
30
35
23
70
83
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
December 1990
5
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT73
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
nK
nR
nCP, nJ
0.60
0.65
1.00
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74 HCT
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nCP to nQ
18
21
20
7
38
36
34
15
48
45
43
19
57
54
51
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
Fig.6
Fig.6
Fig.7
Fig.6
Fig.6
Fig.7
Fig.7
Fig.6
Fig.6
Fig.6
tPHL/ tPLH propagation delay
nCP to nQ
t
PHL/ tPLH propagation delay
nR to nQ, nQ
tTHL/ tTLH output transition time
tW
clock pulse width
HIGH or LOW
16
18
14
12
3
8
20
23
18
15
3
24
27
21
18
3
tW
reset pulse width
HIGH or LOW
9
trem
tsu
th
removal time
nR to nCP
8
set-up time
nJ, nK to nCP
6
hold time
−2
72
nJ, nK to nCP
fmax
maximum clock pulse
frequency
30
24
20
MHz 4.5
December 1990
6
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT73
AC WAVEFORMS
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J
and K to nCP set-up and hold times, the output transition times and the maximum clock pulse frequency.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays and the reset pulse width
and the nR to nCP removal time.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
7
相关型号：
74HCT73U
IC HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC, DIE, FF/Latch
NXP
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