74HCT73DB [NXP]
IC HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, SSOP-14, FF/Latch;
| 型号： | 74HCT73DB |
| 厂家： | 
NXP |
| 描述： | IC HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, SSOP-14, FF/Latch |
| 文件： | 总21页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Rev. 03 — 12 November 2004
Product data sheet
1. General description
The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC
standard no. 7A.
The 74HC is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock
(nCP) and reset (nR) inputs; also complementary nQ and nQ outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock
transition for predictable operation.
The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock
and data inputs, forcing the nQ output LOW and the nQ output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features
■ Low-power dissipation
■ Complies with JEDEC standard no. 7A
■ ESD protection:
◆ HBM EIA/JESD22-A114-B exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V.
■ Multiple package options
■ Specified from −40 °C to +80 °C and from −40 °C to +125 °C.
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
tPHL, tPLH
propagation delay
nCP to nQ
CL = 15 pF; VCC = 5 V
-
-
-
-
-
-
16
16
15
77
-
-
-
-
ns
nCP to nQ
ns
nR to nQ, nQ
ns
fmax
maximum clock
frequency
CL = 15 pF; VCC = 5 V
VI = GND to VCC
MHz
CI
input capacitance
-
-
3.5
30
-
-
pF
pF
[1]
CPD
power dissipation
capacitance per flip-flop
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
4. Ordering information
Table 2:
Type number Package
Temperature range Name
Ordering information
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
Version
74HC73N
74HC73D
74HC73DB
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
DIP14
SO14
SOT27-1
SSOP14 plastic shrink small outline package; 14 leads; body width
5.3 mm
SOT337-1
74HC73PW
−40 °C to +125 °C
TSSOP14 plastic thin shrink small outline package; 14 leads; body
width 4.4 mm
SOT402-1
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
2 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
5. Functional diagram
14 1J
1Q 12
1Q 13
J
Q
Q
FF1
1 1CP
3 1K
CP
K
R
2 1R
7 2J
5 2CP
10 2K
2Q 9
2Q 8
J
Q
Q
FF2
CP
K
R
6 2R
001aab981
Fig 1. Functional diagram
4
1
3
2
1J
C1
12
13
14
7
1J
2J
1Q 12
J
Q
Q
2Q
9
1K
R
FF
R
1
5
1CP
2CP
CP
K
3
10
1K
2K
1Q 13
2Q
7
5
1J
9
8
8
C1
10
6
1K
R
1R 2R
2 6
001aab979
001aab980
Fig 2. Logic symbol
Fig 3. IEC logic symbol
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
3 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
C
C
C
C
C
C
C
C
K
J
Q
Q
R
C
C
CP
001aab982
Fig 4. Logic diagram (one flip-flop)
6. Pinning information
6.1 Pinning
1
2
3
4
5
6
7
14
13
12
11
10
9
1CP
1R
1J
1Q
1Q
GND
2K
1K
V
CC
73
2CP
2R
2Q
2Q
8
2J
001aab978
Fig 5. Pin configuration
6.2 Pin description
Table 3:
Symbol
1CP
1R
Pin description
Pin
1
Description
clock input for flip-flop 1 (HIGH-to-LOW, edge-triggered)
asynchronous reset input for flip-flop 1 (active LOW)
synchronous K input for flip-flop 1
2
1K
3
VCC
2CP
2R
4
positive supply voltage
5
clock input for flip-flop 2 (HIGH-to-LOW, edge-triggered)
asynchronous reset input for flip-flop 2 (active LOW)
synchronous J input for flip-flop 2
6
2J
7
2Q
8
complement flip-flop 2 output
2Q
9
true flip-flop 2 output
2K
10
synchronous K input for flip-flop 2
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
4 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
Table 3:
Symbol
GND
1Q
Pin description …continued
Pin
11
12
13
14
Description
ground (0 V)
true flip-flop 1 output
1Q
complement flip-flop 1 output
synchronous J input for flip-flop 1
1J
7. Functional description
7.1 Function table
Table 4:
Function table[1]
Input
nR
L
Output
Operating mode
nCP
X
nJ
X
h
l
nK
X
h
h
l
nQ
L
nQ
H
q
asynchronous reset
toggle
H
↓
q
L
H
L
load 0 (reset)
load 1 (set)
h
l
H
q
l
q
hold (no change)
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW CP transition;
X = don’t care;
↓ = HIGH-to-LOW CP transition.
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
Unit
V
VCC
IIK
supply voltage
−0.5 +7
input diode current
output diode current
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to VCC + 0.5 V
-
-
-
±20
mA
mA
mA
IOK
IO
±20
±25
output source or sink
current
ICC, IGND VCC or GND current
-
±50
mA
Tstg
Ptot
storage temperature
power dissipation
DIP14 package
−65
+150 °C
[1]
[2]
-
-
750
500
mW
mW
SO14, SSOP14 and
TSSOP14 packages
[1] Above 70 °C: Ptot derates linearly with 12 mW/K.
[2] Above 70 °C: Ptot derates linearly with 8 mW/K.
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
5 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
9. Recommended operating conditions
Table 6:
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
6.0
Unit
V
supply voltage
input voltage
output voltage
2.0
5.0
VI
0
-
VCC
VCC
1000
500
V
VO
0
-
V
tr, tf
input rise and fall
times except for
nCP
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
ns
ns
ns
°C
-
6.0
-
-
-
400
Tamb
ambient
−40
+125
temperature
10. Static characteristics
Table 7:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
VIH
HIGH-level input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
1.2
2.4
3.2
0.8
2.1
2.8
-
V
V
V
V
V
V
3.15
-
4.2
-
VIL
LOW-level input voltage
-
-
-
0.5
1.35
1.8
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −20 µA; VCC = 2.0 V
1.9
2.0
-
-
-
-
-
V
V
V
V
V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −4 mA; VCC = 4.5 V
IO = −5.2 mA; VCC = 6.0 V
4.4
4.5
5.9
6.0
3.98
5.48
4.32
5.81
VOL
LOW-level output voltage VI = VIH or VIL
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
-
-
-
-
-
-
-
-
0
0.1
0.1
0.1
0.26
0.26
±0.1
4.0
-
V
0
V
IO = 20 µA; VCC = 6.0 V
0
V
IO = 4 mA; VCC = 4.5 V
0.15
0.16
-
V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
VI = VCC or GND; IO = 0 A; VCC = 6.0 V
V
ILI
input leakage current
quiescent supply current
input capacitance
µA
µA
pF
ICC
CI
-
3.5
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
6 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
Table 7:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +85 °C
VIH
HIGH-level input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
-
-
-
-
-
-
-
V
V
V
V
V
V
3.15
-
4.2
-
VIL
LOW-level input voltage
-
-
-
0.5
1.35
1.8
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −20 µA; VCC = 2.0 V
1.9
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −4 mA; VCC = 4.5 V
IO = −5.2 mA; VCC = 6.0 V
4.4
5.9
3.84
5.34
VOL
LOW-level output voltage VI = VIH or VIL
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.1
V
IO = 20 µA; VCC = 6.0 V
0.1
V
IO = 4 mA; VCC = 4.5 V
0.33
0.33
±1.0
40.0
V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
VI = VCC or GND; IO = 0 A; VCC = 6.0 V
V
ILI
input leakage current
µA
µA
ICC
quiescent supply current
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
7 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
Table 7:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = −40 °C to +125 °C
VIH
HIGH-level input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
-
-
-
-
-
-
-
V
V
V
V
V
V
3.15
-
4.2
-
VIL
LOW-level input voltage
-
-
-
0.5
1.35
1.8
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −20 µA; VCC = 2.0 V
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
IO = −20 µA; VCC = 4.5 V
IO = −20 µA; VCC = 6.0 V
IO = −4 mA; VCC = 4.5 V
IO = −5.2 mA; VCC = 6.0 V
VOL
LOW-level output voltage VI = VIH or VIL
IO = 20 µA; VCC = 2.0 V
IO = 20 µA; VCC = 4.5 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.1
V
IO = 20 µA; VCC = 6.0 V
0.1
V
IO = 4 mA; VCC = 4.5 V
0.4
V
IO = 5.2 mA; VCC = 6.0 V
VI = VCC or GND; VCC = 6.0 V
VI = VCC or GND; IO = 0 A; VCC = 6.0 V
0.4
V
ILI
input leakage current
±1.0
80.0
µA
µA
ICC
quiescent supply current
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
8 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
11. Dynamic characteristics
Table 8:
Dynamic characteristics
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 8.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 °C
tPHL, tPLH propagation delay nCP to nQ
see Figure 6
VCC = 2.0 V
-
-
-
-
52
19
15
16
160
32
27
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
see Figure 6
propagation delay nCP to nQ
propagation delay nR to nQ, nQ
tTHL, tTLH output transition time
VCC = 2.0 V
-
-
-
-
52
19
15
16
160
32
27
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
see Figure 7
VCC = 2.0 V
-
-
-
-
50
18
14
15
145
29
25
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
see Figure 6
VCC = 2.0 V
-
-
-
19
7
75
15
13
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
tW
nCP clock pulse width HIGH or LOW see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
14
22
8
-
-
-
ns
ns
ns
6
nR reset pulse width HIGH or LOW
removal time nR to nCP
80
16
14
22
8
-
-
-
ns
ns
ns
6
trem
80
16
14
22
8
-
-
-
ns
ns
ns
6
tsu
set-up time nJ, nK to nCP
80
16
14
22
8
-
-
-
ns
ns
ns
6
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
9 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
Table 8:
Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 8.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
th
hold time nJ, nK to nCP
see Figure 6
VCC = 2.0 V
3
3
3
−8
−3
−2
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
fmax
maximum clock frequency
see Figure 6
VCC = 2.0 V
6.0
30
35
-
23
70
83
77
30
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
VCC = 6.0 V
VCC = 5.0 V; CL = 15 pF
VI = GND to VCC
[1]
CPD
power dissipation capacitance per
flip-flop
-
Tamb = −40 °C to +85 °C
tPHL, tPLH propagation delay nCP to nQ
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
200
40
ns
ns
ns
34
propagation delay nCP to nQ
propagation delay nR to nQ, nQ
tTHL, tTLH output transition time
-
-
-
-
-
-
200
40
ns
ns
ns
34
-
-
-
-
-
-
180
36
ns
ns
ns
31
-
-
-
-
-
-
95
19
16
ns
ns
ns
tW
nCP clock pulse width HIGH or LOW see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
100
20
-
-
-
-
-
-
ns
ns
ns
17
nR reset pulse width HIGH or LOW
removal time nR to nCP
100
20
-
-
-
-
-
-
ns
ns
ns
17
trem
100
20
-
-
-
-
-
-
ns
ns
ns
17
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
10 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
Table 8:
Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 8.
Symbol Parameter
Conditions
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Typ
Max
Unit
tsu
set-up time nJ, nK to nCP
hold time nJ, nK to nCP
maximum clock frequency
100
20
-
-
-
-
-
-
ns
ns
ns
17
th
3
3
3
-
-
-
-
-
-
ns
ns
ns
fmax
4.8
24
28
-
-
-
-
-
-
MHz
MHz
MHz
Tamb = −40 °C to +125 °C
tPHL, tPLH propagation delay nCP to nQ
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
-
-
-
-
-
-
240
48
ns
ns
ns
41
propagation delay nCP to nQ
propagation delay nR to nQ, nQ
tTHL, tTLH output transition time
-
-
-
-
-
-
240
48
ns
ns
ns
41
-
-
-
-
-
-
220
44
ns
ns
ns
38
-
-
-
-
-
-
110
22
ns
ns
ns
19
tW
nCP clock pulse width HIGH or LOW see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
120
24
-
-
-
-
-
-
ns
ns
ns
20
nR reset pulse width HIGH or LOW
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
120
24
-
-
-
-
-
-
ns
ns
ns
20
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
11 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
Table 8:
Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 8.
Symbol Parameter
Conditions
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
see Figure 6
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Typ
Max
Unit
trem
removal time nR to nCP
set-up time nJ, nK to nCP
hold time nJ, nK to nCP
maximum clock frequency
120
24
-
-
-
-
-
-
ns
ns
ns
20
tsu
120
24
-
-
-
-
-
-
ns
ns
ns
20
th
3
3
3
-
-
-
-
-
-
ns
ns
ns
fmax
4.0
20
24
-
-
-
-
-
-
MHz
MHz
MHz
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
12 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
12. Waveforms
nJ, nK
input
V
M
t
t
h
h
t
t
su
su
1/f
max
V
M
nCP input
t
W
t
t
PLH
PHL
V
V
M
M
nQ output
nQ output
t
t
THL
TLH
t
t
TLH
THL
t
t
PLH
PHL
001aab983
The shaded areas indicate when the input is permitted to change for predictable output
performance.
VM = 0.5 × VI.
Fig 6. Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the
clock pulse width, the J and K to nCP set-up and hold times, the output transition
times and the maximum clock frequency
V
M
nCP input
nR input
t
rem
t
W
V
M
t
PHL
nQ output
nQ input
t
PLH
001aab984
VM = 0.5 × VI.
Fig 7. Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays
and the reset pulse width and the nR to nCP removal time
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
13 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
V
CC
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
L
R
T
mna101
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Fig 8. Load circuitry for switching times
Table 9:
Supply
VCC
Test data
Input
VI
Load
CL
tr, tf
6 ns
6 ns
6 ns
6 ns
2.0 V
VCC
VCC
VCC
VCC
50 pF
50 pF
50 pF
15 pF
4.5 V
6.0 V
5.0 V
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
14 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
13. Package outline
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
14
8
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2.2
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT27-1
050G04
MO-001
SC-501-14
Fig 9. Package outline SOT27-1 (DIP14)
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
15 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 10. Package outline SOT108-1 (SO14)
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
16 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
7
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT337-1
MO-150
Fig 11. Package outline SOT337-1 (SSOP14)
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
17 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 12. Package outline SOT402-1 (TSSOP14)
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
18 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
14. Revision history
Table 10: Revision history
Document ID
Release
date
Data sheet status
Change notice Doc. number
Supersedes
74HC73_3
20041112
Product data sheet
-
9397 750 13815 74HC_HCT73_CNV_2
Modifications:
• The format of this data sheet has been redesigned to comply with the current presentation
and information standard of Philips Semiconductors.
• Removed type number 74HCT73.
• Inserted family specification.
74HC_HCT73_CNV_2 19970911
Product specification
-
-
-
74HC_HCT73_1
-
74HC_HCT73_1
19901201
Product specification
-
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
19 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
15. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
17. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
18. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
20 of 21
74HC73
Philips Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
19. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 5
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 20
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Contact information . . . . . . . . . . . . . . . . . . . . 20
9
10
11
12
13
14
15
16
17
18
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 12 November 2004
Document number: 9397 750 13815
Published in The Netherlands
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