74LVCH32245AEC/G,5_技术文档

74LVCH32245A

32-bit bus transceiver with direction pin; 5 V tolerant; 3-state

Rev. 5 — 15 December 2011

Product data sheet

1. General description

The 74LVCH32245A is a 32-bit transceiver featuring non-inverting 3-state bus compatible

outputs in both send and receive directions. The device features four output enable (nOE)

inputs for easy cascading and four send/receive (nDIR) inputs for direction control.

Pin nOE controls the outputs so that the buses are effectively isolated.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be

applied to the outputs. These features allow the use of these devices in mixed

3.3 V and 5 V applications.

To ensure the high-impedance state during power-up or power-down, pin nOE should be

tied to V_CCthrough a pull-up resistor; the minimum value of the resistor is determined by

the current-sinking capability of the driver.

Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused

inputs.

2. Features and benefits

 5 V tolerant inputs/outputs for interfacing with 5 V logic

 Wide supply voltage range from 2.3 V to 3.6 V

 CMOS low power consumption

 MULTIBYTE flow-through standard pin-out architecture

 Low inductance multiple power and ground pins for minimum noise and ground

bounce

 Direct interface with TTL levels

 Inputs accept voltages up to 5.5 V

 High-impedance when V_CC= 0 V

 All data inputs have bus hold

 Complies with JEDEC standard:

 JESD8-7A (1.65 V to 1.95 V)

 JESD8-5A (2.3 V to 2.7 V)

 JESD8-C/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115B exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Specified from 40 C to +85 C and 40 C to +125 C

 Packaged in plastic fine-pitch ball grid array package

74LVCH32245A

NXP Semiconductors

32-bit bus transceiver with direction pin; 5 V tolerant; 3-state

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVCH32245AEC 40 C to +125 C

LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1

96 balls; body 13.5  5.5  1.05 mm

74LVCH32245A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 15 December 2011

2 of 15

74LVCH32245A

NXP Semiconductors

32-bit bus transceiver with direction pin; 5 V tolerant; 3-state

4. Functional diagram

2DIR

H3

1DIR

A3

1OE

1B0

1B1

1B2

1B3

1B4

1B5

1B6

1B7

2OE

2B0

2B1

2B2

2B3

2B4

2B5

2B6

2B7

A4

A2

A1

B2

B1

C2

C1

D2

D1

H4

E2

E1

F2

F1

G2

G1

H1

H2

2A0

2A1

2A2

2A3

2A4

2A5

2A6

2A7

1A0

A5

E5

E6

F5

F6

G5

G6

H6

H5

1A1

A6

1A2

B5

1A3

B6

1A4

C5

1A5

C6

1A6

D5

1A7

D6

3DIR

J3

4DIR

T3

3OE

3B0

3B1

3B2

3B3

3B4

3B5

3B6

3B7

4OE

4B0

4B1

4B2

4B3

4B4

4B5

4B6

J4

T4

N2

N1

P2

P1

R2

R1

T1

T2

3A0

J5

4A0

4A1

4A2

4A3

4A4

4A5

4A6

4A7

N5

N6

P5

P6

R5

R6

T6

T5

J2

3A1

J6

J1

3A2

K5

K2

K1

L2

L1

M2

M1

3A3

K6

3A4

L5

3A5

L6

3A6

M5

3A7

M6

4B7

mna476

Fig 1. Logic symbol

74LVCH32245A

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Product data sheet

Rev. 5 — 15 December 2011

3 of 15

74LVCH32245A

NXP Semiconductors

32-bit bus transceiver with direction pin; 5 V tolerant; 3-state

V

CC

data input

to internal circuit

mna705

Fig 2. Bus hold circuit

5. Pinning information

5.1 Pinning

mna475

6

5

4

3

2

1

1A1 1A3 1A5 1A7 2A1 2A3 2A5 2A6 3A1 3A3 3A5 3A7 4A1 4A3 4A5 4A6

1A0 1A2 1A4 1A6 2A0 2A2 2A4 2A7 3A0 3A2 3A4 3A6 4A0 4A2 4A4 4A7

1OE GND V

1DIR GND V

GND GND V

GND 2OE 3OE GND V

GND 2DIR 3DIR GND V

GND GND V

GND 4OE

GND 4DIR

CC

1B0 1B2 1B4 1B6 2B0 2B2 2B4 2B7 3B0 3B2 3B4 3B6 4B0 4B2 4B4 4B7

1B1 1B3 1B5 1B7 2B1 2B3 2B5 2B6 3B1 3B3 3B5 3B7 4B1 4B3 4B5 4B6

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

Fig 3. Pin configuration

5.2 Pin description

Table 2.

Symbol

nDIR (n = 1 to 4)

nOE (n = 1 to 4)

1A[0:7]

Pin description

Ball

Description

A3, H3, J3, T3

A4, H4, J4, T4

direction control

output enable input (active LOW)

input or output

A5, A6, B5, B6, C5, C6, D5, D6

A2, A1, B2, B1, C2, C1, D2, D1

E5, E6, F5, F6, G5, G6, H6, H5

E2, E1, F2, F1, G2, G1, H1, H2

J5, J6, K5, K6, L5, L6, M5, M6

J2, J1, K2, K1, L2, L1, M2, M1

N5, N6, P5, P6, R5, R6, T6, T5

N2, N1, P2, P1, R2, R1, T1, T2

1B[0:7]

input or output

2A[0:7]

input or output

2B[0:7]

input or output

3A[0:7]

input or output

3B[0:7]

input or output

4A[0:7]

input or output

4B[0:7]

input or output

GND

B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, ground (0 V)

M3, M4, N3, N4, R3, R4

V_CC

C3, C4, F3, F4, L3, L4, P3, P4

supply voltage

74LVCH32245A

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Product data sheet

Rev. 5 — 15 December 2011

4 of 15

74LVCH32245A

NXP Semiconductors

32-bit bus transceiver with direction pin; 5 V tolerant; 3-state

6. Functional description

Table 3.

Function selection^[1]

Input

nOE

L

Output

nDIR

nAn

A = B

inputs

Z

nBn

inputs

B = A

Z

L

H

X

H

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

0.5

50

0.5

-

Max

+6.5

-

Unit

V

supply voltage

input clamping current

input voltage

V_I< 0 V

mA

V

[1]

V_I

+6.5

50

I_OK

output clamping current

output voltage

V_O> V_CCor V_O< 0 V

output HIGH or LOW state

output 3-state

mA

V

[2]

V_O

0.5

-

V_CC+ 0.5

+6.5

50

V

I_O

output current

V_O= 0 V to V_CC

mA

C

[3]

I_CC

I_GND

T_stg

P_tot

supply current

-

200

ground current

200

65

-

storage temperature

total power dissipation

+150

1000

[4]

T_amb= 40 C to +125 C

mW

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[2] The output voltage ratings may be exceeded if the output current ratings are observed.

[3] All supply and ground pins connected externally to one voltage source.

[4] Above 70 C the value of P_totderates linearly with 1.8 mW/K.

8. Recommended operating conditions

Table 5.

Symbol

V_CC

Recommended operating conditions

Parameter

Conditions

Min

1.65

1.2

0

Typ

Max

3.6

-

Unit

supply voltage

-

V

functional

V

V_I

input voltage

5.5

V_CC

5.5

+125

20

V

V_O

output voltage

output HIGH or LOW state

output 3-state

0

V

0

V

T_amb

ambient temperature

in free air

40

-

C

ns/V

t/V

input transition rise and fall rate

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

-

10

74LVCH32245A

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Product data sheet

Rev. 5 — 15 December 2011

5 of 15

74LVCH32245A

NXP Semiconductors

32-bit bus transceiver with direction pin; 5 V tolerant; 3-state

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C

Unit

Min

Typ^[1]

Max

Min

Max

V_IH

HIGH-level

input voltage

V_CC= 1.2 V

1.08

-

1.08

-

V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_CC= 1.2 V

0.65  V_CC

-

0.65  V_CC

-

1.7

-

1.7

-

2.0

-

0.12

2.0

-

0.12

V_IL

LOW-level

input voltage

-

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_I= V_IHor V_IL

0.35  V_CC

0.7

0.35  V_CC

0.7

0.8

V_OH

HIGH-level

output

voltage

I_O= 100 A;

V_CC= 1.65 V to 3.6 V

V_CC 0.2

-

V_CC 0.3

-

V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 18 mA; V_CC= 3.0 V

I_O= 24 mA; V_CC= 3.0 V

V_I= V_IHor V_IL

1.2

1.8

2.2

2.4

2.2

-

1.05

1.65

2.05

2.25

2.0

-

V

V_OL

LOW-level

output

voltage

I_O= 100 A;

V_CC= 1.65 V to 3.6 V

-

0.2

-

0.3

V

I_O= 4 mA; V_CC= 1.65 V

I_O= 8 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

-

0.45

0.6

-

0.65

0.8

V

-

V

-

0.4

0.6

V

0.55

5

0.8

V

[2]

I_I

input

V_CC= 3.6 V;

V_I= 5.5 V or GND

0.1

20

A

leakage

current

I_OZ

OFF-state

output

V_I= V_IHor V_IL; V_CC= 3.6 V;

V_O= 5.5 V or GND;

-

0.1

5

-

20

A

current

I_OFF

power-off

leakage

current

V

_CC= 0 V; V_Ior V_O= 5.5 V

10

I_CC

supply

current

V_CC= 3.6 V;

V_I= V_CCor GND; I_O= 0 A

-

0.1

5

40

-

160

A

I_CC

additional

supply

current

per input pin;

V_CC= 2.7 V to 3.6 V;

V_I= V_CC 0.6 V; I_O= 0 A

500

5000

C_I

input

V_CC= 0 V to 3.6 V;

-

5.0

-

pF

capacitance V_I= GND to V_CC

74LVCH32245A

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Product data sheet

Rev. 5 — 15 December 2011

6 of 15

74LVCH32245A

NXP Semiconductors

32-bit bus transceiver with direction pin; 5 V tolerant; 3-state

Table 6.

Static characteristics …continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

40 C to +85 C

40 C to +125 C

Unit

Min

Typ^[1]

Max

Min

10

Max

[3][4]

[3][5]

I_BHL

bus hold

LOW current

V_CC= 1.65; V_I= 0.58 V

V_CC= 2.3; V_I= 0.7 V

V_CC= 3.0; V_I= 0.8 V

10

30

-

A

25

75

60

I_BHH

bus hold

HIGH

current

V_CC= 1.65; V_I= 1.07 V

10

30

75

200

300

500

10

25

60

200

300

500

V_CC= 2.3; V_I= 1.7 V

V_CC= 3.0; V_I= 2.0 V

V_CC= 1.95 V

I_BHLO

bus hold

LOW

overdrive

current

V_CC= 2.7 V

V_CC= 3.6 V

[3][5]

I_BHHO

bus hold

HIGH

overdrive

current

V_CC= 1.95 V

V_CC= 2.7 V

V_CC= 3.6 V

200

300

500

-

200

300

500

-

A

[1] All typical values are measured at V_CC= 3.3 V and T_amb= 25 C.

[2] The bus hold circuit is switched off when V_I> V_CCallowing 5.5 V on the input pin.

[3] Valid for data inputs only. Control inputs do not have a bus hold circuit.

[4] The specified sustaining current at the data inputs holds the input below the specified V_Ilevel.

[5] The specified overdrive current at the data input forces the data input to the opposite logic input state.

10. Dynamic characteristics

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 6.

Symbol Parameter

Conditions

T_amb= 40 C to +85 C 40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

[2]

t_pd

propagation

delay

nAn to nBn; nBn to nAn; see Figure 4

V_CC= 1.2 V

-

13.0

5.2

2.8

2.7

2.4

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

1.0

12.2

6.0

4.7

4.5

1.5

1.0

13.8

6.7

6.0

V_CC= 3.0 V to 3.6 V

nOE to nAn, nBn: see Figure 5

V_CC= 1.2 V

[2]

t_en

enable time

-

15.0

5.9

3.3

3.5

2.7

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

1.0

1.5

1.0

15.0

7.9

6.7

5.5

1.5

1.0

1.5

1.0

16.9

8.8

8.5

7.0

V_CC= 3.0 V to 3.6 V

74LVCH32245A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 15 December 2011

7 of 15

74LVCH32245A

NXP Semiconductors

32-bit bus transceiver with direction pin; 5 V tolerant; 3-state

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 6.

Symbol Parameter

Conditions

T_amb= 40 C to +85 C 40 C to +125 C Unit

Min

Typ^[1]

Max

Min

Max

[2]

t_dis

disable time

nOE to nAn, nBn; see Figure 5

V_CC= 1.2 V

-

11.0

4.9

2.7

3.4

3.3

-

ns

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.5

0.5

1.5

-

13.1

7.1

6.6

5.6

1.0

1.5

0.5

1.5

-

14.7

7.9

8.5

7.0

1.5

ns

V_CC= 3.0 V to 3.6 V

ns

[3]

[4]

t_sk(o)

C_PD

output skew

time

power

dissipation

capacitance

per buffer; V_I= GND to V_CC

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

-

11.5

15.2

18.5

-

pF

V_CC= 3.0 V to 3.6 V

[1] Typical values are measured at T_amb= 25 C and V_CC= 1.2, 1.8, 2.5 V, 2.7 V, and 3.3 V respectively.

[2] t_pdis the same as t_PLHand t_PHL

t_enis the same as t_PZLand t_PZH

t_disis the same as t_PLZand t_PHZ

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] _PDis used to determine the dynamic power dissipation (P_Din W).

.

C

P_D= C_PD V_CC² f_i N + (C_L V_CC² f_o) where:

f_i= input frequency in MHz; f_o= output frequency in MHz

C_L= output load capacitance in pF

V_CC= supply voltage in Volts

N = number of inputs switching

(C_L V_CC² f_o) = sum of the outputs.

11. Waveforms

V

I

nAn, nBn

input

V

M

GND

t

PHL

PLH

V

OH

nBn, nAn

output

V

M

mna477

V

OL

V_M= 1.5 V at V_CC 2.7 V.

_M= 0.5  V_CCat V_CC< 2.7 V.

V

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 4. The input (nAn, nBn) to output (nBn, nAn) propagation delays

74LVCH32245A

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Product data sheet

Rev. 5 — 15 December 2011

8 of 15

74LVCH32245A

NXP Semiconductors

32-bit bus transceiver with direction pin; 5 V tolerant; 3-state

V

I

nOE input

GND

V

M

t

PZL

PLZ

V

CC

output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PHZ

PZH

V

OH

V

Y

output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

enabled

outputs

disabled

mna362

V_M= 1.5 V at V_CC 2.7 V.

V_M= 0.5  V_CCat V_CC< 2.7 V.

V

_X= V_OL+ 0.3 V at V_CC 2.7 V;

V_X= V_OL+ 0.15 V at V_CC 2.7 V.

V_Y= V_OH 0.3 V at V_CC 2.7 V;

V

_Y= V_OH 0.15 V at V_CC 2.7 V.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 5. 3-state enable and disable times.

74LVCH32245A

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Product data sheet

Rev. 5 — 15 December 2011

9 of 15

74LVCH32245A

NXP Semiconductors

32-bit bus transceiver with direction pin; 5 V tolerant; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

EXT

R

V

CC

L

V

O

I

G

DUT

R

T

C

L

R

L

001aae331

Test data is given in Table 8.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig 6. Load circuitry for switching times

Table 8.

Test data

Supply voltage

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

t_PLZ, t_PZL

2  V_CC

t_PHZ, t_PZH

GND

1.2 V

V_CC

2.7 V

 2 ns

 2.5 ns

30 pF

50 pF

1 k

500 

1.65 V to 1.95 V

2.3 V to 2.7 V

2.7 V

open

GND

open

GND

open

GND

3.0 V to 3.6 V

open

GND

74LVCH32245A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 15 December 2011

10 of 15

74LVCH32245A

NXP Semiconductors

32-bit bus transceiver with direction pin; 5 V tolerant; 3-state

12. Package outline

LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1

B

A

D

ball A1

index area

A

2

A

E

A

1

detail X

e

1

C

1/2 e

y

∅ v M

∅ w M

C

A B

C

1

e

b

T

R

P

N

e

M

L

K

J

H

G

F

e

2

1/2 e

E

D

C

B

A

ball A1

index area

1

2

3

4

5

6

X

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

e

v

w

y

1

D

E

1

2

1

2

max.

0.41

0.31

1.2

0.9

0.51

0.41

5.6

5.4

13.6

13.4

mm

1.5

4

12

0.1

0.2

0.8

0.15

0.1

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

00-03-04

03-02-05

SOT536-1

Fig 7. Package outline SOT536-1 (LFBGA96)

74LVCH32245A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 15 December 2011

11 of 15

74LVCH32245A

NXP Semiconductors

32-bit bus transceiver with direction pin; 5 V tolerant; 3-state

13. Abbreviations

Table 9.

Acronym

CDM

DUT

Abbreviations

Description

Charged Device Model

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

Machine Model

HBM

MM

TTL

Transistor-Transistor Logic

14. Revision history

Table 10. Revision history

Document ID

Release date

20111215

Data sheet status

Change notice

Supersedes

74LVCH32245A v.5

Modifications:

Product data sheet

-

74LVCH32245A v.4

• Maximum propagation delay value for V_CC= 1.65 V to 1.95 V at +125 C changed from

12.9 ns to 13.8 ns

• Maximum enable time value for V_CC= 1.65 V to 1.95 V at +125 C changed from 15.8 ns

to 16.9 ns

• Maximum disable time value for V_CC= 1.65 V to 1.95 V at +125 C changed from 13.7 ns

to 14.7 ns

74LVCH32245A v.4

Modifications:

20111109

Product data sheet

-

74LVCH32245A v.3

• Table 4, Table 5, Table 6, Table 7 and Table 8: values added for lower voltage ranges.

74LVCH32245A v.3

74LVCH32245A v.2

74LVC_LVCH32245A v.1

20070820

20040511

19990901

Product data sheet

Product specification

-

74LVCH32245A v.2

74LVC_LVCH32245A v.1

-

74LVCH32245A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 15 December 2011

12 of 15

74LVCH32245A

NXP Semiconductors

32-bit bus transceiver with direction pin; 5 V tolerant; 3-state

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

15.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

74LVCH32245A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 15 December 2011

13 of 15

74LVCH32245A

NXP Semiconductors

32-bit bus transceiver with direction pin; 5 V tolerant; 3-state

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

74LVCH32245A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 15 December 2011

14 of 15

74LVCH32245A

NXP Semiconductors

32-bit bus transceiver with direction pin; 5 V tolerant; 3-state

17. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6

Functional description . . . . . . . . . . . . . . . . . . . 5

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended operating conditions. . . . . . . . 5

Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12

7

8

9

10

11

12

13

14

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 13

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

15.1

15.2

15.3

15.4

16

17

Contact information. . . . . . . . . . . . . . . . . . . . . 14

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 15 December 2011

Document identifier: 74LVCH32245A


型号：	74LVCH32245AEC/G,5
厂家：	NXP
描述：	74LVCH32245A - 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state BGA 96-Pin 逻辑集成电路
文件：	总15页 (文件大小：126K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LVCH32245AEC/G,5 [NXP]

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