74LVCH32373AEC/G;5 [NXP]
74LVCH32373A - 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state BGA 96-Pin;
| 型号： | 74LVCH32373AEC/G;5 |
| 厂家： | 
NXP |
| 描述： | 74LVCH32373A - 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state BGA 96-Pin 驱动 逻辑集成电路 |
| 文件： | 总14页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVCH32373A
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
Product specification
2004 May 19
Supersedes data of 1999 Nov 24
Philips Semiconductors
Product specification
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
74LVCH32373A
FEATURES
The 74LVCH32373A is a 32-bit transparent D-type latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. One latch enable
input (nLE) and one output enable input (nOE) are
provided for each octal. Inputs can be driven from either
3.3 V or 5 V devices.
• 5 V tolerant inputs/outputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low power consumption
• MULTIBYTE flow-trough standard pin-out architecture
The 74LVCH32373A consists of 4 sections of eight D-type
transparent latches with 3-state true outputs. When input
nLE is HIGH, data at the nDn inputs enter the latches. In
this condition the latches are transparent, i.e. a latch
output will change each time its corresponding D-input
changes.
• Low inductance multiple power and ground pins for
minimum noise and ground bounce
• Direct interface with TTL levels
• Inputs accept voltages up to 5.5 V
• All data inputs have bushold
• Complies with JEDEC standard JESD8-B/JESD36
When input nLE is LOW, the latches store the information
that was present at the D-inputs one set-up time preceding
the HIGH-to-LOW transition of nLE. When input nOE is
LOW, the contents of the eight latches are available at the
outputs. When input nOE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the nOE input
does not affect the state of the latches.
• ESD protection:
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 °C to +85 °C
• Packaged in plastic fine-pitch ball grid array package.
The 74LVCH32373A bushold data input circuits eliminate
the need for external pull-up resistors to hold unused
inputs.
DESCRIPTION
The 74LVCH32373A is a high-performance, low-power,
low-voltage, Si-gate CMOS device superior to most
advanced CMOS compatible TTL families.
The inputs can be driven from either 3.3 V or 5 V devices.
In 3-state operation, outputs can handle 5 V. These
features allow the use of these devices in a mixed
3.3 V and 5 V environment.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns
SYMBOL
tPHL/tPLH
PARAMETER
CONDITIONS
TYPICAL
3.0
UNIT
propagation delay nDn to nQn
propagation delay nLE to nQn
3-state output enable time nOE to nQn
3-state output disable time nOE to nQn
input capacitance
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
ns
ns
ns
ns
pF
3.4
3.5
3.9
5.0
tPZH/tPZL
PHZ/tPLZ
t
CI
CPD
power dissipation per latch
VCC = 3.3 V; notes 1 and 2
outputs enabled
15
11
pF
pF
outputs disabled
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
2004 May 19
2
Philips Semiconductors
Product specification
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
74LVCH32373A
CL = output load capacity in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC
.
FUNCTION TABLE
See note 1.
INPUT
nLE
OUTPUT
INTERNAL
LATCH
OPERATING MODE
nOE
nDn
nQn
Enable and read register
(transparent mode)
L
L
H
H
L
L
L
L
L
H
l
L
H
L
L
H
L
Latch and read register
L
L
h
l
H
L
H
Z
Z
Latch register and disable
outputs
H
H
h
H
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
−40 °C to +85 °C
PINS
PACKAGE MATERIAL
CODE
SOT536-1
74LVCH32373AEC
96
LFBGA96
plastic
PINNING
BALL SYMBOL
DESCRIPTION
BALL SYMBOL
DESCRIPTION
data output
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
1D2
1D3
1Q5
1Q4
VCC
VCC
1D4
1D5
1Q7
1Q6
GND
data input
data input
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
1Q1
1Q0
1OE
1LE
1D0
1D1
1Q3
1Q2
GND
GND
data output
data output
data output
supply voltage
supply voltage
data input
output enable input (active LOW)
latch enable input (active HIGH)
data input
data input
data output
data input
data output
data output
data output
ground (0 V)
ground (0 V)
ground (0 V)
2004 May 19
3
Philips Semiconductors
Product specification
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
74LVCH32373A
BALL SYMBOL
DESCRIPTION
ground (0 V)
BALL SYMBOL
DESCRIPTION
D4
D5
D6
E1
E2
E3
E4
E5
E6
F1
F2
F3
F4
F5
F6
G1
G2
G3
G4
G5
G6
H1
H2
H3
H4
H5
H6
J1
GND
1D6
1D7
2Q1
2Q0
GND
GND
2D0
2D1
2Q3
2Q2
VCC
VCC
2D2
2D3
2Q5
2Q4
GND
GND
2D4
2D5
2Q6
2Q7
2OE
2LE
2D7
2D6
3Q1
3Q0
3OE
3LE
3D0
3D1
3Q3
3Q2
GND
GND
3D2
3D3
3Q5
3Q4
L3
VCC
VCC
3D4
3D5
3Q7
3Q6
GND
GND
3D6
3D7
4Q1
4Q0
GND
GND
4D0
4D1
4Q3
4Q2
VCC
VCC
4D2
4D3
4Q5
4Q4
GND
GND
4D4
4D5
4Q6
4Q7
4OE
4LE
4D7
4D6
supply voltage
data input
L4
supply voltage
data input
data input
L5
data output
L6
data input
data output
M1
M2
M3
M4
M5
M6
N1
N2
N3
N4
N5
N6
P1
P2
P3
P4
P5
P6
R1
R2
R3
R4
R5
R6
T1
T2
T3
T4
T5
T6
data output
ground (0 V)
ground (0 V)
data input
data output
ground (0 V)
ground (0 V)
data input
data input
data output
data input
data output
data output
supply voltage
supply voltage
data input
data output
ground (0 V)
ground (0 V)
data input
data input
data output
data input
data output
data output
ground (0 V)
ground (0 V)
data input
data output
supply voltage
supply voltage
data input
data input
data output
data input
data output
data output
output enable input (active LOW)
latch enable input (active HIGH)
data input
data output
ground (0 V)
ground (0 V)
data input
data input
data output
data input
J2
data output
data output
J3
output enable input (active LOW)
latch enable input (active HIGH)
data input
data output
J4
output enable input (active LOW)
latch enable input (active HIGH)
data input
J5
J6
data input
K1
K2
K3
K4
K5
K6
L1
L2
data output
data input
data output
ground (0 V)
ground (0 V)
data input
data input
data output
data output
2004 May 19
4
Philips Semiconductors
Product specification
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
74LVCH32373A
mna492
6
5
4
3
2
1
1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D6 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D6
1D0 1D2 1D4 1D6 2D0 2D2 2D4 2D7 3D0 3D2 3D4 3D6 4D0 4D2 4D4 4D7
V
V
V
V
1LE GND
1OE GND
GND GND
GND GND
GND 2LE 3LE GND
GND 2OE 3OE GND
GND GND
GND GND
GND 4LE
CC
CC
CC
CC
CC
CC
CC
CC
V
V
V
V
GND 4OE
1Q0 1Q2 1Q4 1Q6 2Q0 2Q2 2Q4 2Q7 3Q0 3Q2 3Q4 3Q6 4Q0 4Q2 4Q4 4Q7
1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2Q6 3Q1 3Q3 3Q5 3Q7 4Q1 4Q3 4Q5 4Q6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Fig.1 Pin configuration.
1D0
2D0
1Q0
2Q0
D
Q
D
Q
LATCH 1
LE LE
LATCH 9
LE LE
1LE
2LE
1OE
2OE
to 7 other channels
to 7 other channels
3D0
4D0
3Q0
4Q0
D
Q
D
Q
LATCH 17
LE LE
LATCH 25
LE LE
3LE
4LE
3OE
4OE
to 7 other channels
to 7 other channels
mna493
Fig.2 Logic symbol.
5
2004 May 19
Philips Semiconductors
Product specification
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
74LVCH32373A
V
handbook, halfpage
CC
data
input
to internal circuit
MNA473
Fig.3 Bushold circuit.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
2.7
MAX.
3.6
UNIT
VCC
for maximum speed performance
for low-voltage applications
V
V
V
V
V
1.2
0
3.6
5.5
VCC
5.5
+85
20
VI
input voltage
VO
output voltage
output HIGH or LOW state
output 3-state
0
0
Tamb
tr, tf
ambient temperature
in free air
−40
0
°C
input rise and fall times
VCC = 1.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
ns/V
ns/V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+6.5
UNIT
VCC
IIK
V
input diode current
input voltage
VI < 0 V
note 1
−
−50
mA
V
VI
−0.5
−
+6.5
IOK
VO
output diode current
output voltage
VO > VCC or VO < 0 V
output HIGH or LOW state; note 1
output 3-state; note 1
VO = 0 V to VCC
±50
mA
V
−0.5
−0.5
−
VCC + 0.5
+6.5
V
IO
output source or sink current
VCC or GND current
storage temperature
power dissipation
±50
mA
mA
°C
mW
ICC, IGND
Tstg
note 2
−
±200
+150
1000
−65
−
Ptot
Tamb = −40 °C to +85 °C; note 3
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. All supply and ground pins connected externally to one voltage source.
3. Above 70 °C the value of Ptot derates linearly with 1.8 mW/K.
2004 May 19
6
Philips Semiconductors
Product specification
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
74LVCH32373A
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 °C to +85 °C; note 1
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
1.2
VCC
−
−
−
−
−
V
2.7 to 3.6
1.2
2.0
−
−
V
V
V
GND
0.8
2.7 to 3.6
−
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −100 µA
IO = −12 mA
IO = −18 mA
IO = −24 mA
2.7 to 3.6
2.7
V
V
V
V
CC − 0.2
VCC
−
−
−
−
−
V
V
V
V
CC − 0.5
CC − 0.6
CC − 0.8
3.0
−
3.0
−
VOL
LOW-level output voltage
input leakage current
VI = VIH or VIL
IO = 100 µA
IO = 12 mA
IO = 24 mA
2.7 to 3.6
2.7
−
−
−
−
GND
−
0.20
0.40
0.55
±5
V
V
3.0
−
V
ILI
VI = 5.5 V or GND;
note 2
3.6
±0.1
µA
IOZ
3-state output OFF-state
current
VI = VIH or VIL;
VO = 5.5 V or GND;
note 2
3.6
−
0.1
±5
µA
Ioff
power-off leakage supply
current
VI or VO = 5.5 V
0.0
−
−
−
0.1
0.1
5
±10
40
500
−
µA
µA
µA
µA
µA
µA
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0 A
3.6
∆ICC
IBH
additional quiescent supply VI = VCC − 0.6 V;
current per input pin
2.7 to 3.6
3.0
IO = 0 A
bushold LOW sustaining
current
VI = 0.8 V;
notes 3 and 4
75
−
IBHH
IBHLO
IBHHO
bushold HIGH sustaining
current
VI = 2.0 V;
notes 3 and 4
3.0
−75
500
−500
−
−
bushold LOW overdrive
current
notes 3 and 5
3.6
−
−
bushold HIGH overdrive
current
notes 3 and 5
3.6
−
−
Notes
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2. For bushold parts, the bushold circuit is switched off when VI > VCC allowing 5.5 V on the input pin.
3. For data inputs only, control inputs do not have a bushold circuit.
4. The specified sustaining current at the data inputs holds the input below the specified VI level.
5. The specified overdrive current at the data input forces the data input to the opposite logic input state.
2004 May 19
7
Philips Semiconductors
Product specification
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
74LVCH32373A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω.
CONDITIONS
WAVEFORMS VCC (V)
SYMBOL
PARAMETER
MIN.
TYP. MAX. UNIT
Tamb = −40 °C to +85 °C; note 1
tPHL/tPLH propagation delay nDn to nQn
propagation delay nLE to nQn
see Fig 4 and 8
see Fig 5 and 8
1.2
2.7
3.0 to 3.6 1.0
−
12
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5
−
4.9
3.0(2) 4.4
1.2
2.7
−
14
−
1.5
−
5.3
3.0 to 3.6 1.5
3.4(2) 4.8
tPZH/tPZL 3-state output enable time nOE to nQn see Fig 7 and 8
tPHZ/tPLZ 3-state output disable time nOE to nQn see Fig 7 and 8
1.2
2.7
−
18
−
1.5
−
5.7
3.0 to 3.6 1.0
3.5(2) 4.9
1.2
2.7
−
11
−
1.5
−
6.3
3.0 to 3.6 1.5
3.9(2) 5.4
tW
tsu
th
nLE pulse width HIGH
set-up time nDn to nLE
hold time nDn to nLE
skew
see Fig 5
see Fig 6
see Fig 6
1.2
2.7
−
−
−
3.0
−
−
3.0 to 3.6 3.0
2.0(2)
−
1.2
2.7
−
−
−
2.0
−
−
3.0 to 3.6 2.0
1.0(2)
−
1.2
2.7
−
−
−
0.9
−
−
3.0 to 3.6 0.9
3.0 to 3.6
−1.0(2)
−
tsk(0)
−
−
1.0
Notes
1. All typical values are measured at Tamb = 25 °C.
2. Measured at VCC = 3.3 V.
2004 May 19
8
Philips Semiconductors
Product specification
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
74LVCH32373A
AC WAVEFORMS
V
I
V
nDn input
M
GND
t
t
PLH
PHL
V
OH
V
M
nQn output
V
OL
mna494
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V;
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.4 Input (nDn) to output (nQn) propagation delay times.
V
I
nLE input
V
M
V
M
GND
t
W
t
t
PHL
PLH
V
OH
V
M
nQn output
V
OL
mna495
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V;
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5 Latch enable inputs (nLE) pulse width and the latch enable input to outputs (nQn) propagation delay times.
2004 May 19
9
Philips Semiconductors
Product specification
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
74LVCH32373A
V
I
V
M
nDn input
GND
t
t
h
h
t
t
su
su
V
I
V
M
nLE input
GND
mna496
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V.
Fig.6 Set-up and hold times for inputs (nDn) to inputs (nLE).
V
I
nOE input
V
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA478
VM = 1.5 V at VCC ≥ 2.7 V;
VX = VOL + 0.3 V at VCC ≥ 2.7 V;
VOL and VOH are typical output voltage drop that occur with
the output load.
VM = 0.5 × VCC at VCC < 2.7 V.
VX = VOL + 0.1 V at VCC < 2.7 V;
VY = VOH − 0.3 V at VCC ≥ 2.7 V;
VY = VOH − 0.1 V at VCC < 2.7 V.
Fig.7 3-state output enable and disable times.
10
2004 May 19
Philips Semiconductors
Product specification
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
74LVCH32373A
V
EXT
V
CC
R
L
V
I
V
O
PULSE
GENERATOR
D.U.T.
C
R
R
L
L
T
MNA616
VEXT
tPLH/tPHL tPZH/tPHZ tPZL/tPLZ
VCC
VI
VCC
CL
RL
1.2 V
2.7 V
50 pF
50 pF
50 pF
500 Ω(1) open
GND
GND
GND
2 × VCC
2 × VCC
2 × VCC
2.7 V
2.7 V
500 Ω
500 Ω
open
open
3.0 V to 3.6 V
Note
1. The circuit performs better when RL = 1000 Ω.
Definitions for test circuits:
R
L = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.8 Load circuitry for switching times.
2004 May 19
11
Philips Semiconductors
Product specification
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
74LVCH32373A
PACKAGE OUTLINE
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
B
A
D
ball A1
index area
A
2
A
E
A
1
detail X
e
1
C
1/2
e
y
y
v
M
M
C
C
A B
C
1
e
w
b
T
R
P
N
e
M
L
K
J
H
G
F
e
2
1/2
e
E
D
C
B
A
ball A1
index area
1
2
3
4
5
6
X
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
A
b
e
e
e
v
w
y
y
1
D
E
1
2
1
2
max.
0.41
0.31
1.2
0.9
0.51
0.41
5.6
5.4
13.6
13.4
mm
1.5
4
12
0.1
0.2
0.8
0.15
0.1
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
00-03-04
03-02-05
SOT536-1
2004 May 19
12
Philips Semiconductors
Product specification
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
74LVCH32373A
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 May 19
13
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/02/pp14
Date of release: 2004 May 19
Document order number: 9397 750 13227
相关型号：
74LVCH32374AEC,551
74LVCH32374A - 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state BGA 96-Pin
NXP
74LVCH32374AEC/G,5
74LVCH32374A - 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state BGA 96-Pin
NXP
74LVCH32374AEC/G:5
74LVCH32374A - 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state BGA 96-Pin
NXP
©2020 ICPDF网 联系我们和版权申明