74LVCH32374AEC [NXP]
32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state; 32位边沿触发D型触发器与5 V容限输入/输出;三态
| 型号： | 74LVCH32374AEC |
| 厂家： | 
NXP |
| 描述： | 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state |
| 文件： | 总16页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVCH32374A
32-bit edge-triggered D-type
flip-flop with 5 V tolerant
inputs/outputs; 3-state
Product specification
1999 Nov 24
File under Integrated Circuits, IC24
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop with
5 V tolerant inputs/outputs; 3-state
74LVCH32374A
FEATURES
DESCRIPTION
• 5 V tolerant inputs/outputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
The 74LVCH32374A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
The inputs can be driven from either 3.3 or 5 V devices. In
3-state operation, the outputs can handle 5 V. These
features allow the use of these devices in a mixed
3.3 or 5 V environment.
• MULTIBYTE flow-trough standard pin-out architecture
• Low inductance multiple power and ground pins for
minimum noise and ground bounce
• Direct interface with TTL levels
• Bus hold on data inputs
The 74LVCH32374A is a 32-bit edge-triggered flip-flop
featuring separate D-type inputs for each flip-flop and
3-state outputs for bus oriented applications. The
74LVCH32374A consists of 4 sections of eight
• Typical output ground bounce voltage:
VOLP < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
edge-triggered flip-flops. A clock (nCP) input and an
output enable input (nOE) are provided per 8-bit section.
• Typical output undershoot voltage:
VOHV > 2 V at VCC = 3.3 V and Tamb = 25 °C
The flip-flops will store the state of their individual D-inputs
that meet the set-up and hold time requirements on the
LOW-to-HIGH nCP transition.
• Power off disables outputs, permitting live insertion
• Packaged in plastic fine-pitch ball grid array package.
When input nOE is LOW, the contents of the flip-flops are
available at the outputs. When input nOE is HIGH, the
outputs go to the high-impedance OFF-state. Operation of
the nOE input does not affect the state of the flip-flops.
The 74LVCH32374A bus hold data input circuits eliminate
the need for external pull-up resistors to hold unused
inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns
SYMBOL
tPHL/tPLH
PARAMETER
propagation delay nCP to nQn
maximum clock frequency
input capacitance
CONDITIONS
TYPICAL
UNIT
CL = 50 pF; VCC = 3.3 V
3.8
ns
fmax
CI
150
5.0
30
MHz
pF
CPD
power dissipation capacitance per
buffer
VI = GND to VCC; note 1
pF
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ (CL × VCC2 × fo) = sum of the outputs.
1999 Nov 24
2
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop with
5 V tolerant inputs/outputs; 3-state
74LVCH32374A
FUNCTION TABLE
See note 1.
INPUTS
OUTPUTS
INTERNAL
FLIP-FLOPS
OPERATING MODE
nOE
nCP
nDn
nQn
Load and read register
L
L
↑
↑
↑
↑
l
L
H
L
L
H
Z
Z
h
l
Load register and disable
outputs
H
H
h
H
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH CP transition.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
PINS
PACKAGE MATERIAL
LFBGA96 plastic
CODE
SOT536-1
74LVCH32374AEC
−40 to +85 °C
96
PINNING
SYMBOL
DESCRIPTION
nDn
nCP
nQn
data inputs
clock inputs
flip-flop outputs
GND
nOE
VCC
ground (0 V)
output enable inputs (active LOW)
DC supply voltage
1999 Nov 24
3
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop with
5 V tolerant inputs/outputs; 3-state
74LVCH32374A
MNA497
6
5
4
3
2
1
1D
1D
1D
1D
1D
1D
1D
1D
2D
2D
2D
2D
2D
2D
2D
2D
3D
3D
3D
3D
3D
3D
3D
3D
4D
4D
4D
4D
4D
4D
4D
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
6
4D
0
2
4
6
0
2
4
6
0
2
4
6
0
2
4
7
1CP GND V
1OE GND V
GND GND V
GND GND V
GND 2CP 3CP GND V
GND 2OE 3OE GND V
GND GND V
GND GND V
GND 4CP
GND 4OE
CC
CC
CC
CC
CC
CC
CC
CC
1Q 1Q 1Q 1Q 2Q 2Q 2Q 2Q 3Q 3Q 3Q 3Q 4Q 4Q 4Q 4Q
0
2
4
6
0
2
4
6
0
2
4
6
0
2
4
7
1Q 1Q 1Q 1Q 2Q 2Q 2Q 2Q 3Q 3Q 3Q 3Q 4Q 4Q 4Q 4Q
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Fig.1 Pin configuration.
1D
2D
0
1Q
2Q
D
Q
D
Q
0
0
0
CP
FF 1
CP
FF 9
1CP
1OE
2CP
2OE
to 7 other channels
to 7 other channels
3D
0
4D
0
3Q
4Q
D
Q
D
Q
0
0
CP
CP
FF 17
FF 25
3CP
3OE
4CP
4OE
to 7 other channels
to 7 other channels
MNA498
Fig.2 Logic symbol.
4
1999 Nov 24
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop with
5 V tolerant inputs/outputs; 3-state
74LVCH32374A
V
handbook, halfpage
CC
data
input
to internal circuit
MNA473
Fig.3 Bus hold circuit.
1999 Nov 24
5
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop with
5 V tolerant inputs/outputs; 3-state
74LVCH32374A
RECOMMENDED OPERATING CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN. MAX.
VCC
maximum speed performance
low-voltage applications
2.7
1.2
0
3.6
3.6
5.5
VCC
5.5
+85
V
V
VI
DC input voltage
DC output voltage
V
VO
HIGH or LOW state
3-state
0
V
0
V
Tamb
operating ambient temperature
see DC and AC characteristics per
device
−40
°C
tr,tf (∆t/∆f) input rise and fall times
VCC = 1.2 to 2.7 V
0
0
20
10
ns/V
VCC = 2.7 to 3.6 V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN.
MAX.
UNIT
VCC
VI
−0.5
−0.5
−
+6.5
+6.5
−50
±50
V
DC input voltage
note 1
VI < 0
V
IIK
DC input diode current
DC output diode current
DC output voltage
mA
mA
V
IOK
VO
VO > VCC or VO < 0; note 1
HIGH or LOW state; note 1
3-state; note 1
−
−0.5
−0.5
−
VCC + 0.5
+6.5
V
IO
DC output source or sink current
VO = 0 to VCC
±50
mA
mA
°C
mW
ICC, IGND DC VCC or GND current
−
±100
Tstg
PD
storage temperature
−65
−
+150
1000
power dissipation per package
temperature range
−40 to +85 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded, if the input and output current ratings are observed.
2. Above 70 °C the value of PD derates linearly with 1.8 mW/K.
1999 Nov 24
6
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop with
5 V tolerant inputs/outputs; 3-state
74LVCH32374A
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
−40 to +85
TYP.(1) MAX.
UNIT
OTHER
VCC (V)
MIN.
VCC
2.7 to 3.6 2.0
1.2
2.7 to 3.6 −
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
1.2
−
−
−
−
−
V
V
V
V
−
−
GND
0.8
VOH
VI = VIH or VIL
IO = −12 mA
IO = −100 µA
IO = −18 mA
2.7
3.0
3.0
3.0
VCC − 0.5 −
VCC − 0.2 VCC
VCC − 0.6 −
VCC − 0.8 −
−
−
−
−
V
V
V
V
IO = −24 mA
VOL
LOW-level output voltage
input leakage current
VI = VIH or VIL
IO = 12 mA
2.7
3.0
3.0
3.6
3.6
−
−
−
−
−
−
0.40
0.20
0.55
±5
V
IO = 100 µA
−
V
IO = 24 mA
−
V
II
VI = 5.5 V or GND; note 2
±0.1
0.1
µA
µA
IOZ
3-state output OFF-state
current
VI = VIH or VIL;
VO = 5.5 V or GND
±5
Ioff
power off leakage supply
current
VI or VO = 5.5 V
0.0
−
−
0.1
±10
µA
ICC
quiescent supply current
VI = VCC or GND; IO = 0
3.6
0.1
5
40
µA
µA
∆ICC
additional quiescent supply
current per input pin
VI = VCC − 0.6 V; IO = 0
2.7 to 3.6 −
500
IBHL
bus hold LOW sustaining
current
VI = 0.8 V; notes 3, 4 and 5 3.0
VI = 2.0 V; notes 3, 4 and 5 3.0
75
−
−
−
−
−
−
−
−
µA
µA
µA
µA
IBHH
bus hold HIGH sustaining
current
−75
IBHLO
IBHHO
bus hold LOW overdrive
current
notes 3, 4 and 6
notes 3, 4 and 6
3.6
3.6
500
bus hold HIGH overdrive
current
−500
Notes
1. All typical values are at VCC = 3.3 V and Tamb = 25 °C.
2. For bus hold parts the bus hold circuit is switched off when VI exceeds VCC allowing 5.5 V on the input terminal.
3. Valid for data inputs of bus hold parts (LVCH32-A) only.
4. For data inputs only; control inputs do not have a bus hold circuit.
5. The specified sustaining current at the data input holds the input below the specified VI level.
6. The specified overdrive current at the data input forces the data input to the opposite logic input level.
1999 Nov 24
7
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop with
5 V tolerant inputs/outputs; 3-state
74LVCH32374A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω.
TEST CONDITIONS
T
amb = −40 to +85 °C
SYMBOL
tPHL/tPLH
PARAMETER
UNIT
WAVEFORMS
VCC (V)
2.7
3.0 to 3.6 1.5
2.7 1.5
3.0 to 3.6 1.5
2.7 1.5
3.0 to 3.6 1.5
2.7 3.0
3.0 to 3.6 3.0
2.7 2.0
3.0 to 3.6 1.9
2.7 1.5
3.0 to 3.6 +1.1
2.7 80
MIN.
TYP.(1)
MAX.
6.4
propagation delay
nCP to nQn
see Figs 4 and 7
1.5
−
ns
3.8
−
5.4
6.6
5.6
6.5
5.5
−
ns
tPZH/tPZL
3-state output enable time
nOE to nQn
see Figs 6 and 7
ns
3.6
−
ns
tPHZ/tPLZ
3-state output disable time see Figs 6 and 7
nOE to nQn
ns
3.9
−
ns
tW
nCP pulse width HIGH
set-up time nDn to nCP
hold time nDn to nCP
maximum clock frequency
see Figs 4 and 7
see Figs 5 and 7
see Figs 5 and 7
see Figs 4 and 7
ns
1.5
−
−
ns
tsu
−
ns
0.3
−
−
ns
th
−
ns
−0.3
−
−
ns
fmax
−
MHz
MHz
3.0 to 3.6 100
−
−
Note
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
AC WAVEFORMS
1/f
max
V
I
nCP input
V
V
M
t
M
GND
t
W
t
PHL
PLH
V
OH
V
nQ output
n
M
MNA499
V
OL
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.4 Clock (nCP) to output (nQn) propagation delays, the clock pulse width and the maximum clock frequency.
1999 Nov 24
8
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop with
5 V tolerant inputs/outputs; 3-state
74LVCH32374A
V
I
V
t
nCP input
M
GND
t
su
su
t
t
h
h
V
I
V
nD input
n
M
GND
V
OH
V
nQ output
n
M
V
OL
MNA500
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5 Set-up and hold times for inputs (nDn) to inputs (nCP).
V
I
nOE input
V
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA478
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V.
VX = VOL + 0.3 V at VCC ≥ 2.7 V;
VX = VOL + 0.1 V at VCC < 2.7 V.
VY = VOH − 0.3 V at VCC ≥ 2.7 V;
VY = VOH − 0.1 V at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.6 3-state output enable and disable times.
1999 Nov 24
9
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop with
5 V tolerant inputs/outputs; 3-state
74LVCH32374A
S1
2 × V
CC
open
GND
V
CC
R
500 Ω
L
V
V
O
I
PULSE
D.U.T.
GENERATOR
C
50 pF
R
L
500 Ω
L
R
T
MNA479
TEST
S1
open
Definitions for test circuit:
RL = load resistor.
VCC
VI
tPLH/tPHL
CL = load capacitance including jig and probe capacitance.
T = termination resistance should be equal to the output impedance Zo
of the pulse generator.
<2.7 V
VCC
t
PLZ/tPZL
2 × VCC
R
2.7 to 3.6 V 2.7 V
tPHZ/tPZH
GND
Fig.7 Test circuitry for switching times.
1999 Nov 24
10
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop with
5 V tolerant inputs/outputs; 3-state
74LVCH32374A
PACKAGE OUTLINE
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
D
ball A1
index area
A
2
A
E
A
1
detail X
A
b
w M
Z
y
e
v
A
D
Z
E
e
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
X
1
2
3
4
5 6
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
A
b
e
y
D
E
v
w
Z
Z
E
0
5
10 mm
1
2
D
max.
0.41
0.31
1.2
0.9
0.51
0.41
5.6
5.4
13.6
13.4
0.93 0.93
0.58 0.58
scale
mm
1.5
0.1
0.8
0.2
0.15
REFERENCES
JEDEC
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
EIAJ
98-11-25
99-06-03
SOT536-1
1999 Nov 24
11
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop with
5 V tolerant inputs/outputs; 3-state
74LVCH32374A
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Nov 24
12
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop with
5 V tolerant inputs/outputs; 3-state
74LVCH32374A
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
BGA, LFBGA, SQFP, TFBGA
WAVE
not suitable
REFLOW(1)
suitable
suitable
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
PLCC(3), SO, SOJ
not suitable(2)
suitable
LQFP, QFP, TQFP
not recommended(3)(4) suitable
not recommended(5)
suitable
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Nov 24
13
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop with
5 V tolerant inputs/outputs; 3-state
74LVCH32374A
NOTES
1999 Nov 24
14
Philips Semiconductors
Product specification
32-bit edge-triggered D-type flip-flop with
5 V tolerant inputs/outputs; 3-state
74LVCH32374A
NOTES
1999 Nov 24
15
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Pakistan: see Singapore
Belgium: see The Netherlands
Brazil: see South America
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Colombia: see South America
Czech Republic: see Austria
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Middle East: see Italy
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
68
SCA
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245004/01/pp16
Date of release: 1999 Nov 24
Document order number: 9397 750 06467
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