933372760653 [NXP]
4000/14000/40000 SERIES, TRIPLE 3-INPUT NAND GATE, PDSO14, PLASTIC, SOT-108-1, SO-14;
| 型号： | 933372760653 |
| 厂家： | 
NXP |
| 描述： | 4000/14000/40000 SERIES, TRIPLE 3-INPUT NAND GATE, PDSO14, PLASTIC, SOT-108-1, SO-14 输入元件 光电二极管 逻辑集成电路 |
| 文件： | 总3页 (文件大小：25K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4023B
gates
Triple 3-input NAND gate
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4023B
gates
Triple 3-input NAND gate
DESCRIPTION
The HEF4023B provides the positive triple 3-input NAND
function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.
Fig.2 Pinning diagram.
HEF4023BP(N):
HEF4023BD(F):
HEF4023BT(D):
14-lead DIL; plastic
(SOT27-1)
Fig.1 Functional diagram.
14-lead DIL; ceramic (cerdip)
(SOT73)
14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4023B
gates
Triple 3-input NAND gate
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
TYP.
MAX.
Propagation delays
In → On
HIGH to LOW
5
65
25
15
65
30
25
60
30
20
60
30
20
135
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
38 ns + (0,55 ns/pF) CL
14 ns + (0,23 ns/pF) CL
7 ns + (0,16 ns/pF) CL
38 ns + (0,55 ns/pF) CL
19 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10
15
5
tPHL
30
130
60
LOW to HIGH
10
15
5
tPLH
tTHL
tTLH
45
Output transition times
HIGH to LOW
120
60
10
15
5
40
120
60
LOW to HIGH
10
15
40
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
1200 fi + ∑ (foCL) × VDD
where
2
5500 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
16 400 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3
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