933794800602 [NXP]
IC F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16, 0.300 INCH, PLASTIC, SOT-38-4, DIP-16, Counter;
| 型号： | 933794800602 |
| 厂家： | 
NXP |
| 描述： | IC F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16, 0.300 INCH, PLASTIC, SOT-38-4, DIP-16, Counter 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总14页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F191
Up/down binary counter with reset and
ripple clock
Product specification
IC15 Data Handbook
1995 Jul 17
Philips
Semiconductors
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
FEATURES
PIN CONFIGURATION
• High speed –125MHz typical f
MAX
1
2
3
4
5
16
15
D
Q
V
CC
1
• Synchronous, reversible counting
• 4-Bit binary
D
1
0
0
14 CP
13 RC
12 TC
11 PL
Q
• Asynchronous parallel load capability
• Cascadable without external logic
• Single up/down control input
CE
U/D
6
7
8
Q
2
10
9
Q
3
D
D
2
3
DESCRIPTION
GND
The 74F191 is a 4-bit binary counter. It contains four edge-triggered
master/slave flip-flops with internal gating and steering logic to
provide asynchronous preset and synchronous count-up and
count-down operations.
SF00729
Asynchronous parallel load capability permits the counter to be
preset to any desired number. Information present on the parallel
TYPICAL
SUPPLY CURRENT
(TOTAL)
TYPE
TYPICAL f
MAX
data inputs (D - D ) is loaded into the counter and appears on the
0
3
outputs when the Parallel Load (PL) input is Low. This operation
overrides the counting function. Counting is inhibited by a High level
on the count enable (CE) input. When CE is Low, internal state
changes are initiated. Overflow/underflow indications are provided
by two types of outputs, the Terminal Count (TC) and Ripple Clock
(RC).
74F191
125MHz
40mA
ORDERING INFORMATION
COMMERCIAL RANGE
= 5V ±10%,
V
CC
DESCRIPTION
PKG DWG #
The TC output is normally Low and goes High when: 1) the count
reaches zero in the countdown mode or 2) reaches “15” in the count
up mode. The TC output will remain High until a state change
occurs, either by counting or presetting, or until U/D is changed. TC
output should not be used as a clock signal because it is subject to
decoding spikes. The TC signal is used internally to enable the RC
output. When TC is High and CE is Low, the RC follows the clock
pulse. The RC output essentially duplicates the Low clock pulse
width, although delayed in time by two gate delays.
T
amb
= 0°C to +70°C
16-pin plastic DIP
16-pin plastic SO
N74F191N
SOT38-4
N74F191D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
PINS
DESCRIPTION
D - D
Data inputs
1.0/1.0
1.0/3.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
20µA/0.6mA
20µA/1.8mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
1.0mA/20mA
1.0mA/20mA
0
3
CE
CP
PL
Count enable input (active Low)
Clock pulse input (active rising edge)
Asynchronous parallel load control input (active Low)
Up/down count control input
Flip-flop outputs
U/D
Q - Q
0
3
RC
TC
Ripple clock output (active low)
Terminal count output
50/33
50/33
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
2
1995 Jul 17
853–0352 15459
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
15
D
1
10
D
9
4
5
EN1
CTR DIV 10
12
13
M2[DOWN]
M3[UP]
2(CT=0)Z6
3(CT=15)Z6
D
D
0
1
2
3
4
CE
14
11
1,2–/1,3+
6, 4, 1
13
12
5
U/D
CP
PL
RC
TC
G4
C5 [LOAD]
14
11
15
1
3
2
6
7
5D
[1]
[2]
[4]
[8]
+ –
Q
Q
Q
Q
3
0
1
2
10
9
3
2
6
7
V
=Pin 16
CC
GND=Pin 8
SF00730
SF00731
LOGIC DIAGRAM
D
D
D
D
3
0
1
2
15
1
10
9
PL
11
5
U/D
4
CE
14
CP
J
K
J
K
R
J
K
J
K
CP
CP
CP
CP
S
R
S
S
R
S
R
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
13
12
3
2
6
7
Q
0
Q
1
Q
2
Q
3
RC TC
V
= Pin 16
CC
GND = Pin 8
SF00732
3
1995 Jul 17
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
MODE SELECT — FUNCTION TABLE
INPUTS
CE
OUTPUTS
OPERATING MODE
PL
U/D
CP
D
Q
n
n
L
L
X
X
X
X
X
X
L
L
H
Parallel load
H
X
X
X
H
H
H
L
H
X
l
l
↑
↑
Count up
Count down
No change
Count up
Count down
Hold (do nothing)
H
X
TC AND RC FUNCTION TABLE
INPUTS
TERMINAL COUNT STATE
OUTPUTS
U/D
CE
CP
X
Q
Q
Q
Q
3
TC
RC
H
0
1
2
H
H
H
H
H
H
L
L
L
H
L
X
H
H
H
H
H
H
H
H
H
H
H
L
H
X
X
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
H
H = High voltage level steady state
= Low voltage level steady state
L
X = Don’t care
= Low pulse
↑
l
= Low-to-High clock transition
= Low voltage level one set-up time prior to the Low-to-High clock transition
4
1995 Jul 17
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
APPLICATIONS
DIRECTION CONTROL
U/D
CE
CP
RC
U/D
CE
CP
RC
U/D
CE
CP
RC
ENABLE
CLOCK
a. N-Stage Counter Using Ripple Clock
DIRECTION CONTROL
U/D
CE
CP
RC
U/D
CE
CP
RC
U/D
CE
CP
RC
ENABLE
CLOCK
b. Synchronous N-Stage Counter with Common Clock Using Ripple/Clock
DIRECTION CONTROL
ENABLE
U/D
CE
CP
U/D
CE
CP
U/D
CE
CP
*
*
TC
TC
TC
CLOCK
* = Carry Gate
c. Synchronous N-Stage Counter with Common Clock and Terminal Count
SF00733
Figure 1.
The 74F191 simplifies the design of multi-stage counters, as
indicated in Figure 1, each RC output is used as the clock input for
the next higher stage. When the clock source has a limited drive
capability this configuration is particularly advantageous, since the
clock source drives only the first stage. It is only necessary to inhibit
the first stage to prevent counting in all stages, since a High signal
on CE inhibits the RC output pulse as indicated in the Mode Select
Table. The timing skew between state changes in the first and last
stages is represented by the cumulative delay of the clock as it
ripples through the preceding stages. This is a disadvantage of the
configuration in some applications.
ripple fashion and all clock inputs are driven in parallel. The Low
state duration of the clock in this configuration must be long enough
to allow the negative-going edge of the RC signal to ripple through
to the last stage before the clock goes High. Since the RC output of
any package goes High shortly after its clock input goes High, there
is no such restriction on the High state duration of the clock.
In Figure 1c, the configuration shown avoids ripple delays and their
associated restrictions. The combined TC signals from all the
preceding stages forms the CE input signal for a given stage. An
enable signal must also be included in each carry gate in order to
inhibit counting. The TC output of a given stage is not affected by its
own CE, therefore, the simple inhibit scheme of Figure 1a and 1b
does not apply.
Figure 1b shows a method of causing state changes to occur
simultaneously in all stages. The RC output signals propagate in
5
1995 Jul 17
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
V
Supply voltage
Input voltage
Input current
–0.5 to +7.0
–0.5 to +7.0
–30 to +5.0
V
V
CC
IN
I
IN
mA
V
V
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature
–0.5 to +V
40
OUT
OUT
CC
I
mA
o
T
amb
0 to +70
C
o
T
stg
–65 to +150
C
RECOMMENDED OPERATING CONDITIONS
LIMITS
Nom
SYMBOL
PARAMETER
UNIT
Max
Min
4.5
2.0
V
CC
V
IH
V
IL
Supply voltage
5.0
5.5
V
V
High-level input voltage
Low-level input voltage
Input clamp current
0.8
–18
–1
V
I
I
I
mA
mA
mA
IK
High-level output current
Low-level output current
Operating free-air temperature range
OH
OL
20
o
T
amb
0
70
C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
High-level output voltage
Low-level output voltage
TEST CONDITIONS
UNIT
2
Min
2.5
2.7
Typ
Max
±10%V
V
V
CC
V
= Min, V = Max,
IL
CC
V
OH
I
= Max, V = Min
OH
IH
±5%V
3.4
0.30
0.30
–0.73
CC
±10%V
±5%V
0.50
0.50
–1.2
100
20
V
CC
V
CC
= Min, V = Max,
IL
V
V
OL
I
OL
= Max, V = Min
IH
V
CC
Input clamp voltage
V
CC
V
CC
V
CC
= Min, I = I
IK
V
IK
I
I
I
I
Input current at maximum input voltage
High-level input current
= Max, V = 7.0V
µA
µA
mA
mA
mA
mA
I
I
= Max, V = 2.7V
IH
IL
I
Low-level input current
CE
–1.8
–0.6
–150
55
V
CC
= Max, V = 0.5V
I
Others
3
I
I
Short-circuit output current
V
V
= Max
= Max
–60
OS
CC
4
Supply current (total)
40
CC
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4. Measure I all inputs grounded and all outputs open.
CC
6
1995 Jul 17
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
AC ELECTRICAL CHARACTERISTICS
LIMITS
T = +25°C
amb
T = 0°C to +70°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
V
CC
= +5.0V
V
CC
= +5.0V ± 10%
UNIT
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
Min
Typ
Max
Min
Max
Maximum clock frequency
to Qn outputs
f
f
Waveform 1
Waveform 1
Waveform 1
Waveform 1
Waveform 2
Waveform 2
Waveform 2
Waveform 4
Waveform 3
100
85
125
90
75
MHz
MHz
MAX
Maximum clock frequency
to RC outputs
95
MAX
t
t
Propagation delay
2.5
5.0
4.5
7.5
8.0
11.5
2.0
5.0
8.5
12.0
ns
ns
PLH
PHL
CP to Q
n
t
t
Propagation delay
CP to TC
6.5
6.0
9.0
8.0
12.5
11.0
6.0
6.0
13.0
12.0
ns
ns
PLH
PHL
t
t
Propagation delay
CP to RC
2.5
3.0
4.5
5.0
7.5
7.5
2.0
2.5
8.0
8.0
ns
ns
PLH
PHL
t
t
Propagation delay
CE to RC
2.0
3.0
4.0
5.0
7.0
7.5
2.0
3.0
7.5
8.0
ns
ns
PLH
PHL
t
t
Propagation delay
U/D to RC
8.0
4.5
11.0
7.5
16.0
10.5
8.0
4.0
17.0
11.0
ns
ns
PLH
PHL
t
t
Propagation delay
U/D to TC
4.0
3.0
6.5
6.0
9.5
9.5
3.0
3.0
10.5
10.0
ns
ns
PLH
PHL
t
t
Propagation delay
2.0
6.5
4.0
9.0
7.0
12.0
1.5
6.5
7.5
13.0
ns
ns
PLH
PHL
D to Q
n
n
t
t
Propagation delay
D to TC
n
Waveform 3
Waveform 4
5.5
6.5
9.5
9.5
13.0
13.0
5.0
6.0
14.0
14.0
ns
ns
PLH
PHL
t
t
Propagation delay
D to RC
n
Waveform 3
Waveform 4
6.0
6.0
14.0
11.0
18.0
13.5
6.0
6.0
19.5
15.0
ns
ns
PLH
PHL
t
t
Propagation delay
4.5
5.5
6.5
8.0
9.5
11.5
4.0
5.0
10.5
12.0
ns
ns
PLH
PHL
Waveform 5
Waveform 5
Waveform 5
PL to Q
n
t
t
Propagation delay
PL to TC
5.5
6.0
8.5
10.5
12.0
13.5
5.5
6.0
13.0
14.5
ns
ns
PLH
PHL
t
t
Propagation delay
PL to RC
8.5
7.5
16.0
10.0
18.5
13.0
8.5
7.0
21.0
13.5
ns
ns
PLH
PHL
7
1995 Jul 17
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
AC SETUP REQUIREMENTS
LIMITS
T = +25°C
amb
T
amb
= 0°C to +70°C
SYMBOL
PARAMETER
TEST CONDITIONS
V
CC
= +5.0V
V
CC
= +5.0V ± 10%
UNIT
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
Min
Typ
Max
Min
Max
t (H)
t (L)
s
Setup time, High or Low
D to PL
n
4.5
4.5
5.0
5.0
ns
ns
s
Waveform 6
Waveform 6
t (H)
Hold time, High or Low
D to PL
n
2.0
2.0
2.0
2.0
ns
ns
h
t (L)
h
t (L)
Setup time, Low CE to CP
Waveform 6
Waveform 6
10.0
0
10.0
0
ns
ns
s
t (L)
h
Hold time, Low CE to CP
t (H)
t (L)
s
Setup time, High or Low
U/D to CP
12.0
12.0
12.0
12.0
ns
ns
s
Waveform 6
Waveform 6
Waveform 1
t (H)
Hold time, High or Low
U/D to CP
0
0
0
0
ns
ns
h
t (L)
h
t (H)
3.5
6.0
3.5
6.0
ns
ns
w
CP Pulse width, High or Low
t (L)
w
t (L)
PL Pulse width, Low
Waveform 5
Waveform 5
6.0
6.0
6.0
6.0
ns
ns
w
t
Recovery time, PL to CP
rec
8
1995 Jul 17
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
AC WAVEFORMS
NOTE: For all waveforms, V = 1.5V
M
1/f
MAX
CE, CP
U/D
t (L)
W
V
V
M
M
V
t
V
M
CP
M
t
(H)
W
PLH
t
PHL
t
t
PLH
PHL
RC
V
V
M
M
V
RC, Q , TC
n
V
M
M
SF00734
SF00735
Waveform 2. Propagation Delay, Clock, Clock Enable or
Up/Down to Ripple Clock Output
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency.
D
V
t
V
M
U/D, D
n
n
M
V
V
M
M
t
t
t
PLH
PLH
PHL
PHL
RC, TC, Q
V
V
M
RC, TC
V
V
M
n
M
M
SF00736
SF00737
Waveform 4. Propagation Delay, Inverting Path
Waveform 3. Propagation Delay, Non-Inverting Path
CE,
PL
V
V
M
M
V
M
D
n
U/D
t (L)
W
t
REC
t (H)
S
t (L)
S
t (H)
h
t (L)
h
V
CP
M
PL
V
V
M
M
t
t
PLH
TC, Q
n
n
V
V
M
M
CP
V
V
M
M
PHL
The shaded areas indicate when the input is permitted
to change for predictable output performance.
RC, Q
SF00739
SF00738
Waveform 6. Data Set Up and Hold Times
Waveform 5. Parallel Load Pulse Width, Parallel Load to Output
Delay and Parallel Load to Clock Recovery Time
9
1995 Jul 17
Philips Semiconductors
Product specification
Up/Down binary counter with reset and ripple clock
74F191
TEST CIRCUIT AND WAVEFORM
t
w
AMP (V)
90%
V
CC
90%
NEGATIVE
V
V
M
M
PULSE
10%
10%
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
Termination resistance should be equal to Z
pulse generators.
family
V
rep. rate
t
t
t
amplitude
3.0V
M
w
TLH
THL
of
OUT
2.5ns 2.5ns
74F
1.5V
1MHz
500ns
SF00006
10
1995 Jul 17
Philips Semiconductors
Product specification
Up/down binary counter with reset and ripple clock
74F191
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
11
1995 Jul 17
Philips Semiconductors
Product specification
Up/down binary counter with reset and ripple clock
74F191
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
12
1995 Jul 17
Philips Semiconductors
Product specification
Up/down binary counter with reset and ripple clock
74F191
NOTES
13
1995 Jul 17
Philips Semiconductors
Product specification
Up/down binary counter with reset and ripple clock
74F191
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
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Date of release: 10-98
9397-750-05093
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Philips
Semiconductors
相关型号：
933794820602
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