933929390116 [NXP]
TRANSISTOR 40 V, N-CHANNEL, Si, SMALL SIGNAL, JFET, TO-92, PLASTIC, SPT, SC-43, 3 PIN, FET General Purpose Small Signal;
| 型号： | 933929390116 |
| 厂家： | 
NXP |
| 描述： | TRANSISTOR 40 V, N-CHANNEL, Si, SMALL SIGNAL, JFET, TO-92, PLASTIC, SPT, SC-43, 3 PIN, FET General Purpose Small Signal 开关 晶体管 |
| 文件： | 总6页 (文件大小：36K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
PN4391 to 4393
N-channel silicon field-effect
transistors
April 1989
Product specification
File under Discrete Semiconductors, SC07
Philips Semiconductors
Product specification
N-channel silicon field-effect transistors
PN4391 to 4393
DESCRIPTION
Symmetrical silicon n-channel
junction FETs in plastic TO-92
envelopes. They are intended for
applications such as analog switches,
choppers, commutators etc.
PINNING
1
handbook, halfpage
2
3
d
1
2
3
= gate
g
s
= source
= drain
MAM042
Note: Drain and source are
interchangeable.
Fig.1 Simplified outline and symbol, TO-92.
QUICK REFERENCE DATA
Drain-source voltage
Total power dissipation
up to Tamb = 25 °C
± VDS
max.
max.
40
V
Ptot
360
mW
PN4391 PN4392 PN4393
Drain current
VDS = 20 V; VGS = 0
IDSS
min.
50
25
5 mA
Gate-source cut-off voltage
min.
4
2
5
0.5 V
V
DS = 20 V; ID = 1 nA
−VGS off
max.
10
3 V
Drain-source on-resistance
ID = 1 mA; VGS = 0
RDS on
max.
30
60
100 Ω
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Drain-source voltage
Gate-source voltage
Gate-drain voltage
± VDS
−VGSO
−VGDO
IG
max.
max.
max.
max.
40
40
40
50
V
V
V
Forward gate current (DC)
Total power dissipation
up to Tamb = 25 °C
mA
Ptot
Tstg
Tj
max.
max.
360
mW
°C
Storage temperature range
Junction temperature
−65 to+150
150
°C
April 1989
2
Philips Semiconductors
Product specification
N-channel silicon field-effect transistors
PN4391 to 4393
THERMAL RESISTANCE
From junction to ambient in free air
Rth j-a
=
350
K/W
STATIC CHARACTERISTICS
Tj = 25 °C unless otherwise specified
PN4391 PN4392 PN4393
Reverse gate current
−VGS = 20 V; VDS = 0
−VGS = 20 V; VDS = 0
−IGSS
max.
max.
1.0
200
1.0
1.0
1.0 nA
200 nA
Tamb = 100 °C
−IGSS
200
Drain cut-off current
−VGS = 12 V
IDSX
IDSX
IDSX
max.
max.
max.
nA
nA
−VGS = 7 V
−VGS = 5 V
VDS = 20 V
1.0
1.0 nA
−VGS = 12 V
−VGS = 7 V
−VGS = 5 V
IDSX
IDSX
IDSX
max.
max.
max.
200
nA
nA
VDS = 20 V;
Tamb = 100 °C
200
200 nA
Drain saturation current
min.
50
25
5 mA
V
DS = 20 V; VGS = 0
IDSS
max.
150
100
60 mA
Gate-source breakdown voltage
−IG = 1 µA; VDS = 0
−V(BR)GSS
−VGS off
RDS on
min.
40
40
40 V
Gate-source cut-off voltage
min.
4.0
10
2.0
5.0
0.5 V
3.0 V
V
DS = 20 V; ID = 1 nA
max.
Drain-source on-resistance
ID = 1 mA; VGS = 0
max.
30
60
100 Ω
Drain-source on-voltage
VGS = 0; ID = 12 mA
VDS on
VDS on
VDS on
max.
max.
max.
0.4
V
V
VGS = 0; ID = 6 mA
GS = 0; ID = 3 mA
0.4
V
0.4 V
April 1989
3
Philips Semiconductors
Product specification
N-channel silicon field-effect transistors
PN4391 to 4393
DYNAMIC CHARACTERISTICS
Tj = 25 °C unless otherwise specified
PN4391 PN4392 PN4393
Drain-source on-resistance
V
DS = 0 V; VGS = 0; f = 1 kHz; Ta = 25 °C
RDS on
max.
max.
30
16
5
60
16
100 Ω
Input capacitance
VDS = 20 V; VGS = 0; f = 1 MHz; Ta = 25 °C
Feedback capacitance
Ciss
16 pF
V
DS = 0; −VGS = 12 V
VDS = 0; −VGS = 7 V
DS = 0; −VGS = 5 V
Crss
Crss
Crss
max.
max.
max.
pF
pF
f = 1 MHz
5
V
5 pF
Switching times
test conditions
VDD = 10 V; VGS = 0 to VGS off
ID
=
12
12
750
5
6.0
7.0
1550
5
3.0 mA
5.0 V
−VGS off
=
RL
tr
=
3150 Ω
5 ns
Rise time
max.
max.
max.
max.
Turn-on time
Fall time
ton
tf
15
15
20
15
15 ns
30 ns
50 ns
20
Turn-off time
toff
35
V
V
= 0 V
GS
10%
90%
1 µF
k, halfpage
50 Ω
10 µF
V
DD
i
10 nF
R
L
−V
GS off
SAMPLING
SCOPE
50 Ω
t
t
on
off
DUT
t
t
f
r
50 Ω
90%
10%
V
o
MBK289
MBK288
Fig.2 Switching times test circuit.
Fig.3 Input and output waveforms.
April 1989
4
Philips Semiconductors
Product specification
N-channel silicon field-effect transistors
PN4391 to 4393
PACKAGE OUTLINE
Plastic single-ended leaded (through hole) package; 3 leads
SOT54
c
E
d
A
L
b
1
2
e
1
e
D
3
b
1
L
1
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
UNIT
A
b
b
c
D
d
E
e
e
L
L
1
1
1
5.2
5.0
0.48
0.40
0.66
0.56
0.45
0.40
4.8
4.4
1.7
1.4
4.2
3.6
14.5
12.7
mm
2.54
1.27
2.5
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-02-28
SOT54
TO-92
SC-43
April 1989
5
Philips Semiconductors
Product specification
N-channel silicon field-effect transistors
PN4391 to 4393
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
Short-form specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
The data in this specification is extracted from a full data sheet with the same type
number and title. For detailed information see the relevant data sheet or data handbook.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
April 1989
6
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