934054300118 [NXP]

TRANSISTOR 75 A, 55 V, 0.008 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power;


型号：	934054300118
厂家：	NXP
描述：	TRANSISTOR 75 A, 55 V, 0.008 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power
文件：	总11页 (文件大小：108K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP125N06LT, PHB125N06LT

FEATURES

SYMBOL

QUICK REFERENCE DATA

• ’Trench’ technology

• Very low on-state resistance

• Fast switching

• Stable off-state characteristics

• High thermal cycling performance

• Low thermal resistance

V_DSS= 55 V

I_D= 75 A

_DS(ON)≤ 8 mΩ (V_GS= 5 V)

_DS(ON)≤ 7 mΩ (V_GS= 10 V)

GENERAL DESCRIPTION

N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.

The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching

applications.

The PHP125N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB125N06LT is supplied in the SOT404 surface mounting package.

PINNING

SOT78 (TO220AB)

SOT404

DESCRIPTION

tab

gate

drain ¹

source

drain

tab

1 2 3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DSS

V_DGR

V_GS

I_D

Drain-source voltage

Drain-gate voltage

Gate-source voltage

Continuous drain current

T_j= 25 ˚C to 175˚C

T_j= 25 ˚C to 175˚C; R_GS= 20 kΩ

± 13

˚C

T_mb= 25 ˚C

T_mb= 100 ˚C

T_mb= 25 ˚C

I_DM

P_D

T_j, T_stg

Pulsed drain current

Total power dissipation

Operating junction and

storage temperature

240

250

175

- 55

March 1998

Rev 1.400

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP125N06LT, PHB125N06LT

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R_{th j-mb}

Thermal resistance junction

to mounting base

0.6

K/W

R_{th j-a}

Thermal resistance junction SOT78 package, in free air

to ambient SOT404 package, pcb mounted, minimum

K/W

footprint

ESD LIMITING VALUE

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_C

Electrostatic discharge

capacitor voltage, all pins

Human body model (100 pF, 1.5 kΩ)

ELECTRICAL CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

V_(BR)DSS

V_(BR)GSS

V_GS(TO)

Drain-source breakdown

voltage

Gate-source breakdown

voltage

V_GS= 0 V; I_D= 0.25 mA;

T_j= -55˚C

I_G= ±1 mA;

Gate threshold voltage

V_DS= V_GS; I_D= 1 mA

1.0

0.5

1.5

6.5

4.9

0.02

2.0

2.3

500

T_j= 175˚C

T_j= -55˚C

R_DS(ON)

Drain-source on-state

resistance

V_GS= 5 V; I_D= 25 A

V_GS= 10 V; I_D= 25 A

mΩ

µA

T_j= 175˚C

g_fs

I_GSS

Forward transconductance

Gate source leakage current V_GS= ±5 V; V_DS= 0 V

V_DS= 25 V; I_D= 25 A

T_j= 175˚C

I_DSS

Zero gate voltage drain

current

V_DS= 55 V; V_GS= 0 V;

0.05

Q_g(tot)

Q_gs

Q_gd

Total gate charge

Gate-source charge

Gate-drain (Miller) charge

I_D= 50 A; V_DD= 44 V; V_GS= 5 V

t_{d on}

t_r

t_{d off}

t_f

Turn-on delay time

Turn-on rise time

Turn-off delay time

Turn-off fall time

V_DD= 30 V; I_D= 25 A;

V_GS= 5 V; R_G= 10 Ω

Resistive load

120

225

100

170

300

135

L_d

Internal drain inductance

Measured from tab to centre of die

Measured from drain lead to centre of die

(SOT78 package only)

3.5

4.5

L_s

Internal source inductance

Measured from source lead to source

bond pad

7.5

C_iss

C_oss

C_rss

Input capacitance

Output capacitance

Feedback capacitance

V_GS= 0 V; V_DS= 25 V; f = 1 MHz

5200 6900

840 1000

350

480

March 1998

Rev 1.400

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP125N06LT, PHB125N06LT

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

I_S

Continuous source current

(body diode)

Pulsed source current (body

diode)

Diode forward voltage

I_SM

V_SD

240

I_F= 25 A; V_GS= 0 V

I_F= 75 A; V_GS= 0 V

0.85

1.0

1.2

t_rr

Q_rr

Reverse recovery time

Reverse recovery charge

I_F= 75 A; -dI_F/dt = 100 A/µs;

V_GS= -10 V; V_R= 30 V

0.18

µC

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

500

UNIT

W_DSS

Drain-source non-repetitive I_D= 75 A; V_DD≤ 25 V; V_GS= 5 V;

unclamped inductive turn-off R_GS= 50 Ω; T_mb= 25 ˚C

energy

Normalised Power Derating

PD%

Current Derating

ID (A)

120

150

125

110

100

Limited by package

100

Tmb /

100 120 140 160 180

Tmb /

100 120 140 160 180

Fig.1. Normalised power dissipation.

PD% = 100 P_D/P_{D 25 ˚C}= f(T_mb)

Fig.2. Normalised continuous drain current.

ID% = 100 I_D/I_{D 25 ˚C}= f(T_mb); conditions: V_GS≥ 5 V

March 1998

Rev 1.400

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP125N06LT, PHB125N06LT

BUKX508-55

RDS(ON) / mOhm

BUK9508-55

3.4

1000

VGS / V =

3.2

ID / A

3.6

RDS(ON) = VDS/ID

100

tp = 10 us

100 us

1 ms

10 ms

100 ms

¹1

ID / A

100

120

100

VDS / V

Fig.3. Safe operating area. T_mb= 25 ˚C

I_D& I_DM= f(V_DS); I_DMsingle pulse; parameter t_p

Fig.6. Typical on-state resistance, T_j= 25 ˚C.

R_DS(ON)= f(I_D); parameter V_GS

Zth / (K/W)

1E+00

100

ID/A

0.5

1E-01

0.2

0.1

0.05

0.02

D =

Tj/C =

175

1E-02

1E-03

1E-07

1E-05

1E-03

t / s

1E-01

1E+01

VGS/V

Fig.4. Transient thermal impedance.

Z_{th j-mb}= f(t); parameter D = t_p/T

Fig.7. Typical transfer characteristics.

I_D= f(V_GS) ; conditions: V_DS= 25 V; parameter T_j

Drain current, ID (A)

Transconductance, gfs (S)

120

100

3.4

4.0

110

100

VGS = 3.2 V

3.0

2.8

2.6

2.4

2.2

100

Drain-source voltage, VDS (V)

Drain current, ID (A)

Fig.5. Typical output characteristics, T_j= 25 ˚C.

I_D= f(V_DS); parameter V_GS

Fig.8. Typical transconductance, T_j= 25 ˚C.

g_fs= f(I_D); conditions: V_DS= 25 V

March 1998

Rev 1.400

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP125N06LT, PHB125N06LT

BUK959-60

Rds(on) normlised to 25degC

2.5

1.5

Ciss

hTuonad(spF)

0.5

-100

Coss

Crss

100

-50

Tmb / degC

100

150

200

VDS/V

0.01

0.1

Fig.9. Normalised drain-source on-state resistance.

a = R_DS(ON)/R_{DS(ON)25 ˚C}= f(T_j); I_D= 25 A; V_GS= 5 V

Fig.12. Typical capacitances, C_iss, C_oss, C_rss.

C = f(V_DS); conditions: V_GS= 0 V; f = 1 MHz

BUK959-60

VGS(TO) / V

max.

2.5

VGS/V

VDS = 14V

VDS = 44V

typ.

1.5

min.

0.5

QG/nC

-100

-50

Tj / C

100

150

200

Fig.10. Gate threshold voltage.

V_GS(TO)= f(T_j); conditions: I_D= 1 mA; V_DS= V_GS

Fig.13. Typical turn-on gate-charge characteristics.

V_GS= f(Q_G); conditions: I_D= 50 A; parameter V_DS

100

IF/A

Sub-Threshold Conduction

1E-01

1E-02

1E-03

1E-04

1E-05

typ

98%

Tj/C = 175

0.2

0.4

0.6

VSDS/V

0.8

1.2

0.5

1.5

2.5

Fig.11. Sub-threshold drain current.

I_D= f(V_GS); conditions: T_j= 25 ˚C; V_DS= V_GS

Fig.14. Typical reverse diode current.

I_F= f(V_SDS); conditions: V_GS= 0 V; parameter T_j

March 1998

Rev 1.400

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP125N06LT, PHB125N06LT

WDSS%

120

VDD

110

100

VDS

VGS

-ID/100

T.U.T.

R 01

RGS

shunt

100

120

140

160

180

Tmb /

Fig.16. Avalanche energy test circuit.

Fig.15. Normalised avalanche energy rating.

W_DSS% = f(T_mb); conditions: I_D= 75 A

W_DSS= 0.5 LI_D²BV_DSS/(BV_DSS− V_DD

)

March 1998

Rev 1.400

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP125N06LT, PHB125N06LT

MECHANICAL DATA

Dimensions in mm

Net Mass: 2 g

4,5

max

10,3

max

1,3

3,7

2,8

5,9

min

15,8

max

3,0 max

not tinned

3,0

13,5

min

1,3

1 2 3

max

(2x)

0,9 max (3x)

0,6

2,4

2,54 2,54

Fig.17. SOT78 (TO220AB); pin 2 connected to mounting base.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent

damage to MOS gate oxide.

2. Refer to mounting instructions for SOT78 (TO220) envelopes.

3. Epoxy meets UL94 V0 at 1/8".

March 1998

Rev 1.400

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP125N06LT, PHB125N06LT

MECHANICAL DATA

Dimensions in mm

Net Mass: 1.4 g

4.5 max

1.4 max

10.3 max

11 max

15.4

2.5

0.85 max

(x2)

0.5

2.54 (x2)

Fig.18. SOT404 : centre pin connected to mounting base.

MOUNTING INSTRUCTIONS

Dimensions in mm

11.5

9.0

17.5

2.0

3.8

5.08

Fig.19. SOT404 : soldering pattern for surface mounting.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent

damage to MOS gate oxide.

2. Epoxy meets UL94 V0 at 1/8".

March 1998

Rev 1.400

Philips Semiconductors

Product specification

TrenchMOS transistor

Logic level FET

PHP125N06LT, PHB125N06LT

DEFINITIONS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Electronics N.V. 1998

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury. Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

March 1998

Rev 1.400

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N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology. The device has

Communications

PC/PC-peripherals

very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications.

The PHP125N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB125N06LT is supplied in the SOT404 surface mounting package.

Cross reference

Models

Packages

Application notes

Selection guides

934054300118 [NXP]

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