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934055717118 [NXP]

TRANSISTOR 50 A, 150 V, 0.035 ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, D2PAK-3, FET General Purpose Power;
934055717118
型号： 934055717118
厂家： NXP    NXP
描述：

TRANSISTOR 50 A, 150 V, 0.035 ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, D2PAK-3, FET General Purpose Power

开关 脉冲 晶体管
文件： 总14页 (文件大小：167K)
中文：  中文翻译
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DISCRETE SEMICONDUCTORS  
DATA SHEET  
PSMN035-150B; PSMN035-150P  
N-channel TrenchMOS(TM)  
transistor  
Product specification  
August 1999  
Philips Semiconductors  
Product specification  
N-channel TrenchMOS(TM) transistor PSMN035-150B; PSMN035-150P  
FEATURES  
SYMBOL  
QUICK REFERENCE DATA  
d
• ’Trench’ technology  
• Very low on-state resistance  
• Fast switching  
VDSS = 150 V  
ID = 50 A  
• Low thermal resistance  
g
RDS(ON) ≤ 35 mΩ  
s
GENERAL DESCRIPTION  
SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in  
each package at each voltage rating.  
Applications:-  
• d.c. to d.c. converters  
• switched mode power supplies  
The PSMN035-150P is supplied in the SOT78 (TO220AB) conventional leaded package.  
The PSMN035-150B is supplied in the SOT404 surface mounting package.  
PINNING  
SOT78 (TO220AB)  
SOT404 (D2PAK)  
PIN  
DESCRIPTION  
tab  
tab  
1
2
gate  
drain1  
3
source  
drain  
2
tab  
1
3
1 2 3  
LIMITING VALUES  
Limiting values in accordance with the Absolute Maximum System (IEC 134)  
SYMBOL PARAMETER  
CONDITIONS  
MIN.  
MAX.  
UNIT  
VDSS  
VDGR  
VGS  
ID  
Drain-source voltage  
Drain-gate voltage  
Gate-source voltage  
Continuous drain current  
Tj = 25 ˚C to 175˚C  
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ  
-
-
-
-
150  
150  
± 20  
50  
V
V
V
A
A
Tmb = 25 ˚C  
Tmb = 100 ˚C  
-
36  
IDM  
PD  
Tj, Tstg  
Pulsed drain current  
Total power dissipation  
Operating junction and  
storage temperature  
Tmb = 25 ˚C  
Tmb = 25 ˚C  
-
-
200  
250  
175  
A
W
˚C  
- 55  
1 It is not possible to make connection to pin:2 of the SOT404 package  
August 1999  
2
Rev 1.000  
Philips Semiconductors  
Product specification  
N-channel TrenchMOS(TM) transistor  
PSMN035-150B; PSMN035-150P  
AVALANCHE ENERGY LIMITING VALUES  
Limiting values in accordance with the Absolute Maximum System (IEC 134)  
SYMBOL PARAMETER  
EAS Non-repetitive avalanche  
CONDITIONS  
MIN.  
MAX.  
UNIT  
Unclamped inductive load, IAS = 47 A;  
tp = 100 µs; Tj prior to avalanche = 25˚C;  
-
460  
mJ  
energy  
VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V; refer  
to fig;15  
IAS  
Non-repetitive avalanche  
current  
-
50  
A
THERMAL RESISTANCES  
SYMBOL PARAMETER  
CONDITIONS  
TYP.  
MAX.  
UNIT  
Rth j-mb  
Thermal resistance junction  
to mounting base  
-
0.6  
K/W  
Rth j-a  
Thermal resistance junction SOT78 package, in free air  
to ambient SOT404 package, pcb mounted, minimum  
footprint  
60  
50  
-
-
K/W  
K/W  
ELECTRICAL CHARACTERISTICS  
Tj= 25˚C unless otherwise specified  
SYMBOL PARAMETER  
V(BR)DSS Drain-source breakdown  
CONDITIONS  
MIN. TYP. MAX. UNIT  
VGS = 0 V; ID = 0.25 mA;  
VDS = VGS; ID = 1 mA  
150  
133  
-
-
-
-
V
V
voltage  
Gate threshold voltage  
Tj = -55˚C  
VGS(TO)  
2.0  
1.0  
3.0  
-
4.0  
-
V
V
Tj = 175˚C  
Tj = -55˚C  
-
-
-
-
-
-
-
30  
-
2
0.05  
-
6
V
RDS(ON)  
Drain-source on-state  
resistance  
VGS = 10 V; ID = 25 A  
35  
98  
100  
10  
500  
mΩ  
mΩ  
nA  
µA  
µA  
Tj = 175˚C  
IGSS  
IDSS  
Gate source leakage current VGS = ±10 V; VDS = 0 V  
Zero gate voltage drain  
current  
VDS = 150 V; VGS = 0 V;  
Tj = 175˚C  
Qg(tot)  
Qgs  
Qgd  
Total gate charge  
Gate-source charge  
Gate-drain (Miller) charge  
ID = 50 A; VDD = 120 V; VGS = 10 V  
-
-
-
79  
17  
33  
-
-
-
nC  
nC  
nC  
td on  
tr  
td off  
tf  
Turn-on delay time  
Turn-on rise time  
Turn-off delay time  
Turn-off fall time  
VDD = 75 V; RD = 1.5 Ω;  
VGS = 10 V; RG = 5.6 Ω  
Resistive load  
-
-
-
-
25  
138  
79  
-
-
-
-
ns  
ns  
ns  
ns  
93  
Ld  
Ld  
Internal drain inductance  
Internal drain inductance  
Measured from tab to centre of die  
Measured from drain lead to centre of die  
(SOT78 package only)  
-
-
3.5  
4.5  
-
-
nH  
nH  
Ls  
Internal source inductance  
Measured from source lead to source  
bond pad  
-
7.5  
-
nH  
Ciss  
Coss  
Crss  
Input capacitance  
Output capacitance  
Feedback capacitance  
VGS = 0 V; VDS = 25 V; f = 1 MHz  
-
-
-
4720  
456  
208  
-
-
-
pF  
pF  
pF  
August 1999  
3
Rev 1.000  
Philips Semiconductors  
Product specification  
N-channel TrenchMOS(TM) transistor  
PSMN035-150B; PSMN035-150P  
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS  
Tj = 25˚C unless otherwise specified  
SYMBOL PARAMETER  
CONDITIONS  
MIN. TYP. MAX. UNIT  
IS  
Continuous source current  
(body diode)  
Pulsed source current (body  
diode)  
Diode forward voltage  
-
-
-
-
50  
200  
1.2  
A
A
V
ISM  
-
VSD  
IF = 25 A; VGS = 0 V  
0.85  
trr  
Qrr  
Reverse recovery time  
Reverse recovery charge  
IF = 20 A; -dIF/dt = 100 A/µs;  
VGS = 0 V; VR = 30 V  
-
-
118  
0.66  
-
-
ns  
µC  
August 1999  
4
Rev 1.000  
Philips Semiconductors  
Product specification  
N-channel TrenchMOS(TM) transistor  
PSMN035-150B; PSMN035-150P  
Transient thermal impedance, Zth j-mb (K/W)  
1
Normalised Power Derating, PD (%)  
100  
D = 0.5  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
0.2  
0.1  
0.1  
0.05  
0.02  
P
D = tp/T  
D
0.01  
tp  
single pulse  
T
0.001  
1E-06  
1E-05  
1E-04  
1E-03  
1E-02  
1E-01  
1E+00  
0
25  
50  
75  
100  
125  
150  
175  
Pulse width, tp (s)  
Mounting Base temperature, Tmb (C)  
Fig.1. Normalised power dissipation.  
PD% = 100 PD/PD 25 ˚C = f(Tmb)  
Fig.4. Transient thermal impedance.  
th j-mb = f(t); parameter D = tp/T  
Z
Drain Current, ID (A)  
Tj = 25 C  
50  
45  
40  
35  
30  
25  
20  
15  
10  
5
Normalised Current Derating, ID (%)  
VGS = 10V  
8 V  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
6 V  
5.4 V  
5.2 V  
5 V  
4.8 V  
4.6 V  
4.4 V  
1.6  
0
0
25  
50  
75  
100  
125  
150  
175  
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
1.8  
2
Mounting Base temperature, Tmb (C)  
Drain-Source Voltage, VDS (V)  
Fig.2. Normalised continuous drain current.  
ID% = 100 ID/ID 25 ˚C = f(Tmb)  
Fig.5. Typical output characteristics, Tj = 25 ˚C.  
ID = f(VDS); parameter VGS  
Peak Pulsed Drain Current, IDM (A)  
Drain-Source On Resistance, RDS(on) (Ohms)  
0.15  
1000  
4.8 V  
4.4 V  
Tj = 25 C  
0.14  
0.13  
0.12  
0.11  
0.1  
4.6V  
5 V  
RDS(on) = VDS/ ID  
5.2V  
100  
10  
1
tp = 10 us  
100 us  
1 ms  
0.09  
0.08  
0.07  
0.06  
0.05  
0.04  
0.03  
0.02  
0.01  
0
5.4V  
D.C.  
6 V  
10 ms  
VGS = 10V  
100 ms  
8 V  
1
10  
100  
1000  
0
5
10  
15  
20  
25  
30  
Drain-Source Voltage, VDS (V)  
Drain Current, ID (A)  
Fig.3. Safe operating area. Tmb = 25 ˚C  
ID & IDM = f(VDS); IDM single pulse; parameter tp  
Fig.6. Typical on-state resistance, Tj = 25 ˚C.  
RDS(ON) = f(VGS)  
August 1999  
5
Rev 1.000  
Philips Semiconductors  
Product specification  
N-channel TrenchMOS(TM) transistor  
PSMN035-150B; PSMN035-150P  
Threshold Voltage, VGS(TO) (V)  
4.5  
Drain current, ID (A)  
50  
VDS > ID X RDS(ON)  
4
45  
maximum  
40  
35  
30  
3.5  
typical  
3
2.5  
2
175 C  
25  
minimum  
Tj = 25 C  
20  
15  
10  
5
1.5  
1
0.5  
0
0
0
1
2
3
4
5
6
7
8
9
10  
-60 -40 -20  
0
20 40 60 80 100 120 140 160 180  
Junction Temperature, Tj (C)  
Gate-source voltage, VGS (V)  
Fig.7. Typical transfer characteristics.  
ID = f(VGS); parameter Tj  
Fig.10. Gate threshold voltage.  
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS  
Transconductance, gfs (S)  
VDS > ID X RDS(ON)  
Drain current, ID (A)  
55  
50  
45  
40  
35  
30  
25  
20  
15  
10  
5
1.0E-01  
Tj = 25 C  
1.0E-02  
1.0E-03  
1.0E-04  
1.0E-05  
1.0E-06  
175 C  
minimum  
typical  
maximum  
0
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
4.5  
5
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
Gate-source voltage, VGS (V)  
Drain current, ID (A)  
Fig.8. Typical transconductance, Tj = 25 ˚C.  
gfs = f(ID)  
Fig.11. Sub-threshold drain current.  
ID = f(VGS); Tj = 25 ˚C  
Normalised On-state Resistance  
2.9  
2.7  
2.5  
2.3  
2.1  
1.9  
1.7  
1.5  
1.3  
1.1  
0.9  
0.7  
0.5  
Capacitances, Ciss, Coss, Crss (pF)  
10000  
1000  
100  
Ciss  
Coss  
Crss  
-60 -40 -20  
0
20 40 60 80 100 120 140 160 180  
0.1  
1
10  
100  
Junction temperature, Tj (C)  
Drain-Source Voltage, VDS (V)  
Fig.9. Normalised drain-source on-state resistance.  
RDS(ON)/RDS(ON)25 ˚C = f(Tj)  
Fig.12. Typical capacitances, Ciss, Coss, Crss.  
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz  
August 1999  
6
Rev 1.000  
Philips Semiconductors  
Product specification  
N-channel TrenchMOS(TM) transistor  
PSMN035-150B; PSMN035-150P  
Maximum Avalanche Current, IAS (A)  
100  
Gate-source voltage, VGS (V)  
15  
ID = 50A  
14  
13  
12  
11  
10  
9
Tj = 25 C  
VDD = 30 V  
25 C  
10  
8
7
VDD = 120 V  
6
5
Tj prior to avalanche = 150 C  
4
3
2
1
0
1
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
100  
0.001  
0.01  
0.1  
1
10  
Gate charge, QG (nC)  
Avalanche time, tAV (ms)  
Fig.13. Typical turn-on gate-charge characteristics  
GS = f(QG)  
Fig.15. Maximum permissible non-repetitive  
avalanche current (IAS) versus avalanche time (tAV);  
unclamped inductive load  
V
Source-Drain Diode Current, IF (A)  
VGS = 0 V  
50  
45  
40  
35  
30  
25  
20  
15  
10  
5
175 C  
Tj = 25 C  
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9  
Source-Drain Voltage, VSDS (V)  
1
1.1 1.2  
Fig.14. Typical reverse diode current.  
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj  
August 1999  
7
Rev 1.000  
Philips Semiconductors  
Product specification  
N-channel TrenchMOS(TM) transistor  
PSMN035-150B; PSMN035-150P  
MECHANICAL DATA  
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220  
SOT78  
E
P
A
A
1
q
D
1
D
(1)  
L
L
2
1
Q
b
1
L
1
2
3
b
c
e
e
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
L
2
b
e
A
b
D
E
L
D
L
1
A
c
UNIT  
P
q
Q
1
1
1
max.  
4.5  
4.1  
1.39  
1.27  
0.9  
0.7  
1.3  
1.0  
0.7  
0.4  
15.8  
15.2  
6.4  
5.9  
10.3  
9.7  
15.0  
13.5  
3.30  
2.79  
3.8  
3.6  
3.0  
2.7  
2.6  
2.2  
mm  
3.0  
2.54  
Note  
1. Terminals in this zone are not tinned.  
REFERENCES  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
JEDEC  
EIAJ  
97-06-11  
SOT78  
TO-220  
Fig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)  
Notes  
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static  
discharge during transport or handling.  
2. Refer to mounting instructions for SOT78 (TO220AB) package.  
3. Epoxy meets UL94 V0 at 1/8".  
August 1999  
8
Rev 1.000  
Philips Semiconductors  
Product specification  
N-channel TrenchMOS(TM) transistor  
PSMN035-150B; PSMN035-150P  
MECHANICAL DATA  
2
Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads  
(one lead cropped)  
SOT404  
A
A
E
1
mounting  
base  
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
D
E
A
A
b
UNIT  
c
D
e
L
H
Q
1
1
p
D
max.  
4.50  
4.10  
1.40  
1.27  
0.85  
0.60  
0.64  
0.46  
1.60  
1.20  
10.30  
9.70  
2.90 15.40 2.60  
2.10 14.80 2.20  
mm  
11  
2.54  
REFERENCES  
JEDEC  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
EIAJ  
98-12-14  
99-06-25  
SOT404  
Fig.17. SOT404 surface mounting package. Centre pin connected to mounting base.  
Notes  
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static  
discharge during transport or handling.  
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.  
3. Epoxy meets UL94 V0 at 1/8".  
August 1999  
9
Rev 1.000  
Philips Semiconductors  
Product specification  
N-channel TrenchMOS(TM) transistor  
PSMN035-150B; PSMN035-150P  
MOUNTING INSTRUCTIONS  
Dimensions in mm  
11.5  
9.0  
17.5  
2.0  
3.8  
5.08  
Fig.18. SOT404 : soldering pattern for surface mounting.  
DEFINITIONS  
Data sheet status  
Objective specification  
This data sheet contains target or goal specifications for product development.  
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.  
Product specification  
This data sheet contains final product specifications.  
Limiting values  
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and  
operation of the device at these or at any other conditions above those given in the Characteristics sections of  
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
Philips Electronics N.V. 1999  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the  
copyright owner.  
The information presented in this document does not form part of any quotation or contract, it is believed to be  
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any  
consequence of its use. Publication thereof does not convey nor imply any license under patent or other  
industrial or intellectual property rights.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices or systems where malfunction of these  
products can be reasonably expected to result in personal injury. Philips customers using or selling these products  
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting  
from such improper use or sale.  
August 1999  
10  
Rev 1.000  
Philips Semiconductors  
Product specification  
N-channel TrenchMOS(TM) transistor  
PSMN035-150B; PSMN035-150P  
NOTES  
August 1999  
11  
Rev 1.000  
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Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,  
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745  
India: Philips INDIA Ltd, Band Box Building, 2nd floor,  
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,  
Tel. +91 22 493 8541, Fax. +91 22 493 0966  
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,  
Tel. +41 1 488 2741 Fax. +41 1 488 3263  
Indonesia: PT Philips Development Corporation, Semiconductors Division,  
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,  
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080  
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,  
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874  
Ireland: Newstead, Clonskeagh, DUBLIN 14,  
Tel. +353 1 7640 000, Fax. +353 1 7640 200  
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,  
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Tel. +66 2 745 4090, Fax. +66 2 398 0793  
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,  
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007  
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,  
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813  
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),  
Tel. +39 039 203 6838, Fax +39 039 203 6800  
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,  
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Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,  
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057  
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,  
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421  
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,  
Tel. +82 2 709 1412, Fax. +82 2 709 1415  
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,  
Tel. +1 800 234 7381, Fax. +1 800 943 0087  
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,  
Tel. +60 3 750 5214, Fax. +60 3 757 4880  
Uruguay: see South America  
Vietnam: see Singapore  
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,  
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087  
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,  
Middle East: see Italy  
Tel. +381 11 3341 299, Fax.+381 11 3342 553  
For all other countries apply to: Philips Semiconductors,  
Internet: http://www.semiconductors.philips.com  
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,  
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825  
69  
SCA  
© Philips Electronics N.V. 2000  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
603502/300/03/pp12  
Date of release: August 1999  
Document order number: 9397 750 06973  
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