935271501518_技术文档

INTEGRATED CIRCUITS

DATA SHEET

SAA7724H

Car radio digital signal processor

Preliminary speciﬁcation

2003 Nov 18

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

CONTENTS

6.10

Clock circuit and oscillator

6.10.1

6.10.2

6.10.3

6.10.4

6.11

Circuit description

External clock input mode

Crystal oscillator supply

Application guidelines

PLL circuits

1

2

FEATURES

GENERAL INFORMATION

2.1

2.2

2.3

DSP radio system

SAA7724H

Sample rates

6.12

RDS

6.12.1

6.12.2

6.12.3

6.12.4

6.12.5

General description

RDS I/O modes

RDS demodulator

RDS bit buffer

3

4

5

6

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING

RDS/RBDS decoder

FUNCTIONAL DESCRIPTION

7

LIMITING VALUES

6.1

6.2

6.2.1

6.2.2

6.2.3

6.2.4

Voltage regulator

Audio analog front-end

Selector diagram

Realization of the common mode input with AIN

Realization of the differential ADIFF input

Realization of the auxiliary input with volume

control

8

THERMAL RESISTANCE

DC CHARACTERISTICS

AC CHARACTERISTICS

Timing diagrams

9

10

10.1

11

I²C-BUS CONTROL

6.2.5

6.3

6.3.1

6.3.2

6.4

6.4.1

6.4.2

6.4.3

6.4.4

6.5

Supplies and references

AD decimation paths (DAD)

LDF and AUX decimation path

ADF and audio decimation path

Digital audio input/output

General

11.1

11.1.1

11.2

11.3

11.4

11.5

I²C-bus protocol

Protocol of the I²C-bus commands

MPI data transfer formats

Reset initialization

Defined I²C-bus address

I²C-bus memory map specification

I²S-BUS CONTROL

External I²S-bus input/output ports

External SPDIF input

12

EPICS host I²S-bus port

Sample rate converter

IF_AD

12.1

12.2

12.3

Basic system requirements

Serial data

Word select

6.6

6.6.1

6.6.2

6.7

6.7.1

6.7.2

6.8

6.8.1

6.8.2

6.8.3

6.8.4

6.8.5

6.8.6

6.9

IF_AD single block diagram

IF_AD detailed functional description

AUDIO_EPICS specific information

AUDIO_EPICS start-up

AUDIO_EPICS memory overview

SDAC output path

13

PACKAGE OUTLINE

SOLDERING

14

14.1

Introduction to soldering surface mount

packages

Reflow soldering

Wave soldering

Manual soldering

14.2

14.3

14.4

14.5

DAC upsampling filter

DAC noise shaper

Suitability of surface mount IC packages for

wave and reflow soldering methods

DAC CoDEM scrambler

Multi-bit SDAC

Analog summer function

SDAC application diagram

Reset block functional overview

Asynchronous reset

15

16

17

18

DATA SHEET STATUS

DEFINITIONS

DISCLAIMERS

PURCHASE OF PHILIPS I²C COMPONENTS

6.9.1

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

1

FEATURES

• AM and FM digitize at IF

• AM and FM narrow-band/IF AGC

• AM and FM IF filtering

• AM and FM adjustable channel detection/variable IF

• IF filter for WX

• CD gain adjust, calibration and compression (from

analog or digital SPDIF/I²S-bus input)

• AM and FM demodulation

• AM and FM stereo decoding

• AM and FM stereo pilot detection

• FM pilot notch

• Parametric equalization

• Volume control

• Bass control

• Treble control

• AM pilot filter

• Balance/fade control

• DC blocking filter

• Dual source select

• Dual playback

• FM stereo blend, high blend, high cut, soft muting and

de-emphasis

• AM stereo blend, LP filter, high cut and soft muting

• AM and FM noise blanker

• Channel delays

• AM and FM gain adjust and calibration (audio)

• FM multipath detection

• Analog summer for four channels (through inputs

MONO1 and MONO2)

• FM multipath correction

• Audio limiting.

• Diversity switching

1.1

Sample rates

• Radio Data System (RDS) and Radio Broadcast Data

System (RBDS) demodulation and decoding

The SAA7724H runs at a master clock of 43.2 MHz. Audio

processing runs at a sample rate of

• Tape head calibration, equalization, Dolby B and AMS

43.2 MHZ

1024

(from analog tape input)

1 × f_s= 42.1875 kHz =

-------------------------

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

2

GENERAL INFORMATION

DSP radio system

2.2

SAA7724H

2.1

The SAA7724H digitizes up to two IF signals and performs

DSP to generate left front, right front, left rear, and right

rear audio and RDS/RBDS data output. The SAA7724H

also samples analog baseband tape, FM MPX, AUX

inputs, analog and digital CD, performs signal processing

on these sampled waveforms and multiplexes the proper

signal to the output. A microcontroller interface allows the

SAA7724H to be controlled and monitored.

The Digital Signal Processing (DSP) radio system (see

Fig.1) consists of:

• Analog tuner (also called RF/IF)

• SAA7724H

• Audio power amplifier

• Microcontroller

The SAA7724H is composed of hardwired and

programmable DSP circuitry, with programmable

parameters, such as injection frequencies, filter

coefficients and control parameters. Some functions or

groups of functions are implemented with programmable

sequence processors.

• IF co-processor

• Audio co-processor.

The microcontroller interfaces to the RF/IF and SAA7724H

via an I²C-bus. Analog tape and CD inputs are input from

other parts of the radio. The IF co-processor and audio

co-processor interfaces to the SAA7724H via an I²S-bus.

handbook, full pagewidth

AUDIO

IF

CO-PROCESSOR

2

I S-

bus

I S-

bus

10.7 MHz/FM

450 kHz/AM

IF

ANALOG

TUNER

AUDIO

POWER

SAA7724H

AMPLIFIER

2

I C-

bus

MICRO-

CONTROLLER

Tape, CD analog, Aux,

CD digital, FM MPX

MGW194

Fig.1 System overview.

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

3

ORDERING INFORMATION

TYPE

PACKAGE

NUMBER

NAME

DESCRIPTION

VERSION

SAA7724H

QFP100

plastic quad ﬂat package; 100 leads (lead length 1.95 mm);

SOT317-3

body 14 × 20 × 2.8 mm

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

4

BLOCK DIAGRAM

handbook, full pagewidth

1

8

9

10

26

33

34

44

45

58

aux1_sel_lev_voice

AAD

LDF_1

85

86

3

COMP

FILTER

IFSS1

IFSS2

AUXAD_1

AUXAD_2

LPF_1

LPF_2

16

4

MONO1_N

MONO1_P

MONO2_N

MONO2_P

aux2_sel_lev_voice

2

5

LDF_2

16

COMP

FILTER

4

99

100

97

98

89

88

87

96

95

94

ADIFF_RP

ADIFF_RN

ADIFF_LP

ADIFF_LN

AIN1_R

SELECTOR

ADF1_1

16

ADF2_1

DC

OFFSET

AUDIOAD_1

8

SAT

AIN1_REF

AIN1_L

ch1_dc_offset

ch1_wide_narrow

AIN2_R

ADF1_2

16

ADF2_2

8

DC

OFFSET

AIN2_REF

AIN2_L

AUDIOAD_2

SAT

ch2_wide_narrow

ch2_dc_offset

14

SPDIF1

SPDIF_1

EXTIIS_1

20

21

22

A

EXT_IIS_WS1

EXT_IIS_BCK1

EXT_IIS_IO1

SRC-EPICS bus

SRC_1

25

24

23

EXT_IIS_IO2

EXT_IIS_BCK2

EXT_IIS_WS2

SAA7724H

EXTIIS_2

SPDIF_2

SRC_2

15

SPDIF2

DIT1

SWB-EPICS bus and FLAG

IFP status

B

82

83

84

IF_AD

IF_IN1

IF_VG

IF_IN2

AND DITHER

C

D

IFP

IF_AD

AND DITHER

MPX1

MPX2

38

39

40

41

42

43

35

47

46

SWB

AND

INTERFACES

E

IFP_IIS_IN1

IFP_IIS_I2O6

IFP_IIS_I3O4

IFP_IIS_OUT1

IFP_IIS_OUT2

IFP_IIS_OUT3

IFP_IIS_OUT5

IFP_IIS_WS

DIT2

BOOT ROM

F

2

IFP I S-bus

FLAG

G

IFP_IIS_BCK

MGW191

Fig.2 Block diagram (continued in Fig.3).

6

2003 Nov 18

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

handbook, full pagewidth

64

65

66

67

68

69

70

71

79

72

73

74

80

81

90

91

92

93

VOLTAGE

REGULATOR

11

RFV

LFV

RRV

LRV

SAA7724H

SDAC_F

SDAC_R

F

12

6

INTERPOLATOR

128

NOISE

SHAPER

R

7

27

28

29

37

36

30

31

32

IIS_IN1

IIS_IN2

IIS_IN3

IIS_WS

SRC-EPICS bus

IIS_BCK

IIS_OUT1

IIS_OUT2

IIS_OUT3

2

EPICS I S-bus

DIO

A

54

55

56

57

59

60

61

62

63

DSP_IO0

DSP_IO1

DSP_IO2

DSP_IO3

DSP_IO4

DSP_IO5

DSP_IO6

DSP_IO7

DSP_IO8

ch.st. SPDIF_1

ch.st. SPDIF_2

IIC_REG

lock SPDIF_1

lock SPDIF_2

AUDIO_EPICS

SWB-EPICS bus and LFLAG

B

IFP status

C

D

AUDIO_EPICS

SRC_EPICS

MPX1

MPX2

RDSDEM_1

RDSDEC_1

E

TCB

RESET

PLL1

PLL2

RDS

MPI

RDSDEM_2

RDSDEC_2

F

OSCILLATOR

AND CLOCK

FLAG

G

sel_rds_clk1_davn2

sel_davn2_rds_flag

50

51

52 53

49 48 13

17 19 18

16

75 78 77 76

MGW192

Fig.3 Block diagram (continued from Fig.2)

7

2003 Nov 18

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

5

PINNING

Table 1 Functional pin description

SYMBOL

V_DD(REG)

DESCRIPTION

1

supply voltage for 2.5 V regulator circuit and bias for ADCs (3.3 V)

differential positive analog input to AUX_AD2, AUDIOAD_1 and AUDIOAD_2

differential negative analog input to AUX_AD2, AUDIOAD_1 and AUDIOAD_2

differential positive analog input to AUX_AD2, AUDIOAD_1 and AUDIOAD_2

differential negative analog input to AUX_AD2, AUDIOAD_1 and AUDIOAD_2

analog audio voltage output for the right-rear speaker

analog audio voltage output for the left-rear speaker

negative reference voltage for the SDAC

MONO1_P

MONO1_N

MONO2_P

MONO2_N

RRV

2

3

4

5

6

LRV

7

VDACN

8

V_DDA2

9

analog supply voltage for the SDAC (2.5 V)

VDACP

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

positive reference voltage for the SDAC

RFV

analog audio voltage output for the right-front speaker

analog audio voltage output for the left-front speaker

slave subaddress for I²C-bus selection

LFV

A0

SPDIF1

SPDIF input channel 1 from digital media source

SPDIF input channel 2 from digital media source

reset input (active LOW)

SPDIF2

RESET

TSCAN

scan control

SHTCB

shift clock test control block

RTCB

asynchronous reset test control block (active LOW)

word select input from digital media source 1 (I²S-bus)

bit clock input from digital media source 1 (I²S-bus)

data input/output digital media source 1 (I²S-bus)

word select input from digital media source 2 (I²S-bus)

bit clock input from digital media source 2 (I²S-bus)

data input/output digital media source 2 (I²S-bus)

ground supply 1 for external digital ports

data channel input 1 (front channels) from external DSP IC (I²S-bus)

data channel input 2 (rear channels) from external DSP IC (I²S-bus)

data channel input 3 from external DSP IC (I²S-bus)

data channel output 1 for external DSP IC activated by en_host_io (I²S-bus)

data channel output 2 to external DSP IC activated by en_host_io (I²S-bus)

data channel output 3 to external DSP IC activated by en_host_io (I²S-bus)

ground supply 2 for external digital ports

EXT_IIS_WS1

EXT_IIS_BCK1

EXT_IIS_IO1

EXT_IIS_WS2

EXT_IIS_BCK2

EXT_IIS_IO2

V_SS(I/O1)

IIS_IN1

IIS_IN2

IIS_IN3

IIS_OUT1

IIS_OUT2

IIS_OUT3

V_SS(I/O2)

V_DD(I/O2)

supply voltage 2 for external digital ports (3.3 V)

IFP_IIS_OUT5

IFP data channel output 5 to external DSP IC activated by ifp_iis_en; can also

be used as 256 × f_sclock output enabled by en_256FS (I²S-bus)

IIS_BCK

36

37

38

clock output for external DSP IC enabled by en_host_io (I²S-bus)

word select output for external DSP IC enabled by en_host_io (I²S-bus)

IFP data channel input 1 from external DSP IC (I²S-bus)

IIS_WS

IFP_IIS_IN1

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

SYMBOL

IFP_IIS_I2O6

DESCRIPTION

39

IFP data channel input 2 from external DSP IC or output data channel 6 to

external DSP IC selected by ifp_iis_io_mode (I²S-bus)

IFP_IIS_I3O4

40

IFP data channel input 3 from external DSP IC or output data channel 4 to

external DSP IC selected by ifp_iis_io_mode (I²S-bus)

IFP_IIS_OUT1

IFP_IIS_OUT2

IFP_IIS_OUT3

V_DD(I/O3)

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

IFP data channel output 1 to external DSP IC activated by ifp_iis_en (I²S-bus)

IFP data channel output 2 to external DSP IC activated by ifp_iis_en (I²S-bus)

IFP data channel output 3 to external DSP IC activated by ifp_iis_en (I²S-bus)

supply voltage 3 for external digital ports (3.3 V)

ground supply 3 for external digital ports

IFP output clock for external DSP IC enabled by ifp_iis_en (I²S-bus)

IFP word select output for external DSP IC enabled by ifp_iis_en (I²S-bus)

serial clock input (I²C-bus)

V_SS(I/O3)

IFP_IIS_BCK

IFP_IIS_WS

SCL

SDA

serial data input/output (I²C-bus)

RDS_CLK2

RDS_DATA2

RDS_CLK1_DAVN2

RDS_DATA1_DAVN1

DSP_IO0

DSP_IO1

DSP_IO2

DSP_IO3

V_SS(I/O4)

RDS2 bit clock input/output; default input enabled by rds2_clkin

RDS2 data output of RDS2 demodulator

DAVN2 or RDS1 bit clock input/output; default input enabled by rds1_clkin

RDS1 data output of RDS1 demodulator or RDS1 decoder DAVN1

general purpose input/output for EPICS (F0 of status register)

general purpose input/output for EPICS (F1 of status register)

general purpose input/output for EPICS (F2 of status register)

general purpose input/output for EPICS (F3 of status register)

ground supply 4 for external digital ports

DSP_IO4

DSP_IO5

DSP_IO6

DSP_IO7

DSP_IO8

V_SSD6

general purpose input/output for EPICS (F4 of status register)

general purpose input/output for EPICS (F5 of status register)

general purpose input/output for EPICS (F6 of status register)

general purpose input/output for EPICS (F7 of status register)

general purpose input/output for EPICS (F8 of status register)

ground supply for digital circuitry

V_DDD1(MEM)

V_SSD1

digital supply voltage 1 for memories (2.5 V)

digital ground supply 1

V_DDD2

digital supply voltage 2 (2.5 V)

V_SSD2

digital ground supply 2

V_SSD5

digital ground supply 5

V_DDD3

digital supply voltage 3 (2.5 V)

V_SSD3

digital ground supply 3

CONREG

FEBREG

GAPREG

V_SS(OSC)

2.5 V regulator control output

2.5 V regulator feedback input

band gap reference decoupling pin for voltage regulator

ground supply for crystal oscillator circuitry

OSC_IN

crystal oscillator input: local crystal oscillator sense for gain control or forced

input in slave mode

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

SYMBOL

OSC_OUT

V_DD(OSC)

V_SS(IF)

DESCRIPTION

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

crystal oscillator output: drive output to crystal

positive supply voltage for crystal oscillator circuitry

IF_AD ground supply

VREFIF

V_DD(IF)

IF_AD reference voltage output

IF_AD 2.5 V supply voltage

IF_IN1

analog input to IF_AD1 from tuner IF output

IF_AD virtual ground

IF_VG

IF_IN2

analog input to IF_AD2 from tuner IF output

analog IFSS1 input to AUXAD_1

IFSS1

IFSS2

analog IFSS2 input to AUXAD_2

AIN1_L

AIN1_REF

AIN1_R

V_DDA1

analog input 1 to AAD for left input buffer signal

common reference voltage input for AIN1 input buffer

analog input 1 to AAD for right input buffer signal

analog supply voltage 1 for AUXAD and AAD analog circuitry (2.5 V)

positive reference voltage input for AAD

VADCP

VADCN

VREFAD

AIN2_L

AIN2_REF

AIN2_R

ADIFF_LP

ADIFF_LN

ADIFF_RP

ADIFF_RN

ground reference voltage input for AAD

common mode reference voltage output for AAD, AUXAD and buffers

analog input 2 to AAD for left input buffer signal

common reference voltage input for AIN2 input buffer

analog input 2 to AAD for right input buffer signal

analog input to AAD for left positive differential signal

analog input to AAD for left negative differential signal

analog input to AAD for right positive differential signal

analog input to AAD for right negative differential signal

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

Table 3 Used padcells and functional speciﬁcation; notes 1 and 2

PADCELL

NAME

LIBRARY NAME

FUNCTIONAL SPECIFICATION

Inputs

ipthd

iolib_nlm

input pad; hysteresis; pull-down; TTL levels

iptht5v

ipthdt5v

iolib_nlm_danger input pad; hysteresis; TTL levels; 5 V tolerant

iolib_nlm_danger input pad; hysteresis; pull-down; TTL levels; 5 V tolerant

Outputs

ot4mc

ops10c

ots10c

iolib_nlm

output; 3-state; 4 mA

output plain; 10 ns slew rate

output; 3-state; 10 ns slew rate

I/Os

iic400kt5v

bpt4mthd

bpts10thd

bpts10tht5v

iolib_nlm_danger input/output; 400 kHz I²C-bus special cell; 5 V tolerant

iolib_nlm

input/output; 4 mA; hysteresis; pull-down; TTL input levels

input/output; 10 ns slew rate; hysteresis; pull-down; TTL input levels

iolib_nlm_danger input/output; 10 ns slew rate; hysteresis; TTL input levels; 5 V tolerant

bptons10tht5v iolib_nlm_danger input/output; open-drain N-channel; 10 ns slew rate; hysteresis; TTL input levels;

5 V tolerant

Special

apio

aprf

iolib_nlm

analog pad input or output

analog high frequency pad input or output

Supply

vddco

vssco

iolib_nlm

V_DDcore only supply; not connected to internal supply ring

V_SScore only supply; not connected to internal supply ring

V_DDcore supply; connected to internal supply ring

V_SScore supply; connected to internal supply ring and substrate

V_DDsupply peripheral only

vddi

vssis

vdde3v3

vsse3v3

V_SSsupply peripheral only

Notes

1. All pull-down inputs or disabled I/Os with pull-down, may be left open-circuit. Internally the logic level is guaranteed

LOW, but the pull-down doesn’t behave as a normal resistor seen at the pin itself.

2. 5 V tolerant means that the input or 3-stated/disabled output is functioning correctly and will not be damaged when

applying externally 5 V, and can thus be used in a normal application. The tolerances of the 5 V are given in the

limiting values; see Chapter 7.

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

handbook, full pagewidth

V

1

2

VREFIF

80

79

78

77

DD(REG)

V

MONO1_P

MONO1_N

MONO2_P

MONO2_N

RRV

SS(IF)

V

3

DD(OSC)

4

OSC_OUT

5

76 OSC_IN

V

6

75

74

SS(OSC)

GAPREG

7

LRV

8

VDACN

73 FEBREG

V

9

72 CONREG

V

DDA2

VDACP

RFV

LFV

10

11

12

13

71

70

69

68

67

66

65

64

SSD3

V

DDD3

SSD5

A0

SSD2

SPDIF1 14

SPDIF2 15

DDD2

SSD1

SAA7724H

16

RESET

DDD1(MEM)

SSD6

17

TSCAN

SHTCB 18

63 DSP_IO8

19

DSP_IO7

DSP_IO6

62

61

RTCB

20

EXT_IIS_WS1

EXT_IIS_BCK1 21

EXT_IIS_IO1 22

EXT_IIS_WS2 23

60 DSP_IO5

59 DSP_IO4

V

58

57

SS(I/O4)

DSP_IO3

24

EXT_IIS_BCK2

EXT_IIS_IO2 25

56 DSP_IO2

55 DSP_IO1

V

26

27

SS(I/O1)

IIS_IN1

DSP_IO0

54

53

IIS_IN2 28

IIS_IN3 29

RDS_DATA1_DAVN1

52 RDS_CLK1_DAVN2

51 RDS_DATA2

IIS_OUT1 30

MGW193

Fig.4 Pin configuration.

16

2003 Nov 18

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

6

FUNCTIONAL DESCRIPTION

Voltage regulator

6.1

A voltage regulator (see Fig.5) controls all 2.5 V supplies of the chip (see Fig.6). The input supply voltage is 3.3 V. An

external PMOS power transistor (e.g. BSH207) is used to handle power. The regulated 2.5 V supply is derived from a

band gap voltage, which is AC-decoupled by an external capacitor.

handbook, full pagewidth

on-chip

off-chip

V

1

DD(REG)

74 GAPREG

BSH207

BAND GAP

72 CONREG

73 FEBREG

external

PMOS

external

1 µF

decoupling

R1

V

gap

R2

V

SS

MGW195

Fig.5 Voltage regulator schematic diagram.

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

handbook, full pagewidth

on-chip

off-chip

V

DD(REG)

DD(I/O3)

DD(I/O2)

1

44

34

74

1 µH

100 nF

GAPREG

BSH207

CONREG

FEBREG

72

73

1 µH

V

DDD3

70

67

V

1 µF

DDD2

V

DDD1(MEM)

65

78

81

3.3 V

2.5 V

V

DD(OSC)

V

DD(IF)

1 µH

V

DDA1

90

9

10 µF

1 µF

V

DDA2

V

SS

MGW196

Fig.6 Voltage regulator connection diagram.

2003 Nov 18

18

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

6.2

Audio analog front-end

The analog front-end consists of two identical 3rd-order sigma delta stereo ADCs (ADC1 and ADC2) with several input

control blocks for handling common mode signals and acting as input selector (see Fig.7).

handbook, full pagewidth

SAA7724H

AAD

refc1

aic1[1:0]

intref1 = 0

00

01

10

11

87

94

AIN1_L

AIN2_L

s1

0

1

0

1

0

1

LEFT1

AUDIOAD_1

STEREO

ADF1_1

RIGHT1

0

1

89

96

00

01

10

11

AIN1_R

AIN2_R

CLKADC1

99, 100

97, 98

93

2

ADIFF_R (P/N)

ADIFF_L (P/N)

VREFAD

00

01

10

11

s2

INT

REF

88

95

AIN1_REF

AIN2_REF

0

1

0

1

0

1

LEFT2

AUDIOAD_2

STEREO

ADF1_2

RIGHT2

0

1

00

01

10

11

CLKADC2

intref2 = 0

aic2[1:0]

refc2

4

5

2

3

MONO2_P

CMRR

volmix[5:2]

volmix[1:0]

1

0

MONO2_N

MONO1_P

MIX

CMRR

mixc

located in

SDAC

MONO1_N

aic3[1:0]

00

01

10

11

AUXAD_2

AUXAD_1

AUXO2

CLKAUX

AUXO1

86

85

IFSS2

IFSS1

MGW197

Fig.7 Analog front-end switch diagram.

19

2003 Nov 18

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

The inputs ADIFF, AIN1, AIN2, MONO1 and MONO2 can

be selected with the audio input controls (aic1 and aic2).

The ground reference (REF1 and REF2) can be selected

(refc1 and refc2) to enable the handling of common mode

signals for AIN1 and AIN2. The switches s1 and s2 are

needed for handling fully differential inputs at the ADIFF

pins.

the AUXAD (controlled by aic3) or directly mix the same

MONO input with four DAC output channels, incorporating

volume control.

6.2.1

SELECTOR DIAGRAM

Three bits are available to make it possible to redirect the

inputs with their corresponding reference to the required

AUDIOAD (see Tables 4 and 5). The input control for the

AUXAD_2 is given in Table 6. The input selection of the

mixer is given in Table 7.

The MONO1 and MONO2 inputs have their own CMRR

input stage and can be redirected to ADC1 and/or ADC2

via the audio input control (aic1 and aic2). In this event, the

ground reference should be switched to internal

(intref = 1). It is also possible to pass MONO1/MONO2 to

Table 4 Reference connection for AUDIOAD_1 and AUDIOAD_2

I²C-BUS BIT

REFERENCE CONNECTION FOR

AUDIOAD_1 and AUDIOAD_2

refc1, refc2

intref1, intref2

s1, s2

0

1

−

0

1

−

0

1

REF1

REF2

VREFAD

differential

Table 5 Input connection for AUDIOAD_1 and AUDIOAD_2

I²C-BUS BIT

INPUT CONNECTION FOR

AUDIOAD_1 and AUDIOAD_2

PREFERRED REFERENCE

aic1[1], aic2[1] aic1[0], aic2[0]

0

1

0

1

0

1

REF1

AIN1

REF2

AIN2

differential

VREFAD

ADIFF

MONO1 and MONO2

Table 6 Input connection for AUXAD_2

I²C-BUS BIT

INPUT CONNECTION FOR AUXAD_2

aic3[1]

aic3[0]

0

1

0

1

0

1

MONO1

MONO2

not connected

IFSS2

Table 7 Input connection for the MIXER

I²C-BUS BIT

mixc

INPUT CONNECTION FOR THE MIXER

0

1

MONO1

MONO2

2003 Nov 18

20

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

6.2.2

REALIZATION OF THE COMMON MODE INPUT WITH

AIN

The actual input can be selected with the audio input

control (bits aic1[1:0] and aic2[1:0]). In Fig.8 the AIN1 input

is selected. In this situation both signal lines going to the

ADC will contain the common mode signal. The ADC itself

will suppress this common mode signal with a high

rejection ratio.

A high CMRR can be created by the use of REF1 and

REF2. These pins can be connected to the positive input

of the second operational amplifier in the signal path with

bits intref1, intref2, refc1 and refc2 (see Fig.8). The signal

(of which a high CMRR is required) has a signal and a

common signal as input. The common signal is connected

to pin REF1 and/or REF2 and can be selected with bits

refc1 and/or refc2.

The input pins AIN1_L and AIN1_R are connected directly

to the source. The 1 MΩ resistor provides the DC biasing

of OA3 and OA4. The impedance level, in combination

with the parasitic capacitance at input pin AIN_L or AIN_R,

greatly determines the achievable common rejection ratio.

handbook, full pagewidth

10 kΩ

to AD

11

10

01

10 kΩ

OA3

OA1

AIN1_L 87

CD player

left

00

1

0

60

kΩ

aic1[1:0] = 00

1

0

ground

CD player

cable

1

0

AIN1_REF 88

VREFAD 93

s1 = 0

intref1 = 0

refc1 = 0

1 MΩ

60

kΩ

0

1

MIDREF

10 kΩ

AIN1_R 89

CD player

left

00

10 kΩ

to AD

01

10

11

10 kΩ

OA4

OA2

MGW198

off-chip

on-chip

Fig.8 Example of the use of common mode analog input AIN1.

21

2003 Nov 18

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

6.2.3

REALIZATION OF THE DIFFERENTIAL ADIFF INPUT

The ADIFF input is fully differential. The signal that is connected to this input should be a symmetrical signal.

Besides bits aic1[1:0] and aic2[1:0], to select the ADIFF_L and ADIFF_R input, the switches s1 and s2 are needed to put

the ADIFF_L and ADIFF_R inputs in true differential mode (see Fig.9).

handbook, full pagewidth

10 kΩ

ADIFF_LN 98

ADIFF_LP 97

to AD

11

10

01

00

10 kΩ

OA3

OA1

1

0

aic1[1:0] = 10

1

0

1

0

s1 = 1

AIN1_REF 88

VREFAD 93

intref1 = 0

refc1 = 0

MIDREF

0

1

10 kΩ

00

01

10

11

10 kΩ

to AD

ADIFF_RP 99

ADIFF_RN 100

10 kΩ

OA4

OA2

MGW199

off-chip

on-chip

Fig.9 Example of the use of differential analog input ADIFF_L and ADIFF_R.

2003 Nov 18

22

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

6.2.4

REALIZATION OF THE AUXILIARY INPUT WITH VOLUME

CONTROL

0 to −22.5 dB in 1.5 dB steps. The attenuated signal can

be added to the left and/or right front and/or left and/or right

rear DAC channels. When the mix signal is added to the

output, the gain of the output is automatically adjusted to

prevent clipping at high input levels.

A common mode input with volume control for mixing with

four DAC outputs is provided (see Fig.10). The inputs

consist of pins MONO1_P and MONO2_P, both

accompanied with their ground signals (pins MONO1_N

and MONO2_N). After selection of MONO1 or MONO2,

with bit mixc, the volume can be changed from

The inverse output signal of both CMRR circuits can also

be switched to the AUDIOAD_1 and/or AUDIOAD_2

and/or AUXAD_2.

handbook, full pagewidth

off-chip

on-chip

AUDIOAD_1 or

AUDIOAD_2 or

AUXAD_2

AUDIOAD_1 or

AUDIOAD_2 or

AUXAD_2

volmix[5:2]

R = 60 kΩ

R

rlm = 1

rrm = 1

flm = 1

frm = 1

R

MONO1_P

MONO1_N

2

3

R

volmix[1:0]

0

1

R

MONO2_P

MONO2_N

4

5

R

mixc

Midref

VREFAD 93

MGW200

Fig.10 MONO input circuit.

Table 8 Mix volume control

I²C-BUS BIT

OUTPUT MIX GAIN (dB)

I²C-BUS BIT

volmix[5:0] (hex)

OUTPUT MIX GAIN (dB)

volmix[5:0] (hex)

17

13

0F

0E

0D

0C

00

−15.0

−16.5

−18.0

−19.5

−21.0

−22.5

MUTE

3F

3B

37

33

2F

2B

27

23

1F

1B

0

−1.5

−3.0

−4.5

−6.0

−7.5

−9.0

−10.5

−12.0

−13.5

The bits volmix[5:2] are binary weighted organized and

used for setting the mixer gain from 0 to −18 dB. The

selection bits are connected to the mixer in the QSDAC.

2003 Nov 18

23

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

The bits volmix[1:0] are also binary weighted organized

and connected to the analog front-end.

6.2.5.2

Reference pin VREFAD

The midref voltage of the ADCs is filtered via this pin. This

midref voltage is used for half supply reference of the

ADCs. External capacitors (connected to groundplane)

prevent crosstalk between the switched capacitor DACs of

the internal ADCs and buffers and improves the power

supply rejection ratio of all components (see Fig.11).

The MIX signal can be added to all outputs independant of

each other.

Table 9 Mix output control; note 1

I²C-BUS BIT

BIT VALUE

DAC OUTPUT

V

_VADCP– V_VADCN

=

---------------------------------------------

V_VREFAD

2

FL

FR

RL

RR

ﬂm

frm

rlm

rrm

0

1

0

1

0

1

0

1

off

on

X

off

on

X

handbook, halfpage

VADCP

X

off

on

X

off

on

VREFAD

X

Note

MGW201

VADCN

1. X = not controlled by this bit.

6.2.5

SUPPLIES AND REFERENCES

6.2.5.1

Reference pins VADCN and VADCP

Fig.11 VREFAD reference circuit.

Analog supply inputs

These pins are used as a negative and positive reference

for the AUDIOAD_1 and AUDIOAD_2 and the level ADC.

These references needs to be “clean”.

6.2.5.3

The analog input circuit has separate power supply

(V_DDA1) connections to allow maximum filtering. The input

stage of every operational amplifier within the analog

front-end is supplied by a 3.3 V supply voltage so as to

enable a rail-to-rail input signal.

2003 Nov 18

24

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

6.3

AD decimation paths (DAD)

The DAD block consists of a Level Decimation Filter (LDF)

which handles the AUX decimation and an Audio

Decimation Filter (ADF) which handles the AUDIO

decimation.

The AD decimation paths for both the level and audio are

achieved in the DAD block; (see Fig.12). There are two

DAD blocks implemented for the SAA7724H.

handbook, full pagewidth

LDF

aux(n)_sel_lev_voice

1-BIT CODE

FILTER

ADF

1-BIT CODE

FILTER

CEAD

INTERFACE

CEAD

BLOCK

CONTROLLER

MGW202

ch(n)_dc_offset

(n) is 1 or 2.

Fig.12 DAD block diagram.

6.3.1

LDF AND AUX DECIMATION PATH

between the level characteristic and the audio

characteristic for voice input.

The input signal has a sample frequency of 128 × f_sand

comes from a 1st-order ADC. The first part of the

decimation is done using a CIC filter. For the AUX

decimating filter a 2nd-order CIC filter is implemented.

The transfer characteristics, level and audio, of the AUX

decimation filter are illustrated in Fig.13. It should be noted

that the figure corresponds with a 38 kHz sample rate. For

the SAA7724H a 42.1875 kHz sample rate is used, the

horizontal values need to be scaled with a factor of

A branch is also available from this filter for a signal having

a sample frequency of 8 × f_s. This signal also passes a

built-in high-pass filter section to make it adequate for level

IAC detection purposes. With a sampling frequency of

8 × 42.1875 kHz the −3 dB point of this filter is at

approximately 60 kHz.

42.1875

---------------------

38

Remark: The absolute gain or attenuation of the graphs in

Fig.13 has no meaning. The relative levels however have.

When bit aux1_sel_lev_voice or aux2_sel_lev_voice is

logic 1, the coefficient for audio processing is active.

When bit aux1_sel_lev_voice or aux2_sel_lev_voice is

logic 0, the coefficient for level processing is selected.

The CIC filter decimates the sample frequency by 64. The

sinx

new output sample rate is 2 × f_s. The

roll-off of the

-----------

x

CIC filter needs to be compensated for, therefore, a roll-off

compensation filter is utilized.

The last stage of the AUX decimation filter is the realization

of the appropriate bandwidth characteristic. The bits

aux1_sel_lev_voice and aux2_sel_lev_voice selects

2003 Nov 18

25

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

MGW203

80

handbook, full pagewidth

G

audio

characteristic

(dB)

40

0

−40

−80

80

40

level

characteristic

0

−40

−80

0

10000

20000

30000

40000

50000

60000

70000

80000

f (Hz)

Fig.13 AUX decimation path transfer characteristics.

6.3.2

ADF AND AUDIO DECIMATION PATH

6.4

Digital audio input/output

The input signal has a sample frequency of 128 × f_sand

comes from a third order sigma delta ADC. The first step

in the decimation process is done by the 1-bit code (CIC)

filter. This CIC filter decimates the input sample rate by a

factor of 16, which results in a sample rate of 8 × f_s.

This section describes the external I²S-bus input/output

ports, the EPICS host I²S-bus port and the SPDIF inputs.

6.4.1

GENERAL

There are two external I²S-bus input/output ports available

on the circuit, and three host I²S-bus ports. The I²S-bus

inputs and host I²S-bus outputs are capable of handling

Philips I²S-bus, and LSB-justified formats of

16, 18, 20 and 24-bit word sizes. The external I²S-bus

output ports only support Philips I²S-bus. For the general

waveforms of the five possible formats see Fig.14. More

general information on the Philips I²S-bus format is given

in Chapter 12.

After the 1-bit code filter, sample rehashing is necessary

prior to entering the CEAD block. The CEAD block

decimates the audio samples further by a factor of 8,

resulting in a sample rate of 1 × f_s. The overall gain in the

pass-band of the decimation filter, including the CIC filter

and CEAD block becomes 4.85 dB. A nominal input level

of −7.36 dB coming from the ADC will result in a −2.5 dB

level after decimation.

The DC filter in the CEAD block is controlled by I²C-bus bit

ch1_dc_offset or ch2_dc_offset; see Table 27. There is no

power-on reset circuitry implemented. This means that

after power-up, all filters will go through a fast transient

phase before they reach their steady state behaviour.

Note: When the applied word length is smaller than

24 bits, the LSB bits will get (internally) a zero value. When

the applied word length exceeds 24 bits, the LSBs are

skipped.

2003 Nov 18

26

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

EXTERNAL I²S-BUS INPUT/OUTPUT PORTS

6.4.2.1

SRC audio signal ﬂows

6.4.2

An I²S-bus interface is provided for communication with

external digital sources. It is a serial 3-line bus, having one

line for data, one line for clock and one line for the word

select. For external digital sources the circuit acts as a

slave, so the external source is master and supplies the Bit

Clock (BCK) and Word Select (WS).

Figure 16 shows the audio signal flow possibilities for the

sample rate converters SRC1 and SRC2. The inputs to the

SRCs can be either an external source, or an internal

signal from the AUDIO_EPICS.

The outputs from the SRCs can either work as a slave

output from an externally connected bus to an external

I²S-bus Port 1 or 2, or it can convert the internal

SAA7724H sample rate directly to the AUDIO_EPICS and

the switchboard in the IFP. If conversion to an external

sample rate is selected, the audio signals to the IFPs

switchboard and the AUDIO_EPICS are muted, while their

sample rates are maintained at the internal SAA7724H

sample rate.

Figure 15 shows the external I²S-bus receiver and

controls.

Table 10 defines the possible modes that must be set for

the I²S-bus inputs.

An extra function that is provided is that the EXT_IIS ports

can also be set, as an output, from the Sample Rate

Converters (SRC). In this event only the Philips I²S-bus

format is supported.

All I/O possibilities of the SRCs can be set by eight

independent I²C-bus bits. Some selections are conflicting

or make no sense. In order to keep as much flexibility as

possible there is no detection of conflicting settings,

however the circuitry is guaranteed not to cause a hang-up

situation.

handbook, halfpage

EXT_IIS_BCK(n)

2

I S-BUS

EXT_IIS_WS(n)

to SRC

All audio paths to and from the SRCs are 24 bits wide.

Inside the switchboard from the IFP, the audio is always

truncated to 16 bits.

RECEIVER

EXT_IIS_DATA(n)

3

MGW205

ext_host_io_format(n)[2:0]

(n) is 1 or 2.

Fig.15 External I²S-bus input and controls.

Table 10 External I²S-bus input formats

ext_host_io_format1 [2:0]

FORMAT

ext_host_io_format2 [2:0]

0

1

X⁽¹⁾

0

X⁽¹⁾

0

Philips I²S-bus

LSB -justiﬁed 16 bits

LSB-justiﬁed 18 bits

LSB-justiﬁed 20 bits

LSB-justiﬁed 24 bits

0

1

0

1

Note

1. X = don’t care.

2003 Nov 18

28

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

EXT_IIS_IO1

22

EXT_IIS_IO2

25

handbook, full pagewidth

src1_ext_sel_out

OUT1

SRC1

14

22

IN1

SPDIF1

OUT1

IN1

EXT_IIS_IO1

src1_int_ext_in

src2_int_ext_in

src1_int_ext_out

sel_SPDIF1_IIS1

IFP_SWB

AUDIO_EPICS

IN2

sel_SPDIF2_IIS2

25

src2_int_ext_out

SRC2

EXT_IIS_IO2

SPDIF2

15

IN2

OUT2

src2_ext_sel_out

22

25

MGW206

EXT_IIS_IO1

EXT_IIS_IO2

Fig.16 SRC audio signal flows.

6.4.2.2

Sampling frequency range limitations

6.4.3

EXTERNAL SPDIF INPUT

The external I²S-bus inputs are guaranteed for a

continuous 8 kHz to 48 kHz sampling frequency range.

A signal can be applied to one or both of the SPDIF inputs

that conforms to the IEC 60958 specification.

The SPDIF receivers support SPDIF audio data up to

24 bits. Some channel status bits are also decoded and

made available to the system.

6.4.2.3

BCK and WS limitations

The rate at which the I²S-bus receivers decode data

available to the system, depends on the WS frequency.

For normal application only 1 × f_sis used. The WS duty

cycle does not need to be 50 % for any of the applied

formats.

There is no support for user data decoding, nor availability

of the validity bit.

Figure 17 shows the SPDIF receiver and its outputs. The

exact meaning of the output bits is given in Table 30. The

SPDIF inputs do not have any specific control signals.

The BCK is limited to a maximum frequency of 256 × f_s.

The lower limit is defined by the number of bits that are

required to be sent. For LSB-justified formats the number

of BCKs must be at least the number of bits that is selected

per channel.

2003 Nov 18

29

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

handbook, full pagewidth

off chip

on chip

Audio to SRC

LOCK

14 or

15

SPDIF

RECEIVER

SPDIF(n)_content

SPDIF(n)_emphasis

SPDIF(n)_fs

SPDIF(n)

channel

status

bits

2

SPDIF(n)_accuracy

MGW207

(n) is 1 or 2.

Fig.17 SPDIF receiver and its outputs.

6.4.3.1

SPDIF input application diagram

Figure 18 shows the general set-up for an SPDIF input for consumer applications.

Figure 19 shows an example of how to prevent crosstalk from two adjacent SPDIF inputs, due to the parasitic

capacitance from lead finger and bond wires. Therefore extra capacitors are added near the pins.

handbook, halfpage

100 nF

SPDIF input

100 pF

75 Ω

MGW208

Fig.18 General SPDIF input application.

handbook, full pagewidth

100 nF

SPDIF1 14

100 pF

75 Ω

100 nF

SPDIF2 15

100 pF

leadfinger/bondwire

capacitor

75 Ω

MGW209

Fig.19 Example of crosstalk prevention for SPDIF inputs.

30

2003 Nov 18

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

6.4.3.2

Sampling frequency range limitations

6.4.3.4

Lock indicator

The external SPDIF input sample rates are 32, 44.1 and

48 kHz.

The SPDIF receiver has a LOCK pin. The polarity is

described in the I²C-bus map. When the system is not in

lock, the audio data will be muted (being zero data values).

In the event that the SPDIF signal is missing or very

distorted, the timing information to the SRC from the

SPDIF receiver will not be good or may even disappear.

This will cause the SRC to get unlocked.

The accuracies of the supported standardized sampling

frequencies at the SPDIF inputs meets the requirements of

Level II accuracy as specified in IEC 60958, being 0.1 %.

6.4.3.3

Channel status bits

Locking will occur within 5 ms after reset, or 5 ms after the

availability of a proper SPDIF signal at the input.

The channel status bits given in Table 11 are available

from the SPDIF receiver. The information is taken from the

left audio channel.

The lock indicator is available at one of the EPICS status

flags, and thus also readable via the I²C-bus. The exact

location is given in Table 25.

The channel status bits are available in the I²C-bus map,

where the exact meaning of the bits can also be found; see

Table 30.

6.4.4

EPICS HOST I²S-BUS PORT

Because this is a master I/O port the EPICS host I²S-bus

generates its own WS and BCK. There is one WS and

BCK for all three output and input data paths. The

definition of how the WS and BCK are generated can be

found in Chapter 11. Figure 20 shows the EPICS host

I²S-bus I/O and controls.

Table 11 SPDIF channel status bits

CHANNEL

STATUS BIT

NUMBER

CONSUMER FORMAT MEANING

1

data/audio mode

pre-emphasis

3

The EPICS host I²S-bus has its own setting for selecting

the formats; see Table 12. The setting of the EPICS rate

should be taken into account, for setting the desired host

I²S-bus format. The LSB-justified formats

25 and 24

29 and 28

sampling frequency

clock accuracy

18, 20 and 24 bits are not available when the EPICS is

running at a rate other than 1 × f_s.

handbook, halfpage

on chip

off chip

27

IIS_IN1

IIS_IN2

IIS_IN3

28

29

to EPICS

37

36

2

I S-BUS

IIS_WS

TRANSCEIVER

IIS_BCK

30

31

32

IIS_OUT1

IIS_OUT2

IIS_OUT3

from EPICS

3

MGW210

host_io_format[2:0]

Fig.20 EPICS host I²S-bus with controls.

31

2003 Nov 18

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

Table 12 External EPICS host I²S-bus formats

host_io_format2 host_io_format1 host_io_format0

FORMAT

0

1

X⁽¹⁾

0

X⁽¹⁾

0

Philips I²S-bus

LSB-justiﬁed 16 bits

0

1

LSB-justiﬁed 18 bits; note 2

LSB-justiﬁed 20 bits; note 2

LSB-justiﬁed 24 bits; note 2

1

0

1

Notes

1. X = don’t care.

2. Not supported for EPICS rates other than 1 × f_s.

6.5

Sample rate converter

There are two Sample Rate Converters (SRCs) available in the SAA7724H. The input of each SRC can be an external

source or internal audio from the AUDIO_EPICS. The outputs are fed to the IFPs switchboard and the AUDIO_EPICS

or to an external I²S-bus port; see Section 6.4.2.1.

Both SRCs meet the requirements given in Table 13.

Table 13 SRC speciﬁcation

SRC CHARACTERISTIC

SPECIFICATION

Input sample rate

continuously 8 kHz to 48 kHz; absolute accuracy 0.1 %

Output sample rate

continuously 8 kHz to 48 kHz

≥ 96 dB at 1 kHz

0 dB

THD + N

Overall gain

Maximum ripple amplitude (0 to 0.45 f_s)

Stop band suppression (0.55 f_sto 1 f_s)

Output word width

0.1 dB

≥ 98 dB

24 bits

Lock time

≤ 45 ms

Audio during unlocked state

muted (zero data)

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SAA7724H

6.6

IF_AD

The IF_AD performs the analog-to-digital conversion of the FM/AM-IF signal. It generates 10-bit data. For dual radio two

IF_AD convertors are incorporated (see Fig.21).

handbook, full pagewidth

off chip

IF_IN1

on chip

82

IF_IN

IF_AD_OUT

DITHER_GAIN

DIT_IN

IF_AD_OUT1

dith_gain_1

DIT_IN1

IF_VG

V

DD(IF)

IF_AD1

VREFIF

IF_AD_CLK

V

SS(IF)

84

IF_IN2

IF_IN

IF_AD_OUT

DITHER_GAIN

DIT_IN

IF_AD_OUT2

dith_gain_2

DIT_IN2

83

81

80

79

IF_VG

DD(IF)

IF_VG

V

DD(IF)

IF_AD2

VREFIF

IF_AD_CLK

V

IF_AD_CLK

V

SS(IF)

MGW211

Fig.21 IF_AD dual block diagram.

6.6.1

IF_AD SINGLE BLOCK DIAGRAM

The IF_AD block diagram shows the analog part. It consists of a buffer and dither block and a two-step ADC.

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SAA7724H

6.6.2

IF_AD DETAILED FUNCTIONAL DESCRIPTION

The IF_AD consists of several blocks. These blocks are the ADC itself preceded by a buffer and dither differential

summing point. The dither is made with a dither DAC (DIT_DAC) combined with gain variation in G_DAC. The interface

to the IFP is fed via the registers shown in Fig.22.

handbook, full pagewidth

off-chip

on-chip

BUFFER AND DITHER

82,

84

R1

IF_IN(n)

234 Ω

10

kΩ

Rdit

10

DIT_IN(n)

bd0

kΩ

V

81

DD(IF)

DIT_DAC

bd7

234

Ω

234

Ω

234

Ω

I

R1

R2

g

dith_gain_(n)

0

IF_VG 83

4-BIT G_DAC

3

V

SS(IF) 79

IF_AD_CLK

IF_AD_OUT(n)

b0

b1

b2

b3

b4

b5

b6

b7

b8

b9

TWO STEP ADC

MGW212

(n) is 1 or 2.

Fig.22 IF_AD single block diagram; analog part.

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Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

6.6.2.1

ADC

The I²C-bus registers, some of which are mapped onto

XMEM address space, are shown in Chapter 11.5,

Tables 21 to 23.

The ADC is based on the two-step principle.

6.6.2.2

Buffer

6.7.1

AUDIO_EPICS START-UP

The buffer is configured as a single-ended to differential

convertor.

The AUDIO_EPICS will start running the code after the

reset procedure has been completed. This code will start

running from address 0 by default, if not reprogrammed by

the user before releasing the pc_reset bit.

6.6.2.3

Dithering

Dither can be applied via the dither DACs DIT_DAC and

G_DAC. The input voltage range and the dither level are

both proportional to the supply voltage.

6.7.2

AUDIO_EPICS MEMORY OVERVIEW

The memory sizes for the AUDIO_EPICS are given in

Table 14.

DIT_DAC is driven by the IFP. The source is an 8-bit word

having 9 values representing −4 (00000000)

to +4 (11111111). The total number of 1s in the 8-bit input

word represent the code that the DIT_DAC is using. The

maximum negative output voltage is represented by all 0s

on the 8-bit word, and the maximum positive output

voltage is represented by all 1s on the 8-bit word. A

nominal value of 0 V, which is half way between the

maximum positive output voltage and the maximum

negative output voltage at the output of the DIT_DAC, is

represented by setting any four of the eight bits to logic 1

and the other four bits to logic 0.

Table 14 AUDIO_EPICS memory list

MEMORY TYPE

DSP program memory

DSP X memory

PRODUCT VERSION

ROM: 5120 words

RAM: 3584 words

RAM: 1024 words

DSP Y memory

6.8

SDAC output path

There are two SDACs implemented in the SAA7724H, one

for the front channels (SDAC_F) and one for the rear

channels (SDAC_R).

To adjust the G_DAC dither to the required level, the

multiplying current of the DIT_DAC can be changed with a

binary weighted current DAC. The reference current is

derived from an internal reference source which is

proportional to V_DD(IF). As a reference point for the

equivalent input dither level, at nominal supply voltage, the

following equation is used:

The total digital-to-analog conversion path, consists of the

following components (see Fig.23):

1. An upsample filter

2. A 3rd-order noise shaper

3. A compensation and dynamic element matching

(CoDEM) scrambler

V_ditppeq= 3.7 × ditgain (mV).

4. The multibit SDAC with current compensation.

6.7

AUDIO_EPICS speciﬁc information

All circuitry including the analog part use a 128 × f_sclock.

This chapter contains specific additional information, over

the EPICS7A programmers guide, specifically for the

SAA7724H.

UPSAMPLE FILTER

NOISE SHAPER

CODEM

MULTIBIT DAC

handbook, full pagewidth

1

0

1

0

1f

128f

s

MGW213

Fig.23 SDAC path diagram.

35

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Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

6.8.1

DAC UPSAMPLING FILTER

Element Matching (DEM) algorithm. Thirdly, by using this

code, matching errors in the analog part of the SDAC have

less influence on the performance. The CoDEM also

generates a compensation vector for the compensation

part of the DAC.

The upsampling filter interpolates a 24-bit stereo signal

from 1 × f_sto 8 × f_sby cascading two half-band FIR filters.

Interpolating to 128 × f_sis done by a sample-and-hold

filter.

6.8.4

MULTI-BIT SDAC

6.8.2

DAC NOISE SHAPER

The SDAC is a multi-bit DAC based upon 31 switched

resistors. The 31 resistors form a network which can

create 32 DC output levels. The exact analog output level

is the sum of the DC level and the superimposed bitstream

signal. In the application a simple low-pass filter (one

capacitor) must be used at the outputs of the SDAC.

A 3rd-order noise shaper is used to quantize the 24-bit

input signal that is fed from the upsampling filter into a 5-bit

output signal. The generated quantization noise is shaped

outside the audio band.

6.8.3

DAC CODEM SCRAMBLER

The overall DAC filters spectral plot is illustrated in Fig.24.

The CoDEM scrambler has three different functions.

Firstly it converts the 5-bit signal from the noise shaper into

a thermometer code. Secondly, after conversion, the

thermometer code is scrambled by means of a Dynamic

As an example a left filtered output is selected, which also

has a 3.3 nF output filtering capacitor connected.

MGW214

0

handbook, full pagewidth

α

(dB)

filter

−25

−50

left_filtered

−75

−100

−125

−150

−175

−200

20

100

1 k

10 k

100 k

1 M

3 M

f (Hz)

Fig.24 DAC filters spectral diagram.

6.8.5

ANALOG SUMMER FUNCTION

The SDAC is featured with the analog summing of signals from the ADCs; for details of this function see Chapter 6.2.

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Car radio digital signal processor

SAA7724H

6.8.6

SDAC APPLICATION DIAGRAM

An example of the circuitry surrounding the DAC outputs is illustrated in Fig.25.

handbook, full pagewidth

47 µF

3.3 nF

LFV

12

47 µF

3.3 nF

RFV

11

SAA7724H

47 µF

3.3 nF

LRV

7

47 µF

3.3 nF

RRV

6

8

9

10

VDACP

VDACN

100 nF

V

DDA2

100 µF 100 nF

47 µF

MGW215

Fig.25 DAC outputs application diagram.

6.9

Reset block functional overview

6.10 Clock circuit and oscillator

The reset block uses the asynchronous reset signal from

pin RESET to generate synchronous reset signals. The

generated reset signals are described in the following

sections.

6.10.1 CIRCUIT DESCRIPTION

The chip has an on-board crystal clock oscillator with

amplitude control based on a Pierce oscillator; see Fig.26.

The oscillator is implemented as an inverter with

capacitive coupling at the input. When the

transconductance of this inverter is sufficiently high, the

feedback loop becomes unstable and the circuit starts to

oscillate.

6.9.1

ASYNCHRONOUS RESET

The asynchronous reset signal from pin RESET

asynchronously disables the SDA pin (set HIGH)

whenever the reset signal is active.

This oscillation grows until its amplitude has reached a

specific value which is detected by the AGC. In this way,

clipping of the output voltage against the supply voltages

is prevented. The AGC also ensures that the

transconductance builds up very rapidly after power-on

and stays sufficiently high during oscillation.

Furthermore, all 3-state and bidirectional outputs are kept

3-state asynchronously as long as pin RESET is kept

LOW, and the internal reset sequence is still ongoing. It

requires approximately 1100 OSCIN_CLK cycles to

complete the reset sequence after the RESET pin has

gone HIGH. After reset the state of the SAA7724H will be

as specified in Table 2.

The sinusoidal output is converted into a CMOS

compatible clock by the comparator.

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Car radio digital signal processor

SAA7724H

handbook, full pagewidth

AGC

Gm

R

CLKOUT

78

bias

on-chip

XTAL1

XTAL2

77

100 kΩ

76

OSC_IN

75

OSC_OUT

V

SS(OSC)

DD(OSC)

off-chip

L1

2.2 µH

Cx1

15 pF

Cx2

15 pF

C3

10 nF

MGW224

Fig.26 Schematic diagram of the crystal oscillator circuit.

6.10.2 EXTERNAL CLOCK INPUT MODE

6.10.4 APPLICATION GUIDELINES

It is possible to use the oscillator as a clock input. In

external clock input mode, an external clock signal is input

on pin OSC_IN and this clock signal is transferred to the

output via an extra output inverter stage. In this mode, the

quartz crystal, L1, Cx2 and C3 may be removed, but this is

not obligatory.

For correct operation of the oscillator, two load capacitors

(Cx1 and Cx2) need to be added externally to the chip.

This configuration is adequate for the required crystal

frequency of 43.2 MHz.

The external components shown in Fig.26 are specified in

Table 15. The use of other values may prevent the

oscillator from start-up.

6.10.3 CRYSTAL OSCILLATOR SUPPLY

A quartz crystal oscillator is used to generate the clock

signal CLKOUT. In the case of an overtone oscillator, the

ground harmonic is filtered out by L1 and Cx2.

The power supply connections to the oscillator are

separated from the other supply lines to minimize

feedback from on-chip ground bounce to the oscillator

circuit. Noise on the power supply affects the AGC

operation therefore the power supply should be

decoupled. The V_SS(OSC)pin is used as ground supply and

the V_DD(OSC)as the positive supply.

A quartz crystal should be used with a series resonance

resistance of less than 80 Ω and a capacitance of less than

7 pF. The crystal should be manufactured for a load

capacitance of 10 pF. The value of C3 is not critical as long

as it is not much lower than 10 nF (10 % is accurate

enough). There is no theoretical upper limit.

Table 15 External components speciﬁcation for the crystal oscillator

COMPONENT

MIN.

TYP.

MAX.

UNIT

Cx1

Cx2

C3

13.5

9

15.0

10

16.5

−

pF

nF

µH

L1

1.98

2.2

2.42

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Car radio digital signal processor

SAA7724H

6.11 PLL circuits

The RDS demodulator regenerates the raw RDS bitstream

(bit rate = 1187.5 Hz) from the modulated RDS signal in

two steps. The first step is the demodulation of the double

sideband suppressed carrier signal around 57 kHz into a

baseband signal, by carrier extraction and down-mixing.

The second step is the Binary Phase Shift Key (BPSK)

demodulation of the biphase coded baseband signal, by

clock extraction and correlation.

In the SAA7724H two PLL circuits (PLL1 and PLL2) are

available that deliver the clocks for the AUDIO_EPICS and

the SRC_EPICS block.

6.12 RDS

In the SAA7724H there are two RDS demodulation and

decoder systems available. The description applies to

each of the RDS blocks.

The RDS/RBDS decoder provides block synchronization,

error detection, error correction, complex flywheel function

and programmable block data output. Newly processed

RDS/RBDS block information is signalled to the main

microcontroller as ‘new data available’ using the DAVN

output. The block data itself and the corresponding status

information can be read out via an I²C-bus request.

6.12.1 GENERAL DESCRIPTION

The RDS function recovers the additional inaudible RDS

information which is transmitted by FM radio broadcasting.

The operational functions of the demodulator and decoder

are in accordance with EBU specification EN 50067.

The RDS/RBDS decoder contains the following major

functions needed for RDS/RBDS data processing:

The RDS function processes the RDS signal, that is

frequency multiplexed in the stereo-multiplex signal, to

recover the information transmitted over the RDS data

channel. This processing consists of band-pass filtering,

RDS demodulation and RDS/RBDS decoding.

• RDS and RBDS block detection

• Error detection and correction

• Fast block synchronization

• Synchronization control (flywheel)

• Mode control for RDS/RBDS processing

The stereo-multiplex signal is input from the IFP. Under

control of I²C-bus bit rds_clkin, an internal buffer can be

used to read out the raw RDS stream in bursts of 16 bits.

With the I²C-bus bit rds_clkout the RDS clock can be

enabled or switched off. The RDS band signal level can be

read from a memory location in the SRC_EPICS, which

needs to be defined.

• Different RDS/RBDS block information output modes

(e.g. A/C’ block output mode).

External decoding of the raw RDS bitstream, would require

a microcontroller interrupt every 842 µs. The double 16-bit

RDS buffer allows the RDS data to be monitored at a

16 times lower rate, i.e. every 13.5 ms.

The RDS band-pass filter discards the audio content from

the input signal and reduces the bandwidth.

The RDS band signal level detector removes a possible

Autofahrer Rundfunk Information (ARI) signal from the

RDS band-pass filter output and measures the level of the

remaining signal.

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SAA7724H

handbook, full pagewidth

RDS(n)_CLK

RDS(n)_DATA

rds(n)_clkout

DECODER_BYPASS_MUX

rds(n)_clkin

0

1

SRC_EPICS

BSLP

BSPA

RDCL

STEREO-

MPX

RDS

BAND-PASS

FILTER

DEMODU-

LATOR

RDS/RBDS

DECODER

0

1

RDDA

+

(RBDS )

MGW216

RDS_BUF_MUX

BIT

BUFFER

(n) is 1 or 2.

Fig.27 RDS/RBDS functional block diagram.

6.12.2 RDS I/O MODES

• RDS_CLK: burst clock generated by the microcontroller.

Bursts of 17 clock cycles are expected. The average

time between bursts is 13.5 ms.

Apart from control inputs and data outputs via the I²C-bus,

the following inputs and outputs are related to the RDS

function.

• RDS_DATA: bursts of 16 raw RDS bits are output under

control of the burst clock input. After a data burst, this

output is HIGH. It is pulled LOW when 16 new bits are

made available and a new clock burst is expected. The

microcontroller has to monitor this line at least every

13.4 ms.

Unbuffered raw RDS output mode (rds1_clkin = 0,

rds2_clkin = 0, rds1_clkout = 1, rds2_clkout = 1 and

DAVD mode: dac0 = 1 and dac1 = 1):

• RDS_CLK: clock of the raw RDS bitstream, extracted

from the biphase coded baseband signal by the RDS

demodulator. A clock period of 1.1875 kHz and 50 %

duty cycle. The positive edge can be used to sample the

RDS_DATA output.

DAVA, DAVB and DAVC modes (rds1_clkin = 0,

rds2_clkin = 0, rds1_clkout = 0 and rds2_clkout = 0):

• DAVN: data available signal for synchronization of data

request between main controller and decoder; see

Section 6.12.5.11.

• RDS_DATA: raw RDS bitstream, generated by the

demodulator detection of a positive going edge on the

RDCL input signal. The data output changes every

100 µs (this equals ¹⁄₈of the RDS_BCK period) after the

falling edge of RDS_BCK. This allows for external

receivers of the RDS data to clock the data on the

RDS_BCK signal as well as on its inverse.

rds1_clkin = 1, rds2_clkin = 1, rds1_clkout = 1 and

rds2_clkout = 1 is a not allowed mode.

As shown in Fig.27, the same output is used for

RDS_DATA and DAVN, depending on the selected mode.

Buffered raw RDS output mode (rds1_clkin = 1,

rds2_clkin = 1, rds1_clkout = 0, rds2_clkout = 0 and

DAVD mode: dac0 = 1 and dac1 = 1):

6.12.3 RDS DEMODULATOR

Phase jumps of the extracted RDS clock are detected and

accumulated. If the accumulated phase shift exceeds a

certain threshold, the RDS/RBDS decoder is informed by

the bit slip (BSLP) signal. If the RDS/RBDS decoder

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

detects a bit slip, the RDS demodulator is informed by the

bit slip acknowledge (BSPA) signal. This causes the

accumulation of RDS clock phase shifts to be cleared.

• Bit slip correction

• Data processing control

• Restart of synchronization mode

• Error correction control mode for synchronization

• Data available control modes

6.12.4 RDS BIT BUFFER

The repetition frequency of RDS data is 1187.5 Hz. This

results in an interrupt on the microcontroller every 842 µs.

The double 16-bit buffer enables this timing requirement to

be relaxed.

• Data output of RDS/RBDS information.

The functions which are realized in the decoder are

described in detail in the following Sections.

The two 16-bit buffers are alternately filled. If a buffer is not

read out by the time the other buffer is filled, it will be

overwritten and the old data will be lost.

6.12.5.1 RBDS processing mode

The decoder is suitable for receivers intended for the

European (RDS) and the USA (RBDS) standard. If the

RBDS mode is selected (RBDS = 1) via the I²C-bus, the

block detection and the error detection and correction are

adjusted to RBDS data processing; i.e. E blocks are also

treated as valid blocks. If RBDS is reset to zero then RDS

mode is selected.

When a 16-bit buffer is being filled, the RDS bit buffer

keeps the data line HIGH.

If a 16-bit buffer is full, the data line is pulled down. The

microcontroller has to monitor the data line at least every

13.5 ms. The data line remains LOW until the

microcontroller pulls the clock line LOW. This initiates the

reading of the buffer and the first bit is output on the data

line. The RDS bit buffer outputs a bit on the data line after

every falling clock edge. The data is valid when the clock

is HIGH. After 16 falling and 16 rising edges, the whole

buffer is read out and the bits are stored by the

microcontroller. After a 17th falling clock edge, the data

line is set HIGH until the other 16-bit buffer is full. The

microcontroller stops communication by pulling the clock

line HIGH again.

6.12.5.2 RDS/RBDS block detection

The RDS/RBDS block detection is always active.

For a received sequence of 26 data bits, a valid block and

corresponding offset are identified using syndrome

calculation.

During a synchronization search, the syndrome is

calculated with every newly received data bit (bit-by-bit) for

a received 26-bit sequence. If the decoder is

6.12.5 RDS/RBDS DECODER

synchronized, syndrome calculation is activated only after

26 data bits for each new block are received.

The RDS/RBDS decoder handles the complete data

processing and decoding of the continuously received

serial RDS/RBDS demodulator output data stream (RDDA

and RDCL).

During RBDS reception, including the RDS block

sequences with (A, B, C/C’ and D) offset, block

sequences of 4 blocks with offset E may also be received.

If the decoder detects an ‘E-block’, this block is marked in

the block identification number (BlNr[2:0]) and is available

via an I²C-bus request. In RBDS processing mode the

block is signalled as valid ‘E-block’ and in RDS processing

mode, where only RDS blocks are expected, it is signalled

as invalid ‘E-block’.

Different data processing modes are software controllable

by the external main controller via an I²C-bus request. All

control signals are direct inputs to the decoder and are

also available via the I²C-bus.

Processed RDS/RBDS data blocks with corresponding

decoder status information are available via the I²C-bus.

The output signals of the decoder are direct outputs and

available via the I²C-bus.

This information can be used by the main controller to

detect ‘E-block’ sequences and identify RDS or RBDS

transmitter stations.

The RDS/RBDS decoder contains the following functions:

• RBDS processing mode

6.12.5.3 Error detection and correction

The RDS/RBDS error detection and correction recognizes

and corrects transmission errors within a received block

via parity-check in consideration of the offset word of the

expected block. Burst errors, with a maximum length of

5 bits, are corrected using this method; see Table 16.

• RDS/RBDS block detection

• Error detection and correction

• Synchronization

• Flywheel for synchronization hold

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SAA7724H

After synchronization has been detected the error

correction is always active, depending on the pre-selected

‘error correction mode for synchronization’ (mode SYNCA

to SYNCD), but cannot be carried out in every reception

situation.

reaches the pre-selected max_bad_blocks_gain, then the

bit-by-bit search for the first block is restarted.

If the RDS mode is selected then the next block is always

calculated from the sequence A-B-C or C’-D, because

E blocks are not allowed.

During a synchronization search, the error correction is

disabled for detection of the first block and is enabled for

processing of the second block, depending on the

pre-selected error correction mode for synchronization.

If the RBDS mode is selected additional E blocks are

allowed. However, while the synchronization search is

active the block sequence E-E is always invalid (no

synchronization will be found with E-E blocks in a row).

If the first correctly detected block is block E, then the next

expected block is block A; in this case no further expected

blocks will be calculated. The decoder waits for an A block

until the bad_blocks_counter value reaches the

pre-selected max_bad_blocks_gain or a valid A block is

received.

The processed block of data and the status of error

correction are available for data request, via the I²C-bus,

for the last two blocks.

Table 16 RDS processed error correction

EXB1 EXB0

DESCRIPTION

no errors detected

If the first correct detected block is block D (in RBDS

mode) then the next expected block will be block A. If the

next expected block is block A (in RBDS mode) then a

valid uncorrected block E is always allowed to be

synchronized. If both blocks A and E fail, the next

expected block calculated is block B and so on.

0

1

0

1

0

1

burst error of maximum 2 bits corrected

burst error of maximum 5 bits corrected

uncorrectable block

For the second block, error correction may also be

enabled, depending on the pre-selected correction mode

SYNCA to SYNCD. Only valid and/or correctable second

blocks are accepted for synchronization.

Processed blocks are characterized as uncorrectable

under the following conditions:

• During a synchronization search; if the burst error (for

the second block) is higher than allowed by the

pre-selected correction mode SYNCA to SYNCD

If the pre-selected max_bad_blocks_gain value is set to

zero, then (in this case only) the two-path synchronization

search function is active independent of the selected RDS

or RBDS mode. That is, if the first block was detected as a

valid block, then Path 1 is open and the next expected

block is calculated and stored.

• After synchronization has been detected; if the burst

error exceeds the correctable maximum 5-bit burst error

or if errors are detected but error correction is not

possible.

With each new received bit (bit-by-bit) syndrome

calculation is started again until a second valid block is

detected or 26 bits are received.

6.12.5.4 Synchronization

The decoder is synchronized if two valid blocks in a valid

sequence are detected by the block detector; see

Figs 8 and 9 for synchronization strategy overview.

If a second valid block was detected before 26 bits were

received, then Path 2 is open, the block position (bit

counter) is stored and the next expected block for Path 2

is calculated.

The search for the first block is done by a bit-by-bit

syndrome calculation, starting after the first 26 bits have

been received. This bit-by-bit syndrome calculation is

carried out until the first valid, and error free, block has

been received. The next block is then calculated and

syndrome calculation is done after the next 26 bits have

been received. The block-span in which the second valid

and expected block can be received is selectable via the

previous setting of the maximum bad blocks gain

(RDS2_MBBG[4:0] or RDS1_MBBG[4:0]). If the second

received block is an invalid block, then the

If 26 bits have been received (after the first block Path 1)

and the syndrome calculation gives the valid expected

block for Path 1, then synchronization is detected and

Path 2 is ignored.

If 26 bits have been received (after the first block Path 1)

and the syndrome calculation gives no validity or it is not

the expected block for Path 1, then Path 1 is set to Path 2

values (if Path 2 is active):

bit_count_path1 ≤ bit_count_path2 and

expected_block_path1 ≤ expected_block_path2. Path 2is

bad_blocks_counter is incremented and the next new

block is calculated. If the bad_blocks_counter value

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

then cleared and ready for new input, but only after

reception of the next few bits (until 26) may

synchronization be detected.

6.12.5.7 Data processing control

The decoder provides different operating modes

selectable by the NWSY, SYM0, SYM1, DAC0 and DAC1

inputs via the external I²C-bus. The data processing

control performs the pre-selected operating modes and

controls the requested output of the RDS/RBDS

information.

Thus using this Path 2 implementation a much faster

synchronization is given in cases of wrong block

interpretation of the first detected block.

If synchronization is detected, the synchronization status

flag (SYNC) is set and available via an I²C-bus request.

The synchronization is held until the bad_blocks_counter

value reaches the pre-selected max_bad_blocks_lose

value (used for synchronization hold) or an external restart

of synchronization is performed (NWSY = 1 or Power-on

reset).

6.12.5.8 Restart of synchronization mode

The ‘restart synchronization’ (NWSY) control mode

immediately terminates the actual synchronization and

restarts a new synchronization search procedure

(NWSY = 1). The NWSY flag is automatically reset after

the restart of synchronization by the decoder [NeW

SYnchronization Restart (NWSYRe pulse)].

6.12.5.5 Flywheel for synchronization hold

An internal flywheel is implemented to enable a fast

detection of loss of synchronization. Therefore one

counter (bad_blocks_counter) checks the number of

uncorrectable blocks and a second counter

(good_blocks_counter) checks the number of error free or

correctable blocks. Error blocks increment the

bad_blocks_counter value and valid blocks increment the

good_blocks_counter value. If the counter value of the

good_blocks_counter reaches the pre-selected

max_good_blocks_lose value (MGBL[5:0]) then the

good_blocks_counter and bad_blocks_counters are reset

to zero. However, if the bad_blocks_counter value

reaches the pre-selected max_bad_blocks_lose value

(MBBL[5:0]) then a new synchronization search (bit-by-bit)

is started (SYNC = 0) and both counters are reset to zero.

This mode is required for a fast new synchronization on the

RDS/RBDS data from a new transmitter station if the

tuning frequency is changed by the radio set.

Restart of a synchronization search is automatically

carried out if the internal flywheel signals a loss of

synchronization.

6.12.5.9 Error correction control mode for

synchronization

For error correction and identification of valid blocks during

a synchronization search and synchronization hold, four

different modes can be selected by control mode inputs

SYM1 and SYM0:

1. Mode SYNCA (SYM1 = 0 and SYM0 = 0): no error

correction; the blocks that are detected as correctable

are treated as invalid blocks, the internal

The flywheel function is only activated if the decoder is

synchronized. The synchronization is held until the

bad_blocks_counter value reaches the pre-selected

max_bad_blocks_lose value (loss of synchronization) or

an external forced start of a new synchronization search

(NWSY = 1) is performed. The maximum values for the

flywheel counters are both adjustable via the I²C-bus in a

range of 0 to 63.

bad_blocks_counter value is still incremented even if

correctable errors are detected. If synchronized, only

error free blocks increment the good_blocks_counter

value. All blocks except error free blocks increment the

bad_blocks_counter value.

2. Mode SYNCB (SYM1 = 0 and SYM0 = 1): error

correction of burst error maximum 2 bits; the blocks

that are corrected are treated as valid blocks, all other

errors detected are treated as invalid blocks. If

6.12.5.6 Bit slip correction

During poor reception situations phase shifts of one bit to

the left or right (±1-bit slip) between the RDS/RBDS clock

and data may occur, depending on the lock conditions of

the demodulators clock regeneration.

synchronized, error free and correctable maximum

2-bit errors increment the good_blocks_counter value.

3. Mode SYNCC (SYM1 = 1 and SYM0 = 0): error

correction of burst error maximum 5 bits; the blocks

that are corrected are treated as valid blocks, all other

errors detected are treated as invalid blocks. If

If the decoder is synchronized and detects a bit slip

(BSLP = 1), the synchronization is corrected by +1, 0 or

−1 bit via block detection on the respectively shifted

expected new block.

synchronized, error free and correctable maximum

5-bit errors increment the good_blocks_counter value.

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

4. Mode SYNCD (SYM1 = 1 and SYM0 = 1): no error

correction; the blocks that are detected as correctable

are treated as invalid blocks, if in synchronization

search mode. The internal bad_blocks_counter value

is always incremented even if correctable errors are

detected. If synchronized, error free blocks and

correctable maximum 5-bit errors increment the

good_blocks_counter value. Only uncorrectable

blocks increment the bad_blocks_counter value.

received before the previously processed block was

completely transmitted via the I²C-bus. After detection of

data overflow the interface registers are not updated (no

DecWrE) until reset of the data overflow flag (DOFL = 0)

by reading via the I²C-bus or if NWSY = 1 which results in

the start of a new synchronization search (SYNC = 0).

6.12.5.11 Data output of RDS/RBDS information

The decoded RDS/RBDS block information and the

current decoder status is available via the I²C-bus. For

synchronization of data request between the main

controller and decoder the additional data available output

(DAVN) is used. For timing information see Section 10.1.

6.12.5.10 Data available control modes

The decoder provides three different RDS/RBDS data

output processing modes plus one decoder bypass mode

which are selectable via the ‘data available’ control mode

inputs DAC1 and DAC0.

If the decoder has processed new information for the main

controller the data available signal (DAVN) is activated

(LOW) under the following conditions:

• Mode DAVA (DAC1 = 0 and DAC0 = 0): standard output

mode; if the decoder is synchronized and a new block is

received (every 26 bits), the actual RDS/RBDS

information of the last two blocks is available with every

new received block (approximately every 21.9 ms).

• During a synchronization search in DAVB mode if a valid

A or C’ block has been detected. This mode can be

used for fast search tuning (detection and comparison of

the PI code contained in the A and C’ blocks).

• Mode DAVB (DAC1 = 0 and DAC0 = 1): fast PI search

mode; during synchronization search and if a new

A or C’ block is received, the actual RDS/RBDS

information of this or the last two A or C’ blocks

respectively is available with every new received

A or C’ block. If the decoder is synchronized, the

‘standard output mode’ is active.

• During a synchronization search in any DAV mode

(except DAVD mode), if two blocks in the correct

sequence have been detected (synchronization criterion

fulfilled)

• If the decoder is synchronized and, in mode DAVA and

DAVB, a new block has been processed; this mode is

the standard data output mode

• Mode DAVC (DAC1 = 1 and DAC0 = 0): reduced data

request output mode; if the decoder is synchronized and

two new blocks are received (every 52 bits), the actual

RDS/RBDS information of the last two blocks is

available with every two new received blocks

(approximately every 43.8 ms).

• If the decoder is synchronized and, in DAVC mode, two

new blocks have been processed

• If the decoder is synchronized and, in any DAV mode

(except DAVD mode), loss of synchronization is

detected (flywheel loss of synchronization, resulting in a

restart of the synchronization search)

• Mode DAVD (DAC1 = 1 and DAC0 = 1): decoder

bypassed mode; if this mode is selected then the

OutMux output of the decoder is reset to LOW

(OutMux = 0). The MADRE internal row buffer output is

then active and the decoder is bypassed.

• In any DAV mode (except DAVD mode), if a reset

caused by power-on or a voltage drop is detected

(PresN = 0).

Remark: If the decoder is synchronized, the DAVN signal

is always activated after 21.9 ms in DAVA or DAVB mode

and after 43.8 ms in DAVC mode independent of valid or

invalid blocks being received.

The decoder provides data output of the block

identification of the last and previously processed blocks,

the RDS/RBDS information words and error

detection/correction status of the last two blocks together

with general decoder status information.

The processed RDS/RBDS data is available for an I²C-bus

request for at least 20 ms after the DAVN signal was

activated. The DAVN signal is always automatically

deactivated (HIGH) after ~10 ms or almost after the main

controller has read the RDS/RBDS status byte via the

I²C-bus (see DAVN timing).

In addition the decoder output is controlled indirectly by the

data request from the external main controller. The

decoder receives a ‘data overflow’ (DOFL) signal

controlled by the I²C-bus register interface.

This DOFL signal has to be set HIGH (DOFL = 1) if the

decoder is synchronized and a new RDS/RBDS block is

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

The decoder ignores new processed RDS/RBDS blocks if the DAVN signal is active or if data overflow occurs

(DOFL = 1).

Tables 17 and 18 show the block identification number and processed error status outputs of the decoder and how to

interpret the output data.

Table 17 RDS block identiﬁcation number

BLNR2

BLNR1

BLNR0

BLOCK IDENTIFICATION

0

1

0

1

0

1

0

1

0

1

0

1

0

1

block A

block B

block C

block D

block C’

block E (RBDS mode)

invalid block E (RDS mode)

invalid block

Table 18 RDS processed error correction

EXB1

EXB0

DESCRIPTION

0

1

0

1

0

1

no errors detected

burst error of maximum 2 bits corrected

burst error of maximum 5 bits corrected

uncorrectable block

6.12.5.12 Power-on reset

Reset of the chip will cause a number of I²C-bus registers to be set to specific default values; see Chapter 11.5.

If the decoder detects the reset, the status bit ‘reset detected’ (RSTD) is set and available via an I²C-bus request. The

RSTD flag is deactivated after the decoder status register is read by the I²C-bus.

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

7

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); note 1

SYMBOL

PARAMETER

supply voltage on pin V_DDD

supply voltage on pin V_DD(I/O)

CONDITIONS

MIN. TYP.

MAX.

+3.3

UNIT

V

V_DDD

−0.5

−

+2.5

+3.3

+2.5

−

V_DD(I/O)

+4.2

+3.3

750

10

V

V_DD(REG)supply voltage on pin V_DD(REG)

V

V_DDA

I_DDD

supply voltage on pin V_DDA

supply current pin V_DDD

supply current pin V_SSD

supply current pin V_DD(I/O)

supply current pin V_SS(I/O)

DC input clamp diode current

V

f_c= 43.2 MHz; V_DDD= 2.5 V

f_c= 43.2 MHz; V_DDD= 3.3 V

mA

I_SSD

−

I_DD(I/O)

I_SS(I/O)

I_IK

−

V_IL< −0.5 V or

−

V_IH> V_DD(I/O)+ 0.5 V; note 2

V_lim(5V)

5 V tolerant pins voltage limits

5 V tolerant outputs: disabled

mode

−0.5

−

+5.8

V

T_amb

T_stg

ambient temperature

−40

−55

2000

200

100

−

+85

+150

−

°C

V

storage temperature

V_esd

electrostatic discharge voltage

HBM: 100 pF; 1500 Ω

MM: 200 pF; 2.5 µH; 15 Ω

GQS (SNW-FQ-611 part E)

−

V

I_lu(prot)

latch-up protection current

−

mA

Notes

1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or at any other condition above those listed in the following

recommended operating and characteristics section is not implied. Exposure to absolute maximum rating conditions

for extended periods of time may affect device reliability.

2. Not applicable for 5 V tolerant pins.

8

THERMAL RESISTANCE

SYMBOL

PARAMETER

CONDITION

VALUE

UNIT

R_th(j-a)

thermal resistance from junction to

ambient

in free air

45

K/W

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

9

DC CHARACTERISTICS

Positive current ﬂows into the device; 3.13 V ≤ V_DD(I/O),

2.38 V ≤ V_DDA, V_DDD, V_{DD(OSC), DD(IF)}≤ 2.62 V; T_amb= −40 °C to +85 °C.

V_DD(REG)≤ 3.47 V;

V

SYMBOL

PARAMETER CONDITIONS

MIN.

TYP. MAX. UNIT

Digital parameters

V_DDD

supply voltage on pin V_DDD

supply voltage on pin V_DD(OSC)

supply voltage on pin V_DD(I/O)

supply voltage on pin V_DD(REG)

total supply current

2.38

3.13

2.5

3.3

2.62

3.47

V

V_DD(OSC)

V_DD(I/O)

V_DD(REG)

I_DD(tot)

f_{osc_in}= 43.2 MHz

pins V_DDD

−

215

5

260

10

mA

pins V_DD(I/O)

pins V_DDA1, V_DDA2, V_DD(IF),

V_DD(OSC)

180

216

V_IH

HIGH-level input voltage

V_DD(I/O)= 3.3 V; inputs TTL;

excluding 5 V tolerant pins

1.7

2.0

−

3.3

5.5

V

V_DD(I/O)= 3.3 V; 5 V tolerant

inputs TTL; including SDA pin

V_IL

LOW-level input voltage

HIGH-level output voltage

inputs TTL; excluding SDA pin

0

−

0.7

0.8

V

5 V tolerant inputs TTL;

including SDA pin

V_OH

I_OH= −4 mA; V_DD(I/O)= 3.3 V

10 ns slew rate outputs

4 mA outputs

2.9

−

V

−

V_OL

LOW-level output voltage

input leakage current

10 ns slew rate outputs;

I_OL= 4 mA; V_DD(I/O)= 3.3 V

0.4

4 mA outputs; I_OL= 4 mA

−

0.4

V

SDA output; I_OL= 3 mA;

V_DD(I/O)= 3.3 V

I_LI

Schmitt trigger input without

pull-down; excluding 5 V

tolerant pins

V_I= V_SS(I/O)

V_I= V_DD(I/O)

−

−1

µA

1

Schmitt trigger input without

pull-down; 5 V tolerant pins only

V_I= 5 V

V_I= 0 V

−

4.5

µA

−4.5

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

SYMBOL

I_OL(Z)

PARAMETER

CONDITIONS

MIN.

TYP. MAX. UNIT

3-state leakage current

V_I= V_SS(I/O); 3-state outputs

without pull-down; excluding

5 V tolerant pins

−

−1

µA

V_I= V_DD(I/O); 3-state outputs;

excluding 5V tolerant pins

−

1

µA

V_I= 5 V; 3-state outputs and

open-drain outputs without

pull-down; 5 V tolerant pins only

64

V_hys

Schmitt trigger hysteresis

Schmitt trigger inputs; excluding 0.4

SDA pin

−

V

Schmitt trigger inputs;

5 V tolerant pins only

0.3

pin SDA; V_DD(I/O)= 3.3 V

0.15

−

V

I_DD(q)

I_I(pd)

digital quiescent current

input pull-down current

V_DDD= 2.62 V;

−

1

mA

V_DD(I/O)= 3.47 V; note 1

V_DD< V_i< V_DD(I/O); all pins with 15

pull-down

50

100

µA

Analog parameters

V_DDA1

analog supply voltage

2.38

45

2.5

50

2.62

55

V

V_VREFAD

common-mode reference voltage

V_VREFADis determined by

V_VADCPand V_VADCN

%

[V_VADCP− V_VADCN

]

Z_O

output impedance pin VREFAD

IF_AD supply voltage

I_O< 2 mA

−

10

100

2.62

1

Ω

V_DD(IF)

V_VREFIF

V_DAC

2.38

−

2.5

V

IF_AD reference voltage

DAC supply voltage

0.775

2.5

V

2.38

−

2.62

−

V

V_VDACP

Z_O(DAC)

I_ADC(pos)

V_DD(OSC)

DAC positive reference voltage

DAC output impedance

ADC reference current

oscillator supply voltage

V

_DDA2− V_VDACN

100

0.9

%

kΩ

µA

V

pins LRV, RRV, LFV and RFV

0.65

−

1.2

−

180

2.5

2.38

2.62

Regulator

V_DD(REG)

regulator supply voltage

PMOST BSH207 in application 2.5

V_DD(REG)= 3.3 V

2.58

2.66

3.3

V

V_{DD(REG)(ctrl)}regulator control range

1

−

Note

1. I_DD(q)quiescent device current testing is a proven technique to increase device quality. The testing will be performed

in several different logic states, but no guarantee can be given that the current will stay below the specified maximum

value in every arbitrary static device state.

2003 Nov 18

48

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

10 AC CHARACTERISTICS

Positive current ﬂows into the device; 3.13V ≤ V_DD(I/O),V_DD(REG)≤ 3.47 V;

2.38V ≤ V_DDA, V_DDD, V_DD(OSC),

V

_DD(IF)≤ 2.62 V; T_amb= −40 °C to +85 °C.

SYMBOL

PARAMETER CONDITIONS

MIN.

TYP. MAX.

UNIT

Analog inputs

DIFFERENTIAL MEASUREMENTS VIA AUDIOAD_1 AND AUDIOAD_2; B = 20 KHZ

PSRR

power supply rejection ratio

V_i= 0.1 V (peak); f_i= 1 kHz 35

−

dB

α_ct

cross-talk between pins AIN(x) V_AIN(x)= 0.5 V (RMS);

f_i= 15 kHz; ADIFF(x) path

−

−70

dB

measured

Pins ADIFF_LP, ADIFF_LN, ADIFF_RP and ADIFF_RN

V_i(dif)(rms)

differential input voltage

(RMS value)

nominal digital output level

−2.5 dB

0.85

1

1.15

V

(THD + N)/S total harmonic

distortion-plus-noise to signal

f_i= 1 kHz; V_i= 1 V (RMS)

0 dB input level

−

−75

−25

72

dB

kΩ

dB

ratio

−60 dB input level

−

R_i

input resistance

45

−

57

−

α_cs

channel separation

V_AIN(x)= 0.5 V (RMS);

f_i= 15 kHz; ADIFF(x) path

measured

−70

V_o(ub)

CMRR

CMIR

f_res

left and right unbalance

V_i= 1 V (RMS); f_i= 1 kHz

−0.5

−

+0.5

−

dB

V

common mode rejection ratio f_i= 1 kHz; V_i= 0.1 V

40

common mode input range

frequency response

f_i= 1 kHz; V_i= 0.5 V (RMS) 1.0

1.5

−

f_cat −3 dB

20

45

kHz

SINGLE-ENDED MEASUREMENTS VIA AUDIOAD_1 AND AUDIOAD_2; B = 20 KHZ

PSRR

power supply rejection ratio

V_i= 0.1 V (p); f_i= 1 kHz

−

dB

Pins ADIFF_LP, ADIFF_LN, ADIFF_RP, ADIFF_RN, AIN1_L, AIN1_R, AIN2_L and AIN2_R

α_ct

cross-talk

V_i= 0.5 V (RMS);

f_i= 15 kHz; AIN(x) path

measured

−

−70

α_cs

channel separation

V_i= 0.5 V (RMS);

f_i= 15 kHz; AIN(x) path

measured

−

−60

dB

V

Pins AIN1_L, AIN1_R, AIN2_L and AIN2_R

V_i(rms)input voltage (RMS value)

nominal digital output level

0.4

0.5

0.6

−2.5 dB

(THD + N)/S total harmonic

distortion-plus-noise to signal

f_i= 1 kHz; V_i= 0.5 V (RMS)

0 dB input level

−

−75

−25

72

dB

kΩ

dB

V

ratio

−60 dB input level

−

R_i

input resistance

45

57

−

V_o(ub)

CMRR

CMIR

left and right unbalance

V_i= 0.5 V (RMS); f_i= 1 kHz −0.5

40

+0.5

−

common mode rejection ratio f_i= 1 kHz; V_i= 0.1 V

−

common mode input range

f_i= 1 kHz; V_i= 0.5 V (RMS) 1.0

−

1.5

2003 Nov 18

49

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

SYMBOL

f_res

PARAMETER

CONDITIONS

f_cat −3 dB

MIN.

TYP. MAX.

UNIT

kHz

frequency response

20

−

MPX; PINS AIN1_L, AIN2_L ADIFF_LP AND ADIFF_LN; SINGLE-ENDED AND DIFFERENTIAL INPUTS MEASUREMENT VIA

AUDIOAD_1 AND AUDIOAD_2 LEFT

(THD + N)/S total harmonic

f_i= 1 kHz; V_i= 0.5 V (RMS);

−

−75

−15

−70

−10

dB

distortion-plus-noise to signal single-ended;

ratio

V_i= 1 V (RMS); differential;

B = 40 kHz

f_i= 1 kHz;

V_i= 0.5 mV (RMS);

single-ended;

V_i= 1 mV (RMS);

differential; B = 40 kHz

RDS; PINS AIN1_R, AIN2_R ADIFF_RP AND ADIFF_RN; SINGLE-ENDED AND DIFFERENTIAL INPUTS MEASUREMENT VIA

AUDIOAD_1 AND AUDIOAD_2 RIGHT

(THD + N)/S total harmonic

f_i= 57 kHz; B = 4 kHz;

−

−65

dB

distortion-plus-noise to signal V_i= 0.5 V (RMS);

ratio

single-ended;

V_i= 1 V (RMS); differential;

0 dB input level;

reference level = V_i

f_i= 57 kHz; B = 4 kHz;

V_i= 0.5 mV (RMS);

single-ended;

−

−5

dB

V_i= 1 mV (RMS);

differential; −60 dB input

level; reference level = V_i

PINS MONO1_P, MONO1_N, MONO2_P AND MONO2_N; DIFFERENTIAL MEASUREMENTS VIA AUXAD_2

V_i(dif)(rms)

differential input voltage

(RMS value)

f_i= 1 kHz; nominal digital

output level = −5 dB

0.4

0.5

0.6

V

(THD + N)/S total harmonic

distortion-plus-noise to signal

f_i= 1 kHz; B = 4 kHz

V_i= 0.5 V (RMS);

0 dB input level

−

−45

dB

ratio

V_i= 50 mV (RMS)

−

−35

dB

PSRR

power supply rejection ratio

input resistance

amplitude = 0.1 V (p);

f_i= 1 kHz

15

−

R_i

90

40

1.0

32

120

−

150

−

kΩ

dB

V

CMRR

CMIR

f_res

common mode rejection ratio f_i= 1 kHz; V_i= 0.1 V

common mode input range

frequency response

f_i= 1 kHz

−

1.5

−

f_cat −3 dB

−

kHz

2003 Nov 18

50

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP. MAX.

UNIT

PINS MONO1_P, MONO1_N, MONO2_P AND MONO2_N; DIFFERENTIAL MEASUREMENTS VIA AUDIOAD_1 AND

AUDIOAD_2

V_i(dif)(rms)

differential input voltage

(RMS value)

f_i= 1 kHz; nominal digital

output level −2.5 dB

0.4

0.5

0.6

V

(THD + N)/S total harmonic

distortion-plus-noise to signal

f_i= 1 kHz; B = 4 kHz

V_i= 0.5 V (RMS); 0 dB

input level

−

−70

−25

dB

ratio

V_i= 0.5 mV (RMS);

-

−60 dB input level

PSRR

R_i

power supply rejection ratio

input resistance

V_i= 0.1 V (p-p); f_i= 1 kHz

30

90

40

1.0

20

−

dB

kΩ

dB

V

120

−

150

−

CMRR

CMIR

f_res

common mode rejection ratio f_i= 1 kHz; V_i= 0.10 V

common mode input range

frequency response

f_i= 1 kHz

−

1.5

−

f_cat −3 dB

−

kHz

Analog inputs; pins IFSS1 and IFSS2 single-ended measurements via AUXAD_1 and AUXAD_2; B = 32 kHz

V_i

input voltage

offset voltage

V_VADCP− V_VADCN= 2.5 V

2.35

2.5

2.65

V

V_offset

−150

+20

+150 mV

(THD + N)/S total harmonic

distortion-plus-noise to signal

f_i= 1 kHz

V_i= 90 % × V_R(p-p)

V_i= 9 % × V_R(p-p)

f_s= 5.4 MHz

−

−45

−28

−

dB

ratio

−

−34

−

dB

R_i

input resistance

500

32

kΩ

kHz

f_res

frequency response

f_cat −3 dB

−

PINS IF_IN1, IF_IN2, IF_AD1 AND IF_AD2

V_i(FS)(p-p)

full-scale input voltage

(peak-to-peak value)

nominal digital output level

0 dB

f_i= 451 kHz

0.82

0.96

1.04

1.09

1.16

V

f_i= 10.701 MHz; includes 0.815

influence of f_c(LPF)

V_offset

R_i

offset voltage

ADC + buffer + dither

−100

−

+100 mV

input resistance

16

20

24

kΩ

HD_AM

AM harmonic distortion

−34 dB (FS); measurement

with respect to 0 dB (FS)

f_i= 225.500 kHz

f_i= 150.333 kHz

−

−52

−82

dB

ID_AM

AM intermodulation distortion f₁= 430 kHz; −12 dB (FS);

f₂= 411 kHz; −22 dB (FS);

measurement with respect

to 0 dB (FS)

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

SYMBOL

HD_FM

PARAMETER

CONDITIONS

MIN.

TYP. MAX.

UNIT

FM harmonic distortion

measurement with respect

to 0 dB (FS)

f_i= 10.7802 MHz;

−6 dB (FS)

−

−40

−44

−66

−67

dB

f_i= 5.3505 MHz;

−10 dB (FS)

−

dB

f_i= 3.567 MHz;

−10 dB (FS)

f_i= 10.833 MHz;

−9 dB (FS)

ID_FM

FM intermodulation distortion −12 dB (FS); measurement

with respect to 0 dB (FS);

f₁= 10.833 MHz;

f₂= 10.967 MHz

S/N_AM

AM signal-to-noise ratio

narrow-band

f₁= 451 kHz;

83

65

88

72

−

dB

f₂= 534.809 kHz;

V_i= 85.3 mV (RMS);

B = 6 kHz; measurement

with respect to 0 dB (FS);

DITGAIN = 8

S/N_FM

FM signal-to-noise ratio

narrow-band

f₁= 10.701 MHz;

f₂= 10.89255 MHz;

V_i= 171 mV (RMS);

B = 180 kHz; measurement

with respect to 0 dB (FS);

DITGAIN = 8

PSRR

power supply rejection ratio

FM cross-talk

V_i= 0.1 V (p); f_i= 1 kHz

3

6

−

dB

α_ct(FM)

f_i= 10.701 MHz;

−

−39

amplitude = −12 dB (FS);

measurement with respect

to 0 dB (FS)

α_ct(AM)

AM cross-talk

f_i= 451 kHz;

−

−47

dB

amplitude = −12 dB (FS);

measurement with respect

to 0 dB (FS)

R_{i(IF_VG)}

input resistance pin IF_VG

−

400

70

−

Ω

Analog IF_AD dither DAC

V_dither(p-p)

dither level (peak-to-peak)

DITGAIN = 15

56

84

mV

Analog IF_AD dither gain DAC

G_step

G_res

number of gain steps

gain resolution

−

16

−

3.5

4.4

5.3

mV

-------------

steps

2003 Nov 18

52

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP. MAX.

UNIT

DAC measurements; 0 dB via I²S-bus; minimum AC impedance on DAC outputs = 100 kΩ; ﬁlter capacitance

on DAC outputs = 3.3 nF; B = 20 Hz to 20 kHz, Mixer muted

PSRR

power supply rejection ratio

pin V_DDA2

f_ripple= 1 kHz;

V_ripple= 0.1 V (p-p);

C_VDACP= 22 µF

3

6

−

dB

∆V_DAC

deviation in output level of the amplitude = 0 dB (FS);

front DAC voltage outputs with f_i= 1 kHz

respect to the average of the

front outputs

pins RRV and LRV

−0.38

−

+0.38 dB

pins RFV and LFV

PINS RRV, LRV, RFV AND LFV

m_(f-r)

matching of the front to rear

averages

amplitude = 0 dB (FS);

f_i= 1 kHz

−0.5

−

+0.5

dB

α_ct

crosstalk between the four

DAC output voltages

amplitude = 0 dB; f_i= 1 kHz;

one output digital silence;

three others 0 dB (FS); for

all combinations

−

−70

−60

(THD + N)/S total harmonic

f_i= 1 kHz; all four DAC

distortion-plus-noise to signal outputs driven

ratio

0 dB (FS); all mixers

muted

−

−80

−75

dB

−60 dB (FS)

−

−45

−40

−60

dB

0 dB (FS); all mixers on

and set to 0 dB

−

DS

digital silence

all zero digital input with

respect to 0 dB (FS)

−

−110

−105

dB

V

V_o(DAC)(rms)

DAC output voltage at

AC impedance ≥ 100 kΩ;

0.74

0.75

0.77

maximum signal (RMS value) f_i= 1 kHz; V_DDA2= 2.5 V

Analog MIX output; pins RRV, LRV, RFV AND LFV

THD

total harmonic distortion

summer input

f_i= 1 kHz;

gain setting = 0 dB

V_i= 0.50 V (RMS)

V_i= 0.5 mV (RMS)

−

−40

−20

dB

SPDIF measurements; pins SPDIF1 and SPDIF2

V_i(p-p)

input voltage level

0.2

0.5

2.5

V

(peak-to-peak value)

R_i

input resistance

input hysteresis

−

7

−

kΩ

V_i(hys)

30

mV

Quartz crystal oscillator measurements; pins OSC_IN and OSC_OUT; V_DD(OSC)= 2.5 V; f_i= 4 MHz

Z_o(xtal)

crystal oscillator output

impedance

V_i= 20 mV (RMS)

400

−

Ω

G_xtal

oscillator gain

V_i= 20 mV (RMS)

12

2

−

mA/V

mA

∆I_xtal

oscillator level dependent

current difference

V_i= 20 mV and 200 mV

(RMS)

2003 Nov 18

53

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP. MAX.

UNIT

Digital output rise and fall times; T_amb= 25 °C; C_L= 30 pF

t_o(r)

output rise time LOW-to-HIGH 10 ns slew rate outputs

−

10

−

ns

transition

4 mA outputs

5

−

ns

t_o(f)

output fall time HIGH-to-LOW 10 ns slew rate outputs

10

5

−

transition

4 mA outputs

−

t_o(f)(SDA)

output fall time HIGH-to-LOW C_b= 10 pF to 400 pF

transition pin SDA

20 + 0.1C_b

250

I²S-bus inputs and outputs (see Fig.29)

T_cy(BCK)

I²S-bus bit clock cycle time

f_s= 48 kHz; pins

EXT_IIS_BCK1 and

EXT_IIS_BCK2

81.3

−

ns

t_s;DAT

data set-up time

pins EXT_IIS_IO1 and

EXT_IIS_IO2

10

−

ns

pins IIS_IN1, IIS_IN2,

IIS_IN3, IFP_IIS_IN1,

IFP_IIS_I2O6 and

IFP_IIS_I3O4

22.9

t_h;DAT

data hold time

data delay time

pins EXT_IIS_IO1 and

EXT_IIS_IO2

5

0

−

ns

pins IIS_IN1, IIS_IN2,

IIS_IN3, IFP_IIS_IN1,

IFP_IIS_I2O6 and

IFP_IIS_I3O4

t_d;DAT

pins IIS_OUT1, IIS_OUT2,

IIS_OUT3, EXT_IIS_WS1,

EXT_IIS_BCK1,

−

27

ns

EXT_IIS_IO1,

EXT_IIS_WS2,

EXT_IIS_BCK2 and

EXT_IIS_IO2

t_s;WS

t_h;WS

t_d;WS

word select set-up time

word select hold time

word select delay time

pins EXT_IIS_WS1 and

EXT_IIS_WS2

10

2

−

ns

pins EXT_IIS_WS1 and

EXT_IIS_WS2

−

pins IIS_WS1 and

IFP_IIS_WS

−

27

RDS inputs and outputs; pins RDS_DATA and RDS_BCK; see Figs 30, 31, 32 and 33

T_TDAV

data valid period

DAVA and DAVB mode

24.5

49.0

11.25

100

26.0

52.0

12.0

−

27.0

54.0

12.5

−

RDS bit

periods

DAVC mode

RDS bit

periods

t_DAVNL

t_sr

time data available signal is

LOW

DAVA, DAVB and DAVC

mode

RDS bit

periods

clock set-up time

µs

2003 Nov 18

54

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

SYMBOL

T_pr

PARAMETER

period time

CONDITIONS

MIN.

TYP. MAX.

UNIT

µs

−

842

−

t_hr

t_lr

clock HIGH time

220

100

1

−

640

−

µs

clock LOW time

t_dr

t_wb

T_pb

t_hb

t_lb

data hold time

wait time (burst mode)

period time (burst mode)

clock HIGH time (burst mode)

clock LOW time (burst mode)

−

2

−

1

−

1

−

I²C-bus inputs and outputs; pins SCL and SDA; value referenced to V_IHminimum and V_ILmaximum levels;

see Fig.28

f_SCL

t_BUF

SCL clock frequency

0

−

400

kHz

bus free time between a STOP

and START condition

1.3

−

µs

t_HD;STA

hold time (repeated) START

condition

0.6

−

µs

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

1.3

0.6

−

µs

t_HIGH

t_SU;STA

set-up time for a repeated

START condition

t_HD;DAT

t_SU;DAT

t_r

data hold time

0

−

0.9

µs

data set-up time

100

−

ns

rise time of both SDA and SCL C_b= total capacitance of

signals

one bus line in pF

_SCL= 400 kHz

f_SCL= 100 kHz

fall time of both SDA and SCL C_b= total capacitance of

f

20 + 0.1C_b

−

300

ns

1000 ns

t_f

300

ns

signals

one bus line in pF

t_SU;STO

C_b

set-up time for STOP condition

0.6

−

µs

capacitive load for each bus

line

−

400

pF

t_SP

pulse width of spikes which

must be suppressed by the

input ﬁlter

0

−

50

ns

2003 Nov 18

55

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

t

s;WS

handbook, full pagewidth

WS (IN)

h;WS

LEFT

WS (OUT)

RIGHT

t

d;WS

t

BCK(L)

d;DAT

r

BCK(H)

f

BCK

t

h;DAT

T

cy

t

s;DAT

DATA (IN)

DATA (OUT)

MGW231

Fig.29 I²S-bus timing diagram for digital audio inputs/outputs.

handbook, full pagewidth

RDS_DATA

RDS_BCK

t

T

t

dr

sr

pr

hr

lr

MGW226

Fig.30 RDS timing diagram in direct output mode.

57

2003 Nov 18

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

handbook, full pagewidth

RDS_DATA

D0

D1

D2

D13

D14

D15

RDS_BCK

MGW227

T

pb

t

lb

wb

t

hb

Fig.31 Timing diagram of interface signals between RDS function and microcontroller in buffered output mode.

t

DAVNL

handbook, full pagewidth

DAVN

MGW228

T

TDAV

Fig.32 RDS data available signal (DAVN); no I²C-bus request during DAVN LOW time (decoder is synchronized).

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

handbook, full pagewidth

R(B)DS status

register read

2

I C-bus

t

DAVNL

DAVN

MGW229

T

TDAV

Fig.33 RDS data available signal (DAVN); DAVN LOW timing shorten by data request via I²C-bus (decoder is

synchronized).

11 I²C-BUS CONTROL

11.1 I²C-bus protocol

General description of the I²C-bus format in a booklet can

be obtained at Philips Semiconductors, International

Marketing and Sales.

The bidirectional I²C-bus interface acts as a slave

transceiver while an external microcontroller acts as a

master transceiver. Communication between the MPI and

the microcontroller is based on the I²C-bus protocol. The

data transfer on the I²C-bus is shown in Fig.34.

For the external control of the chip a fast I²C-bus is

implemented. This is a 400 kHz bus which is downward

compatible with the standard 100 kHz bus. There are two

different types of control instructions:

The I²C-bus has two lines: a Serial Clock line SCL and a

Serial Data line SDA. Because the I²C-bus is a

multi-master bus, arbitration between different master

devices is achieved by using a START condition. The

master device pulls the open-drain data line LOW while the

clock line remains HIGH. After the bus has been ‘won’ in

this way, data is transmitted serially in packets of 8 bits

plus an extra clock pulse for an acknowledgement flag

from the receiving device.

• Instructions to control the DSP programs, programming

the coefficient RAM and reading the values of

parameters

• Instructions controlling the DATA I²S-bus flow, like

source selection and clock speed.

handbook, full pagewidth

7

6

0

ACK

SDA

SCL

7

6

0

START

data MSB

data 2

data LSB

acknowledge STOP

MGW217

Fig.34 I²C-bus interface data transfer sequence.

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

address (2 bytes over the I²C-bus) which represents the

starting memory address for the data transfer.

11.1.1 PROTOCOL OF THE I²C-BUS COMMANDS

The SAA7724H acts as a slave receiver or slave

transmitter; therefore the clock signal is only an input

signal. The data signal is a bidirectional open-drain line at

the IC pin level. The SAA7724H slave address has a

subaddress bit A0 (bit 1) which allows the device to have

1 or 2 different addresses. The least significant bit (bit 0)

represents the read/write mode.

In the event that a read command is received before the

address register has been written, a negative

acknowledgement will be generated.

In the write mode, the transfer of data words continues

until the master device stops the transfer with a STOP

condition (P). In the read mode, the data transfer continues

until a negative acknowledgement and STOP condition is

generated by the master. In the read mode the last word

will not be transmitted to the I²C-bus while the I²C-bus

interface is stopped by the master.

The read and write I²C-bus commands are illustrated in

Figs 35 to 40, showing SDA. The I²C-bus interface will

generate a negative acknowledge on the SDA line in the

event that the data transfer was not completed

successfully.

When reading from or writing to an invalid address a

negative acknowledge will be generated after the first data

byte, and the master must then send a STOP condition. An

acknowledge is generated on all memory locations if

selected. Also, within a given boundary, an acknowledge

will be generated when selected, although the physical

size of the memory may not be that large. These are the

reserved locations in the I²C-bus memory map. A negative

acknowledge will only be generated in unused spaces of

the I²C-bus map.

After generating a START condition, the master device

has to transmit a slave address. The slave I²C-bus

interface responds to its own address (given in the first

data byte) by sending an acknowledgement to the master

device. The direction flag (bit 0) is always transmitted in

this first byte so that the slave knows in which mode it has

to operate. Initially, the I²C-bus interface receives a 16-bit

handbook, full pagewidth

S

Device W A AddrH

A

AddrL

A

DataH

A

DataM

A

DataL

A

DataH

A

DataM

A

DataL

A

......

P

MHC653

0

1 1 1 0 A0 R/W

Fig.35 Write cycle EPICS (XRAM).

handbook, full pagewidth

S

Device W A AddrH

A

AddrL A Sr Device

R

A

DataH

A

DataM

A

DataL

A

DataH

A

...... NA P

MHC654

0

1 1 1 0 A0 R/W

Fig.36 Read cycle EPICS (XRAM).

60

2003 Nov 18

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

handbook, full pagewidth

S

0

Device

W

1

A

0

AddrH

A

AddrL

A

DataM

A

DataL

A

DataM

A

DataL

DataM

A

......

P

MHC655

0

1

A0 R/W

Fig.37 Write cycle EPICS (YRAM).

handbook, full pagewidth

S

Device W A AddrH

A

AddrL A Sr Device

R

A

DataM

A

DataL

A

...... NA P

MHC656

0

0 1 1 1 0 A0 R/W

Fig.38 Read cycle EPICS (YRAM).

handbook, full pagewidth

S

Device W A AddrH

A

AddrL

A

DataM

A

DataL

A

DataM

A

DataL

A

DataL

A

......

P

MHC657

0

1 1 1 0 A0 R/W

Fig.39 Write cycle IFP.

handbook, full pagewidth

S

Device W A AddrH

A

AddrL A Sr Device

R

A

DataM

A

DataL

A

DataM

A

DataL

A

...... NA P

MHC658

0

1 1 1 0 A0 R/W

Fig.40 Read cycle IFP.

61

2003 Nov 18

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

Table 19 I²C-bus symbol description

SYMBOL

DESCRIPTION

S

START condition

repeated START condition

STOP condition

read bit (1)

Sr

P

R

W

write bit (0)

A

acknowledge from slave (SAA7724H)

acknowledge from master (microcontroller)

negative acknowledge from master to stop the data transfer

device address

A

NA

Device

AddrH and AddrL

DataH, DataM and DataL

DataM and DataL

address memory map

data of XRAM (3 bytes)

data of YRAM or IFP (2 bytes)

11.2 MPI data transfer formats

Table 20 Data transfer formats; note 1

TRANSFER

FROM

TO

Y transfer MPI → YRAM

Y transfer YRAM → I²C-bus

X transfer I²C-bus → XRAM

X transfer XRAM → I²C-bus

transfer I²C-bus → IFP

I²C-bus:

XXXXM----------L YRAM:

M----------L I²C-bus:

M----------L

XXXXM----------L

M----------------------L

M--------------L

YRAM:

I²C-bus:

M----------------------L XRAM:

M----------------------L I²C-bus:

M--------------L IFP:

XRAM:

I²C-bus:

IFP_DATA_R:

transfer IFP → I²C-bus

M--------------L I²C-bus:

M----------L

Note

1. M = MSB, L = LSB and X = don’t care.

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

11.3 Reset initialization

• If A0 = 1 the following addresses are available:

– Write: 00111010 = 3Ah

– Read: 00111011 = 3Bh.

With a synchronous reset the SAA7724H will turn to their

idle position (state 0), the address counter is set to zero

and the SDA_OUT line remains high-impedance. For the

SDA line an asynchronous reset is also implemented

which is connected directly to the RESET pin. During the

asynchronous reset period the internal SDA_OUT line

remains HIGH which results in a high-impedance SDA

line. These two resets should have an overlap to have a

proper initialization. It is also possible to reset the internal

I²C-bus registers separately, and these registers will be

set to their default values.

11.5 I²C-bus memory map speciﬁcation

The I²C-bus memory map contains all defined I²C-bus bits

related to RDS, SRC and EPICS control and allocates

EPICS, SRC and IFP RAM sizes.

The memory spaces belonging to the AUDIO_EPICS are

referred to as EPICS registers, and memory spaces

belonging to the SRC/RDS EPICS are referred to as SRC

registers.

11.4 Deﬁned I²C-bus address

The RDS registers control the RDS1 and RDS2 blocks

simultaneously while providing each RDS1 and RDS2

block with its own decoded data and status registers: the

memory map is given in Table 21. Detailed memory map

locations of the hardware registers related to the I²C-bus

EPICS control are given in Table 23 and the I²C-bus RDS

control are given in Table 24.

The I²C-bus address is defined for location: 001110P; the

least significant bit is a programmable bit with the external

pin A0_pin. Two possible options are available with this

pin:

• If A0 = 0 the following addresses are available:

– Write: 00111000 = 38h

– Read: 00111001 = 39h.

Table 21 I²C-bus memory map; notes 1 and 2

NUMBER OF

WORDS × BIT

BLOCK

START (HEX)

END (HEX)

NAME

ACCESS

WIDTH

(DEBUG PART)

−

E000

B880

B800

B000

AFFF

AFFE

A300

A000

9000

6030

602F

6010

6000

FFFF

DFFF

B87F

B7FF

AFFF

AFFE

AFFD

A2FF

9FFF

8FFF

602F

602E

600F

not used

−

SRC

−

reserved

−

SRC_YRAM

reserved

128 × 12

R/W

−

IIC_SRC_PC

IIC_SRC_STAT

reserved

1 × 24

R/W

1 × 24

R/W

−

SRC_XRAM

reserved

768 × 24

R/W

−

not used

−

Global

−

IIC_DSP_CTR

not used

1 × 24

−

R/W

−

RDS

RDS 1 and 2

registers

12 × 16

see Table 24

EPICS

−

5FFF

4000

3000

2C64

5FFF

5FFE

3FFF

2FFF

IIC_SILICON_ID

reserved

1 × 32

read

−

not used

−

IFP

IFP registers

all 16-bit width

R/W

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

NUMBER OF

WORDS × BIT

WIDTH

BLOCK

START (HEX)

END (HEX)

NAME

ACCESS

(DEBUG PART)

−

1400

2C00

2700

2600

2500

2400

2300

2200

2100

2081

2080

2000

1400

1000

0FFF

0FFE

0FF0

0E00

0000

2C63

2BFF

26FF

25FF

24FF

23FF

22FF

21FF

20FF

2080

207F

1FFF

13FF

0FFF

0FFE

0FFD

0FEF

0DFF

reserved

−

IFP

FP_RAM

reserved

100 × 16

−

R/W

−

VY3_RAM

VX3_RAM

VY2_RAM

VX2_RAM

VY1_RAM

VX1_RAM

reserved

256 × 16

−

R/W

−

IIC_SWB_ERR_STAT 1 × 16

R/W

−

SWB_RAM

128 × 16

EPICS

reserved

−

EPICS_YRAM

IIC_EPICS_PC

IIC_EPICS_STAT

EPICS registers

reserved

1024 × 12

1 × 24

14 × 24

−

R/W

−

EPICS_XRAM

3584 × 24

R/W

Notes

1. At all ‘reserved’ spaces an acknowledge (ACK) will be generated.

2. At all ‘not used’ spaces a negative acknowledge (NACK) will be generated.

Table 22 I²C-bus memory map SRC_EPICS hardware register overview

LOCATION (HEX)

AFFF

REGISTER NAME

IIC_SRC_PC

IIC_SRC_STAT

# USED BITS

READ/WRITE

24

R/W

AFFE

Table 23 I²C-bus memory map AUDIO_EPICS hardware register overview

LOCATION (HEX)

REGISTER NAME

IIC_EPICS_PC

# USED BITS

READ/WRITE

0FFF

0FFE

0FFD

0FFC

0FFB

0FFA

24

9

R/W

IIC_EPICS_STAT

IIC_DSPIO_CONF

IIC_SEL

20

10

12

IIC_IFAD_SEL

IIC_HOST

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

LOCATION (HEX)

REGISTER NAME

IIC_SPDIF_STAT

# USED BITS

READ/WRITE

read

0FF9

0FF8

0FF7

13

16

IIC_SUM

R/W

IIC_EPICS_START_ADDR

R/W

Table 24 I²C-bus memory map RDS hardware register overview

LOCATION (HEX)

REGISTER NAME

not used

# USED BITS

READ/WRITE

600F and 600E

600D

−

IIC_RDS2_CTR

IIC_RDS2_SET

IIC_RDS2_CNT

IIC_RDS2_PDAT

IIC_RDS2_LDAT

IIC_RDS2_STAT

not used

11

15

16

8

write

read

−

600C

600B

600A

6009

6008

6007 and 6006

6005

−

IIC_RDS1_CTR

IIC_RDS1_SET

IIC_RDS1_CNT

IIC_RDS1_PDAT

IIC_RDS1_LDAT

IIC_RDS1_STAT

11

15

16

8

write

read

6004

6003

6002

6001

6000

Table 25 I²C_EPICS_STAT status register (0FFEh)

BIT

SYMBOL

DEFAULT

DESCRIPTION

23 to 13

−

0h

−

internal ﬂags

not used

12 and 11 F12 and F11

10

F10

F9

F8

F7

F6

0

SPDIF2 lock status

0: not locked

1: locked

9

0

SPDIF1 lock status

0: not locked

1: locked

8

DSPIO8 status

0: input

1: output

7

DSPIO7 status

0: input

1: output

6

DSPIO6 status

0: input

1: output

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Philips Semiconductors

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Car radio digital signal processor

SAA7724H

BIT

SYMBOL

DEFAULT

DESCRIPTION

5

F5

F4

F3

F2

F1

F0

0

DSPIO5 status

0: input

1: output

4

3

2

1

0

DSPIO4 status

0: input

1: output

DSPIO3 status

0: input

1: output

DSPIO2 status

0: input

1: output

DSPIO1 status

0: input

1: output

DSPIO0 status

0: input

1: output

Table 26 IIC_DSPIO_CONF conﬁguration register (0FFDh)

BIT

23 to 9

8

SYMBOL

DEFAULT

DESCRIPTION

−

not used

conﬁg_DSPIO8

conﬁg_DSPIO7

conﬁg_DSPIO6

conﬁg_DSPIO5

conﬁg_DSPIO4

conﬁg_DSPIO3

0

port conﬁguration for DSPIO8

0: input

1: output

7

6

5

4

3

0

port conﬁguration for DSPIO7

0: input

1: output

port conﬁguration for DSPIO6

0: input

1: output

port conﬁguration for DSPIO5

0: input

1: output

port conﬁguration for DSPIO4

0: input

1: output

port conﬁguration for DSPIO3

0: input

1: output

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

BIT

SYMBOL

DEFAULT

DESCRIPTION

port conﬁguration for DSPIO2

2

conﬁg_DSPIO2

0

0: input

1: output

1

0

conﬁg_DSPIO1

conﬁg_DSPIO0

0

port conﬁguration for DSPIO1

0: input

1: output

port conﬁguration for DSPIO0

0: input

1: output

Table 27 IIC_SEL selection register (0FFCh)

BIT

23 to 20

19

SYMBOL

DEFAULT

DESCRIPTION

−

not used

ch2_dc_offset

1

DC offset ﬁlter for audio channel 2

0: disable

1: enable

18

17

16

15

14

13

12

ch1_dc_offset

1

0

DC offset ﬁlter for audio channel 1

0: disable

1: enable

aux2_sel_lev_

voice

select behavioural of the compensation ﬁlter for AUX channel 2

0: level inputs

1: voice inputs

aux1_sel_lev_

voice

select behavioural of the compensation ﬁlter for AUX channel 1

0: level inputs

1: voice inputs

ch2_wide_narrow

ch1_wide_narrow

sel_SPDIF2_IIS2

sel_SPDIF1_IIS1

select bandwidth for audio channel 2

0: audio + RDS information

1: only audio data

select bandwidth for audio channel 1

0: audio + RDS information

1: only audio data

select input for SRC2

0: SPDIF 2

1: EXT_IIS2

select input for SRC1

0: SPDIF 1

1: EXT_IIS1

11 and 10 aic3[1:0]

11

1

analog input control 3; see Table 6

AD normal/differential selection 2; see Table 4

AD internal reference 2; see Table 4

analog input control 2; see Table 5

9

8

s2

intref2

aic2[1:0]

0

7 and 6

01

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

BIT

SYMBOL

DEFAULT

DESCRIPTION

AD reference control 2; see Table 4

5

refc2

s1

1

0

4

AD normal/differential selection 1; see Table 4

AD internal reference 1; see Table 4

analog input control 1; see Table 5

3

2 and 1

0

intref1

aic1[1:0]

refc1

0

00

0

AD reference control 1; see Table 4

Table 28 IIC_IFAD_SEL selection register (0FFBh)

BIT

SYMBOL

DEFAULT

DESCRIPTION

23 to 10

9

−

not used

ifad2_power

1

controls activity of IFAD2

0: power low

1: power on

8

ifad1_power

1

controls activity of IFAD1

0: power low

1: power on

7 to 4

3 to 0

dith_gain_2[3:0]

dith_gain_1[3:0]

0000

control gain of IF-AD dither source 2

control gain of IF-AD dither source 1

Table 29 IIC_HOST register (0FFAh)

BIT

23 to 20

19

SYMBOL

DEFAULT

DESCRIPTION

not used

−

src2_ext_sel_out

src1_ext_sel_out

src2_int_ext_out

src1_int_ext_out

src2_int_ext_in

src1_int_ext_in

0

selects the external output port for SRC2

0: EXT_IIS1

1: EXT_IIS2

18

17

16

15

14

1

0

1

selects the external output port for SRC1

0: EXT_IIS1

1: EXT_IIS2

selects the output destination for SRC2

0: internal (audio epics)

1: external (Ext_iis)

selects the output destination for SRC1

0: internal (audio epics)

1: external (Ext_iis)

selects the input source for SRC2

0: internal (audio epics)

1: external (Ext_iis/Spdif)

selects the input source for SRC1

0: internal (audio epics)

1: external (Ext_iis/Spdif)

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

BIT

SYMBOL

DEFAULT

DESCRIPTION

13

en_ifp_iis_bck

0

enable ifp_iis_bck

0: disable

1: enable

12

iboc_mode

0

selects outputs of IF decimation paths to come out at IFP_IIS ports

0: disable

1: enable

11 to 9

8 to 6

5

ext_host_io_

format2[2:0]

000

0

input data format for EXT_IIS2 port; see Table 10

ext_host_io_

format1[2:0]

input data format for EXT_IIS1 port; see Table 10

en_host_io

port output enable for IIS_OUT port

0: disable. IIS_OUT1, IIS_OUT2 and IIS_OUT3 set to zero;

IIS_WS and IIS_BCK 3-stated

1: all pins enabled

4 to 2

host_io_format[2:0]

000

−

host input/output data format for I²S-bus port; see Table 12

1

0

−

not used

en_256FS

0

256 × f_sclock output

0: disable

1: enable

Table 30 IIC_SPDIF_STAT status register (0FF9h)

BIT

23 to 17

16

SYMBOL

DEFAULT

DESCRIPTION

−

not used

IFP_Status

0: disabled

1: enabled

15 and 14

−

not used

13 and 12 SPDIF2_

accuracy[1:0]

accuracy of sampling frequency of SPDIF2 channel

00: level II

10: level III

01: level I

11: reserved

11 and 10 SPDIF2_fs[1:0]

-

audio sampling frequency of SPDIF2 channel

00: 44.1 kHz

10: 48 kHz

01: reserved

11: 32 kHz

9

SPDIF2_emphasis

−

equalization of SPDIF2 channel

0: no pre-emphasis present

1: 50/15 µs pre-emphasis present

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

BIT

SYMBOL

DEFAULT

DESCRIPTION

contents of SPDIF2 channel

8

SPDIF2_content

−

0: normal audio mode

1: data mode

7 and 6

5 and 4

−

not used

SPDIF1_

accuracy[1:0]

accuracy of sampling frequency of SPDIF1 channel

00: level II

10: level III

01: level I

11: reserved

3 and 2

SPDIF1_fs[1:0]

−

audio sampling frequency of SPDIF1 channel

00: 44.1 kHz

10: 48 kHz

01: reserved

11: 32 kHz

1

0

SPDIF1_emphasis

SPDIF1_content

−

equalization of SPDIF1 channel

0: no pre-emphasis present

1: 50/15 µs pre-emphasis present

contents of SPDIF1 channel

0: normal audio mode

1: data mode

Table 31 IIC_SUM summer register (0FF8h)

BIT

SYMBOL

DEFAULT

DESCRIPTION

not used

23 to 13

−

0

12

11

10

9

rrm

rlm

frm

ﬂm

mixc

DAC summer RR enable; see Table 9

DAC summer RL enable; see Table 9

DAC summer FR enable; see Table 9

DAC summer FL enable; see Table 9

DAC summer input selection

0: MONO1

8

1: MONO2

7

6

iﬁn2_inpsel

iﬁn1_inpsel

volmix[5:0]

0

select IFAD for IFIN2 input from IFP

0: for IF_AD2

1: for IF_AD1

select IFAD for IFIN1 input from IFP

0: for IF_AD1

1: for IF_AD2

5 to 0

000000

DAC summer volume setting; see Table 8

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

Table 32 IIC_EPICS_START_ADDR address register (0FF7h)

BIT

SYMBOL

DEFAULT

DESCRIPTION

23 to 16

15 to 0

−

not used

start_addr[15:0]

0000h

start address for the AUDIO_EPICS; can be programmed before

releasing ‘epics_pc_reset’ bit; see Table 33

Table 33 IIC_DSP_CTR control register (602Fh)

BIT

SYMBOL

DEFAULT

DESCRIPTION

23 to 19

−

not used

18 and 17 pll2_clksel[1:0]

01

choose PLL2 clock selection switch

00: low range

01: mid range

16 and 15 pll1_clksel[1:0]

00

choose PLL1 clock selection switch

00: low range

01: mid range

14 to 10

9 to 5

4

pll2_div[4:0]

pll1_div[4:0]

pll2_bypass

01101

10000

0

choose PLL2 division factor

choose PLL1 division factor

bypass option for SRC_EPICS; this is an evaluation mode only

0: PLL2

1: OSCIN_CLK

3

pll1_bypass

0

bypass option for AUDIO_EPICS clock; warning: the OSCIN_CLK is

only used for evaluation; it is functionally not a valid setting

0: PLL2

1: OSCIN_CLK

2

1

−

not used

src_pc_reset

1

program counter for SRC_EPICS reset

0: no reset

1: reset; program counter will always be set to 0000h

program counter for AUDIO_EPICS reset

0: no reset

0

epics_pc_reset

1

1: reset; program counter will be set to the ‘start_addr’ value;

see Table 32

Table 34 IIC_SILICON_ID register (5FFFh);

BIT

SYMBOL

DEFAULT

DESCRIPTION

development number; decimal number

development version number; binary code

mask version number; binary code

31 to 16

15 to 12

11 to 7

6 to 0

dev_number[15:0]

dev_version[3:0]

mask_version[4:0]

−

romcode_

ROM code version number; binary code

version[6:0]

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

Table 35 IIC_RDS2_CTR control register (600Dh)

BIT

SYMBOL

DEFAULT

DESCRIPTION

15 to 11

10

−

not used

sel_DAVN2_RDS_

Flag

0

select DAVN2 control indicator

0: use RDS2 block

1: use FLAG from IFP

see Table 36

9

rds2_clkout

0

1

8

7 and 6

5

rds2_clkin

RDS2_DAC[1:0]

RDS2_NWSY

00

0

see Table 37

start new synchronization

0: no start

1: start

4 to 0

RDS2_MBBG[4:0]

00000

maximum bad blocks gain

Table 36 Description of bits rds2_clkout and rds2_clkin

rds2_clkout

rds2_clkin

DESCRIPTION

0

1

0

1

0

1

rds decoder

burst mode with external clock as input

rds demodulator

not allowed

Table 37 Description of bits RDS2_DAC1 and RDS0_DAC0

RDS2_DAC1

RDS2_DAC0

DESCRIPTION

0

1

0

1

0

1

standard mode

fast PI search mode

reduced data request

decoder bypass

Table 38 IIC_RDS2_SET settings register (600Ch)

BIT

SYMBOL

DEFAULT

DESCRIPTION

15

−

00

not used

14 and 13 RDS2_SYM[1:0]

see Table 39

12 to 7

6

RDS2_MGBL[5:0]

RDS2_RBDS

100000

0

maximum good blocks lose

allow RBDS ‘E’ blocks

0: not allow

1: allow

5 to 0

RDS2_MBBL[5:0]

100000

maximum bad blocks lose

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

Table 39 Description of bits RDS2_SYM1 and RDS2_SYM0

RDS2_SYM1

RDS2_SYMO

DESCRIPTION

0

1

0

1

0

1

no error correction

maximum 2 bits burst error

maximum 5 bits burst error

no error correction

Table 40 IIC_RDS2_CNT counter register (600Bh)

BIT

SYMBOL

DEFAULT

DESCRIPTION

15 to 10

9 to 5

RDS2_BBC[5:0]

RDS2_GBC[4:0]

RDS2_PBIN[2:0]

RDS2_EPB[1:0]

000000

00000

111

bad blocks counter

good blocks counter (only 5 MSBs are available)

previous block identiﬁer

4 to 2

1 and 0

00

error status previously received block; see Table 41

Table 41 Description of bits RDS2_EPB1 and RDS2_EPB0

RDS2_EPB1

RDS2_EPB0

DESCRIPTION

0

1

0

1

0

1

no errors detected

maximum 2 bits

maximum 5 bits

uncorrectable

Table 42 IIC_RDS2_PDAT register (600Ah)

BIT

SYMBOL

DEFAULT

DESCRIPTION

previously processed block data

15 to 0

RDS2_PDAT[15:0]

0000h

Table 43 IIC_RDS2_LDAT register (6009h)

BIT

SYMBOL

DEFAULT

DESCRIPTION

15 to 0

RDS2_LDAT[15:0]

0000h

last processed block data

Table 44 IIC_RDS2_STAT status register (6008h)

BIT

15 to 8

7

SYMBOL

DEFAULT

DESCRIPTION

−

not used

RDS2_SYNC

0

synchronization found

0: no synchronization

1: synchronization

data overﬂow ﬂag

0: no overflow

6

RDS2_DOFL

0

1: overflow

2003 Nov 18

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Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

BIT

SYMBOL

DEFAULT

DESCRIPTION

5

RDS2_RSTD

0

reset detected

0: no reset

1: reset

4 to 2

RDS2_LBIN[2:0]

RDS2_ELB[1:0]

111

00

last block identiﬁcation

1 and 0

error status last block; see Table 45

Table 45 Description of bits RDS2_ELB1 and RDS2_ELB0

RDS2_ELB1

RDS2_ELB0

DESCRIPTION

0

1

0

1

0

1

no errors detected

maximum 2 bits

maximum 5 bits

uncorrectable

Table 46 IIC_RDS1_CTR control register (6005h)

BIT

15 to 11

10

SYMBOL

DEFAULT

DESCRIPTION

−

not used

sel_RDS_CLK1_

DAVN2

0

select usage for pin RDS_CLK1_DAVN2; pin is used for DAVN2 and

IFP ﬂag usage (depending on state of sel_DAVN2_RDS_Flag);

otherwise pin is used as RDS_CLK1 for RDS1 block

1: DAVN2 and IFP flag usage

0: RDS_CLK1

9

rds1_clkout

0

1

see Table 47

8

7 and 6

5

rds1_clkin

RDS1_DAC[1:0]

RDS1_NWSY

00

0

see Table 48

start new synchronization

0: no start

1: start

4 to 0

RDS1_MBBG[4:0]

00000

max bad blocks gain

Table 47 Description of bits rds1_clkout and rds1_clkin

rds1_clkout

rds1_clkin

DESCRIPTION

0

1

0

1

0

1

decoder

burst mode with external clock as input

demodulator

not allowed

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

Table 48 Description of bits RDS1_DAC1 and RDS1_DAC0

RDS1_DAC1

RDS1_DAC0

DESCRIPTION

0

1

0

1

0

1

standard mode

fast PI search mode

reduced data request

decoder bypass

Table 49 IIC_RDS1_SET settings register (6004h)

BIT

SYMBOL

DEFAULT

DESCRIPTION

15

−

00

not used

14 and 13 RDS1_SYM[1:0]

see Table 50

12 to 7

6

RDS1_MGBL[5:0]

RDS1_RBDS

100000

0

maximum good blocks lose

allow RBDS ‘E’ blocks

0: not allowed

1: allowed

5 to 0

RDS1_MBBL[5:0]

100000

maximum bad blocks lose

Table 50 Description of bits RDS1_SYM1 and RDS1_SYM0

RDS1_SYM1

RDS1_SYM0

DESCRIPTION

0

1

0

1

0

1

no error correction

maximum 2 bits burst error

maximum 5 bits burst error

no error correction

Table 51 IIC_RDS1_CNT counter register (6003h)

BIT

SYMBOL

DEFAULT

DESCRIPTION

15 to 10

9 to 5

RDS1_BBC[5:0]

RDS1_GBC[4:0]

RDS1_PBIN[2:0]

RDS1_EPB[1:0]

000000

00000

111

bad blocks counter

good blocks counter (only 5 MSBs are available)

previous block identiﬁer

4 to 2

1 and 0

00

error status previously received block; see Table 52

Table 52 Description of bits RDS1_EPB1 and RDS1_EPB0

RDS1_EPB1

RDS1_EPB0

DESCRIPTION

0

1

0

1

0

1

no errors detected

maximum 2 bits

maximum 5 bits

uncorrectable

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Car radio digital signal processor

SAA7724H

Table 53 IIC_RDS1_PDAT register (6002h)

BIT

SYMBOL

DEFAULT

DESCRIPTION

previously processed block data

15 to 0

RDS1_PDAT[15:0]

0000h

Table 54 IIC_RDS1_LDAT register (6001h)

BIT

SYMBOL

DEFAULT

DESCRIPTION

15 to 0

RDS1_LDAT[15:0]

0000h

last processed block data

Table 55 IIC_RDS1_STAT status register (6000h)

BIT

SYMBOL

DEFAULT

15 to 8

7

−

-

not used

RDS1_SYNC

RDS1_DOFL

RDS1_RSTD

0

synchronization found

0: no synchronization

1: synchronization

data overﬂow ﬂag

0: no overflow

1: overflow

6

5

0

reset detected

0: no reset

1: reset

4 to 2

RDS1_LBIN[2:0]

RDS1_ELB[1:0]

111

00

last block identiﬁcation

1 and 0

error status last block; see Table 56

Table 56 Description of bits RDS1_ELB1 and RDS1_ELB0

RDS1_ELB1

RDS1_ELB0

DESCRIPTION

0

1

0

1

0

1

no errors detected

maximum 2 bits

maximum 5 bits

uncorrectable

2003 Nov 18

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Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

12 I²S-BUS CONTROL

transmitters and receivers which makes it difficult to define

the master. In such systems there is usually a system

master controlling digital audio data-flow between the

various ICs. Transmitters then have to generate data

under the control of an external clock, and so act as a

slave. Figure 41 illustrates some simple system

configurations and the basic interface timing. Note that the

system master can be combined with a transmitter or

receiver, and it may be enabled or disabled under software

control or by pin programming.

12.1 Basic system requirements

The inter-IC sound (I²S-bus) was developed by Philips to

facilitate communications between the ever increasing

number of digital audio processing ICs in a typical audio

system. The bus only has to handle audio data, while the

other signals such as sub-coding and control are

transferred separately. To minimize the number of pins

required and to keep wiring simple, a 3-line serial bus is

used consisting of a line for two time-multiplexed data

channels, a word select line and a clock line.

As shown in Fig.41, the bus has three lines:

• Continuous serial clock (SCK)

• Word Select (WS)

Since the transmitter and receiver have the same clock

signal for data transmission, the transmitter as the master,

has to generate the bit clock, word select signal and data.

In complex systems however, there may be several

• Serial Data (SD).

The device generating SCK and WS is the master.

Clock SCK

Word Select WS

Data SD

SCK

WS

handbook, full pagewidth

TRANSMITTER

RECEIVER

TRANSMITTER

RECEIVER

SD

TRANSMITTER = MASTER

RECEIVER = MASTER

CONTROLLER

SCK

WS

SD

TRANSMITTER

RECEIVER

CONTROLLER = MASTER

SCK

WS

SD

MSB

LSB

MSB

word n − 1

right channel

word n

left channel

word n + 1

right channel

MGW230

Fig.41 Simple system configurations and basic interface timing.

77

2003 Nov 18

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

12.2 Serial data

12.3 Word select

Serial data is transmitted in twos complement with the

MSB first. The MSB is transmitted first because the

transmitter and receiver may have different word lengths.

It is not necessary for the transmitter to know how many

bits the receiver can handle, nor does the receiver need to

know how many bits are being transmitted.

The word select line indicates the channel being

transmitted:

• WS = 0: channel 1 (left)

• WS = 1: channel 2 (right).

WS may change either on a trailing or leading edge of the

serial clock, but it doesn’t need to be symmetrical. In the

slave, this signal is latched on the leading edge of the clock

signal. The WS line changes one clock period before the

MSB is transmitted. This allows the slave transmitter to

derive synchronous timing of the serial data that will be set

up for transmission. Furthermore, it enables the receiver to

store the previous word and clear the input for the next

word (see Fig.41).

When the system word length is greater than the

transmitter word length, the word is truncated (least

significant bits are set to 0) for data transmission. If the

receiver is sent more bits than it’s word length, the bits

after the LSB are ignored. However, if the receiver is sent

fewer bits than it’s word length the missing bits are set to

zero internally. Therefore, the MSB has a fixed position

whereas the position of the LSB depends on the word

length. The transmitter always sends the MSB of the next

word one clock period after the WS changes.

Serial data sent by the transmitter may be synchronized

with either the trailing (HIGH-to-LOW) or the leading

(LOW-to-HIGH) edge of the clock signal. However, the

serial data must be latched into the receiver on the leading

edge of the serial clock signal so there are some

restrictions when transmitting data that is synchronized

with the leading edge.

2003 Nov 18

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Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

13 PACKAGE OUTLINE

QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

SOT317-3

y

X

A

80

51

81

50

Z

E

e

A

2

H

A

E

(A )

3

A

1

θ

w M

p

pin 1 index

L

p

b

L

31

100

detail X

1

30

w M

Z

v

M

D

A

b

p

e

D

B

H

v

M

B

D

0

5

scale

10 mm

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.45 2.90

0.25 2.65

0.40 0.25 20.1 14.1

0.25 0.14 19.9 13.9

24.2 18.2

23.6 17.6

1.0

0.73

0.8

0.4

1.0

0.6

mm

3.4

0.25

0.65

1.95

0.2 0.15 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-15

03-02-25

SOT317-3

MO-112

2003 Nov 18

79

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

14 SOLDERING

To overcome these problems the double-wave soldering

method was specifically developed.

14.1 Introduction to soldering surface mount

packages

If wave soldering is used the following conditions must be

observed for optimal results:

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

• Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for

certain surface mount ICs, but it is not suitable for fine pitch

SMDs. In these situations reflow soldering is

recommended.

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

14.2 Reﬂow soldering

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

Driven by legislation and environmental forces the

The footprint must incorporate solder thieves at the

downstream end.

• For packages with leads on four sides, the footprint must

be placed at a 45° angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example,

convection or convection/infrared heating in a conveyor

type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending

on heating method.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical reflow peak temperatures range from

215 to 270 °C depending on solder paste material. The

top-surface temperature of the packages should

preferably be kept:

Typical dwell time of the leads in the wave ranges from

3 to 4 seconds at 250 °C or 265 °C, depending on solder

material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

• below 225 °C (SnPb process) or below 245 °C (Pb-free

process)

– for all BGA, HTSSON-T and SSOP-T packages

14.4 Manual soldering

– for packages with a thickness ≥ 2.5 mm

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

– for packages with a thickness < 2.5 mm and a

volume ≥ 350 mm³so called thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free

process) for packages with a thickness < 2.5 mm and a

volume < 350 mm³so called small/thin packages.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

Moisture sensitivity precautions, as indicated on packing,

must be respected at all times.

14.3 Wave soldering

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

2003 Nov 18

80

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

14.5 Suitability of surface mount IC packages for wave and reﬂow soldering methods

SOLDERING METHOD

PACKAGE⁽¹⁾

WAVE

not suitable

REFLOW⁽²⁾

BGA, HTSSON..T⁽³⁾, LBGA, LFBGA, SQFP, SSOP..T⁽³⁾, TFBGA,

USON, VFBGA

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,

HTQFP, HTSSOP, HVQFN, HVSON, SMS

PLCC⁽⁵⁾, SO, SOJ

not suitable⁽⁴⁾

suitable

LQFP, QFP, TQFP

not recommended⁽⁵⁾⁽⁶⁾suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L⁽⁸⁾, PMFP⁽⁹⁾, WQCCN..L⁽⁸⁾

not recommended⁽⁷⁾

suitable

not suitable

Notes

1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account

be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature

exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature

must be kept as low as possible.

4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,

the solder might be deposited on the heatsink surface.

5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not

suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted

on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar

soldering process. The appropriate soldering profile can be provided on request.

9. Hot bar or manual soldering is suitable for PMFP packages.

2003 Nov 18

81

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

15 DATA SHEET STATUS

DATA SHEET

STATUS⁽¹⁾

PRODUCT

STATUS⁽²⁾⁽³⁾

LEVEL

DEFINITION

I

Objective data

Development This data sheet contains data from the objective speciﬁcation for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

II

Preliminary data Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Relevant changes will

be communicated via a Customer Product/Process Change Notiﬁcation

(CPCN).

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

16 DEFINITIONS

17 DISCLAIMERS

Short-form specification

The data in a short-form

Life support applications

These products are not

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductors customers using or selling these products

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

at these or at any other conditions above those given in the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Right to make changes

Philips Semiconductors

reserves the right to make changes in the products -

including circuits, standard cells, and/or software -

described or contained herein in order to improve design

and/or performance. When the product is in full production

(status ‘Production’), relevant changes will be

Application information

Applications that are

communicated via a Customer Product/Process Change

Notification (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these

products, conveys no licence or title under any patent,

copyright, or mask work right to these products, and

makes no representations or warranties that these

products are free from patent, copyright, or mask work

right infringement, unless otherwise specified.

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

no representation or warranty that such applications will be

suitable for the specified use without further testing or

modification.

2003 Nov 18

82

Philips Semiconductors

Preliminary speciﬁcation

Car radio digital signal processor

SAA7724H

18 PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

2003 Nov 18

83

Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales ofﬁces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

SCA75

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

753503/02/pp84

Date of release: 2003 Nov 18

Document order number: 9397 750 11426


型号：	935271501518
厂家：	NXP
描述：	SPECIALTY CONSUMER CIRCUIT, PQFP100, 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, MO-112, SOT-317-3, QFP-100 商用集成电路
文件：	总84页 (文件大小：470K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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