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PCA9673

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and

reset

Rev. 2 — 29 September 2011

Product data sheet

1. General description

The PCA9673 provides general purpose remote I/O expansion for most microcontroller

families via the two-line bidirectional bus (I²C-bus) and is a part of the Fast-mode Plus

family.

The PCA9673 is a drop in upgrade for the PCF8575 providing higher Fast-mode Plus

(Fm+) I²C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWM

dimming of LEDs, higher I²C-bus drive (30 mA versus 3 mA) so that many more devices

can be on the bus without the need for bus buffers, higher total package sink capacity

(400 mA versus 100 mA) that supports having all 25 mA LEDs on at the same time and

more device addresses (16 versus 8) are available to allow many more devices on the

bus without address conflicts.

The difference between the PCA9673 and the PCF8575 is that the A2 address pin is

replaced by a RESET input on the PCA9673.

The device consists of a 16-bit quasi-bidirectional port and an I²C-bus interface. The

PCA9673 has a low current consumption and includes latched outputs with 25 mA high

current drive capability for directly driving LEDs.

It also possesses an interrupt line (INT) which can be connected to the interrupt logic of

the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform

the microcontroller if there is incoming data on its ports without having to communicate via

the I²C-bus.

The internal Power-On Reset (POR), hardware reset pin (RESET) or software reset

sequence initializes the I/Os as inputs.

2. Features and benefits

 1 MHz I²C-bus interface

 Compliant with the I²C-bus Fast and Standard modes

 SDA with 30 mA sink capability for 4000 pF buses

 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os

 16-bit remote I/O pins that default to inputs at power-up

 Latched outputs with 25 mA sink capability for directly driving LEDs

 Total package sink capability of 400 mA

 Active LOW open-drain interrupt output

 16 programmable slave addresses using 2 address pins

 Readable device ID (manufacturer, device type, and revision)

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

 Low standby current

 40 C to +85 C operation

 ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

 Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA

 Packages offered: SO24, TSSOP24, HVQFN24, DHVQFN24

3. Applications

 LED signs and displays

 Servers

 Industrial control

 Medical equipment

 PLCs

 Cellular telephones

 Gaming machines

 Instrumentation and test measurement

4. Ordering information

Table 1.

Ordering information

Type number Topside

mark

Package

Name

Description

Version

PCA9673D

SO24

plastic small outline package; 24 leads; body width 7.5 mm

SOT137-1

SOT355-1

PCA9673PW PCA9673PW TSSOP24

plastic thin shrink small outline package; 24 leads;

body width 4.4 mm

PCA9673BQ

PCA9673BS

9673

DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad

SOT815-1

SOT616-1

flat package; no leads; 24 terminals; body 3.5  5.5  0.85 mm

HVQFN24

plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 4  4  0.85 mm

PCA9673

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Product data sheet

Rev. 2 — 29 September 2011

2 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

5. Block diagram

PCA9673

INTERRUPT

LOGIC

LP FILTER

INT

AD0

AD1

P00 to P07

P10 to P17

SCL

SDA

2

SHIFT

REGISTER

I/O

PORT

INPUT

FILTER

I C-BUS

16 BITS

CONTROL

write pulse

read pulse

RESET

POWER-ON

RESET

V

DD

V

SS

002aac300

Fig 1. Block diagram of PCA9673

V

DD

I

OH

write pulse

100 μA

I

trt(pu)

D

Q

data from Shift Register

power-on reset

P00 to P07

P10 to P17

FF

S

OL

CI

V

SS

D

Q

FF

S

CI

read pulse

to interrupt logic

data to Shift Register

002aab631

Fig 2. Simplified schematic diagram of P00 to P17

PCA9673

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Product data sheet

Rev. 2 — 29 September 2011

3 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

6. Pinning information

6.1 Pinning

1

2

3

4

5

6

7

8

9

24

23

22

21

20

19

18

17

16

15

14

13

1

2

24

23

22

21

20

19

18

17

16

15

14

13

INT

AD1

V

INT

AD1

RESET

P00

V

DD

SDA

SCL

AD0

P17

P16

P15

P14

P13

P12

P11

P10

SDA

SCL

AD0

P17

P16

P15

P14

P13

P12

P11

P10

3

RESET

P00

4

5

P01

6

P02

PCA9673D

PCA9673PW

7

P03

8

P04

9

P05

10

11

12

10

11

12

P06

P07

P06

P07

V

SS

V

SS

002aac301

002aac302

Fig 3. Pin configuration for SO24

Fig 4. Pin configuration for TSSOP24

terminal 1

index area

2

3

23

22

21

20

19

18

17

16

15

14

AD1

RESET

P00

SDA

SCL

AD0

P17

P16

P15

P14

P13

P12

P11

terminal 1

index area

4

5

P01

1

2

3

4

5

6

18

17

16

15

14

13

P00

P01

P02

P03

P04

P05

AD0

P17

P16

P15

P14

P13

6

P02

PCA9673BQ

7

P03

PCA9673BS

8

P04

9

P05

10

11

P06

P07

002aac305

002aac306

Transparent top view

Fig 5. Pin configuration for HVQFN24

Fig 6. Pin configuration for DHVQFN24

PCA9673

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Product data sheet

Rev. 2 — 29 September 2011

4 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

6.2 Pin description

Table 2.

Symbol

Pin description

Description

SO24, TSSOP24,

DHVQFN24

HVQFN24

INT

1

22

23

24

1

interrupt output (active LOW)

address input 1

AD1

RESET

P00

P01

P02

P03

P04

P05

P06

P07

V_SS

2

3

reset input (active LOW)

quasi-bidirectional I/O 00

quasi-bidirectional I/O 01

quasi-bidirectional I/O 02

quasi-bidirectional I/O 03

quasi-bidirectional I/O 04

quasi-bidirectional I/O 05

quasi-bidirectional I/O 06

quasi-bidirectional I/O 07

supply ground

4

5

2

6

3

7

4

8

5

9

6

10

11

12^[1]

13

14

15

16

17

18

19

20

21

22

23

24

7

8

9^[1]

10

11

12

13

14

15

16

17

18

19

20

21

P10

P11

P12

P13

P14

P15

P16

P17

AD0

SCL

SDA

V_DD

quasi-bidirectional I/O 10

quasi-bidirectional I/O 11

quasi-bidirectional I/O 12

quasi-bidirectional I/O 13

quasi-bidirectional I/O 14

quasi-bidirectional I/O 15

quasi-bidirectional I/O 16

quasi-bidirectional I/O 17

address input 0

serial clock line input

serial data line input/output

supply voltage

[1] HVQFN24 and DHVQFN24 package die supply ground is connected to both the V_SSpin and the exposed

center pad. The V_SSpin must be connected to supply ground for proper device operation. For enhanced

thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using

a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias

need to be incorporated in the PCB in the thermal pad region.

PCA9673

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Product data sheet

Rev. 2 — 29 September 2011

5 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

7. Functional description

Refer to Figure 1 “Block diagram of PCA9673”.

7.1 Device address

Following a START condition, the bus master must send the address of the slave it is

accessing and the operation it wants to perform (read or write). The address of the

PCA9673 is shown in Figure 7. Slave address pins AD1 and AD0 choose 1 of 16 slave

addresses. To conserve power, no internal pull-up resistors are incorporated on AD1 and

AD0. Address values depending on AD1 and AD0 can be found in Table 3 “PCA9673

address map”.

Remark: The General Call address (0000 0000b) and the Device ID address

(1111 100Xb) are reserved and cannot be used as device address. Failure to follow this

requirement will cause the PCA9673 not to acknowledge.

Remark: Reserved I²C-bus addresses must be used with caution since they can interfere

with:

• “reserved for future use” I²C-bus addresses (0000 011, 1111 101, 1111 110, 1111 111)

• slave devices that use the 10-bit addressing scheme (1111 0xx)

• High speed mode (Hs-mode) master code (0000 1xx)

slave address

A6 A5 A4 A3 A2 A1 A0 R/W

programmable

002aab636

Fig 7. PCA9673 address

The last bit of the first byte defines the operation to be performed. When set to logic 1 a

read is selected, while a logic 0 selects a write operation.

When AD1 and AD0 are held to V_DDor V_SS, the same address as the PCF8575 is applied.

7.1.1 Address maps

Table 3.

AD1

SCL

PCA9673 address map

AD0

V_SS

A6

0

A5

0

A4

1

A3

0

A2

1

A1

0

A0

0

Address (hex)

28h

2Ah

2Ch

2Eh

38h

3Ah

3Ch

3Eh

SCL

V_DD

V_SS

0

1

0

1

0

1

SDA

SCL

0

1

0

1

0

V_DD

SCL

SDA

SCL

SDA

0

1

0

1

0

1

0

SCL

0

1

0

1

SDA

0

1

0

1

PCA9673

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Product data sheet

Rev. 2 — 29 September 2011

6 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

Table 3.

PCA9673 address map …continued

AD1

V_SS

V_DD

V_SS

V_DD

AD0

V_SS

A6

0

A5

1

A4

0

A3

0

A2

1

A1

0

A0

0

Address (hex)

48h

4Ah

4Ch

4Eh

58h

5Ah

5Ch

5Eh

V_DD

V_SS

0

1

0

1

0

1

0

1

0

1

0

V_DD

SCL

SDA

SCL

SDA

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

7.2 Software Reset call, and Device ID addresses

Two other different addresses can be sent to the PCA9673.

• General Call address: allows to reset the PCA9673 through the I²C-bus upon

reception of the right I²C-bus sequence. See Section 7.2.1 “Software Reset” for more

information.

• Device ID address: allows to read ID information from the device (manufacturer, part

identification, revision). See Section 7.2.2 “Device ID (PCA9673 ID field)” for more

information.

R/W

0

002aac155

Fig 8. General Call address

R/W

1

0

002aab638

Fig 9. Device ID address

PCA9673

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Product data sheet

Rev. 2 — 29 September 2011

7 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

7.2.1 Software Reset

The Software Reset Call allows all the devices in the I²C-bus to be reset to the power-up

state value through a specific formatted I²C-bus command. To be performed correctly, it

implies that the I²C-bus is functional and that there is no device hanging the bus.

The Software Reset sequence is defined as following:

1. A START command is sent by the I²C-bus master.

2. The reserved General Call I²C-bus address ‘0000 000’ with the R/W bit set to 0 (write)

is sent by the I²C-bus master.

3. The PCA9673 device(s) acknowledge(s) after seeing the General Call address

‘0000 0000’ (00h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to

the I²C-bus master.

4. Once the General Call address has been sent and acknowledged, the master sends

1 byte. The value of the byte must be equal to 06h.

a. The PCA9673 acknowledges this value only. If the byte is not equal to 06h, the

PCA9673 does not acknowledge it.

If more than 1 byte of data is sent, the PCA9673 does not acknowledge any more.

5. Once the right byte has been sent and correctly acknowledged, the master sends a

STOP command to end the Software Reset sequence: the PCA9673 then resets to

the default value (power-up value) and is ready to be addressed again within the

specified bus free time. If the master sends a Repeated START instead, no reset is

performed.

The I²C-bus master must interpret a non-acknowledge from the PCA9673 (at any time) as

a ‘Software Reset Abort’. The PCA9673 does not initiate a reset of its registers.

The unique sequence that initiates a Software Reset is described in Figure 10.

2

SWRST Call I C-bus address

SWRST data = 06h

S

0

A

0

1

0

A

P

START condition

R/W

acknowledge

from slave(s)

acknowledge

from slave(s)

PCA9673 is(are) reset.

Registers are set to default power-up values.

002aac307

Fig 10. Software Reset sequence

PCA9673

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Product data sheet

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PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

7.2.2 Device ID (PCA9673 ID field)

The Device ID field is a 3-byte read-only (24 bits) word giving the following information:

• 8 bits with the manufacturer name, unique per manufacturer (for example,

NXP Semiconductors).

• 13 bits with the part identification, assigned by manufacturer, the 7 MSBs with the

category ID and the 6 LSBs with the feature ID (for example, PCA9673 16-bit

quasi-output I/O expander).

• 3 bits with the die revision, assigned by manufacturer (for example, Rev X).

The Device ID is read-only, hardwired in the device and can be accessed as follows:

1. START command

2. The master sends the Reserved Device ID I²C-bus address ‘1111 100’ with the R/W

bit set to 0 (write).

3. The master sends the I²C-bus slave address of the slave device it needs to identify.

The LSB is a ‘Don’t care’ value. Only one device must acknowledge this byte (the one

that has the I²C-bus slave address).

4. The master sends a Re-START command.

Remark: A STOP command followed by a START command will reset the slave state

machine and the Device ID read cannot be performed.

Remark: A STOP command or a Re-START command followed by an access to

another slave device will reset the slave state machine and the Device ID read cannot

be performed.

5. The master sends the Reserved Device ID I²C-bus address ‘1111 100’ with the R/W

bit set to 1 (read).

6. The device ID read can be done, starting with the 8 manufacturer bits (first byte +

4 MSB of the second byte), followed by the 13 part identification bits and then the

3 die revision bits (3 LSB of the third byte).

7. The master ends the reading sequence by NACKing the last byte, thus resetting the

slave device state machine and allowing the master to send the STOP command.

Remark: The reading of the Device ID can be stopped anytime by sending a NACK

command.

Remark: If the master continues to ACK the bytes after the third byte, the PCA9673

rolls back to the first byte and keeps sending the Device ID sequence until a NACK

has been detected.

For the PCA9673, the Device ID is as shown in Figure 11.

PCA9673

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Product data sheet

Rev. 2 — 29 September 2011

9 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

manufacturer

0

1

0

1

0

part identification

0

category identification

feature identification

revision

0

002aac333

Fig 11. PCA9673 ID

acknowledge from one

or several slave(s)

acknowledge from

slave to be identified

acknowledge from

slave to be identified

don't care

device ID address

S

1

0

A

A6 A5 A4 A3 A2 A1 A0

X

A

1

0

1

A

2

I C-bus slave address of

device ID address

START condition

R/W

the device to be identified

acknowledge

from master

acknowledge

from master

no acknowledge

from master

M7 M6 M5 M4 M3 M2 M1 M0

A

C6 C5 C4 C3 C2 C1 C0 F5

A

F4 P3 P2 P1 P0 R2 R1 R0

A

P

revision = 000

category identification

= 0000001

manufacturer name

= 00000000

feature identification

= 000100

STOP

condition

002aac334

If more than 2 bytes are read, the slave device loops back to the first byte (manufacturer byte) and

keeps sending data until the master generates a ‘no acknowledge’.

Fig 12. Device ID field reading

PCA9673

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Product data sheet

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10 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

8. I/O programming

8.1 Quasi-bidirectional I/O architecture

The PCA9673’s 16 ports (see Figure 2) are entirely independent and can be used either

as input or output ports. Input data is transferred from the ports to the microcontroller in

the Read mode (see Figure 15). Output data is transmitted to the ports in the Write mode

(see Figure 14).

Every data transmission from the PCA9673 must consist of an even number of bytes, the

first byte will be referred to as P07 to P00, and the second byte as P17 to P10. The third

will be referred to as P07 to P00, and so on.

This quasi-bidirectional I/O can be used as an input or output without the use of a control

signal for data directions. At power-on the I/Os are HIGH. In this mode only a current

source (I_OH) to V_DDis active. An additional strong pull-up to V_DD(I_trt(pu)) allows fast rising

edges into heavily loaded outputs. These devices turn on when an output is written HIGH,

and are switched off by the negative edge of SCL. The I/Os should be HIGH before being

used as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used as

inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the

write mode.

Remark: If a HIGH is applied to an I/O which has been written earlier to LOW, a large

current (I_OL) will flow to V_SS

.

8.2 Writing to the port (Output mode)

To write, the master (microcontroller) first addresses the slave device. By setting the last

bit of the byte containing the slave address to logic 0 the Write mode is entered. The

PCA9673 acknowledges and the master sends the first data byte for P07 to P00. After the

first data byte is acknowledged by the PCA9673, the second data byte P17 to P10 is sent

by the master. Once again, the PCA9673 acknowledges the receipt of the data. Each 8-bit

data is presented on the port lines after it has been acknowledged by the PCA9673.

The number of data bytes that can be sent successively is not limited. After every two

bytes, the previous data is overwritten.

The first data byte in every pair refers to Port 0 (P07 to P00), whereas the second data

byte in every pair refers to Port 1 (P17 to P10). See Figure 13.

first byte

second byte

07 06 05 04 03 02 01 00

P07 P06 P05 P04 P03 P02 P01 P00

A

17 16 15 14 13 12 11 10

P17 P16 P15 P14 P13 P12 P11 P10

A

002aab634

Fig 13. Correlation between bits and ports

PCA9673

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Product data sheet

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PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

SCL

1

2

3

4

5

6

7

8

9

slave address

A6 A5 A4 A3 A2 A1 A0

data to port 0

data to port 1

P

SDA

S

0

A

1

A

1

A

07 06

04 03 02 01 00

17

15 14 13 12 11 10

P05

acknowledge

from slave

P16

acknowledge

from slave

START condition

write to port

R/W

acknowledge

from slave

t

v(Q)

data output from port

P05 output voltage

data A0 and B0 valid

I

trt(pu)

P05 pull-up output current

P16 output voltage

I

OH

I

trt(pu)

P16 pull-up output current

INT

I

OH

t

d(rst)

002aab632

Fig 14. Write mode (output)

8.3 Reading from a port (Input mode)

All ports programmed as input should be set to logic 1. To read, the master

(microcontroller) first addresses the slave device after it receives the interrupt. By setting

the last bit of the byte containing the slave address to logic 1 the Read mode is entered.

The data bytes that follow on the SDA are the values on the ports. If the data on the input

port changes faster than the master can read, this data may be lost.

PCA9673

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Product data sheet

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PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

8.4 Power-on reset

When power is applied to V_DD, an internal Power-On Reset (POR) holds the PCA9673 in

a reset condition until V_DDhas reached V_POR. At that point, the reset condition is released

and the PCA9673 registers and I²C-bus/SMBus state machine will initialize to their default

states. Thereafter V_DDmust be lowered below 0.2 V to reset the device.

8.5 Interrupt output (INT)

The PCA9673 provides an open-drain interrupt (INT) which can be fed to a corresponding

input of the microcontroller (see Figure 15, Figure 16, and Figure 17). This gives these

chips a kind of master function which can initiate an action elsewhere in the system.

An interrupt is generated by any rising or falling edge of the port inputs. After time t_(v)Dthe

signal INT is valid.

The interrupt disappears when data on the port is changed to the original setting or data is

read from or written to the device which has generated the interrupt.

In the write mode, the interrupt may become deactivated (HIGH) on the rising edge of the

write to port pulse. On the falling edge of the write to port pulse the interrupt is definitely

deactivated (HIGH).

The interrupt is reset in the read mode on the rising edge of the read from port pulse.

During the resetting of the interrupt itself, any changes on the I/Os may not generate an

interrupt. After the interrupt is reset any change in I/Os will be detected and transmitted as

an INT.

V

DD

device 1

device 2

device 8

PCA9673

MICROCOMPUTER

INT

002aac308

Fig 17. Application of multiple PCA9673s with interrupt

8.6 RESET input

A reset can be accomplished by holding the RESET pin LOW for a minimum of t_w(rst). The

PCA9673 registers and I²C-bus state machine will be held in their default state until the

RESET input is once again HIGH.

PCA9673

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Product data sheet

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15 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

9. Characteristics of the I²C-bus

The I²C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 18).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 18. Bit transfer

9.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition (P) (see Figure 19).

SDA

SCL

S

P

STOP condition

START condition

mba608

Fig 19. Definition of START and STOP conditions

9.2 System configuration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 20).

PCA9673

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Product data sheet

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16 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

SDA

SCL

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

2

SLAVE

RECEIVER

MASTER

TRANSMITTER

I C-BUS

MULTIPLEXER

SLAVE

002aaa966

Fig 20. System configuration

9.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from master

1

2

8

9

S

clock pulse for

START

condition

acknowledgement

002aaa987

Fig 21. Acknowledgement on the I²C-bus

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Product data sheet

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17 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

10. Application design-in information

10.1 Bidirectional I/O expander applications

In the 8-bit I/O expander application shown in Figure 22, P00 and P01 are inputs, and P02

to P07 are outputs. When used in this configuration, during a write, the input (P00 and

P01) must be written as HIGH so the external devices fully control the input ports. The

desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P02 to

P07). During a read, the logic levels of the external devices driving the input ports (P00

and P01) and the previous written logic level to the output ports (P02 to P07) will be read.

The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of

the microprocessor. By sending an interrupt signal on this line, the remote I/O informs the

microprocessor that there is incoming data or a change of data on its ports without having

to communicate via the I²C-bus.

V

DD

V

DD

V

DD

SDA

SCL

INT

P00

P01

P02

P03

P04

P05

P06

P07

temperature sensor

battery status

CORE

PROCESSOR

control for latch

control for switch

control for audio

control for camera

control for MP3

RESET

AD0

AD1

002aac310

Fig 22. Bidirectional I/O expander application

10.2 High current-drive load applications

The GPIO has a maximum sinking current of 25 mA per bit. In applications requiring

additional drive, two port pins in the same octal may be connected together to sink up to

50 mA current. Both bits must then always be turned on or off together. Up to 8 pins (one

octal) can be connected together to drive 200 mA.

V

DD

V

DD

SDA

SCL

INT

P00

P01

P02

P03

P04

P05

P06

P07

CORE

PROCESSOR

LOAD

RESET

AD0

AD1

002aac311

Fig 23. High current-drive load application

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Product data sheet

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18 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

10.3 Differences between the PCA9673 and the PCF8575

The PCA9673 is a drop in replacement for the PCF8575 and can used without electrical

or software modifications, but there is a difference in interrupt output release timing during

the read operation.

Write operations are identical. At the completion of each 8-bit write sequence the data is

stored in its associated 8-bit write register at ACK or NACK. The first byte goes to P0n

while the second goes to P1n. Subsequent writes without a STOP wrap around to P0n

then P1n again. Any write will update both read registers and clear interrupts.

Read operations are identical. Both devices update the byte register with the pin data as

each 8-bit read is initiated, the very first read after an address cycle corresponds to ports

P0n while the second (even byte) corresponds to P1n and subsequent reads without a

STOP wrap around to P0n then P1n again.

During read operations, the PCA9673 interrupt output will be cleared in a byte-wise

fashion as each byte is read. Reading the first byte will clear any interrupts associated

with the P0n pins. This first byte read operation will have no effect on interrupts associated

with changes of state on the P1n pins. Interrupts associated with the P1n pins will be

cleared when the second byte is read. Reading the second byte has no effect on

interrupts associated with the changes of state on the P0x pins. The PCF8575 interrupt

output will clear after reading both bytes of data regardless of whether data was changed

in the first byte or the second byte or both bytes.

11. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

I_DD

Parameter

Conditions

Min

Max

+6

Unit

V

supply voltage

0.5

supply current

-

100

600

5.5

mA

V

I_SS

ground supply current

input voltage

-

V_I

V_SS 0.5

I_I

input current

-

20

50^[1]

mA

mW

C

I_O

output current

-

P_tot

P/out

T_stg

T_amb

total power dissipation

power dissipation per output

storage temperature

ambient temperature

-

600

-

200

65

40

+150

+85

operating

C

[1] Total package (maximum) output current is 600 mA.

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Product data sheet

Rev. 2 — 29 September 2011

19 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

12. Static characteristics

Table 5.

Static characteristics

V_DD= 2.3 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol Parameter

Supplies

Conditions

Min

Typ

Max

Unit

V_DD

I_DD

supply voltage

supply current

2.3

-

5.5

V

operating mode; no load;

200

500

A

V_I= V_DDor V_SS; f_SCL= 400 kHz

I_stb

standby current

standby mode; no load;

V_I= V_DDor V_SS

-

2.5

1.8

10

A

[1]

V_POR

power-on reset voltage

2.0

V

Input SCL; input/output SDA

V_IL

V_IH

I_OL

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

0.5

0.7V_DD

20

-

4

+0.3V_DD

V

5.5

-

V

V_OL= 0.4 V; V_DD= 2.3 V

V_OL= 0.4 V; V_DD= 3.0 V

V_OL= 0.4 V; V_DD= 4.5 V

V_I= V_DDor V_SS

mA

A

pF

25

-

30

-

I_L

leakage current

1

+1

10

C_i

input capacitance

V_I= V_SS

-

I/Os; P00 to P07 and P10 to P17

[2]

I_OL

LOW-level output current

V_OL= 0.5 V; V_DD= 2.3 V

V_OL= 0.5 V; V_DD= 3.0 V

V_OL= 0.5 V; V_DD= 4.5 V

V_OH= V_SS

12

17

25

-

27

35

42

-

mA

A

-

I_OL(tot)

I_OH

I_trt(pu)

C_i

total LOW-level output current

HIGH-level output current

400

300

-

30

0.5

-

150

1.0

4

transient boosted pull-up current V_OH= V_SS; see Figure 14

input capacitance

mA

pF

[3]

10

C_o

output capacitance

-

4

pF

Interrupt INT

I_OL

C_o

LOW-level output current

output capacitance

V_OL= 0.4 V

6

-

mA

pF

3

5

Input RESET

V_IL

V_IH

I_LI

LOW-level input voltage

0.5

2

-

+0.8

5.5

+1

V

HIGH-level input voltage

input leakage current

input capacitance

-

V

1

-

A

pF

C_i

3

5

Inputs AD0, AD1

V_IL

V_IH

I_LI

LOW-level input voltage

0.5

0.7V_DD

1

-

+0.3V_DD

V

HIGH-level input voltage

input leakage current

input capacitance

-

5.5

+1

5

V

-

A

pF

C_i

-

3

[1] The power-on reset circuit resets the I²C-bus logic with V_DD< V_PORand set all I/Os to logic 1 (with current source to V_DD).

PCA9673

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Product data sheet

Rev. 2 — 29 September 2011

20 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal busing limits.

[3] The value is not tested, but verified on sampling basis.

13. Dynamic characteristics

Table 6.

Dynamic characteristics

V_DD= 2.3 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol Parameter

Conditions

Standard mode Fast mode I²C-bus

I²C-bus

Fast-mode

Plus I²C-bus

Unit

Min

0

Max

100

-

Min

0

Max

400

-

Min

0

Max

1000 kHz

f_SCL

SCL clock frequency

t_BUF

bus free time between a

STOP and START condition

4.7

1.3

0.5

-

s

ns

t_HD;STA

t_SU;STA

hold time (repeated) START

condition

4.0

4.7

4.0

-

0.6

-

0.26

set-up time for a repeated

START condition

t_SU;STOset-up time for STOP

condition

t_HD;DAT

data hold time

0

-

0

-

0

[1]

[2]

t_VD;ACKdata valid acknowledge time

0.3

300

250

4.7

4.0

3.45

0.1

50

0.9

0.05

50

0.45 s

t_VD;DAT

t_SU;DAT

t_LOW

data valid time

-

450 ns

data set-up time

100

1.3

0.6

50

-

ns

s

LOW period of the SCL clock

0.5

0.26

t_HIGH

HIGH period of the SCL

clock

[4][5]

[3]

t_f

fall time of both SDA and

SCL signals

-

300

20 + 0.1C_b

300

50

-

120 ns

t_r

rise time of both SDA and

SCL signals

1000 20 + 0.1C_b

[6]

t_SP

pulse width of spikes that

must be suppressed by the

input filter

50

-

50

ns

Port timing; C_L 100 pF (see Figure 14 and Figure 15)

t_v(Q)

t_su(D)

t_h(D)

data output valid time

data input set-up time

data input hold time

-

4

-

4

-

4

-

s

0

4

0

4

0

4

-

Interrupt timing; C_L 100 pF (see Figure 14 and Figure 15)

t_v(D)

data input valid time

reset delay time

-

4

-

4

-

4

s

t_d(rst)

Reset timing (see Figure 25)

t_w(rst)

t_rec(rst)

t_rst

reset pulse width

reset recovery time

reset time

4

0

-

4

0

-

4

0

-

ns

100

[1] t_VD;ACK= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[2] t_VD;DAT= minimum time for SDA data out to be valid following SCL LOW.

PCA9673

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Product data sheet

Rev. 2 — 29 September 2011

21 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

[3] C_b= total capacitance of one bus line in pF.

[4] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V_ILof the SCL signal) in order to

bridge the undefined region SCL’s falling edge.

[5] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t_fis specified at

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without

exceeding the maximum specified t_f.

[6] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

START

condition

(S)

bit 7

MSB

(A7)

STOP

condition

(P)

bit 6

(A6)

bit 0 acknowledge

(R/W) (A)

protocol

t

HIGH

SU;STA

LOW

1 / f

SCL

0.7 × V

0.3 × V

DD

SCL

SDA

DD

t

BUF

f

t

r

0.7 × V

0.3 × V

DD

t

HD;DAT

VD;DAT

VD;ACK

SU;STO

HD;STA

SU;DAT

002aab175

Rise and fall times refer to V_ILand V_IH

.

Fig 24. I²C-bus timing diagram

ACK or read cycle

START

SCL

SDA

30 %

t

rst

RESET

50 %

t

rec(rst)

t

w(rst)

t

rst

50 %

P0n, P1n

output off

002aac282

Fig 25. Reset timing

PCA9673

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Product data sheet

Rev. 2 — 29 September 2011

22 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

14. Package outline

SO24: plastic small outline package; 24 leads; body width 7.5 mm

SOT137-1

D

E

A

X

c

H

v

M

A

E

y

Z

24

13

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

12

w

detail X

e

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

15.6

15.2

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.1

0.25

0.01

1.27

0.05

1.4

0.25 0.25

0.01

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.61

0.014 0.009 0.60

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches

0.055

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT137-1

075E05

MS-013

Fig 26. Package outline SOT137-1 (SO24)

PCA9673

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Product data sheet

Rev. 2 — 29 September 2011

23 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm

SOT355-1

D

E

A

X

c

H

v

M

A

y

E

Z

13

24

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

1

12

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

7.9

7.7

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.5

0.2

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT355-1

MO-153

Fig 27. Package outline SOT355-1 (TSSOP24)

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Product data sheet

Rev. 2 — 29 September 2011

24 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 4 x 4 x 0.85 mm

SOT616-1

B

A

D

terminal 1

index area

A

1

E

c

detail X

e

1

C

1/2 e

y

C

1

e

v

M

C

A

B

b

7

12

w

L

13

6

e

E

h

2

1/2 e

1

18

terminal 1

index area

24

19

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

max.

(1)

UNIT

mm

A

b

c

E

e

y

D

E

L

v

w

y

1

h

1

2

h

0.05 0.30

0.00 0.18

4.1

3.9

2.25

1.95

4.1

3.9

2.25

1.95

0.5

0.3

0.05

0.1

1

0.2

0.5

2.5

0.1 0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-22

SOT616-1

- - -

MO-220

- - -

Fig 28. Package outline SOT616-1 (HVQFN24)

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Product data sheet

Rev. 2 — 29 September 2011

25 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;

no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm

SOT815-1

D

B

A

E

1

c

detail X

terminal 1

index area

C

e

1

terminal 1

index area

y

v

M

C

A B

C

1

e

b

w M

2

11

L

12

13

1

e

2

E

h

24

23

14

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

D

E

h

e

L

v

w

y

1

2

1

h

max.

0.05 0.30

0.00 0.18

5.6

5.4

4.25

3.95

3.6

3.4

2.25

1.95

0.5

0.3

mm

1

0.2

0.5

4.5

1.5

0.1

0.05 0.05

0.1

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

03-04-29

SOT815-1

- - -

Fig 29. Package outline SOT815-1 (DHVQFN24)

PCA9673

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Product data sheet

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26 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

15. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate precautions are taken as

described in JESD625-A or equivalent standards.

16. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

16.3 Wave soldering

Key characteristics in wave soldering are:

PCA9673

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Product data sheet

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27 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

16.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 30) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 7 and 8

Table 7.

SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

 350

220

< 2.5

235

220

 2.5

220

Table 8.

Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 30.

PCA9673

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 29 September 2011

28 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 30. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

17. Abbreviations

Table 9.

Abbreviations

Description

Acronym

CDM

CMOS

ESD

Charged Device Model

Complementary Metal Oxide Semiconductor

ElectroStatic Discharge

GPIO

HBM

General Purpose Input/Output

Human Body Model

I²C-bus

Inter-Integrated Circuit bus

Identification

ID

LED

Light Emitting Diode

LSB

Least Significant Bit

MSB

Most Significant Bit

PLC

Programmable Logic Controller

Redundant Array of Independent Disks

System Management Bus

RAID

SMBus

PCA9673

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 29 September 2011

29 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

18. Revision history

Table 10. Revision history

Document ID

PCA9673 v.2

Modifications:

Release date

Data sheet status

Change notice

Supersedes

20110929

Product data sheet

-

PCA9673 v.1

• Section 2 “Features and benefits”:]

–

13th bullet item: deleted phrase “200 V MM per JESD22-A115”

–

15th bullet item: deleted “SSOP24, QSOP24”

• Table 1 “Ordering information”: removed discontinued products

–

removed type number PCA9673DB (SSOP24)

–

removed type number PCA9673DK (SSOP24 [also known as QSOP24])

• Section 6.1 “Pinning”:

–

deleted (old) Figure 5, Pin configuration for SSOP24 (QSOP24)

–

deleted (old) Figure 6, Pin configuration for SSOP24

• Table 2 “Pin description”: deleted “SSOP24” from heading of second column

• Table 5 “Static characteristics”, sub-section “Input RESET” is corrected by removing

“I_OH, HIGH-level output current” table row.

• Figure 24 “I²C-bus timing diagram” modified: added 0.7  V_DDand 0.3  V_DDlevel lines

• Section 14 “Package outline”:

–

deleted package outline SOT340-1 (SSOP24)

–

deleted package outline SOT556-1 (SSOP24)

PCA9673 v.1

20070201

Product data sheet

-

PCA9673

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 29 September 2011

30 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

19.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

19.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

PCA9673

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 29 September 2011

31 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

non-automotive qualified products in automotive equipment or applications.

19.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP B.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PCA9673

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 29 September 2011

32 of 33

PCA9673

NXP Semiconductors

Remote 16-bit I/O expander for Fm+ I²C-bus with interrupt and reset

21. Contents

1

2

3

4

5

General description. . . . . . . . . . . . . . . . . . . . . . 1

19.1

19.2

19.3

19.4

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

20

21

Contact information . . . . . . . . . . . . . . . . . . . . 32

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7

7.1

7.1.1

7.2

7.2.1

7.2.2

Functional description . . . . . . . . . . . . . . . . . . . 6

Device address. . . . . . . . . . . . . . . . . . . . . . . . . 6

Address maps. . . . . . . . . . . . . . . . . . . . . . . . . . 6

Software Reset call, and Device ID addresses. 7

Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . 8

Device ID (PCA9673 ID field). . . . . . . . . . . . . . 9

8

I/O programming . . . . . . . . . . . . . . . . . . . . . . . 11

Quasi-bidirectional I/O architecture . . . . . . . . 11

Writing to the port (Output mode) . . . . . . . . . . 11

Reading from a port (Input mode) . . . . . . . . . 12

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 15

Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 15

RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.1

8.2

8.3

8.4

8.5

8.6

9

Characteristics of the I²C-bus . . . . . . . . . . . . 16

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

START and STOP conditions . . . . . . . . . . . . . 16

System configuration . . . . . . . . . . . . . . . . . . . 16

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 17

9.1

9.1.1

9.2

9.3

10

Application design-in information . . . . . . . . . 18

Bidirectional I/O expander applications . . . . . 18

High current-drive load applications . . . . . . . . 18

Differences between the PCA9673

10.1

10.2

10.3

and the PCF8575 . . . . . . . . . . . . . . . . . . . . . . 19

11

12

13

14

15

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19

Static characteristics. . . . . . . . . . . . . . . . . . . . 20

Dynamic characteristics . . . . . . . . . . . . . . . . . 21

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23

Handling information. . . . . . . . . . . . . . . . . . . . 27

16

Soldering of SMD packages . . . . . . . . . . . . . . 27

Introduction to soldering . . . . . . . . . . . . . . . . . 27

Wave and reflow soldering . . . . . . . . . . . . . . . 27

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 27

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 28

16.1

16.2

16.3

16.4

17

18

19

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 30

Legal information. . . . . . . . . . . . . . . . . . . . . . . 31

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 29 September 2011

Document identifier: PCA9673


型号：	935283587118
厂家：	NXP
描述：	18 I/O, PIA-GENERAL PURPOSE, PQCC24 外围集成电路
文件：	总33页 (文件大小：283K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

935283587118 [NXP]

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