935314424557_技术文档

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MPC5604P

Rev. 8, 07/2012

MPC5604P

144 LQFP

20 mm x 20 mm

100 LQFP

14 mm x 14 mm

Qorivva MPC5604P

Microcontroller Data Sheet

•

Up to 64 MHz, single issue, 32-bit CPU core complex

(e200z0h)

—

1 safety port based on FlexCAN with 32 message

objects and up to 7.5 Mbit/s capability; usable as

second CAN when not used as safety port

1 FlexRay™ module (V2.1) with selectable dual or

single channel support, 32 message objects and up to

10 Mbit/s

—

Compliant with Power Architecture embedded

category

—

Variable Length Encoding (VLE)

•

Memory organization

•

Two 10-bit analog-to-digital converters (ADC)

—

Up to 512 KB on-chip code flash memory with ECC

and erase/program controller

Optional 64 (4 × 16) KB on-chip data flash memory

with ECC for EEPROM emulation

—

2 × 15 input channels, 4 channels shared between the

two ADCs

—

Conversion time < 1 µs including sampling time at

full precision

Up to 40 KB on-chip SRAM with ECC

—

Programmable Cross Triggering Unit (CTU)

4 analog watchdogs with interrupt capability

•

Fail safe protection

—

Programmable watchdog timer

Non-maskable interrupt

Fault collection unit

•

On-chip CAN/UART bootstrap loader with Boot Assist

Module (BAM)

1 FlexPWM unit

•

Nexus L2+ interface

Interrupts

—

8 complementary or independent outputs with ADC

synchronization signals

Polarity control, reload unit

Integrated configurable dead time unit and inverter

fault input pins

16-bit resolution, up to 2 × f_CPU

Lockable configuration

—

16-channel eDMA controller

16 priority level controller

—

•

General purpose I/Os individually programmable as input,

output or special function

2 general purpose eTimer units

—

6 timers each with up/down count capabilities

16-bit resolution, cascadable counters

Quadrature decode with rotation direction flag

Double buffer input capture and output compare

•

Clock generation

—

4–40 MHz main oscillator

16 MHz internal RC oscillator

Software controlled FMPLL capable of speeds as fast

as 64 MHz

•

Communications interfaces

—

2 LINFlex channels (LIN 2.1)

4 DSPI channels with automatic chip select

generation

•

Voltage supply

—

3.3 V or 5 V supply for I/Os and ADC

On-chip single supply voltage regulator with external

ballast transistor

—

1 FlexCAN interface (2.0B Active) with 32 message

objects

•

Operating temperature ranges: –40 to 125 °C or –40

to 105 °C

Freescale reserves the right to change the detail specifications as may be required to permit

improvements in the design of its products.

Table of Contents

1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.2.3 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.5.1 High performance e200z0 core processor. . . . . .7

1.5.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . .8

1.5.3 Enhanced direct memory access (eDMA) . . . . . .8

1.5.4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . .8

1.5.5 Static random access memory (SRAM). . . . . . . .9

1.5.6 Interrupt controller (INTC) . . . . . . . . . . . . . . . . . .9

1.5.7 System status and configuration module

3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . 38

3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . 39

3.4 Recommended operating conditions. . . . . . . . . . . . . . 42

3.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 46

3.5.1 Package thermal characteristics . . . . . . . . . . . 46

3.5.2 General notes for specifications at maximum

junction temperature . . . . . . . . . . . . . . . . . . . . 47

3.6 Electromagnetic interference (EMI) characteristics. . . 48

3.7 Electrostatic discharge (ESD) characteristics . . . . . . . 48

3.8 Power management electrical characteristics . . . . . . . 49

3.8.1 Voltage regulator electrical characteristics. . . . 49

3.8.2 Voltage monitor electrical characteristics . . . . . 52

3.9 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . 53

3.10 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . 55

3.10.1 NVUSRO register. . . . . . . . . . . . . . . . . . . . . . . 55

3.10.2 DC electrical characteristics (5 V) . . . . . . . . . . 55

3.10.3 DC electrical characteristics (3.3 V) . . . . . . . . . 57

3.10.4 Input DC electrical characteristics definition . . 58

3.10.5 I/O pad current specification. . . . . . . . . . . . . . . 59

3.11 Main oscillator electrical characteristics . . . . . . . . . . . 64

3.12 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 65

3.13 16 MHz RC oscillator electrical characteristics . . . . . . 67

3.14 Analog-to-digital converter (ADC) electrical

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.14.1 Input impedance and ADC accuracy . . . . . . . . 68

3.14.2 ADC conversion characteristics . . . . . . . . . . . . 72

3.15 Flash memory electrical characteristics. . . . . . . . . . . . 74

3.16 AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.16.1 Pad AC specifications . . . . . . . . . . . . . . . . . . . 75

3.17 AC timing characteristics. . . . . . . . . . . . . . . . . . . . . . . 76

3.17.1 RESET pin characteristics . . . . . . . . . . . . . . . . 76

3.17.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . . 78

3.17.3 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3.17.4 External interrupt timing (IRQ pin) . . . . . . . . . . 83

3.17.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 90

4.1.1 144 LQFP mechanical outline drawing . . . . . . 90

4.1.2 100 LQFP mechanical outline drawing . . . . . . 92

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

(SSCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.5.8 System clocks and clock generation . . . . . . . . .10

1.5.9 Frequency-modulated phase-locked loop

(FMPLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.5.10 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.5.11 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . .11

1.5.12 Periodic interrupt timer (PIT) . . . . . . . . . . . . . . .11

1.5.13 System timer module (STM) . . . . . . . . . . . . . . .11

1.5.14 Software watchdog timer (SWT) . . . . . . . . . . . .11

1.5.15 Fault collection unit (FCU). . . . . . . . . . . . . . . . .12

1.5.16 System integration unit – Lite (SIUL). . . . . . . . .12

1.5.17 Boot and censorship . . . . . . . . . . . . . . . . . . . . .12

1.5.18 Error correction status module (ECSM). . . . . . .13

1.5.19 Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . .13

1.5.20 Controller area network (FlexCAN) . . . . . . . . . .13

1.5.21 Safety port (FlexCAN) . . . . . . . . . . . . . . . . . . . .14

1.5.22 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

1.5.23 Serial communication interface module

(LINFlex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

1.5.24 Deserial serial peripheral interface (DSPI) . . . .15

1.5.25 Pulse width modulator (FlexPWM) . . . . . . . . . .16

1.5.26 eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

1.5.27 Analog-to-digital converter (ADC) module. . . . .17

1.5.28 Cross triggering unit (CTU) . . . . . . . . . . . . . . . .18

1.5.29 Nexus development interface (NDI). . . . . . . . . .18

1.5.30 Cyclic redundancy check (CRC) . . . . . . . . . . . .19

1.5.31 IEEE 1149.1 JTAG controller. . . . . . . . . . . . . . .19

1.5.32 On-chip voltage regulator (VREG). . . . . . . . . . .19

Package pinouts and signal descriptions . . . . . . . . . . . . . . . .20

2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2.2.1 Power supply and reference voltage pins . . . . .21

2.2.2 System pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4

5

2

Appendix AAbbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . 98

6

MPC5604P Microcontroller Data Sheet, Rev. 8

2

Freescale

1

Introduction

1.1

Document overview

This document provides electrical specifications, pin assignments, and package diagrams for the MPC5603P/4P series of

microcontroller units (MCUs). It also describes the device features and highlights important electrical and physical

characteristics. For functional characteristics, refer to the device reference manual.

1.2

Description

This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest achievement in integrated automotive

application controllers. It belongs to an expanding range of automotive-focused products designed to address chassis

applications—specifically, electrical hydraulic power steering (EHPS) and electric power steering (EPS)—as well as airbag

applications.

This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture

technology.

The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture

embedded category. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power

consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported

with software drivers, operating systems and configuration code to assist with users implementations.

1.3

Device comparison

Table 1 provides a summary of different members of the MPC5604P family and their features to enable a comparison among

the family members and an understanding of the range of functionality offered within this family.

Table 1. MPC5604P device comparison

Feature

MPC5603P

MPC5604P

Code flash memory (with ECC)

Data flash memory / EE option (with ECC)

SRAM (with ECC)

384 KB

512 KB

64 KB (optional feature)

36 KB

40 KB

Processor core

32-bit e200z0h

Instruction set

VLE (variable length encoding)

CPU performance

0–64 MHz

2

FMPLL (frequency-modulated phase-locked loop)

module

INTC (interrupt controller) channels

PIT (periodic interrupt timer)

eDMA (enhanced direct memory access) channels

FlexRay¹

147

1 (includes four 32-bit timers)

16

Optional feature

FlexCAN (controller area network)

Safety port

2^2,3

Yes (via second FlexCAN module)

FCU (fault collection unit)

CTU (cross triggering unit)

Yes

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

3

Table 1. MPC5604P device comparison (continued)

Feature

MPC5603P

MPC5604P

eTimer

2 (16-bit, 6 channels)

FlexPWM (pulse-width modulation) channels

ADC (analog-to-digital converter)

LINFlex

8 (capturing on X-channels)

2 (10-bit, 15-channel⁴)

2

DSPI (deserial serial peripheral interface)

CRC (cyclic redundancy check) unit

JTAG controller

4

Yes

Nexus port controller (NPC)

Yes (Level 2+)

Supply

Digital power supply

Analog power supply

Internal RC oscillator

External crystal oscillator

3.3 V or 5 V single supply with external transistor

3.3 V or 5 V

16 MHz

4–40 MHz

Packages

100 LQFP

144 LQFP

Temperature

Standard ambient temperature

–40 to 125 °C

1

32 message buffers, selectable single or dual channel support

Each FlexCAN module has 32 message buffers.

2

3

4

One FlexCAN module can act as a Safety Port with a bit rate as high as 7.5 Mbit/s.

Four channels shared between the two ADCs

1.4

Block diagram

Figure 1 shows a top-level block diagram of the MPC5604P MCU.

MPC5604P Microcontroller Data Sheet, Rev. 8

4

Freescale

External ballast

1.2 V regulator

e200z0 Core

32-bit

general

purpose

registers

control

XOSC

Integer

execution

unit

Special

purpose

registers

Exception

handler

Interrupt

controller

16 MHz

RC oscillator

FMPLL_0

(System)

Variable

length

encoded

instructions

Instruction

unit

FMPLL_1

(FlexRay, MotCtrl)

Branch

prediction

unit

Load/store

unit

JTAG

Nexus port

controller

Nexus 2+

eDMA

16 channels

FlexRay

Instruction

32-bit

Data

32-bit

Master

Crossbar switch (XBAR, AMBA 2.0 v6 AHB)

Slave Slave

Slave

Code Flash

(with ECC)

Data Flash

(with ECC)

SRAM

(with ECC)

Peripheral bridge

10-bit

ADC_0

10-bit

ADC_1

Legend:

ADC

BAM

CRC

CTU

Analog-to-digital converter

Boot assist module

Cyclic redundancy check

Cross triggering unit

LINFlex

Serial communication interface (LIN support)

Mode entry module

MC_CGM Clock generation module

MC_ME

MC_PCU Power control unit

DSPI

ECSM

eDMA

eTimer

FCU

Deserial serial peripheral interface

Error correction status module

Enhanced direct memory access

Enhanced timer

Fault collection unit

Flash memory

MC_RGM Reset generation module

PIT

Periodic interrupt timer

System integration unit Lite

Static random-access memory

System status and configuration module

System timer module

SIUL

SRAM

SSCM

STM

Flash

FlexCAN Controller area network

FlexPWM Flexible pulse width modulation

SWT

Software watchdog timer

Wakeup unit

External oscillator

WKPU

XOSC

XBAR

FMPLL

INTC

JTAG

Frequency-modulated phase-locked loop

Interrupt controller

JTAG controller

Crossbar switch

Figure 1. MPC5604P block diagram

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

5

Table 2. MPC5604P series block summary

Function

Block

Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter

Boot assist module (BAM)

Block of read-only memory containing VLE code which is executed according to

the boot mode of the device

Clock generation module

(MC_CGM)

Provides logic and control required for the generation of system and peripheral

clocks

Controller area network (FlexCAN) Supports the standard CAN communications protocol

Cross triggering unit (CTU)

Enables synchronization of ADC conversions with a timer event from the eMIOS

or from the PIT

Crossbar switch (XBAR)

Supports simultaneous connections between two master ports and three slave

ports; supports a 32-bit address bus width and a 32-bit data bus width

Cyclic redundancy check (CRC) CRC checksum generator

Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices

(DSPI)

Enhanced direct memory access Performs complex data transfers with minimal intervention from a host processor

(eDMA)

via “n” programmable channels

Enhanced timer (eTimer)

Provides enhanced programmable up/down modulo counting

Error correction status module

(ECSM)

Provides a myriad of miscellaneous control functions for the device including

program-visible information about configuration and revision levels, a reset

status register, wakeup control for exiting sleep modes, and optional features

such as information on memory errors reported by error-correcting codes

External oscillator (XOSC)

Provides an output clock used as input reference for FMPLL_0 or as reference

clock for specific modules depending on system needs

Fault collection unit (FCU)

Flash memory

Provides functional safety to the device

Provides non-volatile storage for program code, constants and variables

Frequency-modulated

phase-locked loop (FMPLL)

Generates high-speed system clocks and supports programmable frequency

modulation

Interrupt controller (INTC)

JTAG controller

Provides priority-based preemptive scheduling of interrupt requests

Provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode

LINFlex controller

Manages a high number of LIN (Local Interconnect Network protocol) messages

efficiently with minimum load on CPU

Mode entry module (MC_ME)

Provides a mechanism for controlling the device operational mode and mode

transition sequences in all functional states; also manages the power control unit,

reset generation module and clock generation module, and holds the

configuration, control and status registers accessible for applications

Periodic interrupt timer (PIT)

Peripheral bridge (PBRIDGE)

Power control unit (MC_PCU)

Produces periodic interrupts and triggers

Interface between the system bus and on-chip peripherals

Reduces the overall power consumption by disconnecting parts of the device

from the power supply via a power switching device; device components are

grouped into sections called “power domains” which are controlled by the PCU

MPC5604P Microcontroller Data Sheet, Rev. 8

6

Freescale

Table 2. MPC5604P series block summary (continued)

Function

Block

Pulse width modulator (FlexPWM) Contains four PWM submodules, each of which is capable of controlling a single

half-bridge power stage and two fault input channels

Reset generation module

(MC_RGM)

Centralizes reset sources and manages the device reset sequence of the device

Static random-access memory

(SRAM)

Provides storage for program code, constants, and variables

System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits

of bidirectional, general-purpose input and output signals and supports up to 32

external interrupts with trigger event configuration

System status and configuration Provides system configuration and status data (such as memory size and status,

module (SSCM)

device mode and security status), device identification data, debug status port

enable and selection, and bus and peripheral abort enable/disable

System timer module (STM)

Provides a set of output compare events to support AUTOSAR¹and operating

system tasks

System watchdog timer (SWT)

Wakeup unit (WKPU)

Provides protection from runaway code

Supports up to 18 external sources that can generate interrupts or wakeup

events, 1 of which can cause non-maskable interrupt requests or wakeup events

1

AUTOSAR: AUTomotive Open System ARchitecture (see http://www.autosar.org)

Feature details

1.5

1.5.1

High performance e200z0 core processor

The e200z0 Power Architecture core provides the following features:

•

High performance e200z0 core processor for managing peripherals and interrupts

Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU

Harvard architecture

Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions

— Results in smaller code size footprint

— Minimizes impact on performance

•

Branch processing acceleration using lookahead instruction buffer

Load/store unit

— 1 cycle load latency

— Misaligned access support

— No load-to-use pipeline bubbles

•

Thirty-two 32-bit general purpose registers (GPRs)

Separate instruction bus and load/store bus Harvard architecture

Hardware vectored interrupt support

Reservation instructions for implementing read-modify-write constructs

Long cycle time instructions, except for guarded loads, do not increase interrupt latency

Extensive system development support through Nexus debug port

Non-maskable interrupt support

MPC5604P Microcontroller Data Sheet, Rev. 8

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7

1.5.2

Crossbar switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. The

crossbar supports a 32-bit address bus width and a 32-bit data bus width.

The crossbar allows for two concurrent transactions to occur from any master port to any slave port; but one of those transfers

must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master

port, arbitration logic will select the higher priority master and grant it ownership of the slave port. All other masters requesting

that slave port will be stalled until the higher priority master completes its transactions. Requesting masters will be treated with

equal priority and will be granted access to a slave port in round-robin fashion, based upon the ID of the last master to be granted

access.

The crossbar provides the following features:

•

4 master ports:

— e200z0 core complex Instruction port

— e200z0 core complex Load/Store Data port

— eDMA

— FlexRay

•

3 slave ports:

— Flash memory (code flash and data flash)

— SRAM

— Peripheral bridge

•

32-bit internal address, 32-bit internal data paths

Fixed Priority Arbitration based on Port Master

Temporary dynamic priority elevation of masters

1.5.3

Enhanced direct memory access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data

movements via 16 programmable channels, with minimal intervention from the host processor. The hardware micro architecture

includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,

along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation

is utilized to minimize the overall block size.

The eDMA module provides the following features:

•

16 channels support independent 8, 16 or 32-bit single value or block transfers

Supports variable sized queues and circular queues

Source and destination address registers are independently configured to either post-increment or to remain constant

Each transfer is initiated by a peripheral, CPU, or eDMA channel request

Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block

transfer

•

DMA transfers possible between system memories, DSPIs, ADC, FlexPWM, eTimer and CTU

Programmable DMA channel multiplexer for assignment of any DMA source to any available DMA channel with as

many as 30 request sources

•

eDMA abort operation through software

1.5.4

Flash memory

The MPC5604P provides as much as 576 KB of programmable, non-volatile, flash memory. The non-volatile memory (NVM)

can be used for instruction and/or data storage. The flash memory module interfaces the system bus to a dedicated flash memory

MPC5604P Microcontroller Data Sheet, Rev. 8

8

Freescale

array controller. It supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory.

The module contains four 128-bit wide prefetch buffers. Prefetch buffer hits allow no-wait responses. Normal flash memory

array accesses are registered and are forwarded to the system bus on the following cycle, incurring two wait-states.

The flash memory module provides the following features:

•

As much as 576 KB flash memory

— 8 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 3×128 KB) code flash

— 4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash

— Full Read While Write (RWW) capability between code and data flash

•

Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch buffers can be configured to

prefetch code or data or both)

•

Typical flash memory access time: 0 wait states for buffer hits, 2 wait states for page buffer miss at 64 MHz

Hardware managed flash memory writes handled by 32-bit RISC Krypton engine

Hardware and software configurable read and write access protections on a per-master basis

Configurable access timing allowing use in a wide range of system frequencies

Multiple-mapping support and mapping-based block access timing (up to 31 additional cycles) allowing use for

emulation of other memory types.

•

Software programmable block program/erase restriction control

Erase of selected block(s)

Read page sizes

— Code flash memory: 128 bits (4 words)

— Data flash memory: 32 bits (1 word)

•

ECC with single-bit correction, double-bit detection for data integrity

— Code flash memory: 64-bit ECC

— Data flash memory: 64-bit ECC

•

Embedded hardware program and erase algorithm

Erase suspend, program suspend and erase-suspended program

Censorship protection scheme to prevent flash memory content visibility

Hardware support for EEPROM emulation

1.5.5

Static random access memory (SRAM)

The MPC5604P SRAM module provides up to 40 KB of general-purpose memory.

ECC handling is done on a 32-bit boundary and is completely software compatible with MPC55xx family devices with an

e200z6 core and 64-bit wide ECC.

The SRAM module provides the following features:

•

Supports read/write accesses mapped to the SRAM from any master

Up to 40 KB general purpose SRAM

Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory

Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait state for 8- and 16-bit writes if back to back

with a read to same memory block

1.5.6

Interrupt controller (INTC)

The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt requests, suitable for statically

scheduled hard real-time systems. The INTC handles 147 selectable-priority interrupt sources.

MPC5604P Microcontroller Data Sheet, Rev. 8

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9

For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor

is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt

request source for quick determination of which ISR has to be executed. It also provides a wide number of priorities so that

lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of

interrupt request, the priority of each interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority

ceiling protocol (PCP) for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so

that all tasks which share the same resource can not preempt each other.

The INTC provides the following features:

•

Unique 9-bit vector for each separate interrupt source

8 software triggerable interrupt sources

16 priority levels with fixed hardware arbitration within priority levels for each interrupt source

Ability to modify the ISR or task priority: modifying the priority can be used to implement the Priority Ceiling Protocol

for accessing shared resources.

•

2 external high priority interrupts directly accessing the main core and I/O processor (IOP) critical interrupt mechanism

1.5.7

System status and configuration module (SSCM)

The system status and configuration module (SSCM) provides central device functionality.

The SSCM includes these features:

•

System configuration and status

— Memory sizes/status

— Device mode and security status

— Determine boot vector

— Search code flash for bootable sector

— DMA status

•

Debug status port enable and selection

Bus and peripheral abort enable/disable

1.5.8

System clocks and clock generation

The following list summarizes the system clock and clock generation on the MPC5604P:

•

Lock detect circuitry continuously monitors lock status

Loss of clock (LOC) detection for PLL outputs

Programmable output clock divider (1, 2, 4, 8)

FlexPWM module and eTimer module can run on an independent clock source

On-chip oscillator with automatic level control

Internal 16 MHz RC oscillator for rapid start-up and safe mode: supports frequency trimming by user application

1.5.9

Frequency-modulated phase-locked loop (FMPLL)

The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input clock. Further, the FMPLL supports

programmable frequency modulation of the system clock. The PLL multiplication factor, output clock divider ratio are all

software configurable.

The PLL has the following major features:

•

Input clock frequency: 4–40 MHz

MPC5604P Microcontroller Data Sheet, Rev. 8

10

Freescale

•

Maximum output frequency: 64 MHz

Voltage controlled oscillator (VCO)—frequency 256–512 MHz

Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to relock

Frequency-modulated PLL

— Modulation enabled/disabled through software

— Triangle wave modulation

•

Programmable modulation depth (±0.25% to ±4% deviation from center frequency): programmable modulation

frequency dependent on reference frequency

Self-clocked mode (SCM) operation

1.5.10 Main oscillator

The main oscillator provides these features:

•

Input frequency range: 4–40 MHz

Crystal input mode or oscillator input mode

PLL reference

1.5.11 Internal RC oscillator

This device has an RC ladder phase-shift oscillator. The architecture uses constant current charging of a capacitor. The voltage

at the capacitor is compared by the stable bandgap reference voltage.

The RC oscillator provides these features:

•

Nominal frequency 16 MHz

±5% variation over voltage and temperature after process trim

Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock is detected by the

PLL

•

RC oscillator is used as the default system clock during startup

1.5.12 Periodic interrupt timer (PIT)

The PIT module implements these features:

•

4 general purpose interrupt timers

32-bit counter resolution

Clocked by system clock frequency

Each channel can be used as trigger for a DMA request

1.5.13 System timer module (STM)

The STM module implements these features:

•

One 32-bit up counter with 8-bit prescaler

Four 32-bit compare channels

Independent interrupt source for each channel

Counter can be stopped in debug mode

1.5.14 Software watchdog timer (SWT)

The SWT has the following features:

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

11

•

32-bit time-out register to set the time-out period

Programmable selection of system or oscillator clock for timer operation

Programmable selection of window mode or regular servicing

Programmable selection of reset or interrupt on an initial time-out

Master access protection

Hard and soft configuration lock bits

Reset configuration inputs allow timer to be enabled out of reset

1.5.15 Fault collection unit (FCU)

The FCU provides an independent fault reporting mechanism even if the CPU is malfunctioning.

The FCU module has the following features:

•

FCU status register reporting the device status

Continuous monitoring of critical fault signals

User selection of critical signals from different fault sources inside the device

Critical fault events trigger 2 external pins (user selected signal protocol) that can be used externally to reset the device

and/or other circuitry (for example, safety relay or FlexRay transceiver)

•

Faults are latched into a register

1.5.16 System integration unit – Lite (SIUL)

The MPC5604P SIUL controls MCU pad configuration, external interrupt, general purpose I/O (GPIO), and internal peripheral

multiplexing.

The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and

discrete input/output control of the I/O pins of the MCU.

The SIU provides the following features:

•

Centralized general purpose input output (GPIO) control of as many as 80 input/output pins and 26 analog input-only

pads (package dependent)

•

All GPIO pins can be independently configured to support pull-up, pull down, or no pull

Reading and writing to GPIO supported both as individual pins and 16-bit wide ports

All peripheral pins (except ADC channels) can be alternatively configured as both general purpose input or output pins

ADC channels support alternative configuration as general purpose inputs

Direct readback of the pin value is supported on all pins through the SIUL

Configurable digital input filter that can be applied to some general purpose input pins for noise elimination: as many

as 4 internal functions can be multiplexed onto 1 pin

1.5.17 Boot and censorship

Different booting modes are available in the MPC5604P: booting from internal flash memory and booting via a serial link.

The default booting scheme uses the internal flash memory (an internal pull-down is used to select this mode). Optionally, the

user can boot via FlexCAN or LINFlex (using the boot assist module software).

A censorship scheme is provided to protect the content of the flash memory and offer increased security for the entire device.

A password mechanism is designed to grant the legitimate user access to the non-volatile memory.

MPC5604P Microcontroller Data Sheet, Rev. 8

12

Freescale

1.5.17.1 Boot assist module (BAM)

The BAM is a block of read-only one-time programmed memory and is identical for all MPC560xP devices that are based on

the e200z0h core. The BAM program is executed every time the device is powered on if the alternate boot mode has been

selected by the user.

The BAM provides the following features:

•

Serial bootloading via FlexCAN or LINFlex

Ability to accept a password via the used serial communication channel to grant the legitimate user access to the

non-volatile memory

1.5.18 Error correction status module (ECSM)

The ECSM provides a myriad of miscellaneous control functions regarding program-visible information about the platform

configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes,

and information on platform memory errors reported by error-correcting codes and/or generic access error information for

certain processor cores.

The Error Correction Status Module supports a number of miscellaneous control functions for the platform. The ECSM includes

these features:

•

Registers for capturing information on platform memory errors if error-correcting codes (ECC) are implemented

For test purposes, optional registers to specify the generation of double-bit memory errors are enabled on the

MPC5604P.

The sources of the ECC errors are:

•

Flash memory

SRAM

1.5.19 Peripheral bridge (PBRIDGE)

The PBRIDGE implements the following features:

•

Duplicated periphery

Master access privilege level per peripheral (per master: read access enable; write access enable)

Write buffering for peripherals

Checker applied on PBRIDGE output toward periphery

Byte endianess swap capability

1.5.20 Controller area network (FlexCAN)

The MPC5604P MCU contains one controller area network (FlexCAN) module. This module is a communication controller

implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used

primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in

the EMI environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module contains 32 message

buffers.

The FlexCAN module provides the following features:

•

Full implementation of the CAN protocol specification, version 2.0B

— Standard data and remote frames

— Extended data and remote frames

— Up to 8-bytes data length

— Programmable bit rate up to 1 Mbit/s

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

13

•

32 message buffers of up to 8-bytes data length

Each message buffer configurable as Rx or Tx, all supporting standard and extended messages

Programmable loop-back mode supporting self-test operation

3 programmable mask registers

Programmable transmit-first scheme: lowest ID or lowest buffer number

Time stamp based on 16-bit free-running timer

Global network time, synchronized by a specific message

Maskable interrupts

Independent of the transmission medium (an external transceiver is assumed)

High immunity to EMI

Short latency time due to an arbitration scheme for high-priority messages

Transmit features

— Supports configuration of multiple mailboxes to form message queues of scalable depth

— Arbitration scheme according to message ID or message buffer number

— Internal arbitration to guarantee no inner or outer priority inversion

— Transmit abort procedure and notification

•

Receive features

— Individual programmable filters for each mailbox

— 8 mailboxes configurable as a six-entry receive FIFO

— 8 programmable acceptance filters for receive FIFO

Programmable clock source

— System clock

— Direct oscillator clock to avoid PLL jitter

1.5.21 Safety port (FlexCAN)

The MPC5604P MCU has a second CAN controller synthesized to run at high bit rates to be used as a safety port. The CAN

module of the safety port provides the following features:

•

Identical to the FlexCAN module

Bit rate as fast as 7.5 Mbit/s at 60 MHz CPU clock using direct connection between CAN modules (no physical

transceiver required)

•

32 message buffers of up to 8 bytes data length

Can be used as a second independent CAN module

1.5.22 FlexRay

The FlexRay module provides the following features:

•

Full implementation of FlexRay Protocol Specification 2.1

32 configurable message buffers can be handled

Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate

Message buffers configurable as Tx, Rx or RxFIFO

Message buffer size configurable

Message filtering for all message buffers based on FrameID, cycle count and message ID

Programmable acceptance filters for RxFIFO message buffers

MPC5604P Microcontroller Data Sheet, Rev. 8

14

Freescale

1.5.23 Serial communication interface module (LINFlex)

The LINFlex (local interconnect network flexible) on the MPC5604P features the following:

•

Supports LIN Master mode, LIN Slave mode and UART mode

LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications

Handles LIN frame transmission and reception without CPU intervention

LIN features

— Autonomous LIN frame handling

— Message buffer to store Identifier and as much as 8 data bytes

— Supports message length as long as 64 bytes

— Detection and flagging of LIN errors (sync field, delimiter, ID parity, bit framing, checksum, and time-out)

— Classic or extended checksum calculation

— Configurable Break duration as long as 36-bit times

— Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)

— Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection

— Interrupt-driven operation with 16 interrupt sources

LIN slave mode features

•

— Autonomous LIN header handling

— Autonomous LIN response handling

UART mode

— Full-duplex operation

— Standard non return-to-zero (NRZ) mark/space format

— Data buffers with 4-byte receive, 4-byte transmit

— Configurable word length (8-bit or 9-bit words)

— Error detection and flagging

— Parity, Noise and Framing errors

— Interrupt-driven operation with four interrupt sources

— Separate transmitter and receiver CPU interrupt sources

— 16-bit programmable baud-rate modulus counter and 16-bit fractional

— 2 receiver wake-up methods

1.5.24 Deserial serial peripheral interface (DSPI)

The deserial serial peripheral interface (DSPI) module provides a synchronous serial interface for communication between the

MPC5604P MCU and external devices.

The DSPI modules provide these features:

•

Full duplex, synchronous transfers

Master or slave operation

Programmable master bit rates

Programmable clock polarity and phase

End-of-transmission interrupt flag

Programmable transfer baud rate

Programmable data frames from 4 to 16 bits

Up to 20 chip select lines available

— 8 on DSPI_0

— 4 each on DSPI_1, DSPI_2 and DSPI_3

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

15

•

8 clock and transfer attributes registers

Chip select strobe available as alternate function on one of the chip select pins for deglitching

FIFOs for buffering as many as 5 transfers on the transmit and receive side

Queueing operation possible through use of the eDMA

General purpose I/O functionality on pins when not used for SPI

1.5.25 Pulse width modulator (FlexPWM)

The pulse width modulator module (PWM) contains four PWM submodules, each capable of controlling a single half-bridge

power stage. There are also four fault channels.

This PWM is capable of controlling most motor types: AC induction motors (ACIM), permanent magnet AC motors (PMAC),

both brushless (BLDC) and brush DC motors (BDC), switched (SRM) and variable reluctance motors (VRM), and stepper

motors.

The FlexPWM block implements the following features:

•

16-bit resolution for center, edge-aligned, and asymmetrical PWMs

Maximum operating clock frequency of 120 MHz

PWM outputs can operate as complementary pairs or independent channels

Can accept signed numbers for PWM generation

Independent control of both edges of each PWM output

Synchronization to external hardware or other PWM supported

Double buffered PWM registers

— Integral reload rates from 1 to 16

— Half cycle reload capability

•

Multiple ADC trigger events can be generated per PWM cycle via hardware

Write protection for critical registers

Fault inputs can be assigned to control multiple PWM outputs

Programmable filters for fault inputs

Independently programmable PWM output polarity

Independent top and bottom deadtime insertion

Each complementary pair can operate with its own PWM frequency and deadtime values

Individual software-control for each PWM output

All outputs can be programmed to change simultaneously via a “Force Out” event

PWMX pin can optionally output a third PWM signal from each submodule

Channels not used for PWM generation can be used for buffered output compare functions

Channels not used for PWM generation can be used for input capture functions

Enhanced dual-edge capture functionality

eDMA support with automatic reload

2 fault inputs

Capture capability for PWMA, PWMB, and PWMX channels not supported

1.5.26 eTimer

The MPC5604P includes two eTimer modules. Each module provides six 16-bit general purpose up/down timer/counter units

with the following features:

•

Maximum operating clock frequency of 120 MHz

Individual channel capability

MPC5604P Microcontroller Data Sheet, Rev. 8

16

Freescale

— Input capture trigger

— Output compare

— Double buffer (to capture rising edge and falling edge)

— Separate prescaler for each counter

— Selectable clock source

— 0–100% pulse measurement

— Rotation direction flag (Quad decoder mode)

Maximum count rate

•

— External event counting: max. count rate = peripheral clock/2

— Internal clock counting: max. count rate = peripheral clock

Counters are:

— Cascadable

— Preloadable

•

Programmable count modulo

Quadrature decode capabilities

Counters can share available input pins

Count once or repeatedly

Pins available as GPIO when timer functionality not in use

1.5.27 Analog-to-digital converter (ADC) module

The ADC module provides the following features:

Analog part:

•

2 on-chip AD converters

— 10-bit AD resolution

— 1 sample and hold unit per ADC

— Conversion time, including sampling time, less than 1 µs (at full precision)

— Typical sampling time is 150 ns min. (at full precision)

— Differential non-linearity error (DNL) ±1 LSB

— Integral non-linearity error (INL) ±1.5 LSB

— TUE <3 LSB

— Single-ended input signal up to 5.0 V

— The ADC and its reference can be supplied with a voltage independent from V

DDIO

— The ADC supply can be equal or higher than V

DDIO

— The ADC supply and the ADC reference are not independent from each other (they are internally bonded to the

same pad)

— Sample times of 2 (default), 8, 64, or 128 ADC clock cycles

Digital part:

•

2 × 13 input channels including 4 channels shared between the 2 converters

4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in

the appropriate ADC result location,

•

2 modes of operation: Normal mode or CTU control mode

Normal mode features

— Register-based interface with the CPU: control register, status register, 1 result register per channel

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

17

— ADC state machine managing 3 request flows: regular command, hardware injected command, software injected

command

— Selectable priority between software and hardware injected commands

— 4 analog watchdogs comparing ADC results against predefined levels (low, high, range)

— DMA compatible interface

•

CTU control mode features

— Triggered mode only

— 4 independent result queues (2 × 16 entries, 2 × 4 entries)

— Result alignment circuitry (left justified; right justified)

— 32-bit read mode allows to have channel ID on one of the 16-bit part

— DMA compatible interfaces

1.5.28 Cross triggering unit (CTU)

The cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without CPU

load during the PWM period and with minimized CPU load for dynamic configuration.

It implements the following features:

•

Double buffered trigger generation unit with as many as eight independent triggers generated from external triggers

Trigger generation unit configurable in sequential mode or in triggered mode

Each Trigger can be appropriately delayed to compensate the delay of external low pass filter

Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation

Double buffered ADC command list pointers to minimize ADC-trigger unit update

Double buffered ADC conversion command list with as many as 24 ADC commands

Each trigger has the capability to generate consecutive commands

ADC conversion command allows to control ADC channel from each ADC, single or synchronous sampling,

independent result queue selection

1.5.29 Nexus development interface (NDI)

The NDI (Nexus Development Interface) block provides real-time development support capabilities for the MPC5604P Power

Architecture based MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for

MCUs without requiring external address and data pins for internal visibility. The NDI block is an integration of several

individual Nexus blocks that are selected to provide the development support interface for this device. The NDI block interfaces

to the host processor and internal busses to provide development support as per the IEEE-ISTO 5001-2003 Class 2+ standard.

The development support provided includes access to the MCU’s internal memory map and access to the processor’s internal

registers during run time.

The Nexus Interface provides the following features:

•

Configured via the IEEE 1149.1

All Nexus port pins operate at V

Nexus 2+ features supported

— Static debug

(no dedicated power supply)

DDIO

— Watchpoint messaging

— Ownership trace messaging

— Program trace messaging

— Real time read/write of any internally memory mapped resources through JTAG pins

— Overrun control, which selects whether to stall before Nexus overruns or keep executing and allow overwrite of

information

MPC5604P Microcontroller Data Sheet, Rev. 8

18

Freescale

— Watchpoint triggering, watchpoint triggers program tracing

Auxiliary Output Port

•

— 4 MDO (Message Data Out) pins

— MCKO (Message Clock Out) pin

— 2 MSEO (Message Start/End Out) pins

— EVTO (Event Out) pin

Auxiliary Input Port

— EVTI (Event In) pin

1.5.30 Cyclic redundancy check (CRC)

The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The CRC module features:

•

Support for CRC-16-CCITT (x25 protocol):

16

12

5

— x + x + x + 1

Support for CRC-32 (Ethernet protocol):

32

26

23

22

16

12

11

10

8

7

5

4

2

— x + x + x + x + x + x + x + x + x + x + x + x + x + x + 1

Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the maximum frequency

1.5.31 IEEE 1149.1 JTAG controller

The JTAG controller (JTAGC) block provides the means to test chip functionality and connectivity while remaining transparent

to system logic when not in test mode. All data input to and output from the JTAGC block is communicated in serial format.

The JTAGC block is compliant with the IEEE standard.

The JTAG controller provides the following features:

•

IEEE Test Access Port (TAP) interface with 4 pins (TDI, TMS, TCK, TDO)

Selectable modes of operation include JTAGC/debug or normal system operation.

A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

— BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD

•

A 5-bit instruction register that supports the additional following public instructions:

— ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_ONCE

•

3 test data registers: a bypass register, a boundary scan register, and a device identification register.

A TAP controller state machine that controls the operation of the data registers, instruction register and associated

circuitry.

1.5.32 On-chip voltage regulator (VREG)

The on-chip voltage regulator module provides the following features:

•

Uses external NPN (negative-positive-negative) transistor

Regulates external 3.3 V /5.0 V down to 1.2 V for the core logic

Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

19

2

Package pinouts and signal descriptions

2.1

Package pinouts

The LQFP pinouts are shown in the following figures.

1

2

3

4

5

6

7

8

108

107

106

105

104

103

102

101

100

A[4]

VPP_TEST

F[12]

D[14]

G[3]

C[14]

G[2]

C[13]

G[4]

NMI

A[6]

D[1]

F[4]

F[5]

VDD_HV_IO0

VSS_HV_IO0

F[6]

9

MDO[0]

A[7]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

99

D[12]

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

G[6]

C[4]

A[8]

C[5]

A[5]

C[7]

C[3]

VDD_HV_FL

VSS_HV_FL

D[13]

VSS_LV_COR1

VDD_LV_COR1

A[3]

VDD_HV_IO2

VSS_HV_IO2

TDO

TCK

TMS

TDI

G[5]

A[2]

G[7]

C[12]

G[8]

C[11]

G[9]

D[11]

G[10]

VSS_LV_COR0

VDD_LV_COR0

F[7]

144 LQFP

F[8]

VDD_HV_IO1

VSS_HV_IO1

F[9]

F[10]

F[11]

D[9]

VDD_HV_OSC

VSS_HV_OSC

XTAL

EXTAL

RESET

D[8]

D[5]

D[6]

D[10]

G[11]

A[1]

A[0]

VSS_LV_COR3

VDD_LV_COR3

Note: Availability of port pin alternate functions depends on product selection.

Figure 2. 144-pin LQFP pinout (top view)

MPC5604P Microcontroller Data Sheet, Rev. 8

20

Freescale

75

74

73

72

71

70

69

68

67

66

A[4]

NMI

A[6]

D[1]

A[7]

C[4]

A[8]

C[5]

A[5]

C[7]

1

2

3

4

5

6

7

8

9

VPP_TEST

D[14]

C[14]

C[13]

D[12]

VDD_HV_FL

VSS_HV_FL

D[13]

VSS_LV_COR1

C[3] 10

VSS_LV_COR0 11

VDD_LV_COR0 12

VDD_HV_IO1 13

VSS_HV_IO1 14

D[9] 15

65 VDD_LV_COR1

64 A[3]

63 VDD_HV_IO2

62 VSS_HV_IO2

61 TDO

100 LQFP

60 TCK

VDD_HV_OSC 16

VSS_HV_OSC 17

XTAL 18

TMS

TDI

A[2]

59

58

57

56

55

54

53

52

51

EXTAL 19

C[12]

C[11]

D[11]

D[10]

A[1]

RESET 20

D[8] 21

D[5] 22

D[6] 23

VSS_LV_COR3 24

VDD_LV_COR3 25

A[0]

Note: Availability of port pin alternate functions depends on product selection.

Figure 3. 100-pin LQFP pinout (top view)

2.2

Pin description

The following sections provide signal descriptions and related information about the functionality and configuration of the

MPC5604P devices.

2.2.1

Power supply and reference voltage pins

Table 3 lists the power supply and reference voltage for the MPC5604P devices.

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

21

Table 3. Supply pins

Description

Supply

Symbol

100-pin

144-pin

VREG control and power supply pins. Pins available on 100-pin and 144-pin package.

BCTRL

Voltage regulator external NPN ballast base control pin

47

50

69

72

V_{DD_HV_REG}(3.3 V Voltage regulator supply voltage

or 5.0 V)

V_{DD_LV_REGCOR}

1.2 V decoupling pins for core logic and regulator feedback.

Decoupling capacitor must be connected between this pins

and V_{SS_LV_REGCOR}

48

49

70

71

.

V_{SS_LV_REGCOR}

1.2 V decoupling pins for core logic and regulator feedback.

Decoupling capacitor must be connected between this pins

and V_{DD_LV_REGCOR}

.

ADC_0/ADC_1 reference and supply voltage. Pins available on 100-pin and 144-pin package.

1

V_{DD_HV_ADC0}

V_{SS_HV_ADC0}

V_{DD_HV_ADC1}

V_{SS_HV_ADC1}

ADC_0 supply and high reference voltage

ADC_0 ground and low reference voltage

ADC_1 supply and high reference voltage

ADC_1 ground and low reference voltage

33

34

39

40

50

51

56

57

Power supply pins (3.3 V or 5.0 V). All pins available on 144-pin package.

Five pairs (V_DD; V_SS) available on 100-pin package.

2

V_{DD_HV_IO0}

Input/Output supply voltage

Input/Output ground

—

13

14

63

62

87

88

69

68

16

17

6

7

2

V_{SS_HV_IO0}

V_{DD_HV_IO1}

V_{SS_HV_IO1}

V_{DD_HV_IO2}

V_{SS_HV_IO2}

V_{DD_HV_IO3}

V_{SS_HV_IO3}

V_{DD_HV_FL}

V_{SS_HV_FL}

V_{DD_HV_OSC}

V_{SS_HV_OSC}

Input/Output supply voltage

Input/Output ground

21

22

91

90

126

127

97

96

27

28

Input/Output supply voltage

Input/Output ground

Input/Output supply voltage

Input/Output ground

Code and data flash supply voltage

Code and data flash supply ground

Crystal oscillator amplifier supply voltage

Crystal oscillator amplifier ground

Power supply pins (1.2 V). All pins available on 100-pin and 144-pin package.

V_{DD_LV_COR0}

1.2 V Decoupling pins for core logic. Decoupling capacitor

must be connected between these pins and the nearest

V_{SS_LV_COR}pin.

12

18

MPC5604P Microcontroller Data Sheet, Rev. 8

22

Freescale

Table 3. Supply pins (continued)

Supply

Symbol

Description

100-pin

144-pin

V_{SS_LV_COR0}

1.2 V Decoupling pins for core logic. Decoupling capacitor

must be connected between these pins and the nearest

V_{DD_LV_COR}pin.

11

17

V_{DD_LV_COR1}

V_{SS_LV_COR1}

V_{DD_LV_COR2}

V_{SS_LV_COR2}

V_{DD_LV_COR3}

V_{SS_LV_COR3}

1.2 V Decoupling pins for core logic. Decoupling capacitor

must be connected between these pins and the nearest

V_{SS_LV_COR}pin.

65

66

92

93

25

24

93

94

1.2 V Decoupling pins for core logic. Decoupling capacitor

must be connected between these pins and the nearest

V_{DD_LV_COR}pin.

1.2 V Decoupling pins for core logic. Decoupling capacitor

must be connected between these pins and the nearest

V_{SS_LV_COR}pin.

131

132

36

1.2 V Decoupling pins for core logic. Decoupling capacitor

must be connected between these pins and the nearest

V_{DD_LV_COR}pin.

1.2 V Decoupling pins for on-chip PLL modules. Decoupling

capacitor must be connected between this pin and

V_{SS_LV_COR3}

.

1.2 V Decoupling pins for on-chip PLL modules. Decoupling

capacitor must be connected between this pin and

35

V_{DD_LV_COR3}

.

1

2

Analog supply/ground and high/low reference lines are internally physically separate, but are shorted via a

double-bonding connection on V_{DD_HV_ADCx}/V_{SS_HV_ADCx}pins.

Not available on 100-pin package.

2.2.2

System pins

Table 3 and Table 4 contain information on pin functions for the MPC5604P devices. The pins listed in Table 4 are

single-function pins. The pins shown in Table 5 are multi-function pins, programmable via their respective Pad Configuration

Register (PCR) values.

Table 4. System pins

Pad speed¹

SRC = 0 SRC = 1 100-pin 144-pin

Dedicated pins. Available on 100-pin and 144-pin package.

Symbol

Description

Direction

MDO[0]

NMI

Nexus Message Data Output—line 0

Non-Maskable Interrupt

Output only

Input only

—

Fast

—

1

9

1

Slow

—

XTAL

Analog output of the oscillator amplifier

circuit; needs to be grounded if oscillator

is used in bypass mode

18

29

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

23

Table 4. System pins (continued)

Pad speed¹

Symbol

Description

Direction

SRC = 0 SRC = 1 100-pin 144-pin

EXTAL

• Analog input of oscillator amplifier

circuit, when oscillator not in bypass

mode

—

19

30

• Analog input for clock generator when

oscillator in bypass mode

TMS

TCK

TDI

JTAG state machine control

JTAG clock

Bidirectional

Input only

Slow

Fast

—

59

60

58

61

87

88

86

89

Test Data In

Input only

Medium

Fast

TDO

Test Data Out

Output only

Reset pin, available on 100-pin and 144-pin package.

RESET

Bidirectional reset with Schmitt trigger

characteristics and noise filter

Bidirectional

Medium

—

20

31

Test pin, available on 100-pin and 144-pin package.

VPP_TEST Pin for testing purpose only. To be tied to

ground in normal operating mode.

—

74

107

1

SCR values refer to the value assigned to the Slew Rate Control bits of the pad configuration register.

2.2.3

Pin muxing

Table 5 defines the pin list and muxing for the MPC5604P devices.

Each row of Table 5 shows all the possible ways of configuring each pin, via alternate functions. The default function assigned

to each pin after reset is the ALT0 function.

MPC5604P devices provide four main I/O pad types, depending on the associated functions:

•

Slow pads are the most common, providing a compromise between transition time and low electromagnetic emission.

Medium pads provide fast enough transition for serial communication channels with controlled current to reduce

electromagnetic emission.

•

Fast pads provide maximum speed. They are used for improved NEXUS debugging capability.

Symmetric pads are designed to meet FlexRay requirements.

Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.

For more information, see the data sheet’s “Pad AC Specifications” section.

MPC5604P Microcontroller Data Sheet, Rev. 8

24

Freescale

Table 5. Pin muxing

Pad speed⁵

Pin No.

Pad

configuration

register (PCR)

Port

Alternate

I/O

Functions

Peripheral³

function^1,2

direction⁴

SRC = 0

SRC = 1

Port A (16-bit)

A[0]

A[1]

PCR[0]

PCR[1]

PCR[2]

ALT0

ALT1

ALT2

ALT3

—

GPIO[0]

ETC[0]

SCK

F[0]

EIRQ[0]

SIUL

eTimer_0

DSPI_2

FCU_0

SIUL

I/O

O

I

Slow

Medium

51 73

52 74

57 84

ALT0

ALT1

ALT2

ALT3

—

GPIO[1]

ETC[1]

SOUT

F[1]

SIUL

eTimer_0

DSPI_2

FCU_0

SIUL

I/O

O

I

Medium

EIRQ[1]

A[2]⁶

ALT0

ALT1

ALT2

ALT3

—

GPIO[2]

ETC[2]

—

A[3]

SIN

SIUL

eTimer_0

—

FlexPWM_0

DSPI_2

MC_RGM

SIUL

I/O

—

O

I

—

ABS[0]

EIRQ[2]

I

A[3]⁶

PCR[3]

PCR[4]

ALT0

ALT1

ALT2

ALT3

—

GPIO[3]

ETC[3]

CS0

B[3]

ABS[2]

EIRQ[3]

SIUL

eTimer_0

DSPI_2

FlexPWM_0

MC_RGM

SIUL

I/O

O

I

Slow

Medium

64 92

—

A[4]⁶

ALT0

ALT1

ALT2

ALT3

—

GPIO[4]

ETC[0]

CS1

ETC[4]

FAB

SIUL

eTimer_1

DSPI_2

eTimer_0

MC_RGM

SIUL

I/O

O

I/O

I

75 108

—

EIRQ[4]

I

A[5]

A[6]

A[7]

PCR[5]

PCR[6]

PCR[7]

ALT0

ALT1

ALT2

ALT3

—

GPIO[5]

CS0

ETC[5]

CS7

SIUL

DSPI_1

eTimer_1

DSPI_0

SIUL

I/O

O

Slow

Medium

8

2

4

14

2

EIRQ[5]

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[6]

SCK

—

EIRQ[6]

SIUL

DSPI_1

—

SIUL

I/O

—

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[7]

SOUT

—

EIRQ[7]

SIUL

DSPI_1

—

SIUL

I/O

O

—

I

10

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

25

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Pin No.

Pad

configuration

register (PCR)

Port

Alternate

Functions

Peripheral³

function^1,2

direction⁴

SRC = 0

SRC = 1

A[8]

PCR[8]

ALT0

ALT1

ALT2

ALT3

—

GPIO[8]

—

SIN

EIRQ[8]

SIUL

—

DSPI_1

SIUL

I/O

—

I

Slow

Medium

6

12

—

I

A[9]

PCR[9]

PCR[10]

PCR[11]

PCR[12]

PCR[13]

ALT0

ALT1

ALT2

ALT3

—

GPIO[9]

CS1

—

B[3]

SIUL

DSPI_2

I/O

O

—

O

I

Slow

Medium

94 134

81 118

82 120

83 122

95 136

—

FlexPWM_0

FAULT[0]

A[10]

A[11]

A[12]

A[13]

ALT0

ALT1

ALT2

ALT3

—

GPIO[10]

CS0

B[0]

X[2]

EIRQ[9]

SIUL

DSPI_2

FlexPWM_0

SIUL

I/O

O

I/O

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[11]

SCK

A[0]

A[2]

EIRQ[10]

SIUL

DSPI_2

FlexPWM_0

SIUL

I/O

O

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[12]

SOUT

A[2]

B[2]

EIRQ[11]

SIUL

DSPI_2

FlexPWM_0

SIUL

I/O

O

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[13]

—

SIUL

—

FlexPWM_0

—

DSPI_2

FlexPWM_0

SIUL

I/O

—

O

—

I

B[2]

—

SIN

—

FAULT[0]

EIRQ[12]

I

A[14]

A[15]

PCR[14]

PCR[15]

ALT0

ALT1

ALT2

ALT3

—

GPIO[14]

TXD

ETC[4]

—

SIUL

Safety Port_0

eTimer_1

—

I/O

O

I/O

—

I

Slow

Medium

99 143

EIRQ[13]

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[15]

—

ETC[5]

—

RXD

EIRQ[14]

SIUL

—

eTimer_1

—

Safety Port_0

SIUL

I/O

—

I/O

—

I

Medium 100 144

—

I

MPC5604P Microcontroller Data Sheet, Rev. 8

26

Freescale

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Pin No.

Pad

configuration

register (PCR)

Port

Alternate

Functions

Peripheral³

function^1,2

direction⁴

SRC = 0

SRC = 1

Port B (16-bit)

B[0]

B[1]

PCR[16]

PCR[17]

ALT0

ALT1

ALT2

ALT3

—

GPIO[16]

TXD

ETC[2]

DEBUG[0]

EIRQ[15]

SIUL

FlexCAN_0

eTimer_1

SSCM

I/O

O

I/O

—

I

Slow

Medium

76 109

77 110

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[17]

—

ETC[3]

DEBUG[1]

RXD

SIUL

—

eTimer_1

SSCM

FlexCAN_0

SIUL

I/O

—

I/O

—

I

Medium

—

EIRQ[16]

I

B[2]

B[3]

B[6]

B[7]

PCR[18]

PCR[19]

PCR[22]

PCR[23]

ALT0

ALT1

ALT2

ALT3

—

GPIO[18]

TXD

SIUL

LIN_0

—

SSCM

SIUL

I/O

O

—

I

Slow

—

Medium

—

79 114

80 116

96 138

29 43

—

DEBUG[2]

EIRQ[17]

ALT0

ALT1

ALT2

ALT3

—

GPIO[19]

—

SIUL

—

SSCM

LIN_0

I/O

—

I

—

DEBUG[3]

RXD

ALT0

ALT1

ALT2

ALT3

—

GPIO[22]

CLKOUT

CS2

SIUL

MC_CGL

DSPI_2

—

I/O

O

—

I

—

EIRQ[18]

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[23]

—

AN[0]

RXD

SIUL

—

ADC_0

LIN_0

Input only

—

B[8]

B[9]

PCR[24]

PCR[25]

ALT0

ALT1

ALT2

ALT3

—

GPIO[24]

—

AN[1]

ETC[5]

SIUL

—

31 47

—

ADC_0

eTimer_0

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[25]

—

AN[11]

SIUL

—

35 52

ADC_0 / ADC_1

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

27

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Pin No.

Pad

configuration

register (PCR)

Port

Alternate

Functions

Peripheral³

function^1,2

direction⁴

SRC = 0

SRC = 1

B[10]

B[11]

B[12]

B[13]

PCR[26]

PCR[27]

PCR[28]

PCR[29]

ALT0

ALT1

ALT2

ALT3

—

GPIO[26]

—

AN[12]

SIUL

—

Input only

—

36 53

ADC_0 / ADC_1

ALT0

ALT1

ALT2

ALT3

—

GPIO[27]

—

AN[13]

SIUL

—

Input only

—

37 54

38 55

42 60

ADC_0 / ADC_1

ALT0

ALT1

ALT2

ALT3

—

GPIO[28]

—

AN[14]

SIUL

—

ADC_0 / ADC_1

ALT0

ALT1

ALT2

ALT3

—

GPIO[29]

—

AN[0]

RXD

SIUL

—

ADC_1

LIN_1

—

B[14]

B[15]

PCR[30]

PCR[31]

ALT0

ALT1

ALT2

ALT3

—

GPIO[30]

—

SIUL

—

Input only

—

44 64

—

AN[1]

ETC[4]

EIRQ[19]

ADC_1

eTimer_0

SIUL

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[31]

—

SIUL

—

ADC_1

SIUL

43 62

—

AN[2]

EIRQ[20]

—

Port C (16-bit)

C[0]

C[1]

PCR[32]

PCR[33]

ALT0

ALT1

ALT2

ALT3

—

GPIO[32]

SIUL

—

ADC_1

Input only

—

45 66

—

AN[3]

ALT0

ALT1

ALT2

ALT3

—

GPIO[33]

SIUL

—

ADC_0

28 41

—

AN[2]

MPC5604P Microcontroller Data Sheet, Rev. 8

28

Freescale

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Pin No.

Pad

configuration

register (PCR)

Port

Alternate

Functions

Peripheral³

function^1,2

direction⁴

SRC = 0

SRC = 1

C[2]

C[3]

C[4]

C[5]

PCR[34]

PCR[35]

PCR[36]

PCR[37]

ALT0

ALT1

ALT2

ALT3

—

GPIO[34]

SIUL

—

ADC_0

Input only

—

30 45

—

AN[3]

ALT0

ALT1

ALT2

ALT3

—

GPIO[35]

CS1

ETC[4]

TXD

SIUL

DSPI_0

eTimer_1

LIN_1

I/O

O

I/O

O

Slow

Medium

10 16

EIRQ[21]

SIUL

I

ALT0

ALT1

ALT2

ALT3

—

GPIO[36]

CS0

X[1]

DEBUG[4]

EIRQ[22]

SIUL

DSPI_0

FlexPWM_0

SSCM

I/O

—

I

5

7

11

13

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[37]

SCK

SIUL

DSPI_0

—

SSCM

FlexPWM_0

SIUL

I/O

—

I

—

DEBUG[5]

FAULT[3]

EIRQ[23]

—

I

C[6]

C[7]

C[8]

C[9]

C[10]

PCR[38]

PCR[39]

PCR[40]

PCR[41]

PCR[42]

ALT0

ALT1

ALT2

ALT3

—

GPIO[38]

SOUT

B[1]

DEBUG[6]

EIRQ[24]

SIUL

DSPI_0

FlexPWM_0

SSCM

I/O

O

—

I

Slow

Medium

98 142

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[39]

—

A[1]

DEBUG[7]

SIN

SIUL

—

FlexPWM_0

SSCM

I/O

—

O

—

I

9

15

DSPI_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[40]

CS1

—

CS6

FAULT[2]

SIUL

DSPI_1

—

DSPI_0

FlexPWM_0

I/O

O

—

O

I

91 130

84 123

78 111

ALT0

ALT1

ALT2

ALT3

—

GPIO[41]

CS3

—

X[3]

FAULT[2]

SIUL

DSPI_2

I/O

O

—

I/O

I

—

FlexPWM_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[42]

CS2

—

A[3]

FAULT[1]

SIUL

DSPI_2

I/O

O

—

O

I

—

FlexPWM_0

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

29

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Pin No.

Pad

configuration

register (PCR)

Port

Alternate

Functions

Peripheral³

function^1,2

direction⁴

SRC = 0

SRC = 1

C[11]

C[12]

C[13]

PCR[43]

PCR[44]

PCR[45]

ALT0

ALT1

ALT2

ALT3

GPIO[43]

ETC[4]

CS2

SIUL

I/O

O

Slow

Medium

55 80

56 82

71 101

eTimer_0

DSPI_2

DSPI_3

CS0

I/O

ALT0

ALT1

ALT2

ALT3

GPIO[44]

ETC[5]

CS3

SIUL

I/O

O

Medium

eTimer_0

DSPI_2

DSPI_3

CS1

O

ALT0

ALT1

ALT2

ALT3

—

GPIO[45]

ETC[1]

—

SIUL

eTimer_1

—

I/O

—

I

—

EXT_IN

EXT_SYNC

CTU_0

FlexPWM_0

—

I

C[14]

C[15]

PCR[46]

PCR[47]

ALT0

ALT1

ALT2

ALT3

GPIO[46]

ETC[2]

EXT_TGR

—

SIUL

eTimer_1

CTU_0

—

I/O

O

Slow

Medium

72 103

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[47]

CA_TR_EN

ETC[0]

A[1]

EXT_IN

SIUL

I/O

O

I/O

O

I

Symmetric 85 124

FlexRay_0

eTimer_1

FlexPWM_0

CTU_0

—

EXT_SYNC

FlexPWM_0

I

Port D (16-bit)

D[0]

D[1]

PCR[48]

PCR[49]

ALT0

ALT1

ALT2

ALT3

GPIO[48]

CA_TX

ETC[1]

B[1]

SIUL

I/O

O

I/O

O

Slow

Symmetric 86 125

FlexRay_0

eTimer_1

FlexPWM_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[49]

—

ETC[2]

EXT_TRG

CA_RX

SIUL

—

eTimer_1

CTU_0

FlexRay_0

I/O

—

I/O

O

Medium

3

I

D[2]

D[3]

PCR[50]

PCR[51]

ALT0

ALT1

ALT2

ALT3

—

GPIO[50]

—

ETC[3]

X[3]

SIUL

—

eTimer_1

FlexPWM_0

FlexRay_0

I/O

—

I/O

I

Slow

97 140

CB_RX

ALT0

ALT1

ALT2

ALT3

GPIO[51]

CB_TX

ETC[4]

A[3]

SIUL

I/O

O

I/O

O

Symmetric 89 128

FlexRay_0

eTimer_1

FlexPWM_0

MPC5604P Microcontroller Data Sheet, Rev. 8

30

Freescale

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Pin No.

Pad

configuration

register (PCR)

Port

Alternate

Functions

Peripheral³

function^1,2

direction⁴

SRC = 0

SRC = 1

Symmetric 90 129

D[4]

D[5]

D[6]

PCR[52]

PCR[53]

PCR[54]

ALT0

ALT1

ALT2

ALT3

GPIO[52]

CB_TR_EN

ETC[5]

SIUL

I/O

O

I/O

O

Slow

FlexRay_0

eTimer_1

FlexPWM_0

B[3]

ALT0

ALT1

ALT2

ALT3

GPIO[53]

CS3

F[0]

SOUT

SIUL

I/O

O

Slow

Medium

22 33

23 34

DSPI_0

FCU_0

DSPI_3

O

ALT0

ALT1

ALT2

ALT3

—

GPIO[54]

CS2

SCK

SIUL

DSPI_0

DSPI_3

—

I/O

O

I/O

—

I

—

FAULT[1]

FlexPWM_0

D[7]

D[8]

PCR[55]

PCR[56]

ALT0

ALT1

ALT2

ALT3

—

GPIO[55]

CS3

SIUL

I/O

O

I

Slow

Medium

26 37

DSPI_1

FCU_0

DSPI_0

DSPI_3

F[1]

CS4

SIN

ALT0

ALT1

ALT2

ALT3

—

GPIO[56]

CS2

—

CS5

FAULT[3]

SIUL

DSPI_1

—

DSPI_0

FlexPWM_0

I/O

O

—

O

I

21 32

D[9]

D[10]

D[11]

D[12]

PCR[57]

PCR[58]

PCR[59]

PCR[60]

ALT0

ALT1

ALT2

ALT3

GPIO[57]

X[0]

TXD

SIUL

FlexPWM_0

LIN_1

I/O

O

Slow

Medium

15 26

53 76

54 78

70 99

—

ALT0

ALT1

ALT2

ALT3

GPIO[58]

A[0]

SIUL

FlexPWM_0

DSPI_3

—

I/O

O

I/O

—

CS0

—

ALT0

ALT1

ALT2

ALT3

GPIO[59]

B[0]

CS1

SCK

SIUL

FlexPWM_0

DSPI_3

I/O

O

DSPI_3

I/O

ALT0

ALT1

ALT2

ALT3

—

GPIO[60]

X[1]

—

RXD

SIUL

FlexPWM_0

—

I/O

—

I

—

LIN_1

D[13]

PCR[61]

ALT0

ALT1

ALT2

ALT3

GPIO[61]

A[1]

CS2

SOUT

SIUL

FlexPWM_0

DSPI_3

I/O

O

Slow

Medium

67 95

DSPI_3

O

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

31

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Pin No.

Pad

configuration

register (PCR)

Port

Alternate

Functions

Peripheral³

function^1,2

direction⁴

SRC = 0

SRC = 1

D[14]

PCR[62]

PCR[63]

ALT0

ALT1

ALT2

ALT3

—

GPIO[62]

B[1]

SIUL

FlexPWM_0

DSPI_3

—

I/O

O

—

I

Slow

—

Medium

73 105

CS3

—

SIN

DSPI_3

D[15]

ALT0

ALT1

ALT2

ALT3

—

GPIO[63]

SIUL

—

ADC_1

Input only

—

41 58

—

AN[4]

Port E(16-bit)

E[0]

E[1]

E[2]

E[3]

E[4]

E[5]

PCR[64]

PCR[65]

PCR[66]

PCR[67]

PCR[68]

PCR[69]

ALT0

ALT1

ALT2

ALT3

—

GPIO[64]

SIUL

—

ADC_1

Input only

—

46 68

27 39

32 49

—

AN[5]

ALT0

ALT1

ALT2

ALT3

—

GPIO[65]

SIUL

—

ADC_0

—

AN[4]

ALT0

ALT1

ALT2

ALT3

—

GPIO[66]

SIUL

—

ADC_0

—

AN[5]

ALT0

ALT1

ALT2

ALT3

—

GPIO[67]

SIUL

—

ADC_0

—

40

42

44

—

AN[6]

ALT0

ALT1

ALT2

ALT3

—

GPIO[68]

SIUL

—

ADC_0

—

AN[7]

ALT0

ALT1

ALT2

ALT3

—

GPIO[69]

SIUL

—

ADC_0

—

AN[8]

MPC5604P Microcontroller Data Sheet, Rev. 8

32

Freescale

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Pin No.

Pad

configuration

register (PCR)

Port

Alternate

Functions

Peripheral³

function^1,2

direction⁴

SRC = 0

SRC = 1

E[6]

PCR[70]

PCR[71]

PCR[72]

PCR[73]

PCR[74]

PCR[75]

PCR[76]

PCR[77]

PCR[78]

ALT0

ALT1

ALT2

ALT3

—

GPIO[70]

SIUL

—

ADC_0

Input only

—

46

48

—

AN[9]

E[7]

ALT0

ALT1

ALT2

ALT3

—

GPIO[71]

—

AN[10]

SIUL

—

ADC_0

Input only

—

E[8]

ALT0

ALT1

ALT2

ALT3

—

GPIO[72]

SIUL

—

ADC_1

—

59

—

AN[6]

E[9]

ALT0

ALT1

ALT2

ALT3

—

GPIO[73]

SIUL

—

ADC_1

—

61

—

AN[7]

E[10]

E[11]

E[12]

E[13]

E[14]

ALT0

ALT1

ALT2

ALT3

—

GPIO[74]

SIUL

—

ADC_1

—

63

—

AN[8]

ALT0

ALT1

ALT2

ALT3

—

GPIO[75]

SIUL

—

ADC_1

—

65

—

AN[9]

ALT0

ALT1

ALT2

ALT3

—

GPIO[76]

—

AN[10]

SIUL

—

ADC_1

—

67

ALT0

ALT1

ALT2

ALT3

—

GPIO[77]

SCK

SIUL

DSPI_3

—

SIUL

I/O

—

I

Slow

Medium

117

119

—

EIRQ[25]

ALT0

ALT1

ALT2

ALT3

—

GPIO[78]

SOUT

—

SIUL

DSPI_3

—

SIUL

I/O

O

—

I

—

EIRQ[26]

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

33

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Pin No.

Pad

configuration

register (PCR)

Port

Alternate

Functions

Peripheral³

function^1,2

direction⁴

SRC = 0

SRC = 1

E[15]

PCR[79]

ALT0

ALT1

ALT2

ALT3

—

GPIO[79]

SIUL

—

DSPI_3

SIUL

I/O

—

I

Slow

Medium

—

121

—

SIN

EIRQ[27]

—

I

Port F (16-bit)

F[0]

F[1]

PCR[80]

PCR[81]

ALT0

ALT1

ALT2

ALT3

—

GPIO[80]

DBG0

CS3

SIUL

FlexRay_0

DSPI_3

—

I/O

O

—

I

Slow

Medium

—

133

135

—

EIRQ[28]

SIUL

ALT0

ALT1

ALT2

ALT3

—

GPIO[81]

DBG1

CS2

SIUL

FlexRay_0

DSPI_3

—

I/O

O

—

I

—

EIRQ[29]

SIUL

F[2]

F[3]

F[4]

F[5]

F[6]

F[7]

F[8]

PCR[82]

PCR[83]

PCR[84]

PCR[85]

PCR[86]

PCR[87]

PCR[88]

ALT0

ALT1

ALT2

ALT3

GPIO[82]

DBG2

CS1

SIUL

FlexRay_0

DSPI_3

—

I/O

O

Slow

Medium

Fast

—

137

139

4

—

ALT0

ALT1

ALT2

ALT3

GPIO[83]

DBG3

CS0

SIUL

FlexRay_0

DSPI_3

—

I/O

O

I/O

—

ALT0

ALT1

ALT2

ALT3

GPIO[84]

MDO[3]

—

SIUL

NEXUS_0

—

I/O

O

—

ALT0

ALT1

ALT2

ALT3

GPIO[85]

MDO[2]

—

SIUL

NEXUS_0

—

I/O

O

—

Fast

5

—

ALT0

ALT1

ALT2

ALT3

GPIO[86]

MDO[1]

—

SIUL

NEXUS_0

—

I/O

O

—

Fast

8

—

ALT0

ALT1

ALT2

ALT3

GPIO[87]

MCKO

—

SIUL

NEXUS_0

—

I/O

O

—

Fast

19

20

—

ALT0

ALT1

ALT2

ALT3

GPIO[88]

MSEO1

—

SIUL

NEXUS_0

—

I/O

O

—

Fast

—

MPC5604P Microcontroller Data Sheet, Rev. 8

34

Freescale

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Pin No.

Pad

configuration

register (PCR)

Port

Alternate

Functions

Peripheral³

function^1,2

direction⁴

SRC = 0

SRC = 1

F[9]

F[10]

F[11]

PCR[89]

PCR[90]

PCR[91]

ALT0

ALT1

ALT2

ALT3

GPIO[89]

MSEO0

—

SIUL

NEXUS_0

—

I/O

O

—

Slow

Fast

—

23

24

25

—

ALT0

ALT1

ALT2

ALT3

GPIO[90]

EVTO

—

SIUL

NEXUS_0

—

I/O

O

—

Fast

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[91]

SIUL

—

I/O

—

I

Medium

—

EVTI

NEXUS_0

F[12]

F[13]

F[14]

F[15]

PCR[92]

PCR[93]

PCR[94]

PCR[95]

ALT0

ALT1

ALT2

ALT3

GPIO[92]

ETC[3]

—

SIUL

eTimer_1

—

I/O

—

Slow

Medium

—

106

112

115

113

—

ALT0

ALT1

ALT2

ALT3

GPIO[92]

ETC[4]

—

SIUL

eTimer_1

—

I/O

—

ALT0

ALT1

ALT2

ALT3

GPIO[94]

TXD

—

SIUL

LIN_1

—

I/O

O

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[95]

SIUL

—

LIN_1

I/O

—

I

—

RXD

Port G (12-bit)

G[0]

G[1]

G[2]

PCR[96]

PCR[97]

PCR[98]

ALT0

ALT1

ALT2

ALT3

—

GPIO[96]

F[0]

SIUL

FCU_0

—

SIUL

I/O

O

—

I

Slow

Medium

—

38

—

EIRQ[30]

ALT0

ALT1

ALT2

ALT3

—

GPIO[97]

F[1]

SIUL

FCU_0

—

SIUL

I/O

O

—

I

141

102

—

EIRQ[31]

ALT0

ALT1

ALT2

ALT3

GPIO[98]

SIUL

FlexPWM_0

I/O

—

X[2]

—

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

35

Table 5. Pin muxing (continued)

I/O

Pad speed⁵

Pin No.

Pad

configuration

register (PCR)

Port

Alternate

Functions

Peripheral³

function^1,2

direction⁴

SRC = 0

SRC = 1

G[3]

G[4]

G[5]

G[6]

G[7]

G[8]

PCR[99]

PCR[100]

PCR[101]

PCR[102]

PCR[103]

PCR[104]

ALT0

ALT1

ALT2

ALT3

GPIO[99]

SIUL

FlexPWM_0

I/O

O

—

Slow

Medium

—

104

100

85

A[2]

—

ALT0

ALT1

ALT2

ALT3

GPIO[100]

SIUL

FlexPWM_0

I/O

O

—

Medium

B[2]

—

ALT0

ALT1

ALT2

ALT3

GPIO[101]

SIUL

FlexPWM_0

I/O

—

X[3]

—

ALT0

ALT1

ALT2

ALT3

GPIO[102]

SIUL

FlexPWM_0

I/O

O

—

98

A[3]

—

ALT0

ALT1

ALT2

ALT3

GPIO[103]

SIUL

FlexPWM_0

I/O

O

—

83

B[3]

—

ALT0

ALT1

ALT2

ALT3

—

GPIO[104]

SIUL

—

I/O

—

I

81

—

FAULT[0]

FlexPWM_0

G[9]

G[10]

G[11]

PCR[105]

PCR[106]

PCR[107]

ALT0

ALT1

ALT2

ALT3

—

GPIO[105]

SIUL

—

I/O

—

I

Slow

Medium

—

79

77

75

—

FAULT[1]

FlexPWM_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[106]

SIUL

—

I/O

—

I

—

FAULT[2]

FlexPWM_0

ALT0

ALT1

ALT2

ALT3

—

GPIO[107]

SIUL

—

I/O

—

I

—

FAULT[3]

FlexPWM_0

1

ALT0 is the primary (default) function for each port after reset.

MPC5604P Microcontroller Data Sheet, Rev. 8

36

Freescale

2

Alternate functions are chosen by setting the values of the PCR[PA] bitfields inside the SIU module.

PCR[PA] = 00  ALT0; PCR[PA] = 01  ALT1; PCR[PA] = 10  ALT2; PCR[PA] = 11  ALT3. This is intended to

select the output functions; to use one of the input-only functions, the PCR[IBE] bit must be written to ‘1’, regardless

of the values selected in the PCR[PA] bitfields. For this reason, the value corresponding to an input only function is

reported as “—”.

3

4

Module included on the MCU.

Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by

setting the values of the PSMI[PADSELx] bitfields inside the SIUL module.

5

6

Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.

Weak pull down during reset.

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

37

3

Electrical characteristics

3.1

Introduction

This section contains device electrical characteristics as well as temperature and power considerations.

This microcontroller contains input protection against damage due to high static voltages. However, it is advisable to take

precautions to avoid application of any voltage higher than the specified maximum rated voltages.

To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V or V ). This can be done by the

DD

SS

internal pull-up or pull-down resistors, which are provided by the device for most general purpose pins.

The following tables provide the device characteristics and its demands on the system.

In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller

Characteristics is included in the Symbol column.

In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol

“SR” for System Requirement is included in the Symbol column.

CAUTION

All of the following parameter values can vary depending on the application and must be

confirmed during silicon characterization or silicon reliability trial.

3.2

Parameter classification

The electrical parameters are guaranteed by various methods. To give the customer a better understanding, the classifications

listed in Table 6 are used and the parameters are tagged accordingly in the tables where appropriate.

Table 6. Parameter classifications

Classification tag

Tag description

P

C

Those parameters are guaranteed during production testing on each individual device.

Those parameters are achieved by the design characterization by measuring a statistically

relevant sample size across process variations.

T

Those parameters are achieved by design characterization on a small sample size from typical

devices under typical conditions unless otherwise noted. All values shown in the typical column

are within this category.

D

Those parameters are derived mainly from simulations.

NOTE

The classification is shown in the column labeled “C” in the parameter tables where

appropriate.

MPC5604P Microcontroller Data Sheet, Rev. 8

38

Freescale

3.3

Absolute maximum ratings

1

Table 7. Absolute maximum ratings

Value

Symbol

Parameter

Conditions

Unit

Min

Max²

V_SS

SR Device ground

—

0

V

3

V_{DD_HV_IOx}SR 3.3 V / 5.0 V input/output supply

voltage with respect to ground (V_SS

–0.3

6.0

)

V_{SS_HV_IOx}SR Input/output ground voltage with

—

–0.1

–0.3

0.1

6.0

V

respect to ground (V_SS

)

V_{DD_HV_FL}SR 3.3 V / 5.0 V code and data flash

supply voltage with respect to ground

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}+ 0.3

(V_SS

)

V_{SS_HV_FL}SR Code and data flash ground with

respect to ground (V_SS

—

–0.1

–0.3

0.1

V

)

V_{DD_HV_OSC}SR 3.3 V / 5.0 V crystal oscillator

amplifier supply voltage with respect

—

6.0

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}+ 0.3

to ground (V_SS

)

V_{SS_HV_OSC}SR 3.3 V / 5.0 V crystal oscillator

amplifier reference voltage with

—

–0.1

–0.3

0.1

V

respect to ground (V_SS

)

V_{DD_HV_REG}SR 3.3 V / 5.0 V voltage regulator supply

—

6.0

voltage with respect to ground (V_SS

)

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}+ 0.3

4

V_{DD_HV_ADC0}SR 3.3 V / 5.0 V ADC_0 supply and high V_{DD_HV_REG}

<

>

–0.3

V_{DD_HV_REG}

0.3

+

V

reference voltage with respect to

ground (V_SS

2.7 V

)

V_{DD_HV_REG}

2.7 V

6.0

V_{SS_HV_ADC0}SR ADC_0 ground and low reference

voltage with respect to ground (V_SS

—

–0.1

–0.3

0.1

V

)

4

V_{DD_HV_ADC1}SR 3.3 V / 5.0 V ADC_0 supply and high V_{DD_HV_REG}

<

>

V_{DD_HV_REG}

0.3

+

reference voltage with respect to

ground (V_SS

2.7 V

)

V_{DD_HV_REG}

2.7 V

6.0

V_{SS_HV_ADC1}SR ADC_1 ground and low reference

voltage with respect to ground (V_SS

—

–0.1

3.0

0.1

V

)

TV_DD

SR Slope characteristics on all V_DD

during power up⁵with respect to

—

500 x 10³

(0.5 [V/µs])

V/s

ground (V_SS

)

V_IN

SR Voltage on any pin with respect to

—

–0.3

6.0

V

ground (V_{SS_HV_IOx}) with respect to

ground (V_SS

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}+ 0.

3

)

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

39

1

Table 7. Absolute maximum ratings (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Max²

V_{DD_HV_REG}

2.7 V

>

V_{SS_HV_ADV0} V_{DD_HV_ADV0}+

V

0.3

V_{DD_HV_ADV0}

ADC0 and shared ADC0/1 analog

input voltage⁶

V_INAN0

SR

V_{DD_HV_REG}

2.7 V

<

>

<

V_{SS_HV_ADV0}

V_{DD_HV_REG}

2.7 V

V_{SS_HV_ADV1} V_{DD_HV_ADV1}+

0.3

V_{SS_HV_ADV1}

–10

0.3

V_{DD_HV_ADV1}

10

V_INAN1

SR ADC1 analog input voltage⁷

V_{DD_HV_REG}

2.7 V

V

I_INJPAD

I_INJSUM

I_{VDD_LV}

SR Injected input current on any pin

during overload condition

—

mA

SR Absolute sum of all injected input

currents during overload condition

–50

—

50

mA

SR Low voltage static current sink

through V_{DD_LV}

155

T_STG

T_J

SR Storage temperature

—

–55

–40

150

°C

SR Junction temperature under bias

1

Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress

ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect

device reliability or cause permanent damage to the device.

2

3

Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device

stress have not yet been determined.

The difference between each couple of voltage supplies must be less than 300 mV,

|V_{DD_HV_IOy}– V_{DD_HV_IOx}| < 300 mV.

4

5

6

7

The difference between ADC voltage supplies must be less than 100 mV, |V_{DD_HV_ADC1}– V_{DD_HV_ADC0}| < 100 mV.

Guaranteed by device validation

Not allowed to refer this voltage to V_{DD_HV_ADV1}, V_{SS_HV_ADV1}

Not allowed to refer this voltage to V_{DD_HV_ADV0}, V_{SS_HV_ADV0}

Figure 4 shows the constraints of the different power supplies.

MPC5604P Microcontroller Data Sheet, Rev. 8

40

Freescale

VDD_HV_xxx

6.0 V

VDD_HV_IOx

–0.3 V

6.0 V

Figure 4. Power supplies constraints (–0.3 V  V_{DD_HV_IOx} 6.0 V)

The MPC5604P supply architecture allows of having ADC supply managed independently from standard V

Figure 5 shows the constraints of the ADC power supply.

supply.

DD_HV

VDD_HV_ADCx

6.0 V

VDD_HV_REG

–0.3 V

2.7 V

6.0 V

Figure 5. Independent ADC supply (–0.3 V  V_{DD_HV_REG} 6.0 V)

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

41

3.4

Recommended operating conditions

Table 8. Recommended operating conditions (5.0 V)

Value

Symbol

Parameter

Conditions

Unit

Min

Max¹

V_SS

SR Device ground

—

0

V

2

V_{DD_HV_IOx}

SR 5.0 V input/output supply

voltage

4.5

5.5

V_{SS_HV_IOx}

V_{DD_HV_FL}

SR Input/output ground voltage

—

0

V

SR 5.0 V code and data flash

supply voltage

4.5

5.5

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}– 0.1 V_{DD_HV_IOx}+ 0.1

V_{SS_HV_FL}

SR Code and data flash ground

—

0

V

V_{DD_HV_OSC}

SR 5.0 V crystal oscillator amplifier

supply voltage

4.5

5.5

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}– 0.1 V_{DD_HV_IOx}+ 0.1

V_{SS_HV_OSC}

V_{DD_HV_REG}

SR 5.0 V crystal oscillator amplifier

reference voltage

—

0

V

SR 5.0 V voltage regulator supply

voltage

—

4.5

5.5

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}– 0.1 V_{DD_HV_IOx}+ 0.1

3

V_{DD_HV_ADC0}

SR 5.0 V ADC_0 supply and high

reference voltage

—

4.5

5.5

—

V

Relative to

V_{DD_HV_REG}– 0.1

V_{DD_HV_REG}

V_{SS_HV_ADC0}

SR ADC_0 ground and low

reference voltage

—

0

V

3

V_{DD_HV_ADC1}

SR 5.0 V ADC_1 supply and high

reference voltage

—

4.5

5.5

—

Relative to

V_{DD_HV_REG}– 0.1

V_{DD_HV_REG}

V_{SS_HV_ADC1}

SR ADC_1 ground and low

reference voltage

—

0

V

4,5

4

V_{DD_LV_REGCOR}

CC Internal supply voltage

—

0

—

0

V

V_{SS_LV_REGCOR}SR Internal reference voltage

4,5

V_{DD_LV_CORx}

V_{SS_LV_CORx}

T_A

CC Internal supply voltage

—

0

—

0

V

4

SR Internal reference voltage

V

SR Ambient temperature under

bias

–40

125

°C

1

2

3

Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full

functionality. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.

The difference between each couple of voltage supplies must be less than 100 mV, |V_{DD_HV_IOy}– V_{DD_HV_IOx}| <

100 mV.

The difference between ADC voltage supplies must be less than 100 mV, |V_{DD_HV_ADC1} V_{DD_HV_ADC0}| < 100 mV.

MPC5604P Microcontroller Data Sheet, Rev. 8

42

Freescale

4

5

To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced

by an on-chip voltage regulator—but for the device to function properly the low voltage grounds (V_{SS_LV_xxx}) must

be shorted to high voltage grounds (V_{SS_HV_xxx}) and the low voltage supply pins (V_{DD_LV_xxx}) must be connected

to the external ballast emitter.

The low voltage supplies (V_{DD_LV_xxx}) are not all independent.

V_{DD_LV_COR1}and V_{DD_LV_COR2}are shorted internally via double bonding connections with lines that provide the

low voltage supply to the data flash module. Similarly, V_{SS_LV_COR1}and V_{SS_LV_COR2}are internally shorted.

V_{DD_LV_REGCOR}and V_{DD_LV_REGCORx}are physically shorted internally, as are V_{SS_LV_REGCOR}and V_{SS_LV_CORx}

.

Table 9. Recommended operating conditions (3.3 V)

Value

Symbol

Parameter

Conditions

Unit

Min

Max¹

V_SS

SR Device ground

—

0

V

2

V_{DD_HV_IOx}

SR 3.3 V input/output supply

voltage

3.0

3.6

V_{SS_HV_IOx}

V_{DD_HV_FL}

SR Input/output ground voltage

—

0

V

SR 3.3 V code and data flash

supply voltage

3.0

3.6

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}– 0.1 V_{DD_HV_IOx}+ 0.1

V_{SS_HV_FL}

SR Code and data flash ground

—

0

V

V_{DD_HV_OSC}

SR 3.3 V crystal oscillator amplifier

supply voltage

3.0

3.6

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}– 0.1 V_{DD_HV_IOx}+ 0.1

V_{SS_HV_OSC}

V_{DD_HV_REG}

SR 3.3 V crystal oscillator amplifier

reference voltage

—

0

V

SR 3.3 V voltage regulator supply

voltage

—

3.0

3.6

Relative to

V_{DD_HV_IOx}

V_{DD_HV_IOx}– 0.1 V_{DD_HV_IOx}+ 0.1

3

V_{DD_HV_ADC0}

SR 3.3 V ADC_0 supply and high

reference voltage

—

3.0

5.5

V

Relative to

V_{DD_HV_REG}– 0.1

V_{DD_HV_REG}

V_{SS_HV_ADC0}

SR ADC_0 ground and low

reference voltage

—

0

V

3

V_{DD_HV_ADC1}

SR 3.3 V ADC_1 supply and high

reference voltage

3.0

5.5

Relative to

V_{DD_HV_REG}– 0.1

V_{DD_HV_REG}

V_{SS_HV_ADC1}

SR ADC_1 ground and low

reference voltage

—

0

V

4,5

V_{DD_LV_REGCOR}

CC Internal supply voltage

—

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

43

Table 9. Recommended operating conditions (3.3 V) (continued)

Value

Symbol

Parameter

Conditions

Unit

Min

Max¹

4

V_{SS_LV_REGCOR}SR Internal reference voltage

—

0

—

0

—

0

V

4,5

V_{DD_LV_CORx}

V_{SS_LV_CORx}

T_A

CC Internal supply voltage

4

SR Internal reference voltage

V

SR Ambient temperature under

bias

–40

125

°C

1

2

3

Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full

functionality. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.

The difference between each couple of voltage supplies must be less than 100 mV, |V_{DD_HV_IOy}– V_{DD_HV_IOx}| <

100 mV.

The difference between each couple of voltage supplies must be less than 100 mV, |V_{DD_HV_ADC1}– V_{DD_HV_ADC0}

|

< 100 mV. As long as that condition is met, ADC_0 and ADC_1 can be operated at 5 V with the rest of the device

operating at 3.3 V.

4

5

To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced

by an on-chip voltage regulator—but for the device to function properly the low voltage grounds (V_{SS_LV_xxx}) must

be shorted to high voltage grounds (V_{SS_HV_xxx}) and the low voltage supply pins (V_{DD_LV_xxx}) must be connected

to the external ballast emitter.

The low voltage supplies (V_{DD_LV_xxx}) are not all independent.

V_{DD_LV_COR1}and V_{DD_LV_COR2}are shorted internally via double bonding connections with lines that provide the

low voltage supply to the data flash module. Similarly, V_{SS_LV_COR1}and V_{SS_LV_COR2}are internally shorted.

V_{DD_LV_REGCOR}and V_{DD_LV_REGCORx}are physically shorted internally, as are V_{SS_LV_REGCOR}and V_{SS_LV_CORx}

.

MPC5604P Microcontroller Data Sheet, Rev. 8

44

Freescale

Figure 6 shows the constraints of the different power supplies.

VDD_HV_xxx

5.5 V

3.3 V

3.0 V

VDD_HV_IOx

5.5 V

3.0 V

3.3 V

Note: IO AC and DC characteristics are guaranteed only in the range of 3.0–3.6 V when

PAD3V5V is low, and in the range of 4.5–5.5 V when PAD3V5V is high.

Figure 6. Power supplies constraints (3.0 V  V_{DD_HV_IOx} 5.5 V)

The MPC5604P supply architecture allows the ADC supply to be managed independently from the standard V

Figure 7 shows the constraints of the ADC power supply.

supply.

DD_HV

VDD_HV_ADCx

5.5 V

3.0 V

VDD_HV_REG

3.0 V

5.5 V

Figure 7. Independent ADC supply (3.0 V  V_{DD_HV_REG} 5.5 V)

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

45

3.5

Thermal characteristics

3.5.1

Package thermal characteristics

Table 10. Thermal characteristics for 144-pin LQFP

Symbol

Parameter

Conditions

Typical value Unit

R_JA

Thermal resistance junction-to-ambient,

natural convection¹

Single layer board—1s

Four layer board—2s2p

54.2

44.4

29.9

9.3

°C/W

R_JB

Thermal resistance junction-to-board²

R_JCtopThermal resistance junction-to-case (top)³Single layer board—1s

_JB

_JC

Junction-to-board, natural convection⁴

Junction-to-case, natural convection⁵

Operating conditions

30.2

0.8

1

2

3

Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board

meets JEDEC specification for this package.

Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets

JEDEC specification for the specified package.

Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold

plate temperature is used for the case temperature. Reported value includes the thermal resistance

of the interface layer.

4

5

Thermal characterization parameter indicating the temperature difference between the board and the

junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal

characterization parameter is written as Psi-JB.

Thermal characterization parameter indicating the temperature difference between the case and the

junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal

characterization parameter is written as Psi-JC.

Table 11. Thermal characteristics for 100-pin LQFP

Symbol

Parameter

Conditions

Typical value Unit

R_JA

Thermal resistance junction-to-ambient,

natural convection¹

Single layer board—1s

Four layer board—2s2p

47.3

35.3

19.1

9.7

°C/W

R_JB

Thermal resistance junction-to-board²

R_JCtopThermal resistance junction-to-case (top)³Single layer board—1s

_JB

_JC

Junction-to-board, natural convection⁴

Junction-to-case, natural convection⁵

Operating conditions

19.1

0.8

1

2

3

Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board

meets JEDEC specification for this package.

Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets

JEDEC specification for the specified package.

Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold

plate temperature is used for the case temperature. Reported value includes the thermal resistance

of the interface layer.

4

Thermal characterization parameter indicating the temperature difference between the board and the

junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal

characterization parameter is written as Psi-JB.

MPC5604P Microcontroller Data Sheet, Rev. 8

46

Freescale

5

Thermal characterization parameter indicating the temperature difference between the case and the

junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal

characterization parameter is written as Psi-JC.

3.5.2

General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, T , can be obtained from Equation 1:

J

T = T + (R

* P )

Eqn. 1

J

A

JA

D

where:

T

= ambient temperature for the package (°C)

A

R

= junction to ambient thermal resistance (°C/W)

= power dissipation in the package (W)

JA

P

D

The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal

performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value

obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which

value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a

single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal

planes is usually appropriate if the board has low power dissipation and the components are well separated.

When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance

and a case to ambient thermal resistance:

R

= R

+ R

CA

Eqn. 2

JA

JC

where:

R

= junction to ambient thermal resistance (°C/W)

= junction to case thermal resistance (°C/W)

= case to ambient thermal resistance (°C/W)

JA

JC

CA

R

is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to

JC

ambient thermal resistance, R

. For instance, the user can change the size of the heat sink, the air flow around the device, the

CA

interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit

board surrounding the device.

To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal

Characterization Parameter ( ) can be used to determine the junction temperature with a measurement of the temperature at

JT

the top center of the package case using Equation 3:

T = T + ( x P )

Eqn. 3

J

T

JT

D

where:

T

= thermocouple temperature on top of the package (°C)

= thermal characterization parameter (°C/W)

= power dissipation in the package (W)

T



JT

P

D

The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied

to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the

package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the

junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects

of the thermocouple wire.

References:

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

47

Semiconductor Equipment and Materials International

3081 Zanker Road

San Jose, CA 95134

(408) 943-6900

U.S.A.

MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at

800-854-7179 or 303-397-7956.

JEDEC specifications are available on the WEB at http://www.jedec.org.

1. C.E. Triplett and B. Joiner, An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller

Module, Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.

2. G. Kromann, S. Shidore, and S. Addison, Thermal Modeling of a PBGA for Air-Cooled Applications, Electronic

Packaging and Production, pp. 53–58, March 1998.

3. B. Joiner and V. Adams, Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in

Thermal Modeling, Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.

3.6

Electromagnetic interference (EMI) characteristics

Table 12. EMI testing specifications

Level

(Max)

Symbol

Parameter

Conditions

Clocks

Frequency

Unit

V_EMERadiated emissions Device configuration, test

f_OSC8 MHz

150 kHz–150 MHz 16 dBµV

conditions and EM testing per f_CPU64 MHz

150–1000 MHz

IEC Level

15

M

standard IEC61967-2

No PLL frequency

modulation

—

Supply voltage = 5 V DC

Ambient temperature = 25 °C

Worst-case orientation

f_OSC8 MHz

150 kHz–150 MHz 15 dBµV

f_CPU64 MHz

1% PLL frequency

modulation

150–1000 MHz

IEC Level

14

M

—

3.7

Electrostatic discharge (ESD) characteristics

1,2

Table 13. ESD ratings

Symbol

Parameter

Conditions

Value

Unit

V_ESD(HBM)

V_ESD(CDM)

SR Electrostatic discharge (Human Body Model)

SR Electrostatic discharge (Charged Device Model)

—

2000

V

750 (corners)

500 (other)

1

2

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated

Circuits.

A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification requirements. Complete DC parametric and functional testing shall be performed per applicable

device specification at room temperature followed by hot temperature, unless specified otherwise in the device

specification.

MPC5604P Microcontroller Data Sheet, Rev. 8

48

Freescale

3.8

Power management electrical characteristics

Voltage regulator electrical characteristics

3.8.1

The internal voltage regulator requires an external NPN ballast to be connected as shown in Figure 8. Table 14 contains all

approved NPN ballast components. Capacitances should be placed on the board as near as possible to the associated pins. Care

should also be taken to limit the serial inductance of the V

Table 15.

, BCTRL and V

pins to less than L , see

DD_HV_REG

DD_LV_CORx Reg

NOTE

The voltage regulator output cannot be used to drive external circuits. Output pins are used

only for decoupling capacitances.

V

must be generated using internal regulator and external NPN transistor. It is

DD_LV_COR

not possible to provide V

through external regulator.

DD_LV_COR

For the MPC5604P microcontroller, capacitors, with total values not below C

, should be placed between

DEC1

V

/V

close to external ballast transistor emitter. 4 capacitors, with total values not below C

, should

DEC2

DD_LV_CORx SS_LV_CORx

be placed close to microcontroller pins between each V

/V

supply pairs and the

DD_LV_CORx SS_LV_CORx

V

/V

pair . Additionally, capacitors with total values not below C

, should be placed between

DEC3

DD_LV_REGCOR SS_LV_REGCOR

the V

/V

pins close to ballast collector. Capacitors values have to take into account capacitor accuracy,

DD_HV_REG SS_HV_REG

aging and variation versus temperature.

All reported information are valid for voltage and temperature ranges described in recommended operating condition, Table 8

and Table 9.

VDD_HV_REG

C_DEC3

MPC5604P

BJT⁽¹⁾

BCTRL

R_B

VDD_LV_COR

C_DEC2

C_DEC1

1

Refer to Table 14.

Figure 8. Configuration with resistor on base

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

49

Table 14. Approved NPN ballast components (configuration with resistor on base)

Part

Manufacturer

Approved derivatives¹

BCP68

ON Semi

NXP

BCP68

BCP68-25

Infineon

NXP

BCP68-25

BCX68

BC868

BC817

BCX68-10;BCX68-16;BCX68-25

BC868

Infineon

NXP

BC817-16;BC817-25;BC817SU;

BC817-16;BC817-25

BCP56-16

BCP56

ST

Infineon

ON Semi

NXP

BCP56-10;BCP56-16

BCP56-10

BCP56-10;BCP56-16

1

For automotive applications please check with the appropriate transistor vendor for automotive grade

certification

Table 15. Voltage regulator electrical characteristics (configuration with resistor on base)

Value

Symbol

C

Parameter

Conditions

Unit

Min Typ Max

V_{DD_LV_REGCOR}CC P Output voltage under maximum Post-trimming

1.15

—

1.32

V

load run supply current

configuration

R_B

SR — External resistance on bipolar

junction transistor (BJT) base

—

18

—

22 k

C_DEC1

SR — External decoupling/stability

ceramic capacitor

BJT from Table 14. 3

capacitances (i.e. X7R or X8R

capacitors) with nominal value

of 10 µF

19.5 30

—

µF

BJT BC817, one capacitance 14.3 22

of 22 µF

µF

MPC5604P Microcontroller Data Sheet, Rev. 8

50

Freescale

Table 15. Voltage regulator electrical characteristics (configuration with resistor on base) (continued)

Value

Symbol

C

Parameter

Conditions

Unit

Min Typ Max

R_REG

SR — Resulting ESR of all three

capacitors of C_DEC1

BJT from Table 14. 3x10 µF.

Absolute maximum value

between 100 kHz and 10 MHz

—

50 m

40 m

Resulting ESR of the unique BJT BC817, 1x 22 µF.

10

—

capacitor C_DEC1

Absolute maximum value

between 100 kHz and 10 MHz

C_DEC2

SR — External decoupling/stability

ceramic capacitor

4 capacitances (i.e. X7R or

X8R capacitors) with nominal

value of 440 nF

1200 1760

19.5 30

—

nF

µF

C_DEC3

SR — External decoupling/stability

ceramic capacitor on

3 capacitances (i.e. X7R or

X8R capacitors) with nominal

value of 10 µF; C_DEC3has to

be equal or greater than

C_DEC1

V_{DD_HV_REG}

L_Reg

SR — Resulting ESL of V_{DD_HV_REG}

,

—

15 nH

BCTRL and V_{DD_LV_CORx}pins

VDD_HV_REG

C_DEC3

MPC5604P

BCP56,

BCP68,

BCX68,

BC817

BCTRL

VDD_LV_COR

C_DEC2

C_DEC1

Figure 9. Configuration without resistor on base

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

51

Table 16. Voltage regulator electrical characteristics (configuration without resistor on base)

Value

Symbol

C

Parameter

Conditions

Unit

Min Typ Max

V_{DD_LV_REGCOR}CC P Output voltage under maximum Post-trimming

1.15

1.32

V

load run supply current

configuration

—

C_DEC1

R_REG

C_DEC2

C_DEC3

SR — External decoupling/stability

ceramic capacitor

4 capacitances

µF

m

nF

40

—

56

—

45

—

SR — Resulting ESR of all four C_DEC1Absolute maximum value

between 100 kHz and 10 MHz

SR — External decoupling/stability

ceramic capacitor

4 capacitances of 100 nF each

400

SR — External decoupling/stability

ceramic capacitor on

µF

—

40

—

VDD_HV_REG

L_Reg

SR — Resulting ESL of V_{DD_HV_REG}

,

—

15 nH

BCTRL and V_{DD_LV_CORx}pins

3.8.2

Voltage monitor electrical characteristics

The device implements a Power-on Reset module to ensure correct power-up initialization, as well as three low voltage

detectors to monitor the V and the V voltage while device is supplied:

DD

DD_LV

•

POR monitors V during the power-up phase to ensure device is maintained in a safe reset state

DD

LVDHV3 monitors V to ensure device reset below minimum functional supply

DD

LVDHV5 monitors V when application uses device in the 5.0V ± 10% range

DD

LVDLVCOR monitors low voltage digital power domain

Table 17. Low voltage monitor electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Max

V_PORH

T

P

Power-on reset threshold

—

1.5

1.0

—

2.7

—

V

V_PORUP

Supply for functional POR module

T_A= 25 °C

V_{REGLVDMOK_H}

V_{REGLVDMOK_L}

V_{FLLVDMOK_H}

V_{FLLVDMOK_L}

V_{IOLVDMOK_H}

V_{IOLVDMOK_L}

Regulator low voltage detector high threshold

Regulator low voltage detector low threshold

Flash low voltage detector high threshold

Flash low voltage detector low threshold

I/O low voltage detector high threshold

I/O low voltage detector low threshold

—

2.95

—

2.6

—

2.95

—

2.6

—

2.95

—

2.6

MPC5604P Microcontroller Data Sheet, Rev. 8

52

Freescale

Table 17. Low voltage monitor electrical characteristics (continued)

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Max

V_{IOLVDM5OK_H}

V_{IOLVDM5OK_L}

V_{MLVDDOK_H}

V_{MLVDDOK_L}

P

I/O 5V low voltage detector high threshold

I/O 5V low voltage detector low threshold

Digital supply low voltage detector high

Digital supply low voltage detector low

—

3.8

—

4.4

—

V

1.145

—

1.08

1

V_DD= 3.3V ± 10% / 5.0V ± 10%, T_A= –40 °C to T_{A MAX}, unless otherwise specified

3.9

Power up/down sequencing

To prevent an overstress event or a malfunction within and outside the device, the MPC5604P implements the following

sequence to ensure each module is started only when all conditions for switching it ON are available:

•

A POWER_ON module working on voltage regulator supply controls the correct start-up of the regulator. This is a

key module ensuring safe configuration for all voltage regulator functionality when supply is below 1.5V. Associated

POWER_ON (or POR) signal is active low.

•

Several low voltage detectors, working on voltage regulator supply monitor the voltage of the critical modules (voltage

regulator, I/Os, flash memory and low voltage domain). LVDs are gated low when POWER_ON is active.

A POWER_OK signal is generated when all critical supplies monitored by the LVD are available. This signal is active

high and released to all modules including I/Os, flash memory and RC16 oscillator needed during power-up phase and

reset phase. When POWER_OK is low the associated module are set into a safe state.

V_LVDHV3H

V_PORH

3.3V

VDD_HV_REG

V_{POR_UP}

0V

3.3V

POWER_ON

LVDM (HV)

0V

3.3V

0V

V_{MLVDOK_H}

VDD_LV_REGCOR

1.2V

0V

3.3V

LVDD (LV)

0V

3.3V

POWER_OK

0V

RC16MHz Oscillator

1.2V

0V

~1us

1.2V

0V

Internal Reset Generation Module

FSM

P0

P1

Figure 10. Power-up typical sequence

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

53

V_LVDHV3L

3.3V

V_PORH

VDD_HV_REG

0V

3.3V

LVDM (HV)

POWER_ON

0V

3.3V

0V

1.2V

0V

VDD_LV_REGCOR

LVDD (LV)

3.3V

0V

3.3V

POWER_OK

0V

RC16MHz Oscillator

1.2V

0V

Internal Reset Generation Module

FSM

1.2V

0V

IDLE

P0

Figure 11. Power-down typical sequence

V_LVDHV3H

V_LVDHV3L

3.3V

VDD_HV_REG

0V

3.3V

LVDM (HV)

POWER_ON

0V

3.3V

0V

1.2V

0V

VDD_LV_REGCOR

LVDD (LV)

3.3V

0V

3.3V

POWER_OK

0V

RC16MHz Oscillator

1.2V

0V

~1us

Internal Reset Generation Module

1.2V

0V

FSM

IDLE

P0

P1

Figure 12. Brown-out typical sequence

MPC5604P Microcontroller Data Sheet, Rev. 8

54

Freescale

3.10 DC electrical characteristics

3.10.1 NVUSRO register

Portions of the device configuration, such as high voltage supply, and watchdog enable/disable after reset are controlled via bit

values in the non-volatile user options (NVUSRO) register.

For a detailed description of the NVUSRO register, please refer to the device reference manual.

3.10.1.1 NVUSRO[PAD3V5V] field description

The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 18 shows how NVUSRO[PAD3V5V]

controls the device configuration.

Table 18. PAD3V5V field description

Value¹

Description

0

1

High voltage supply is 5.0 V

High voltage supply is 3.3 V

1

Default manufacturing value before flash initialization is ‘1’ (3.3 V).

3.10.2 DC electrical characteristics (5 V)

Table 19 gives the DC electrical characteristics at 5 V (4.5 V < V

< 5.5 V, NVUSRO[PAD3V5V] = 0); see Figure 13.

DD_HV_IOx

Table 19. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)

Value

Symbol

C

Parameter

Conditions

Unit

Min

Max

V_IL

D Low level input voltage

—

–0.1¹

—

V

µA

P

—

0.35 V_{DD_HV_IOx}

V_IH

P High level input voltage

D

—

0.65 V_{DD_HV_IOx}

—

V_{DD_HV_IOx}+ 0.1¹

V_HYS

T Schmitt trigger hysteresis

—

0.1 V_{DD_HV_IOx}

—

V_{OL_S}P Slow, low level output voltage

V_{OH_S}P Slow, high level output voltage

V_{OL_M}P Medium, low level output voltage

V_{OH_M}P Medium, high level output voltage

V_{OL_F}P Fast, low level output voltage

V_{OH_F}P Fast, high level output voltage

V_{OL_SYM}P Symmetric, low level output voltage

V_{OH_SYM}P Symmetric, high level output voltage

I_OL= 3 mA

I_OH= –3 mA

I_OL= 3 mA

I_OH= –3 mA

I_OL= 3 mA

I_OH= –3 mA

I_OL= 3 mA

I_OH= –3 mA

V_IN= V_IL

V_IN= V_IH

—

0.1 V_{DD_HV_IOx}

0.8 V_{DD_HV_IOx}

—

0.1 V_{DD_HV_IOx}

0.8 V_{DD_HV_IOx}

—

0.1 V_{DD_HV_IOx}

0.8 V_{DD_HV_IOx}

—

0.8 V_{DD_HV_IOx}

–130

0.1 V_{DD_HV_IOx}

—

I_PU

P Equivalent pull-up current

—

–10

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

55

Table 19. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0) (continued)

Value

Symbol

C

Parameter

Conditions

Unit

Min

Max

I_PD

P Equivalent pull-down current

V_IN= V_IL

10

—

–1

—

130

1

µA

V_IN= V_IH

I_IL

C_IN

I_PU

P Input leakage current (all

bidirectional ports)

T_A= –40 to 125 °C

µA

P Input leakage current (all ADC

input-only ports)

T_A= –40 to 125 °C

–0.5

0.5

D Input capacitance

—

V_IN= V_IL

V_IN= V_IH

—

–130

—

10

—

pF

µA

D RESET, equivalent pull-up current

–10

1

“SR” parameter values must not exceed the absolute maximum ratings shown in Table 7.

Table 20. Supply current (5.0 V, NVUSRO[PAD3V5V] = 0)

Value

Typ Max

Symbol

C

Parameter

Conditions

Unit

I_{DD_LV_CORx}

T

RUN—Maximum mode¹

V_{DD_LV_CORx}

externally forced at 1.3 V

40 MHz 62

64 MHz 71

40 MHz 45

64 MHz 52

64 MHz 60

77 mA

88

56

65

75

RUN—Typical mode²

P

RUN—Maximum mode³

HALT mode⁴

V_{DD_LV_CORx}

externally forced at 1.3 V

V_{DD_LV_CORx}

externally forced at 1.3 V

—

1.5

1

10

STOP mode⁵

V_{DD_LV_CORx}

externally forced at 1.3 V

I_{DD_FLASH}

T

Flash during read

V_{DD_HV_FL}at 5.0 V

—

10

15

12

19

Flash during erase operation on 1 V_{DD_HV_FL}at 5.0 V

flash module

I_{DD_ADC}

ADC—Maximum mode¹

ADC—Typical mode²

Oscillator

V_{DD_HV_ADC0}at 5.0 V

V_{DD_HV_ADC1}at 5.0 V

f_ADC= 16 MHz

ADC_1 3.5

ADC_0

ADC_1 0.8

5

4

1

3

ADC_0 0.005 0.006

8 MHz 2.6 3.2

I_{DD_OSC}

T

V_{DD_OSC}at 5.0 V

1

2

Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled. I/O

supply current excluded.

Typical mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only. I/O supply current excluded.

MPC5604P Microcontroller Data Sheet, Rev. 8

56

Freescale

3

Code fetched from RAM, PLL_0: 64 MHz system clock (x4 multiplier with 16 MHz XTAL), PLL_1 is ON at

PHI_div2 = 120 MHz and PHI_div3 = 80 MHz, auxiliary clock sources set that all peripherals receive maximum

frequency, all peripherals enabled.

4

5

Halt mode configurations: code fetched from RAM, code and data flash memories in low power mode,

OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.

STOP “P” mode Device Under Test (DUT) configuration: code fetched from RAM, code and data flash memories

OFF, OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.

3.10.3 DC electrical characteristics (3.3 V)

Table 21 gives the DC electrical characteristics at 3.3 V (3.0 V < V

Figure 13.

< 3.6 V, NVUSRO[PAD3V5V] = 1); see

DD_HV_IOx

1

Table 21. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)

Value

Symbol C

Parameter

Conditions

Unit

Min

Max

V_IL

V_IH

D Low level input voltage

—

–0.1²

—

V

µA

P

—

0.35 V_{DD_HV_IOx}

P High level input voltage

D

—

0.65 V_{DD_HV_IOx}

—

V_{DD_HV_IOx}+ 0.1²

V_HYST Schmitt trigger hysteresis

—

0.1 V_{DD_HV_IOx}

—

0.5

—

V_{OL_S}P Slow, low level output voltage

V_{OH_S}P Slow, high level output voltage

V_{OL_M}P Medium, low level output voltage

V_{OH_M}P Medium, high level output voltage

V_{OL_F}P Fast, low level output voltage

V_{OH_F}P Fast, high level output voltage

V_{OL_SYM}P Symmetric, low level output voltage

V_{OH_SYM}P Symmetric, high level output voltage

I_OL= 1.5 mA

I_OH= –1.5 mA

I_OL= 2 mA

I_OH= –2 mA

I_OL= 1.5 mA

I_OH= –1.5 mA

I_OL= 1.5 mA

I_OH= –1.5 mA

V_IN= V_IL

V_IN= V_IH

V_IN= V_IL

—

V_{DD_HV_IOx}– 0.8

—

0.5

—

V_{DD_HV_IOx}– 0.8

—

0.5

—

V_{DD_HV_IOx}– 0.8

—

0.5

—

V_{DD_HV_IOx}– 0.8

I_PU

P Equivalent pull-up current

–130

—

–10

—

I_PD

P Equivalent pull-down current

10

µA

V

_IN= V_IH

—

130

1

I_IL

C_IN

I_PU

P Input leakage current (all

bidirectional ports)

T_A= –40 to 125 °C

—

µA

P Input leakage current (all ADC

input-only ports)

—

0.5

D Input capacitance

—

–130

—

10

—

pF

µA

V

_IN= V_IL

D RESET, equivalent pull-up current

V_IN= V_IH

–10

1

These specifications are design targets and subject to change per device characterization.

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

57

2

“SR” parameter values must not exceed the absolute maximum ratings shown in Table 7.

Table 22. Supply current (3.3 V, NVUSRO[PAD3V5V] = 1)

Value

Symbol

C

Parameter

Conditions

Unit

Typ Max

I_{DD_LV_CORx}

T

RUN—Maximum mode¹

V_{DD_LV_CORx}

externally forced at 1.3 V

40 MHz 62

77

89

56

66

75

mA

64 MHz 71

40 MHz 45

64 MHz 53

64 MHz 60

RUN—Typical mode²

P

RUN—Maximum mode³

HALT mode⁴

V_{DD_LV_CORx}

externally forced at 1.3 V

V_{DD_LV_CORx}

externally forced at 1.3 V

—

1.5

1

10

STOP mode⁵

V_{DD_LV_CORx}

externally forced at 1.3 V

I_{DD_FLASH}

T

Flash during read on single mode

V_{DD_HV_FL}at 3.3 V

—

8

10

12

Flash during erase operation on

single mode

10

I_{DD_ADC}

ADC—Maximum mode¹

ADC—Typical mode²

Oscillator

V_{DD_HV_ADC0}at 3.3 V

V_{DD_HV_ADC1}at 3.3 V

f_ADC= 16 MHz

ADC_1 2.5

ADC_0

ADC_1 0.8

4

1

2

ADC_0 0.005 0.006

8 MHz 2.4

I_{DD_OSC}

T

V_{DD_OSC}at 3.3 V

3

1

Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled. I/O

supply current excluded.

2

3

Typical mode: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only. I/O supply current excluded.

Code fetched from RAM, PLL_0: 64 MHz system clock (x4 multiplier with 16 MHz XTAL), PLL_1 is ON at

PHI_div2 = 120 MHz and PHI_div3 = 80 MHz, auxiliary clock sources set that all peripherals receive maximum

frequency, all peripherals enabled.

4

5

Halt mode configurations: code fetched from RAM, code and data flash memories in low power mode,

OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.

STOP “P” mode Device Under Test (DUT) configuration: code fetched from RAM, code and data flash memories

OFF, OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.

3.10.4 Input DC electrical characteristics definition

Figure 13 shows the DC electrical characteristics behavior as function of time.

MPC5604P Microcontroller Data Sheet, Rev. 8

58

Freescale

V

IN

V

DD

V

IH

V

HYS

V

IL

PDIx = ‘1’

(GPDI register of SIUL)

PDIx = ‘0’

Figure 13. Input DC electrical characteristics definition

3.10.5 I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a V /V supply pair as

DD SS

described in Table 23.

Table 23. I/O supply segment

Supply segment

Package

1

2

3

4

5

6

7

144

pin8 – pin20 pin23 – pin38 pin39 – pin55 pin58 – pin68 pin73 – pin89 pin92 – pin125 pin128 – pin5

LQFP

100

pin15 – pin26 pin27 – pin38 pin41 – pin46 pin51 – pin61 pin64 – pin86 pin89 – pin10

—

LQFP

Table 24 provides the weight of concurrent switching I/Os.

In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain

below 100%.

Table 24. I/O weight

144 LQFP

Weight 3.3V

100 LQFP

Weight 3.3V

Pad

Weight 5V

NMI

1%

6%

1%

5%

1%

14%

—

1%

13%

12%

—

PAD[6]

PAD[49]

PAD[84]

PAD[85]

5%

4%

14%

9%

10%

7%

—

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

59

Table 24. I/O weight (continued)

144 LQFP

100 LQFP

Weight 5V Weight 3.3V

Pad

Weight 5V

Weight 3.3V

PAD[86]

MODO[0]

PAD[7]

9%

12%

4%

6%

8%

4%

9%

6%

7%

11%

5%

7%

11%

12%

13%

22%

24%

1%

—

11%

10%

9%

8%

—

10%

9%

8%

7%

—

PAD[36]

PAD[8]

5%

PAD[37]

PAD[5]

5%

PAD[39]

PAD[35]

PAD[87]

PAD[88]

PAD[89]

PAD[90]

PAD[91]

PAD[57]

PAD[56]

PAD[53]

PAD[54]

PAD[55]

PAD[96]

PAD[65]

PAD[67]

PAD[33]

PAD[68]

PAD[23]

PAD[69]

PAD[34]

PAD[70]

PAD[24]

PAD[71]

PAD[66]

PAD[25]

PAD[26]

5%

12%

9%

—

10%

15%

6%

—

8%

13%

14%

15%

25%

—

7%

11%

12%

13%

22%

—

13%

14%

15%

25%

27%

1%

—

1%

—

1%

—

1%

—

1%

—

1%

—

1%

—

1%

—

1%

—

1%

—

1%

MPC5604P Microcontroller Data Sheet, Rev. 8

60

Freescale

Table 24. I/O weight (continued)

144 LQFP

100 LQFP

Weight 5V Weight 3.3V

Pad

Weight 5V

Weight 3.3V

PAD[27]

PAD[28]

PAD[63]

PAD[72]

PAD[29]

PAD[73]

PAD[31]

PAD[74]

PAD[30]

PAD[75]

PAD[32]

PAD[76]

PAD[64]

PAD[0]

1%

—

1%

—

1%

—

1%

—

1%

—

1%

—

1%

—

1%

—

1%

—

1%

—

1%

23%

21%

—

1%

20%

18%

—

23%

21%

20%

19%

18%

17%

16%

15%

14%

13%

12%

11%

10%

1%

20%

18%

17%

16%

15%

14%

13%

12%

11%

10%

9%

PAD[1]

PAD[107]

PAD[58]

PAD[106]

PAD[59]

PAD[105]

PAD[43]

PAD[104]

PAD[44]

PAD[103]

PAD[2]

19%

—

16%

—

17%

—

15%

—

15%

—

13%

—

13%

—

12%

—

11%

—

10%

—

PAD[101]

PAD[21]

TMS

8%

10%

1%

16%

4%

9%

—

8%

1%

11%

3%

8%

—

1%

TCK

1%

PAD[20]

PAD[3]

16%

4%

11%

3%

PAD[61]

PAD[102]

9%

8%

11%

10%

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

61

Table 24. I/O weight (continued)

144 LQFP

100 LQFP

Weight 5V Weight 3.3V

Pad

Weight 5V

Weight 3.3V

PAD[60]

PAD[100]

PAD[45]

PAD[98]

PAD[46]

PAD[99]

PAD[62]

PAD[92]

VPP_TEST

PAD[4]

11%

12%

13%

1%

10%

11%

12%

1%

11%

—

10%

—

12%

—

10%

—

12%

—

11%

—

13%

—

11%

—

1%

14%

13%

—

1%

12%

11%

—

14%

13%

12%

11%

10%

9%

12%

11%

10%

9%

PAD[16]

PAD[17]

PAD[42]

PAD[93]

PAD[95]

PAD[18]

PAD[94]

PAD[19]

PAD[77]

PAD[10]

PAD[78]

PAD[11]

PAD[79]

PAD[12]

PAD[41]

PAD[47]

PAD[48]

PAD[51]

PAD[52]

PAD[40]

PAD[80]

PAD[9]

—

12%

—

10%

—

11%

—

10%

—

9%

10%

—

9%

—

8%

9%

8%

9%

—

8%

—

8%

7%

5%

4%

5%

6%

—

7%

6%

4%

5%

—

7%

6%

5%

4%

5%

4%

5%

9%

8%

10%

9%

11%

—

10%

—

PAD[81]

9%

MPC5604P Microcontroller Data Sheet, Rev. 8

62

Freescale

Table 24. I/O weight (continued)

144 LQFP

100 LQFP

Weight 5V Weight 3.3V

Pad

Weight 5V

Weight 3.3V

PAD[13]

PAD[82]

PAD[22]

PAD[83]

PAD[50]

PAD[97]

PAD[38]

PAD[14]

PAD[15]

10%

9%

8%

12%

—

11%

—

13%

—

12%

—

14%

—

12%

—

14%

15%

13%

9%

Table 25. I/O consumption

Conditions¹

Value

Symbol

C

Parameter

Unit

Min Typ Max

,2

I_SWTSLW

CC D Dynamic I/O current C_L= 25 pF

V_DD= 5.0 V ± 10%,

PAD3V5V = 0

—

20

16

29

17

mA

for SLOW

configuration

V_DD= 3.3 V ± 10%,

PAD3V5V = 1

(2)

I_SWTMED

CC D Dynamic I/O current C_L= 25 pF

for MEDIUM

V_DD= 5.0 V ± 10%,

PAD3V5V = 0

mA

configuration

V_DD= 3.3 V ± 10%,

PAD3V5V = 1

(2)

I_SWTFST

CC D Dynamic I/O current C_L= 25 pF

V_DD= 5.0 V ± 10%,

PAD3V5V = 0

110 mA

50

for FAST

configuration

V_DD= 3.3 V ± 10%,

PAD3V5V = 1

I_RMSSLW

CC D Root medium square C_L= 25 pF, 2 MHz

V_DD= 5.0 V ± 10%,

PAD3V5V = 0

—

2.3 mA

3.2

I/O current for SLOW

C_L= 25 pF, 4 MHz

configuration

C_L= 100 pF, 2 MHz

C_L= 25 pF, 2 MHz

C_L= 25 pF, 4 MHz

C_L= 100 pF, 2 MHz

6.6

V_DD= 3.3 V ± 10%,

PAD3V5V = 1

1.6

2.3

4.7

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

63

Table 25. I/O consumption (continued)

Conditions¹

Value

Symbol

C

Parameter

Unit

Min Typ Max

I_RMSMEDCC D Root medium square C_L= 25 pF, 13 MHz V_DD= 5.0 V ± 10%,

—

6.6 mA

I/O current for

MEDIUM

configuration

PAD3V5V = 0

C_L= 25 pF, 40 MHz

C_L= 100 pF, 13 MHz

13.4

18.3

5

C_L= 25 pF, 13 MHz V_DD= 3.3 V ± 10%,

PAD3V5V = 1

C_L= 25 pF, 40 MHz

8.5

11

C_L= 100 pF, 13 MHz

I_RMSFST

CC D Root medium square C_L= 25 pF, 40 MHz V_DD= 5.0 V ± 10%,

22

33

56

14

20

35

70

65

mA

I/O current for FAST

configuration

PAD3V5V = 0

C_L= 25 pF, 64 MHz

C_L= 100 pF, 40 MHz

C_L= 25 pF, 40 MHz V_DD= 3.3 V ± 10%,

PAD3V5V = 1

C_L= 25 pF, 64 MHz

C_L= 100 pF, 40 MHz

I_AVGSEG

SR D Sum of all the static V_DD= 5.0 V ± 10%, PAD3V5V = 0

I/O current within a

mA

V

_DD= 3.3 V ± 10%, PAD3V5V = 1

supply segment

V_DD= 3.3 V ± 10% / 5.0 V ± 10%, T_A= –40 to 125 °C, unless otherwise specified

Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.

1

2

3.11 Main oscillator electrical characteristics

The MPC5604P provides an oscillator/resonator driver.

Table 26. Main oscillator output electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)

Value

Symbol

C

Parameter

Unit

Min Max

f_OSCSR — Oscillator frequency

4

6.5

1

40 MHz

25 mA/V

g_m

—

P Transconductance

V_OSC

t_OSCSU

T Oscillation amplitude on XTAL pin

T Start-up time^1,2

—

V

8

ms

1

The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and

excessive capacitive loads can cause long start-up time.

2

Value captured when amplitude reaches 90% of XTAL

MPC5604P Microcontroller Data Sheet, Rev. 8

64

Freescale

Table 27. Main oscillator output electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)

Value

Symbol

C

Parameter

Unit

Min Max

f_OSC

S

R

— Oscillator frequency

P Transconductance

4

40 MHz

g_m

—

4

1

8

20 mA/V

V_OSC

t_OSCSU

T Oscillation amplitude on XTAL pin

T Start-up time^1,2

—

V

ms

1

The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and

excessive capacitive loads can cause long start-up time.

2

Value captured when amplitude reaches 90% of XTAL

Table 28. Input clock characteristics

Value

Symbol

Parameter

Unit

Min

Typ

Max

f_OSCSR Oscillator frequency

f_CLKSR Frequency in bypass

t_rCLKSR Rise/fall time in bypass

t_DCSR Duty cycle

4

—

50

40

64

MHz

ns

—

1

47.5

52.5

%

3.12 FMPLL electrical characteristics

Table 29. FMPLL electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Max

f_{ref_crystal}D PLL reference frequency range²

f_{ref_ext}

Crystal reference

4

40

MHz

f_PLLIN

D Phase detector input frequency range (after

pre-divider)

—

16

f_FMPLLOUTD Clock frequency range in normal mode

—

16

20

120

150

MHz

f_FREE

P Free-running frequency

Measured using clock

division — typically /16

t_CYC

f_LORL

D System clock period

—

Lower limit

Upper limit

—

1.6

24

20

1 / f_SYS

3.7

ns

D Loss of reference frequency window³

MHz

f_LORH

56

f_SCM

D Self-clocked mode frequency^4,5

150

MHz

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

65

Table 29. FMPLL electrical characteristics (continued)

Value

Symbol

C

Parameter

Short-term jitter¹⁰

Conditions¹

Unit

Min

Max

C_JITTERT CLKOUT period

jitter^6,7,8,9

f_SYSmaximum

Long-term jitter (avg. f_PLLIN= 16 MHz

4

4

% f_CLKOUT

ns

—

10

over 2 ms interval) (resonator), f_PLLCLKat

64 MHz, 4,000 cycles

t_lpll

t_dc

f_LCK

f_UL

f_CS

D PLL lock time ^{11, 12}

—

40

6

200

60

µs

D Duty cycle of reference

—

%

D Frequency LOCK range

D Frequency un-LOCK range

D Modulation depth

—

6

% f_SYS

-18

18

Center spread

Down spread

—

±0.25

0.5

—

±4.0¹³

8.0

70

f_DS

f_MOD

D Modulation frequency¹⁴

kHz

1

2

3

V_{DD_LV_CORx}= 1.2 V ±10%; V_SS= 0 V; T_A= –40 to 125 °C, unless otherwise specified

Considering operation with PLL not bypassed

“Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self-clocked

mode.

4

5

Self-clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside

the f_LORwindow.

f_VCOself clock range is 20–150 MHz. f_SCMrepresents f_SYSafter PLL output divider (ERFD) of 2 through 16 in

enhanced mode.

6

7

This value is determined by the crystal manufacturer and board design.

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum

f_SYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock

signal. Noise injected into the PLL circuitry via V_DDPLLand V_SSPLLand variation in crystal oscillator frequency

increase the C_JITTERpercentage for a given interval.

8

9

Proper PC board layout procedures must be followed to achieve specifications.

Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C_JITTERand

either f_CSor f_DS(depending on whether center spread or down spread modulation is enabled).

¹⁰Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.

¹¹This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for

this PLL, load capacitors should not exceed these limits.

¹²This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits

in the synthesizer control register (SYNCR).

¹³This value is true when operating at frequencies above 60 MHz, otherwise f_CSis 2% (above 64 MHz).

¹⁴Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.

MPC5604P Microcontroller Data Sheet, Rev. 8

66

Freescale

3.13 16 MHz RC oscillator electrical characteristics

Table 30. 16 MHz RC oscillator electrical characteristics

Value

Symbol

C

Parameter

Conditions

Unit

Min

Typ Max

f_RC

P RC oscillator frequency

T_A= 25 °C

—

16

—

5

MHz

%

_RCMVARP Fast internal RC oscillator variation over temperature and

supply with respect to f_RCat T_A= 25 °C in high-frequency

configuration

–5

_RCMTRIMT Post Trim Accuracy: The variation of the PTF¹from the

T_A= 25 °C

–1

—

1

%

16 MHz

_RCMSTEPT Fast internal RC oscillator trimming step

1.6

—

1

PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and

temperature

3.14 Analog-to-digital converter (ADC) electrical characteristics

The device provides a 10-bit successive approximation register (SAR) analog-to-digital converter.

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

67

Offset Error OSE

Gain Error GE

1023

1022

1021

1020

1019

1 LSB ideal = V

/ 1024

DD_ADC

1018

(2)

code out

7

(1)

6

5

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(5)

4

3

(3) Differential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer curve

(4)

(3)

2

1

1 LSB (ideal)

0

1

2

3

4

5

6

7

1017 1018 1019 1020 1021 1022 1023

(LSB

V

)

ideal

in(A)

Offset Error OSE

Figure 14. ADC characteristics and error definitions

3.14.1 Input impedance and ADC accuracy

To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor

with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as

possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it sources charge

during the sampling phase, when the analog signal source is a high-impedance source.

A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC

filtering may be limited according to the source impedance value of the transducer or circuit supplying the analog signal to be

measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal

(bandwidth) and the equivalent input impedance of the ADC itself.

MPC5604P Microcontroller Data Sheet, Rev. 8

68

Freescale

In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: C and C being

S

P2

substantially two switched capacitances, with a frequency equal to the ADC conversion rate, it can be seen as a resistive path

to ground. For instance, assuming a conversion rate of 1 MHz, with C +C equal to 3 pF, a resistance of 330 k is obtained

S

P2

(R = 1 / (fc × (C +C )), where fc represents the conversion rate at the considered channel). To minimize the error induced

EQ

S

P2

by the voltage partitioning between this resistance (sampled voltage on C +C ) and the sum of R + R , the external circuit

S

P2

S

F

must be designed to respect the Equation 4:

Eqn. 4

R + R

S

F

1

2

--------------------

V



 -- LSB

A

R

EQ

Equation 4 generates a constraint for external network design, in particular on resistive path.

EXTERNAL CIRCUIT

Filter

INTERNAL CIRCUIT SCHEME

V

DD

Channel

Sampling

Selection

Source

Current Limiter

R

AD

S

F

L

SW1

V

C

S

A

F

P1

P2

R_S: Source impedance

R_F: Filter resistance

C_F: Filter capacitance

R_L: Current limiter resistance

R_SW1: Channel selection switch impedance

_AD: Sampling switch impedance

R

C_P: Pin capacitance (two contributions, C_P1and C_P2

C_S: Sampling capacitance

)

Figure 15. Input equivalent circuit

A second aspect involving the capacitance network shall be considered. Assuming the three capacitances C , C and C are

F

P1

P2

initially charged at the source voltage V (refer to the equivalent circuit reported in Figure 15): A charge sharing phenomenon

A

is installed when the sampling phase is started (A/D switch closed).

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

69

Voltage Transient on C_S

V

CS

V

A

V <0.5 LSB

V

A2

1

2

₁< (R_SW+ R_AD) C_S<< T_S

V

A1

₂= R_L(C_S+ C_P1+ C_P2)

T

t

S

Figure 16. Transient behavior during sampling phase

In particular two different transient periods can be distinguished:

• A first and quick charge transfer from the internal capacitance C and C to the sampling capacitance C occurs (C

S

P1

P2

S

is supposed initially completely discharged): considering a worst case (since the time constant in reality would be

faster) in which C is reported in parallel to C (call C = C + C ), the two capacitances C and C are in series,

P2

P1

P

P1

P2

P

S

and the time constant is

Eqn. 5

C  C

P

S

--------------------

 



= R

+ R

1

SW

AD

C + C

P

S

Equation 5 can again be simplified considering only C as an additional worst condition. In reality, the transient is

S

faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time T

is always much longer than the internal time constant:

S

Eqn. 6



 R

+ R

  C « T

1

SW

AD

S

The charge of C and C is redistributed also on C , determining a new value of the voltage V on the capacitance

P1

P2

S

A1

according to Equation 7:

Eqn. 7

V

 C + C + C  = V  C + C



A1

S

P1

P2

A

P1

P2

•

A second charge transfer involves also C (that is typically bigger than the on-chip capacitance) through the resistance

F

R : again considering the worst case in which C and C were in parallel to C (since the time constant in reality

L

P2

S

P1

would be faster), the time constant is:

Eqn. 8



 R  C + C + C

P1 P2



2

L

S

MPC5604P Microcontroller Data Sheet, Rev. 8

70

Freescale

In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed

well before the end of sampling time T , a constraints on R sizing is obtained:

S

L

Eqn. 9

8.5   = 8.5  R  C + C + C   T

P1 P2 S

2

L

S

Of course, R shall be sized also according to the current limitation constraints, in combination with R (source

L

S

impedance) and R (filter resistance). Being C definitively bigger than C , C and C , then the final voltage V

F

P1 P2

S

A2

(at the end of the charge transfer transient) will be much higher than V . Equation 10 must be respected (charge

A1

balance assuming now C already charged at V ):

S

A1

Eqn. 10

V

 C + C + C + C  = V  C + V  C + C + C 

P1 P2 A1 P1 P2

A2

S

F

A

F

S

The two transients above are not influenced by the voltage source that, due to the presence of the R C filter, is not able to

F

provide the extra charge to compensate the voltage drop on C with respect to the ideal source V ; the time constant R C of

S

A

F F

the filter is very high with respect to the sampling time (T ). The filter is typically designed to act as anti-aliasing.

S

Analog Source Bandwidth (V )

A

T

f

2 R C (Conversion Rate vs. Filter Pole)

F F

C

Noise

 f (Anti-aliasing Filtering Condition)

F

0

2 f f (Nyquist)

0

C

f

0

f

Anti-Aliasing Filter (f = RC Filter pole)

Sampled Signal Spectrum (f = conversion Rate)

C

F

f

C

F

0

f

Figure 17. Spectral representation of input signal

Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f ),

0

F

according to the Nyquist theorem the conversion rate f must be at least 2f ; it means that the constant time of the filter is greater

C

0

than or at least equal to twice the conversion period (T ). Again the conversion period T is longer than the sampling time T ,

C

S

which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a

specific channel): in conclusion it is evident that the time constant of the filter R C is definitively much higher than the

F

sampling time T , so the charge level on C cannot be modified by the analog signal source during the time in which the

S

sampling switch is closed.

The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage

drop on C ; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled

S

voltage on C :

S

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

71

Eqn. 11

V

C

+ C + C

P2

----------- = -------------------------------------------------------

A

P1

F

V

C

+ C + C + C

A2

P1

P2 S

F

From this formula, in the worst case (when V is maximum, that is for instance 5 V), assuming to accept a maximum error of

A

half a count, a constraint is evident on C value:

F

Eqn. 12

C

 2048  C

F

S

3.14.2 ADC conversion characteristics

Table 31. ADC conversion characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

—

V_{SS_HV_ADV}

—

V_{DD_HV_ADV}

ADC0 and shared ADC0/1

analog input voltage^{2, 3}

V_INAN0SR

V

0

0.3

+ 0.3

—

V_{SS_HV_ADV}

—

V_{DD_HV_ADV}

V_INAN1SR

ADC1 analog input voltage^{2, 4}

V

1

0.3

+ 0.3

f_CK

SR — ADC clock frequency (depends

on ADC configuration)

3⁶

60

MHz

(The duty cycle depends on

AD_clk⁵frequency)

f_s

SR — Sampling frequency

—

1.53

—

MHz

ns

t_{ADC_S}

—

D Sample time⁷

f_ADC= 20 MHz,

INPSAMP = 3

125

f

_ADC= 9 MHz,

—

0.650

—

28.2

—

µs

INPSAMP = 255

t_{ADC_C}

—

P Conversion time⁸

f_ADC= 20 MHz⁹,

INPCMP = 1

t_{ADC_PU}SR — ADC power-up delay (time

needed for ADC to settle

—

1.5

exiting from software power

down; PWDN bit = 0)

10

C_S

—

D ADC input sampling

capacitance

—

2.5

pF

10

C_P1

C_P2

—

D ADC input pin capacitance 1

D ADC input pin capacitance 2

—

3

1

pF

MPC5604P Microcontroller Data Sheet, Rev. 8

72

Freescale

Table 31. ADC conversion characteristics (continued)

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

10

R_SW1

—

D Internal resistance of analog

source

V_{DD_HV_ADC}

5 V ± 10%

=

—

0.6

k

mA

V_{DD_HV_ADC}

3.3 V ± 10%

—

–5

—

3

2

5

10

R_AD

—

D Internal resistance of analog

source

—

I_INJ

T Input current injection

Current injection on

one ADC input,

different from the

converted one.

Remains within TUE

spec.

INL

CC P Integral non-linearity

No overload

—

–1.5

–1.0

—

±1

1.5

1.0

—

LSB

DNL CC P Differential non-linearity

OSE CC T Offset error

GE

CC T Gain error

—

±1

—

LSB

TUE CC P Total unadjusted error without

current injection

–2.5

2.5

TUE CC T Total unadjusted error with

current injection

—

–3

—

3

LSB

1

2

V_DD= 3.3 V to 3.6 V / 4.5 V to 5.5 V, T_A= –40 °C to T_{A MAX}, unless otherwise specified and analog input voltage

from V_{SS_HV_ADCx}to V_{DD_HV_ADCx}

V_AINxmay exceed V_{SS_HV_AD}and V_{DD_HV_AD}limits, remaining on absolute maximum ratings, but the results of the

conversion will be clamped respectively to 0x000 or 0x3FF.

.

3

4

5

6

7

Not allowed to refer this voltage to V_{DD_HV_ADV1}, V_{SS_HV_ADV1}

Not allowed to refer this voltage to V_{DD_HV_ADV0}, V_{SS_HV_ADV0}

AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.

When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which precision is lost.

During the sample time the input capacitance CS can be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within t_{ADC_S}. After the

end of the sample time t_{ADC_S}, changes of the analog input voltage have no effect on the conversion result. Values

for the sample clock t_{ADC_S}depend on programming.

8

9

This parameter includes the sample time t_{ADC_S}

.

20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.

¹⁰See Figure 15.

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

73

3.15 Flash memory electrical characteristics

Table 32. Program and erase specifications

Value

Symbol

C

Parameter

Unit

Initial

max²

Min

Typical¹

Max³

T_dwprogram

T_BKPRG

P

Double Word (64 bits) Program Time⁴

Bank Program (512 KB)^{4, 5}

—

22

50

1.65

0.21

500

33

µs

s

1.45

0.18

300

400

800

Bank Program (64 KB)^{4, 5}

4.10

5000

7500

s

T_16kpperase

T_32kpperase

T_128kpperase

16 KB Block Pre-program and Erase Time

32 KB Block Pre-program and Erase Time

128 KB Block Pre-program and Erase Time

ms

600

1300

1

Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to

change pending device characterization.

2

3

Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

The maximum program and erase times occur after the specified number of program/erase cycles. These maximum

values are characterized but not guaranteed.

4

5

Actual hardware programming times. This does not include software overhead.

Typical Bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will

require more than one pulse, adding a small overhead to total bank programming time (see Initial Max column).

Table 33. Flash memory module life

Value

Symbol

C

Parameter

Conditions

Unit

Min

Typ

P/E

C Number of program/erase cycles per block

for 16 KB blocks over the operating

temperature range (T_J)

—

100,000

—

cycles

P/E

C Number of program/erase cycles per block

for 32 KB blocks over the operating

temperature range (T_J)

—

10,000 100,000 cycles

C Number of program/erase cycles per block

for 128 KB blocks over the operating

temperature range (T_J)

1,000

100,000 cycles

Retention C Minimum data retention at 85 °C average Blocks with 0–1,000 P/E

20

10

5

—

years

ambient temperature¹

cycles

Blocks with 10,000 P/E

cycles

Blocks with 100,000 P/E

cycles

1

Ambient temperature averaged over duration of application, not to exceed recommended product operating

temperature range.

MPC5604P Microcontroller Data Sheet, Rev. 8

74

Freescale

Table 34. Flash memory read access timing

Symbol

C

Parameter

Conditions¹

Max value Unit

f_max

C

Maximum working frequency at given number of

wait states in worst conditions

2 wait states

0 wait states

66

18

MHz

1

V_DD= 3.3 V ± 10% / 5.0 V ± 10%, T_A= –40 to 125 °C, unless otherwise specified

3.16 AC specifications

3.16.1 Pad AC specifications

Table 35. Output pin transition times

Value

Symbol

C

Parameter

Conditions¹

Unit

Min Typ Max

t_tr

CC D Output transition time output pin²

C_L= 25 pF V_DD= 5.0 V ± 10%,

—

50

100

125

40

50

75

10

20

40

12

25

40

4

ns

SLOW configuration

PAD3V5V = 0

T

C_L= 50 pF

D

C_L= 100 pF

D

C_L= 25 pF V_DD= 3.3 V ± 10%,

PAD3V5V = 1

T

C_L= 50 pF

D

C_L= 100 pF

t_tr

CC D Output transition time output pin²

C_L= 25 pF V_DD= 5.0 V ± 10%,

MEDIUM configuration

PAD3V5V = 0

SIUL.PCRx.SRC = 1

T

C_L= 50 pF

D

T

C_L= 100 pF

C_L= 25 pF V_DD= 3.3 V ± 10%,

PAD3V5V = 1

SIUL.PCRx.SRC = 1

C_L= 50 pF

D

C_L= 100 pF

t_tr

CC D Output transition time output pin²

FAST configuration

C_L= 25 pF V_DD= 5.0 V ± 10%,

PAD3V5V = 0

SIUL.PCRx.SRC = 1

C_L= 50 pF

6

C_L= 100 pF

12

4

C_L= 25 pF V_DD= 3.3 V ± 10%,

PAD3V5V = 1

SIUL.PCRx.SRC = 1

C_L= 50 pF

7

C_L= 100 pF

12

4

3

t_SYM

CC T Symmetric transition time, same drive V_DD= 5.0 V ± 10%, PAD3V5V = 0

strength between N and P transistor

V_DD= 3.3 V ± 10%, PAD3V5V = 1

5

1

2

3

V_DD= 3.3 V ± 10% / 5.0 V ± 10%, T_A= –40 °C to T_{A MAX}, unless otherwise specified

C_Lincludes device and package capacitances (C_PKG< 5 pF).

Transition timing of both positive and negative slopes will differ maximum 50%

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

75

V_{DD_HV_IOx}/2

Pad

Data Input

Rising

Edge

Falling

Edge

Output

Delay

Output

Delay

V_OH

V_OL

Pad

Output

Figure 18. Pad output delay

3.17 AC timing characteristics

3.17.1 RESET pin characteristics

The MPC5604P implements a dedicated bidirectional RESET pin.

V

DD

V

DDMIN

V_RESET

V

IH

V

IL

device reset forced by V_RESET

device start-up phase

T_POR

Figure 19. Start-up reset requirements

MPC5604P Microcontroller Data Sheet, Rev. 8

76

Freescale

V_RESET

hw_rst

‘1’

V

DD

V

IH

V

IL

‘0’

filtered by

lowpass filter

unknown reset

state

filtered by

hysteresis

filtered by

lowpass filter

device under hardware reset

W

FRST

W

NFRST

Figure 20. Noise filtering on reset signal

Table 36. RESET electrical characteristics

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

V_IH

V_IL

SR P Input High Level CMOS

(Schmitt Trigger)

—

0.65V_DD

—

V_DD+0.4

V

SR P Input low Level CMOS

(Schmitt Trigger)

–0.4

0.1V_DD

—

0.35V_DD

—

V_HYSCC C Input hysteresis CMOS

(Schmitt Trigger)

V_OLCC P Output low level

Push Pull, I_OL= 2mA,

0.1V_DD

V_DD= 5.0 V ± 10%, PAD3V5V = 0

(recommended)

Push Pull, I_OL= 1mA,

—

0.1V_DD

0.5

V_DD= 5.0 V ± 10%, PAD3V5V = 1²

Push Pull, I_OL= 1mA,

V_DD= 3.3 V ± 10%, PAD3V5V = 1

(recommended)

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

77

Table 36. RESET electrical characteristics (continued)

Value

Symbol

C

Parameter

Conditions¹

Unit

Min

Typ

Max

t_tr

CC D Output transition time

output pin³

C_L= 25pF,

V_DD= 5.0 V ± 10%, PAD3V5V = 0

—

10

ns

MEDIUM configuration

C_L= 50pF,

—

20

40

12

25

40

—

1

V_DD= 5.0 V ± 10%, PAD3V5V = 0

C_L= 100pF,

V_DD= 5.0 V ± 10%, PAD3V5V = 0

C_L= 25pF,

V_DD= 3.3 V ± 10%, PAD3V5V = 1

—

C_L= 50pF,

—

V_DD= 3.3 V ± 10%, PAD3V5V = 1

C_L= 100pF,

V_DD= 3.3 V ± 10%, PAD3V5V = 1

—

W_FRSTSR P RESET input filtered

pulse

—

ns

W_NFRSTSR P RESET input not filtered

pulse

—

500

—

t_PORCC D Maximum delay before

internal reset is released

after all V_{DD_HV}reach

Monotonic V_{DD_HV}supply ramp

ms

nominal supply

|I_WPU

|

CC P Weak pull-up current

absolute value

V_DD= 3.3 V ± 10%, PAD3V5V = 1

V_DD= 5.0 V ± 10%, PAD3V5V = 0

10

—

150

250

µA

V

_DD= 5.0 V ± 10%, PAD3V5V = 1⁴

1

2

V_DD= 3.3 V ± 10% / 5.0 V ± 10%, T_A= –40 °C to T_{A MAX}, unless otherwise specified

This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of

device reference manual).

3

4

C_Lincludes device and package capacitance (C_PKG< 5 pF).

The configuration PAD3V5 = 1 when V_DD= 5 V is only transient configuration during power-up. All pads but RESET

and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

3.17.2 IEEE 1149.1 interface timing

Table 37. JTAG pin AC electrical characteristics

Value

No.

Symbol

C

Parameter

Conditions

Unit

Min Max

1

2

3

4

t_JCYC

CC D TCK cycle time

—

100

40

—

5

—

60

3

ns

t_JDC

CC D TCK clock pulse width (measured at V_{DD_HV_IOx}/2)

CC D TCK rise and fall times (40% – 70%)

CC D TMS, TDI data setup time

t_TCKRISE

t_{TMSS, TDIS}

t

—

MPC5604P Microcontroller Data Sheet, Rev. 8

78

Freescale

Table 37. JTAG pin AC electrical characteristics (continued)

Value

No.

Symbol

C

Parameter

Conditions

Unit

Min Max

5

6

t

_TMSH,t_TDIHCC D TMS, TDI data hold time

—

25

—

0

—

40

—

50

—

ns

t_TDOV

t_TDOI

t_TDOHZ

t_BSDV

CC D TCK low to TDO data valid

7

CC D TCK low to TDO data invalid

8

CC D TCK low to TDO high impedance

40

—

50

11

12

13

14

15

CC D TCK falling edge to output valid

t_BSDVZ

t_BSDHZ

t_BSDST

t_BSDHT

CC D TCK falling edge to output valid out of high impedance

CC D TCK falling edge to output high impedance

CC D Boundary scan input valid to TCK rising edge

CC D TCK rising edge to boundary scan input invalid

TCK

2

3

2

1

3

Figure 21. JTAG test clock input timing

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

79

TCK

4

5

TMS, TDI

6

8

7

TDO

Figure 22. JTAG test access port timing

MPC5604P Microcontroller Data Sheet, Rev. 8

80

Freescale

TCK

11

13

Output

Signals

12

Output

Signals

14

15

Input

Signals

Figure 23. JTAG boundary scan timing

3.17.3 Nexus timing

1

Table 38. Nexus debug port timing

Value

Typ

No.

Symbol

C

Parameter

Min

Unit

Max

1

2

3

4

5

t_MCYC

t_MDOV

CC D MCKO cycle time

32

—

6

ns

CC D MCKO low to MDO data valid²

t_MSEOVCC D MCKO low to MSEO data valid²

—

6

t_EVTOV

t_TCYC

CC D MCKO low to EVTO data valid²

—

6

CC D TCK cycle time

64³

—

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

81

1

Table 38. Nexus debug port timing (continued)

Value

Typ

No.

Symbol

C

Parameter

Min

Unit

Max

6

t_NTDIS

t_NTMSSCC D TMS data setup time

t_NTDIHCC D TDI data hold time

t_NTMSHCC D TMS data hold time

CC D TDI data setup time

6

—

35

—

ns

7

10

—

6

8

9

t_TDOV

t_TDOI

CC D TCK low to TDO data valid

CC D TCK low to TDO data invalid

1

2

3

All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal.

MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.

Lower frequency is required to be fully compliant to standard.

1

MCKO

2

3

4

MDO

MSEO

EVTO

Output Data Valid

Figure 24. Nexus output timing

TCK

EVTI

EVTO

5

Figure 25. Nexus event trigger and test clock timings

MPC5604P Microcontroller Data Sheet, Rev. 8

82

Freescale

TCK

6

7

TMS, TDI

9

8

TDO

Figure 26. Nexus TDI, TMS, TDO timing

3.17.4 External interrupt timing (IRQ pin)

1

Table 39. External interrupt timing

Value

No.

Symbol

C

Parameter

Conditions

Unit

Min

Max

1

2

3

t_IPWL

t_IPWH

t_ICYC

CC D IRQ pulse width low

CC D IRQ pulse width high

CC D IRQ edge to edge time²

—

4

—

t_CYC

4 + N ³

1

2

IRQ timing specified at f_SYS= 64 MHz and V_{DD_HV_IOx}= 3.0 V to 5.5 V, T_A= T_Lto T_H, and C_L= 200 pF

with SRC = 0b00.

Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

83

3

N = ISR time to clear the flag

IRQ

1

2

3

Figure 27. External interrupt timing

3.17.5 DSPI timing

1

Table 40. DSPI timing

Value

No. Symbol

C

Parameter

Conditions

Unit

Min

Max

1

t_SCKCC D DSPI cycle time

Master (MTFE = 0)

60

16

26

—

ns

Slave (MTFE = 0)

2

3

4

5

6

t_CSCCC D CS to SCK delay

t_ASCCC D After SCK delay

t_SDCCC D SCK duty cycle

—

ns

—

0.4 * t_SCK0.6 * t_SCKns

t_A

CC D Slave access time

SS active to SOUT valid

—

30

16

ns

t_DISCC D Slave SOUT disable time

SS inactive to SOUT high

impedance or invalid

7

8

9

t_PCSCCC D PCSx to PCSS time

t_PASCCC D PCSS to PCSx time

t_SUICC D Data setup time for inputs

—

13

35

4

—

ns

—

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

Master (MTFE = 0)

Slave

35

–5

4

10

t_HI

CC D Data hold time for inputs

ns

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

11

–5

MPC5604P Microcontroller Data Sheet, Rev. 8

84

Freescale

1

Table 40. DSPI timing (continued)

Value

No. Symbol

C

Parameter

Conditions

Unit

Min

Max

11 t_SUOCC D Data valid (after SCK edge) Master (MTFE = 0)

Slave

—

–2

6

12

36

12

—

ns

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

Master (MTFE = 0)

12

t_HOCC D Data hold time for outputs

ns

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

6

–2

1

All timing is provided with 50 pF capacitance on output, 1 ns transition time on input signal.

2

3

PCSx

1

4

SCK Output

(CPOL=0)

4

SCK Output

(CPOL=1)

10

9

Last Data

SIN

First Data

Data

12

11

Last Data

SOUT

Note: Numbers shown reference Table 40.

Figure 28. DSPI classic SPI timing – Master, CPHA = 0

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

85

PCSx

SCK Output

(CPOL=0)

10

SCK Output

(CPOL=1)

9

Data

First Data

Last Data

SIN

12

11

SOUT

Last Data

First Data

Note: Numbers shown reference Table 40.

Figure 29. DSPI classic SPI timing – Master, CPHA = 1

3

2

SS

1

4

SCK Input

(CPOL=0)

4

SCK Input

(CPOL=1)

5

11

12

Data

6

First Data

Last Data

SOUT

SIN

9

10

Data

Last Data

First Data

Note: Numbers shown reference Table 40.

Figure 30. DSPI classic SPI timing – Slave, CPHA = 0

MPC5604P Microcontroller Data Sheet, Rev. 8

86

Freescale

SS

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

11

5

6

12

Last Data

Data

SOUT

SIN

First Data

10

9

Last Data

First Data

Note: Numbers shown reference Table 40.

Figure 31. DSPI classic SPI timing – Slave, CPHA = 1

3

PCSx

4

1

2

SCK Output

(CPOL=0)

4

SCK Output

(CPOL=1)

9

10

SIN

First Data

12

Last Data

Data

11

SOUT

First Data

Data

Note: Numbers shown reference Table 40.

Figure 32. DSPI modified transfer format timing – Master, CPHA = 0

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

87

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

10

9

SIN

Last Data

First Data

Data

12

Data

11

First Data

Last Data

SOUT

Note: Numbers shown reference Table 40.

Figure 33. DSPI modified transfer format timing – Master, CPHA = 1

3

2

SS

1

SCK Input

(CPOL=0)

4

SCK Input

(CPOL=1)

12

11

6

5

First Data

9

Data

Last Data

10

SOUT

SIN

Last Data

First Data

Note: Numbers shown reference Table 40.

Figure 34. DSPI modified transfer format timing – Slave, CPHA = 0

MPC5604P Microcontroller Data Sheet, Rev. 8

88

Freescale

SS

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

11

5

6

12

Last Data

First Data

10

Data

SOUT

SIN

9

First Data

Last Data

Note: Numbers shown reference Table 40.

Figure 35. DSPI modified transfer format timing – Slave, CPHA = 1

8

7

PCSS

PCSx

Note: Numbers shown reference Table 40.

Figure 36. DSPI PCS strobe (PCSS) timing

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

89

4

Package characteristics

Package mechanical data

4.1

4.1.1

144 LQFP mechanical outline drawing

L

Figure 37. 144 LQFP package mechanical drawing (part 1)

MPC5604P Microcontroller Data Sheet, Rev. 8

90

Freescale

Figure 38. 144 LQFP package mechanical drawing (part 2)

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

91

4.1.2

100 LQFP mechanical outline drawing

Figure 39. 100 LQFP package mechanical drawing (part 1)

MPC5604P Microcontroller Data Sheet, Rev. 8

92

Freescale

Figure 40. 100 LQFP package mechanical drawing (part 2)

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

93

Figure 41. 100 LQFP package mechanical drawing (part 3)

MPC5604P Microcontroller Data Sheet, Rev. 8

94

Freescale

Table 41.

Dimensions

Symbol

mm

Typ

inches¹

Typ

Min

Max

Min

Max

A

A1

A2

b

—

0.050

1.350

0.170

0.090

15.800

13.800

—

1.600

0.150

1.450

0.270

0.200

16.200

14.200

—

0.0630

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

—

0.0020

0.0531

0.0067

0.0035

0.6220

0.5433

—

1.400

0.220

—

0.0551

0.0087

—

c

D

16.000

14.000

12.000

16.000

14.000

12.000

0.500

0.600

1.000

3.5°

0.6299

0.5512

0.4724

0.6299

0.5512

0.4724

0.0197

0.0236

0.0394

3.5°

D1

D3

E

15.800

13.800

—

16.200

14.200

—

0.6220

0.5433

—

0.6378

0.5591

—

E1

E3

e

—

L

0.450

—

0.750

—

0.0177

—

0.0295

—

L1

k

0.0°

7.0°

0.0°

7.0°

ccc²

0.08

0.0031

1

2

Values in inches are converted from millimeters (mm) and rounded to four decimal digits.

Tolerance

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

95

5

Ordering information

Figure 42. Commercial product code structure

Example code:

M

PC

56

0

4

P

G

F0

M

LQ

6

R

Qualification Status

Power Architecture Core

Automotive Platform

Core Version

Flash Size (core dependent)

Product

Optional Fields

Fab & Mask Revision

Temperature spec.

Package Code

Frequency

R = Tape & Reel (blank if Tray)

Qualification Status

M = MC status

S = Automotive qualified

P = PC status

Flash Size (z0 core)

3 = 384 KB

4 = 512 KB

Temperature spec.

V = –40 to 105 °C

M = –40 to 125 °C

Product

P = MPC560xP family

Package Code

LL = 100 LQFP

LQ = 144 LQFP

Automotive Platform

56 = Power Architecture in 90 nm

Optional fields

Core Version

0 = e200z0

E = Data Flash (blank if none)

F = FlexRay (blank if none)

G = Data Flash + FlexRay

Frequency

4 = 40 MHz

6 = 64 MHz

MPC5604P Microcontroller Data Sheet, Rev. 8

96

Freescale

Appendix A Abbreviations

Table A-1 lists abbreviations used in this document.

Table A-1. Abbreviations

Abbreviation

Meaning

CMOS

CPHA

CPOL

CS

Complementary metal–oxide–semiconductor

Clock phase

Clock polarity

Peripheral chip select

Device under test

DUT

ECC

Error code correction

Event out

EVTO

GPIO

MC

General purpose input/output

Modulus counter

MCKO

MCU

MDO

MSEO

MTFE

NPN

Message clock out

Microcontroller unit

Message data out

Message start/end out

Modified timing format enable

Negative-positive-negative

Non-volatile user options register

Post trimming frequency

Pulse width modulation

Resolution bandwidth

Serial communications clock

Serial data out

NVUSRO

PTF

PWM

RBW

SCK

SOUT

TCK

Test clock input

TDI

Test data input

TDO

Test data output

TMS

Test mode select

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

97

6

Document revision history

Table 42 summarizes revisions to this document.

Table 42. Revision history

Revision

Date

Substantive changes

Rev. 1

Rev. 2

Aug 2008 Initial release

Nov 2008 Table 5:

TDO and TDI pins (Port pins B[4:5] are single function pins.

Table 10, Table 11:

Thermal characteristics added.

Table 11, Table 12:

EMI testing specifications split into separate tables for Normal mode and Airbag mode;

data to be added in a later revision.

Table 16, Table 17, Table 19, Table 20:

Supply current specifications split into separate tables for Normal mode and Airbag mode;

data to be added in a later revision.

Table 21:

•

Values for I_OLand I_OH(in Conditions column) changed.

Max values for V_{OH_S}, V_{OH_M}, V_{OH_F}and V_{OH_SYM}deleted.

V_ILRmax value changed.

I_PURmin and max values changed.

Table 27:

Sensitivity value changed.

Table 30:

Most values in table changed.

Rev. 3

Feb 2009

•

Description of system requirements, controller characteristics and how controller

characteristics are guaranteed updated.

•

Electrical parameters updated.

EMI characteristics are now in one table; values have been updated.

ESD characteristics are now in one table.

Electrical parameters are identified as either system requirements or controller

characteristics. Method used to guarantee each controller characteristic is noted

in table.

•

AC Timings: 1149.1 (JTAG) Timing, Nexus Timing, External Interrupt Timing,

and DSPI Timing sections deleted

MPC5604P Microcontroller Data Sheet, Rev. 8

98

Freescale

Table 42. Revision history (continued)

Substantive changes

Revision

Date

Rev. 4

24-Jun-2009 Through all document:

– Replaced all “RESET_B” occurrences with “RESET” through all document.

– AC Timings: 1149.1 (JTAG) Timing, Nexus Timing, External Interrupt Timing, and

DSPI Timing sections inserted again.

– Electrical parameters updated.

–

Table 2

– Added row for Data Flash.

Table 3

– Added a footnote regarding the decoupling capacitors.

Table 5

– Removed the “other function“ column.

– Rearranged the contents.

Table 15

– Updated definition of Condition column.

Table 20

– merged in an unique Table the power consumption data related to "Maximum

mode" and "Airbag mode".

Table 22

– merged in an unique Table the power consumption data related to "Maximum

mode" and "Airbag mode".

Table 30

^{– Updated the parameter definition of}RCMVAR.

^{– Removed the condition definition of}RCMVAR.

Table 30

– Added t_{ADC_C}and TUE rows.

Table 31

– Added t_{ADC_C}and TUE rows.

– Removed R_sw2.

Table 34

– Added.

Table 29

– Updated and added footnotes.

Section 3.17.1, “RESET pin characteristics

– Replaces whole section.

Table 38

– Renamed the “Flash (KB)“ heading column in “Code Flash / Data Flash (EE) (KB)“

– Replaced the value of RAM from 32 to 36KB in the last four rows.

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

99

Table 42. Revision history (continued)

Substantive changes

Revision

Date

Rev. 5

06-Oct-2009 - Removed B[4] and B[5] rows from “Pin muxing” table and inserted them on “System

pins” table.

- Updated package pinout.

- Rewrote entirely section “Power Up/dpwn Sequencing“ section.

- Renamend “V_{DD_LV_PLL}“ and “V_{SS_LV_PLL}“ supply pins with respectively “V_{DD_LV_COR3}

and “V_{SS_LV_COR3”.}

“

- Added explicative figures on “Electrical characteristics” section.

- Updated “Thermal characteristics“ for 100-pin.

- Proposed two different configuration of “voltage regulator. - Inserted Power Up/Down

sequence.

- Added explicative figures on “DC Electrical characteristics”.

- Added “I/O pad current specification” section.

- Renamed the “Airbag mode” with “Typical mode“and updated the values on “supply

current” tables.

Rev. 6

12-Feb-2010 Inserted label of Y-axis in the “Independent ADC supply“ figure.

“Recommended Operating Conditions” tables:

Updated the T_Avalue

Moved the T_Jrow to “Absolute Maximum Ratings“ table.

Rewrite note 1 and 3

Inverted Min a Typ value of C_DEC2on ”Voltage Regulator Electrical Characteristics” table.

Removed an useless duplicate of “Voltage Regulator Electrical Characteristics“ table.

Inserted the name of C_Sinto “Input Equivalent Circuit“ figure.

Removed leakage Ivpp from datasheet.

Updated “Supply Current” tables.

Added note on “Output pin transition times“ table.

Updated ”Temperature Sensor Electrical Characteristics” table.

Updated “16 MHz RC Oscillator Electrical Characteristics” table.

Removed the note about the condition from “Flash read access timing“ table.

Removed the notes that assert the values need to be confirmed before validation.

MPC5604P Microcontroller Data Sheet, Rev. 8

100

Freescale

Table 42. Revision history (continued)

Substantive changes

Revision

Date

Rev. 7

07-Apr-2011 Formatting and editorial changes throughout

Removed all content referencing Junction Temperature Sensor

Section 1, “Introduction: changed title (was: Overview); reorganized contents

MPC5604P device comparison:

• ADC feature: changed “16 channels” to “15-channel”; added footnote to to indicate that

four channels are shared between the two ADCs

• removed MPC5602P column

• indicated that data flash memory is an optional feature

• indicated that FlexRay is an optional feature

• changed “dual channel” to “selectable single or dual channel support” in FlexRay

footnote

• updated “eTimer” feature

• updated footnote relative to “Digital power supply” feature

Updated MPC5604P block diagram

Added MPC5604P series block summary

Added Section 1.5, “Feature details

Section 2.1, “Package pinouts: removed alternate functions from pinout diagrams

Supply pins: updated descriptions of power supply pins (1.2 V)

System pins: updated table

Pin muxing: added rows “B[4]” and “B[5]

Section 3.3, “Absolute maximum ratings: added voltage specifications to titles of Figure 4

and Figure 5; in Table 7, changed row “V_{SS_HV}/ Digital Ground” to “V_SS/ Device

Ground”; updated symbols

Section 3.4, “Recommended operating conditions: added voltage specifications to titles

of Figure 6 and Figure 7

Recommended operating conditions (5.0 V), and Recommended operating conditions

(3.3 V): changed row “V_{SS_HV}/ Digital Ground” to “V_SS/ Device Ground”; updated

symbols

Updated Section 3.5.1, “Package thermal characteristics

Updated Section 3.6, “Electromagnetic interference (EMI) characteristics

Section 3.8.1, “Voltage regulator electrical characteristics: amended titles of Table 15 and

Table 17

Voltage regulator electrical characteristics (configuration without resistor on base) and

Voltage regulator electrical characteristics (configuration with resistor on base):

updated symbol and values for V_{DD_LV_REGCOR}

Low voltage monitor electrical characteristics: Updated V_{MLVDDOK_H}max value—was

1.15 V; is 1.145 V

Section 3.10, “DC electrical characteristics: reorganized contents

Updated Section 3.10.1, “NVUSRO register (includes adding

“NVUSRO[OSCILLATOR_MARGIN] field description” table

Supply current (5.0 V, NVUSRO[PAD3V5V] = 0): updated symbols

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

101

Table 42. Revision history (continued)

Substantive changes

Revision

Date

Rev. 7

(cont’d)

07-Apr-2011 Corrected parameter descriptions in DC electrical characteristics (3.3 V,

NVUSRO[PAD3V5V] = 1):

• V_{OL_F}—was “Fast, high level output voltage”; is “Fast, low level output voltage”

• V_{OL_SYM}—was “Symmetric, high level output voltage”; is “Symmetric, low level output

voltage”

Supply current (3.3 V, NVUSRO[PAD3V5V] = 1): updated symbols

Main oscillator output electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0):

replaced instances of EXTAL with XTAL

Main oscillator output electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1):

replaced instances of EXTAL with XTAL

FMPLL electrical characteristics: replaced “PLLMRFM” with “FMPLL” in table title;

updated conditions; removed f_sysrow; updated f_FMPLLOUTmin value

ADC conversion characteristics: updated symbols; added row t_{ADC_PU}

Flash memory read access timing: added footnote to “Conditions” column

Section 3.16.1, “Pad AC specifications: added Pad output delay diagram

In the range of figures “DSPI Classic SPI Timing — Master, CPHA = 0” to “DSPI PCS

Strobe (PCSS) Timing”: added note

Removed Orderable Part Number Summary table

Updated “Commercial product code structure” figure

Table A-1: Added abbreviations “DUT”, “NPN”, and “RBW”

MPC5604P Microcontroller Data Sheet, Rev. 8

102

Freescale

Table 42. Revision history (continued)

Substantive changes

Revision

Date

Rev. 8

23-May-2012 Section 1.5.4, “Flash memory: Changed “Data flash memory: 32-bit ECC” to “Data flash

memory: 64-bit ECC”

Figure 42 (Commercial product code structure), replaced "C = 60 MHz, 5 V" and "D = 60

MHz, 3.3 V" with respectively "C = 40 MHz, 5 V" and "D = 40 MHz, 3.3 V"

Table 7 (Absolute maximum ratings), updated TV_DDparameter, the minimum value to

3.0 V/s and the maximum value to 0.5 V/µs

Table 5 (Pin muxing), changed the description in the column "I/O direction" from "I/O" to

"O" for the following port pins:

A[10] with function B[0]

A[11] with function A[0]

A[11] with function A[2]

A[12] with function A[2]

A[12] with function B[2]

A[13] with function B[2]

C[7] with function A[1]

C[10] with function A[3]

C[15] with function A[1]

D[0] with function B[1]

D[10] with function A[0]

D[11] with function B[0]

D[13] with function A[1]

D[14] with function B[1]

Updated Section 3.8.1, “Voltage regulator electrical characteristics

Added Table 25 (I/O consumption)

Section 3.10, DC electrical characteristics:

deleted references to “oscillator margin”

deleted subsection “NVUSRO[OSCILLATOR_MARGIN] field description”

Table 19 (DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)), added IPU row

for RESET pin

Table 21 (DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)), added IPU row

for RESET pin

Table 31 (ADC conversion characteristics), added V_INANentry

Removed “Order codes” table

MPC5604P Microcontroller Data Sheet, Rev. 8

Freescale

103

Information in this document is provided solely to enable system and software

implementers to use Freescale products. There are no express or implied copyright

licenses granted hereunder to design or fabricate any integrated circuits based on the

information in this document.

How to Reach Us:

Home Page:

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Freescale reserves the right to make changes without further notice to any products

herein. Freescale makes no warranty, representation, or guarantee regarding the

suitability of its products for any particular purpose, nor does Freescale assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or incidental

damages. “Typical” parameters that may be provided in Freescale data sheets and/or

specifications can and do vary in different applications, and actual performance may

vary over time. All operating parameters, including “typicals,” must be validated for

each customer application by customer’s technical experts. Freescale does not convey

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Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire,

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Expert, QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks of

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QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsic

are trademarks of Freescale Semiconductor, Inc. All other product or service names

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service marks licensed by Power.org.

Document Number: MPC5604P

Rev. 8

07/2012


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