935323737557 [NXP]
Power Supply Support Circuit;
| 型号： | 935323737557 |
| 厂家： | 
NXP |
| 描述： | Power Supply Support Circuit |
| 文件： | 总128页 (文件大小：2538K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MMPF0100Z
Rev. 12.0, 8/2016
NXP Semiconductors
Data sheet: Advance Information
14 channel configurable power
management integrated circuit
PF0100Z
Automotive
The SMARTMOS PF0100Z AEC Q100 grade 2 automotive power management
integrated circuit (PMIC) provides a highly programmable/ configurable
architecture, with fully integrated power devices and minimal external
components. With up to six buck converters, six linear regulators, RTC supply,
and coin-cell charger, the PF0100Z can provide power for a complete system,
including applications processors, memory, and system peripherals, in a wide
range of applications. With on-chip one time programmable (OTP) memory, the
PF0100Z is available in pre-programmed standard versions, or non-
programmed to support custom programming. The PF0100Z is especially suited
to the i.MX 6 family of devices and is supported by full system level reference
designs, and pre-programmed versions of the device.
POWER MANAGEMENT
ES SUFFIX (WF-TYPE)
98ASA00589D
56 QFN 8X8
Features:
Applications:
• Four to six buck converters, depending on configuration
• GPS
• Auto infotainment
•
•
Single/dual phase/ parallel options
DDR termination tracking mode option
• Heads up display (HUD)
• Rear displays
• Digital instrumentation cluster (DIC)
• Boost regulator to 5.0 V output
• Six general purpose linear regulators
• Programmable output voltage, sequence, and timing
• OTP (one time programmable) memory for device configuration
• Coin cell charger and RTC supply
• DDR termination reference voltage
• Power control logic with processor interface and event detection
• I2C control
• Individually programmable on, off, and standby modes
PF0100Z
i.MX 6X
VREFDDR
DDR MEMORY
INTERFACE
DDR Memory
SW4
1000 mA
SW3A/B
2500 mA
SW1A/B
2500 mA
Processor Core
Voltages
SW1C
2000 mA
External AMP
Microphones
Speakers
SW2
2000 mA
SATA - FLASH
SD-MMC/
NAND Mem.
SATA
HDD
NAND
- NOR
SWBST
600 mA
Interfaces
Audio
Codec
Parallel control/GPIOS
I2C Communication
Control Signals
I2C Communication
Sensors
VGEN1
100 mA
Camera
Camera
VGEN2
250 mA
GPS
MIPI
uPCIe
WAM
GPS
MIPI
VGEN3
100 mA
VGEN4
350 mA
HDMI
LDVS Display
VGEN5
100 mA
USB
Ethernet
CAN
LICELL
Charger
VGEN6
200 mA
Main Supply
2.8 – 4.5 V
COINCELL
Front USB
POD
Rear Seat
Infotaiment
Rear USB
POD
Cluster/HUD
Figure 1. Simplified application diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© 2016 NXP B.V.
Table of Contents
1
2
3
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5
6
3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.1 General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.2 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3.1 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3.2 Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional block requirements and behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.1 Device start-up configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.2 One time programmability (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1.3 OTP prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.4 Reading OTP fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.5 Programming OTP fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2 16 MHz and 32 kHz clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2.1 Clock adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3 Bias and references block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3.1 Internal core voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3.2 VREFDDR voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.1 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.2 State machine flow summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4.3 Power tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.4 Buck regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.4.5 Boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.4.6 LDO regulators description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.4.7 VSNVS LDO/switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.5 Control interface I2C block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.5.1 I2C device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.5.2 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.5.3 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.5.4 Interrupt bit summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.5.5 Specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.5.6 Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5
6
PF0100Z
2
NXP Semiconductors
7
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7.1.1 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7.1.2 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.2 PF0100Z layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.2.1 General board recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.2.2 Component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.2.3 General routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.2.4 Parallel routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7.2.5 Switching regulator layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7.3 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7.3.1 Rating data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7.3.2 Estimation of junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.1 Packaging dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Reference section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8
9
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10.1 Document changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
PF0100Z
NXP Semiconductors
3
ORDERABLE PARTS
1
Orderable parts
The PF0100Z is available with both pre-programmed and non-programmed OTP memory configurations. The non-programmed device
uses “NP” as the programming code. The pre-programmed devices are identified using the program codes from Table 1, which also list
the associated NXP reference designs where applicable. Details of the OTP programming for each device can be found in Table 9.
Table 1. Orderable part variations
Temperature (T )
Part Number
Package
Programming
Reference designs
MCIMX6QAICPU1
Notes
A
MMPF0100NPAZES
NP
MCIMX6SAICPU1
MCIMX6DLAICPU1
(1), (2), (3)
MCIMX6Q-SDP
MCIMX6Q-SDB
MCIMX6DL-SDP
MMPF0100F0AZES
F0
56 QFN ES, 8x8 mm
0.5 mm pitch WF-Type
(wettable flank)
-40 °C to 105 °C
(1), (2)
MMPF0100F6AZES
MMPF0100F8AZES
MMPF0100F9AZES
MMPF0100FAAZES
F6
F8
F9
FA
-
-
MCIMX6QPlusAICPU3
-
(1), (2), (3)
Notes
1. For tape and reel add an R2 suffix to the part number.
2. These reference designs use the default startup configuration (VDDOTP = VCOREDIG), which is available on any OTP programmed part.
3. SW2 can support an output current rating of 2.5 A in NP, F9 and FA versions when SW2ILIM=0
1.1
PF0100Z version differences
PF0100AZ is an improved version of the PF0100Z power management IC. Table 2 summarizes the difference between the two versions
and should be referred to when migrating from the PF0100Z to the PF0100AZ.
Table 2. Differences between PF0100Z and PF0100AZ
Description
PF0100Z
PF0100AZ
Reading SILICON REV register at address 0x03 will Reading SILICON REV register at address 0x03 will
return 0x11. DEVICEID register at address 0x00 will return 0x21. DEVICEID register at address 0x00 will
Version identification
VSNVS current limit
read 0x10 in PF0100Z and PF0100AZ
read 0x10 in PF0100Z and PF0100AZ
VSNVS current limit increased in the PF0100AZ. see VSNVS LDO/switch
In the PF0100Z, FUSE_POR1, FUSE_POR2, and
FUSE_POR3 bits are XOR’ed into the
OTP_FUSE_PORx registersetting during OTP FUSE_POR_XOR bit. The FUSE_POR_XOR bit
In the PF0100AZ, the XOR function is removed. It is
required to set FUSE_POR1, FUSE_POR2, and
FUSE_POR3 bits during OTP programming.
programming
has to be 1 for fuses to be loaded during startup.
This can be achieved by setting any one or all of the
FUSE_PORx bits during OTP programming.
Erratum ER19 applicable to PF0100Z. Applications
expecting to operate in the conditions mentioned in
ER19 need to implement an external workaround to
overcome the problem. Refer to the product errata
for details
Errata ER19 fixed in PF0100AZ. External
workaround not required
Erratum ER19
Erratum ER20
Erratum ER20 applicable to PF0100Z
Erratum ER22 applicable to PF0100Z
-40 °C to 85 °C
Errata ER20 fixed in PF0100AZ
Errata ER22 fixed in PF0100AZ. Workaround not
required
Erratum ER22
Ambient operating temperature
-40 °C to 105 °C
PF0100Z
4
NXP Semiconductors
INTERNAL BLOCK DIAGRAM
2
Internal block diagram
SW1FB
VGEN1
100 mA
VIN1
PF0100Z
SW1AIN
VGEN1
O/P
Drive
SW1A/B
Single/Dual
2500 mA
Buck
SW1ALX
VGEN2
250 mA
VGEN2
SW1BLX
O/P
Drive
SW1BIN
VIN2
VGEN3
100 mA
VGEN3
SW1CLX
O/P
Drive
SW1C
2000 mA
Buck
SW1CIN
VGEN4
350 mA
VGEN4
SW1CFB
Core Control logic
SW1VSSSNS
VIN3
VGEN5
100 mA
VGEN5
SW2LX
Initialization State Machine
SW2
2000 mA
Buck
O/P
Drive
SW2IN
SW2IN
SW2FB
VGEN6
200 mA
VGEN6
Supplies
Control
OTP
SW3AFB
SW3AIN
SW3ALX
O/P
Drive
VDDOTP
VDDIO
SW3A/B
Single/Dual
DDR
2500 mA
Buck
CONTROL
I2C
Interface
SW3BLX
SW3BIN
O/P
Drive
SCL
SDA
DVS CONTROL
SW3BFB
DVS Control
SW3VSSSNS
SW4FB
SW4
1000 mA
Buck
SW4IN
O/P
Drive
I2C Register
map
SW4LX
Trim-In-Package
VCOREDIG
VCOREREF
GNDREF1
Reference
Generation
SWBSTLX
Clocks and
resets
SWBST
600 mA
Boost
O/P
Drive
VCORE
SWBSTIN
SWBSTFB
GNDREF
VREFDDR
VINREFDDR
Clocks
32 kHz and 16 MHz
VHALF
VIN
Best
of
Supply
Li Cell
Charger
LICELL
VSNVS
Figure 2. Simplified internal block diagram
PF0100Z
NXP Semiconductors
5
PIN CONNECTIONS
3
Pin connections
3.1
Pinout diagram
56 55 54 53 52 51 50 49 48 47 46 45 44 43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
INTB
1
2
3
4
5
6
7
8
9
LICELL
SDWNB
VGEN6
RESETBMCU
STANDBY
ICTEST
VIN3
VGEN5
SW3AFB
SW3AIN
SW3ALX
SW3BLX
SW3BIN
SW3BFB
SW3VSSSNS
VREFDDR
VINREFDDR
VHALF
SW1FB
SW1AIN
EP
SW1ALX
SW1BLX
SW1BIN 10
SW1CLX 11
SW1CIN 12
SW1CFB 13
SW1VSSSNS 14
15 16 17 18 19 20 21 22 23 24 25 26 27 28
Figure 3. Pinout diagram
PF0100Z
6
NXP Semiconductors
PIN CONNECTIONS
3.2
Pin definitions
Table 3. PF0100Z pin definitions
Pin
function
Pin number
Pin name
Max rating
Type
Definition
Open drain interrupt signal to processor
1
2
INTB
O
O
3.6 V
3.6 V
Digital
Digital
SDWNB
Open drain signal to indicate an imminent system shutdown
Open drain reset output to processor. Alternatively can be used as a power
good output.
3
4
5
RESETBMCU
STANDBY
ICTEST
O
I
3.6 V
3.6 V
7.5 V
Digital
Digital
Standby input signal from processor
Digital/
Analog
I
Reserved pin. Connect to GND in application.
Output voltage feedback for SW1A/B. Route this trace separately from the
high current path and terminate at the output capacitance.
6
7
SW1FB (5)
SW1AIN (5)
I
I
3.6 V
4.8 V
Analog
Analog
Input to SW1A regulator. Bypass with at least a 4.7 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
8
9
SW1ALX (5)
SW1BLX (5)
O
O
4.8 V
4.8 V
Analog
Analog
Regulator 1A switch node connection
Regulator 1B switch node connection
Input to SW1B regulator. Bypass with at least a 4.7 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
10
11
12
SW1BIN (5)
SW1CLX (5)
SW1CIN (5)
I
O
I
4.8 V
4.8 V
4.8 V
Analog
Analog
Analog
Regulator 1C switch node connection
Input to SW1C regulator. Bypass with at least a 4.7 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
Output voltage feedback for SW1C. Route this trace separately from the
high current path and terminate at the output capacitance.
13
14
SW1CFB (5)
I
3.6V
-
Analog
GND
Ground reference for regulators SW1ABC. It is connected externally to
GNDREF through a board ground plane.
SW1VSSSNS
GND
Ground reference for regulators SW2 and SW4. It is connected externally to
GNDREF, via board ground plane.
15
16
17
18
19
GNDREF1
VGEN1
VIN1
GND
-
GND
O
I
2.5 V
3.6 V
2.5 V
3.6 V
Analog
Analog
Analog
Analog
VGEN1 regulator output, Bypass with a 2.2 μF ceramic output capacitor.
VGEN1, 2 input supply. Bypass with a 1.0 μF decoupling capacitor as close
to the pin as possible.
VGEN2
SW4FB (5)
O
I
VGEN2 regulator output, Bypass with a 4.7 μF ceramic output capacitor.
Output voltage feedback for SW4. Route this trace separately from the high
current path and terminate at the output capacitance.
Input to SW4 regulator. Bypass with at least a 4.7 μF ceramic capacitor and
a 0.1 μF decoupling capacitor as close to the pin as possible.
20
SW4IN (5)
I
4.8 V
Analog
21
22
23
SW4LX (5)
SW2LX (5)
SW2IN (5)
O
O
I
4.8 V
4.8 V
4.8 V
Analog
Analog
Analog
Regulator 4 switch node connection
Regulator 2 switch node connection
Input to SW2 regulator. Connect pin 23 together with pin 24 and bypass with
at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as
close to these pins as possible.
24
SW2IN (5)
I
4.8 V
Analog
Output voltage feedback for SW2. Route this trace separately from the high
current path and terminate at the output capacitance.
25
26
27
SW2FB (5)
VGEN3
VIN2
I
O
I
3.6 V
3.6 V
3.6 V
Analog
Analog
Analog
VGEN3 regulator output. Bypass with a 2.2 μF ceramic output capacitor.
VGEN3,4 input. Bypass with a 1.0 μF decoupling capacitor as close to the
pin as possible.
28
29
VGEN4
VHALF
O
I
3.6 V
3.6 V
Analog
Analog
VGEN4 regulator output, Bypass with a 4.7 μF ceramic output capacitor.
Half supply reference for VREFDDR
PF0100Z
NXP Semiconductors
7
PIN CONNECTIONS
Table 3. PF0100Z pin definitions (continued)
Pin
Pin number
Pin name
Max rating
Type
Definition
function
VREFDDR regulator input. Bypass with at least 1.0 μF decoupling capacitor
30
31
32
VINREFDDR
VREFDDR
I
3.6 V
3.6 V
-
Analog
Analog
GND
as close to the pin as possible.
O
VREFDDR regulator output
Ground reference for the SW3 regulator. Connect to GNDREF externally via
the board ground plane.
SW3VSSSNS
GND
Output voltage feedback for SW3B. Route this trace separately from the
high current path and terminate at the output capacitance.
33
34
SW3BFB (5)
SW3BIN (5)
I
I
3.6 V
4.8 V
Analog
Analog
Input to SW3B regulator. Bypass with at least a 4.7 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
35
36
SW3BLX (5)
SW3ALX (5)
O
O
4.8 V
4.8 V
Analog
Analog
Regulator 3B switch node connection
Regulator 3A switch node connection
Input to SW3A regulator. Bypass with at least a 4.7 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
37
SW3AIN (5)
I
4.8 V
Analog
Output voltage feedback for SW3A. Route this trace separately from the
high current path and terminate at the output capacitance.
38
39
40
SW3AFB (5)
VGEN5
VIN3
I
O
I
3.6 V
3.6 V
4.8 V
Analog
Analog
Analog
VGEN5 regulator output. Bypass with a 2.2 μF ceramic output capacitor.
VGEN5, six input. Bypass with a 1.0 μF decoupling capacitor as close to the
pin as possible.
41
42
43
VGEN6
LICELL
VSNVS
O
I/O
O
3.6 V
3.6 V
3.6 V
Analog
Analog
Analog
VGEN6 regulator output. By pass with a 2.2 μF ceramic output capacitor.
Coin cell supply input/output
LDO or coin cell output to processor
Boost regulator feedback. Connect this pin to the output rail close to the
load. Keep this trace away from other noisy traces and planes.
44
SWBSTFB (5)
I
5.5 V
Analog
Input to SWBST regulator. Bypass with at least a 2.2 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
45
46
47
SWBSTIN (5)
SWBSTLX (5)
VDDOTP
I
O
I
4.8 V
7.5 V
Analog
Analog
SWBST switch node connection
Digital &
Analog
10 V(4)
Supply to program OTP fuses
48
49
50
51
52
53
54
55
56
GNDREF
VCORE
VIN
GND
-
GND
Ground reference for the main band gap regulator.
Analog core supply
O
I
3.6 V
4.8 V
1.5 V
1.5 V
3.6 V
3.6 V
3.6 V
3.6 V
Analog
Analog
Analog
Analog
Digital
Digital
Analog
Digital
Main chip supply
VCOREDIG
VCOREREF
SDA
O
O
I/O
I
Digital core supply
Main band gap reference
I2C data line (open drain)
I2C clock
SCL
VDDIO
I
Supply for I2C bus
PWRON
I
Power on/off from processor
Expose pad. Functions as ground return for buck regulators. Tie this pad to
the inner and external ground planes through vias to allow effective thermal
dissipation.
-
EP
GND
-
GND
Notes
4. 10 V Maximum voltage rating during OTP fuse programming. 7.5 V Maximum DC voltage rated otherwise.
5. Unused switching regulators should be connected as follows: Pins SWxLX and SWxFB should be unconnected and pin SWxIN should be
connected to VIN with a 0.1 μF bypass capacitor.
PF0100Z
8
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
4
General product characteristics
4.1
Absolute maximum ratings
Table 4. Absolute maximum ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause malfunction or permanent damage
to the device. The detailed maximum voltage rating per pin can be found in the pin list section.
Symbol
Description
Value
Unit
Notes
Electrical ratings
V
Main input supply voltage
-0.3 to 4.8
-0.3 to 10
-0.3 to 3.6
V
V
V
IN
V
OTP programming input supply voltage
Coin cell voltage
DDOTP
V
LICELL
ESD ratings
Human body model
VSNVS pin
(6)
V
±1800
±2000
±500
V
ESD
All other pins
Charge device model
Notes
6. ESD testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM),
robotic (CZAP = 4.0 pF).
PF0100Z
NXP Semiconductors
9
GENERAL PRODUCT CHARACTERISTICS
4.2
Thermal characteristics
Table 5. Thermal ratings
Symbol
Description (rating)
Min.
Max.
Unit
Notes
Thermal ratings
Ambient operating temperature range
TA
-40
-40
85
105
°C
PF0100Z
PF0100AZ
(7)
TJ
Operating junction temperature range
Storage temperature range
-40
-65
–
125
150
°C
°C
°C
TST
(8)(9)
TPPRT
Peak package reflow temperature
Note 9
QFN56 thermal resistance and package dissipation ratings
Junction to ambient
Natural convection
Four layer board (2s2p)
Eight layer board (2s6p)
(10)(11)(12)
(10)(12)
RθJA
°C/W
°C/W
–
–
28
15
Junction to ambient (at 200 ft/min)
RθJMA
Four layer board (2s2p)
–
–
–
22
10
(13)
(14)
RθJB
Junction to board
°C/W
°C/W
RΘJCBOTTOM Junction to case bottom
1.2
Junction to package top
(15)
–
2.0
°C/W
ΨJT
Natural convection
Notes
7. Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See Table 6 for
thermal protection features.
8. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a
malfunction or permanent damage to the device.
9. NXP’s package reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For peak package reflow temperature and
moisture sensitivity levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable
parts, and review parametrics.
10. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
11. The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5.
12. Per JEDEC JESD51-6 with the board horizontal.
13. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the
board near the package.
14. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
15. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-
2. When the Greek letter (Ψ) is not available, the thermal characterization parameter is written as Psi-JT.
4.2.1 Power dissipation
During operation, the temperature of the die should not exceed the operating junction temperature noted in Table 5. To optimize the
thermal management and to avoid overheating, the PF0100Z provides thermal protection. An internal comparator monitors the die
temperature. Interrupts THERM110I, THERM120I, THERM125I, and THERM130I are generated when the respective thresholds specified
in Table 6 are crossed in either direction. The temperature range can be determined by reading the THERMxxxS bits in register
INTSENSE0.
In the event of excessive power dissipation, thermal protection circuitry shuts down the PF0100Z. This thermal protection acts above the
thermal protection threshold listed in Table 6. To avoid any unwanted power downs resulting from internal noise, the protection is
debounced for 8.0 ms. This protection should be considered as a fail-safe mechanism and therefore the system should be configured so
this protection is not tripped under normal conditions.
PF0100Z
10
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
Table 6. Thermal protection thresholds
Parameter
Min.
Typ.
Max.
Units
Notes
Thermal 110 °C threshold (THERM110)
Thermal 120 °C threshold (THERM120)
Thermal 125 °C threshold (THERM125)
Thermal 130 °C threshold (THERM130)
Thermal warning hysteresis
100
110
115
120
2.0
110
120
125
130
–
120
130
135
140
4.0
°C
°C
°C
°C
°C
°C
Thermal protection threshold
130
140
150
4.3
Electrical characteristics
4.3.1 General Specifications
Table 7. General PMIC Static Characteristics
PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 2.8 V to 4.5 V, VDDIO = 1.7 V to 3.6 V, typical external component
values and full load current range, unless otherwise noted.
Pin name
Parameter
Load condition
Min.
Max.
Unit
VIL
VIH
VOL
VOH
VIL
–
0.0
0.8 * VSNVS
0.0
0.2 * VSNVS
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
PWRON
–
3.6
-2.0 mA
0.4
RESETBMCU
SCL
Open drain
0.7* VIN
0.0
VIN
–
0.2 * VDDIO
VIH
VIL
–
0.8 * VDDIO
0.0
3.6
0.2 * VDDIO
3.6
–
VIH
VOL
VOH
VOL
VOH
VOL
VOH
VIL
–
0.8 * VDDIO
0.0
SDA
-2.0 mA
0.4
Open drain
0.7*VDDIO
0.0
VDDIO
0.4
-2.0 mA
INTB
Open drain
0.7* VIN
0.0
VIN
-2.0 mA
0.4
SDWNB
STANDBY
VDDOTP
Open drain
0.7* VIN
0.0
VIN
–
–
–
–
0.2 * VSNVS
3.6
VIH
VIL
0.8 * VSNVS
0.0
0.3
VIH
1.1
1.7
PF0100Z
NXP Semiconductors
11
GENERAL PRODUCT CHARACTERISTICS
4.3.2 Current consumption
The current consumption of the individual blocks is described in detail throughout this specification. For convenience, a summary table
follows for standard use cases.
Table 8. Current consumption summary
PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VDDIO = 1.7 V to 3.6 V, LICELL = 1.8 V to 3.3 V,
VSNVS = 3.0 V, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V,
VDDIO = 3.3 V, LICELL = 3.0 V, VSNVS = 3.0 V and 25 °C, unless otherwise noted.
Mode
PF0100Z conditions
VSNVS from LICELL
All other blocks off
VIN = 0.0 V
System conditions
Typ.
Max.
Unit
Notes
(16),(18),
(21)
Coin Cell
No load on VSNVS
4.0
7.0
μA
VSNVSVOLT[2:0] = 110
VSNVS from VIN or LICELL
Wake-up from PWRON active
32 k RC on
All other blocks off
VIN ≥ UVDET
Off
(17),(18)
(17),(18)
No load on VSNVS, PMIC able to wake-up
No load on VSNVS, PMIC able to wake-up
16
17
21
25
μA
μA
MMPF0100Z
VSNVS from VIN or LICELL
Wake-up from PWRON active
32 k RC on
Off
MMPF0100AZ
All other blocks off
VIN ≥ UVDET
VSNVS from VIN
Wake-up from PWRON active
Trimmed reference active
SW3A/B PFM
Trimmed 16 MHz RC off
32 k RC on
No load on VSNVS. DDR memories in self
refresh
(18)
Sleep
μA
VREFDDR disabled
T
A = -40 °C to 85 °C
122
122
220
250
TA = -40 °C to 105 °C (PF0100AZ Only)
VSNVS from either VIN or LICELL
SW1A/B combined in PFM
SW1C in PFM
SW2 in PFM
SW3A/B combined in PFM
SW4 in PFM
297
297
450 (19)
No load on VSNVS. Processor enabled in
low power mode. All rails powered on
except boost (load = 0 mA)
Standby
MMPF0100Z
(18)
μA
1000 (20)
SWBST off
Trimmed 16 MHz RC enabled
Trimmed reference active
VGEN1-6 enabled
VREFDDR enabled
PF0100Z
12
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
Table 8. Current consumption summary (continued)
PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VDDIO = 1.7 V to 3.6 V, LICELL = 1.8 V to 3.3 V,
VSNVS = 3.0 V, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V,
VDDIO = 3.3 V, LICELL = 3.0 V, VSNVS = 3.0 V and 25 °C, unless otherwise noted.
VSNVS from either VIN or LICELL
SW1A/B combined in PFM
SW1C in PFM
SW2 in PFM
SW3A/B combined in PFM
SW4 in PFM
SWBST off
Trimmed 16 MHz RC enabled
Trimmed reference active
VGEN1-6 enabled
VREFDDR enabled
No load on VSNVS. Processor enabled in
low power mode. All rails powered on
except boost (load = 0 mA)
Standby
MMPF0100AZ
(18)
μA
T
T
A = -40 °C to 85 °C
A = -40 °C to 105 °C
297
297
450
550
Notes
16. Refer to Figure 4 for coin cell mode characteristics over temperature.
17. When VIN is below the UVDET threshold, in the range of 1.8 V ≤ VIN < 2.65 V, the quiescent current increases by 50 μA, typically.
18. For PFM operation, headroom should be 300 mV or greater.
19. From 0 °C to 85 °C
20. From -40 °C to 85 °C
21. Additional current may be drawn in the coin cell mode when RESETBMCU is pulled up to VSNVS due an internal path from RESETBMCU to VIN.
The additional current is <30 μA with a pull up resistor of 100 kΩ. The i.MX 6x processors have an internal pull up from the POR_B pin to the
VDD_SNVS_IN pin. For i.MX 6x applications, if additional current in the coin cell mode is not desired, use an external switch to disconnect the
RESETBMCU path when VIN is removed. For non-i.MX 6 applications, pull-up RESETBMCU to a rail that is off in the coin cell mode.
Coin cell mode
100
MMPF0100
10
MMPF0100A
1
-40
-20
0
20
40
60
80
Temperature(°C)
Figure 4. Current overtemperature waveforms
PF0100Z
NXP Semiconductors
13
GENERAL DESCRIPTION
5
General description
The PF0100Z is the power management integrated circuit (PMIC) designed primarily for use with NXP’s i.MX 6 series of application
processors.
5.1
Features
This section summarizes the PF0100Z features.
• Input voltage range to PMIC: 2.8 V - 4.5 V
• Buck regulators
•
Four to six channel configurable
• SW1A/B/C, 4.5 A (single); 0.3 V to 1.875 V
• SW1A/B, 2.5 A (single/dual); SW1C 2.0 A (independent); 0.3 V to 1.875 V
• SW2, 2.0 A; 0.4 V to 3.3 V (2.5 A; 1.2 V to 3.3 V (22)
• SW3A/B, 2.5 A (single/dual); 0.4 V to 3.3 V
)
• SW3A, 1.25 A (independent); SW3B, 1.25 A (independent); 0.4 V to 3.3 V
• SW4, 1.0 A; 0.4 V to 3.3 V
• SW4, VTT mode provide DDR termination at 50% of SW3A
Dynamic voltage scaling
Modes: PWM, PFM, APS
Programmable output voltage
Programmable current limit
Programmable soft start
Programmable PWM switching frequency
Programmable OCP with fault interrupt
•
•
•
•
•
•
•
• Boost regulator
•
•
•
SWBST, 5.0 V to 5.15 V, 0.6 A, OTG support
Modes: PFM and Auto
OCP fault interrupt
• LDOs
•
Six user programable LDO
• VGEN1, 0.80 V to 1.55 V, 100 mA
• VGEN2, 0.80 V to 1.55 V, 250 mA
• VGEN3, 1.8 V to 3.3 V, 100 mA
• VGEN4, 1.8 V to 3.3 V, 350 mA
• VGEN5, 1.8 V to 3.3 V, 100 mA
• VGEN6, 1.8 V to 3.3 V, 200 mA
Soft start
•
•
LDO/switch supply
• VSNVS (1.0/1.1/1.2/1.3/1.5/1.8/3.0 V), 400 μA
• DDR memory reference voltage
•
VREFDDR, 0.6 V to 0.9 V, 10 mA
• 16 MHz internal master clock
• OTP (one time programmable) memory for device configuration
•
User programmable start-up sequence and timing
• Battery backed memory including coin cell charger
• I2C interface
• User programmable standby, sleep, and off modes
Notes
22. SW2 capable of 2.5 A in NP/F9/FA versions
PF0100Z
14
NXP Semiconductors
GENERAL DESCRIPTION
5.2
Functional block diagram
PF0100Z functional internal block diagram
Power generation
OTP startup configuration
OTP prototyping
(try before buy)
Switching Regulators
Linear Regulators
Voltage
VGEN1
(0.8 V to 1.55 V, 100 mA)
SW1A/B/C
(0.3 V to 1.875 V)
Configurable 4.5 A or
2.5 A+2.0 A
Sequence and
timing
Phasing and
frequency selection
VGEN2
(0.8 V to 1.55 V, 250 mA)
Bias and references
SW2
Internal core voltage reference
DDR voltage reference
VGEN3
(1.8 V to 3.3 V, 100 mA)
(0.4 V to 3.3 V, 2.0 A)
VGEN4
(1.8 V to 3.3 V, 350 mA)
SW3A/B
(0.4 V to 3.3 V)
Configurable 2.5 A or
1.25 A+1.25 A
Logic and control
VGEN5
Parallel MCU interface
Regulator control
(1.8 V to 3.3 V, 100 mA)
I2C communication and registers
SW4
VGEN6
(1.8 V to 3.3 V, 200 mA)
(0.4 V to 3.3 V, 1.0 A)
Fault detection and protection
VSNVS
(1.0 V to 3.0 V, 400 μA)
RTC supply with coin cell
charger
Boost Regulator
(5.0 V to 5.15 V, 600 mA)
USB OTG Supply
Thermal
Current limit
Short-circuit
Figure 5. Functional block diagram
5.3
Functional description
5.3.1 Power generation
The PF0100Z PMIC features four buck regulators (up to six independent outputs), one boost regulator, six general purpose LDOs, one
switch/LDO combination, and a DDR voltage reference to supply voltages for the application processor and peripheral devices.
The number of independent buck regulator outputs can be configured from four to six, thereby providing flexibility to operate with higher
current capability, or to operate as independent outputs for applications requiring more voltage rails with lower current demands. Further,
SW1 and SW3 regulators can be configured as single/dual phase and/or independent converters. One of the buck regulators, SW4, can
also operate as a tracking regulator when used for memory termination. The buck regulators provide the supply to processor cores and
to other low voltage circuits such as IO and memory. Dynamic voltage scaling is provided to allow controlled supply rail adjustments for
the processor cores and/or other circuitry.
Depending on the system power path configuration, the six general purpose LDO regulators can be directly supplied from the main input
supply or from the switching regulators to power peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. A specific VREFDDR
voltage reference is included to provide accurate reference voltage for DDR memories operating with or without VTT termination. The
VSNVS block behaves as an LDO, or as a bypass switch to supply the SNVS/SRTC circuitry on the i.MX processors; VSNVS may be
powered from VIN, or from a coin cell.
5.3.2 Control logic
The PF0100Z PMIC is fully programmable via the I2C interface. Additional communication is provided by direct logic interfacing including
interrupt and reset. Start-up sequence of the device is selected upon the initial OTP configuration explained in the Start-up section, or by
configuring the “try before buy” feature to test different power up sequences before choosing the final OTP configuration.
The PF0100Z PMIC has the interfaces for the power buttons and dedicated signaling interfacing with the processor. It also ensures supply
of critical internal logic and other circuits from the coin cell during brief interruptions from the main battery. A charger for the coin cell is
included as well.
PF0100Z
NXP Semiconductors
15
GENERAL DESCRIPTION
5.3.2.1
Interface signals
PWRON
5.3.2.1.1
PWRON is an input signal to the IC generating a turn-on event. It can be configured to detect a level, or an edge using the PWRON_CFG
bit. Refer to section 6.4.2.1 Turn on events, page 30 for more details.
5.3.2.1.2
STANDBY
STANDBY is an input signal to the IC. When it is asserted, the part enters standby mode and when de-asserted, the part exits standby
mode. STANDBY can be configured as active high or active low using the STANDBYINV bit. Refer to the section 6.4.1.3 Standby mode,
page 28 for more details.
Note: When operating the PMIC at VIN ≤ 2.85 V and VSNVS is programmed for a 3.0 V output, a coin cell must be present to provide
VSNVS, or the PMIC does not reliably enter and exit the STANDBY mode.
5.3.2.1.3
RESETBMCU
RESETBMCU is an open-drain, active low output configurable for two modes of operation. In its default mode, it is de-asserted 2.0 ms to
4.0 ms after the last regulator in the start-up sequence is enabled; refer to Figure 6 as an example. In this mode, the signal can be used
to bring the processor out of reset, or as an indicator all supplies have been enabled; it is only asserted for a turn-off event.
When configured for its fault mode, RESETBMCU is de-asserted after the start-up sequence is completed only if no faults occurred during
start-up. At anytime, if a fault occurs and persists for 1.8 ms typically, RESETBMCU is asserted, LOW. The PF0100Z is turned off if the
fault persists for more than 100 ms typically. The PWRON signal restarts the part, though if the fault persists, the sequence described
previously is repeated. To enter the fault mode, set bit OTP_PG_EN of register OTP PWRGD EN to “1”. This register, 0xE8, is located on
Table 136. Extended page 1, page 106 of the register map. To test the fault mode, the bit may be set during TBB prototyping, or the mode
may be permanently chosen by programming OTP fuses.
5.3.2.1.4
SDWNB
SDWNB is an open drain, active low output notifying the processor of an imminent PMIC shut down. It is asserted low for one 32 kHz clock
cycle before powering down and then de-asserted in the OFF state.
5.3.2.1.5
INTB
INTB is an open-drain, active low output. It is asserted when any fault occurs, provided the fault interrupt is unmasked. INTB is de-asserted
after the fault interrupt is cleared by software, which requires writing a “1” to the fault interrupt bit.
PF0100Z
16
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6
Functional block requirements and behaviors
6.1
Start-up
The PF0100Z can be configured to start-up from either the internal OTP configuration, or with a hard-coded configuration built in to the
device. The internal hard-coded configuration is enabled by connecting the VDDOTP pin to VCOREDIG through a 100 kΩ resistor. The
OTP configuration is enabled by connecting VDDOTP to GND.
For NP devices, selecting the OTP configuration causes the PF0100Z not to start-up. However, the PF0100Z can be controlled through
the I2C port for prototyping and programming. Once programmed, the NP device starts up with the customer programmed configuration.
6.1.1 Device start-up configuration
Table 9 shows the default configuration, which can be accessed on all devices as described previously, as well as the pre-programmed
OTP configurations.
Table 9. Start-up configuration
Default
Pre-programmed OTP configuration
configuration
Registers
All devices
F0
0x08
3.0 V
1.375 V
1
F6
F8
F9
FA
0x08
3.0 V
1.375 V
5
Default I2C Address
VSNVS_VOLT
SW1AB_VOLT
SW1AB_SEQ
SW1C_VOLT
SW1C_SEQ
0x08
0x08
0x08
0x08
3.0 V
1.375 V
2
3.0 V
3.0 V
3.0 V
1.375 V
1.425 V
1.375 V
1
1
5
1.375 V
1.375 V
2
1.425 V
1.375 V
1.375 V
5
1.375 V
2
1
2
5
SW2_VOLT
3.0 V
3.3 V
5
3.0 V
1.375 V
1.375 V
5
3.3 V
4
SW2_SEQ
2
5
5
SW3A_VOLT
SW3A_SEQ
1.5 V
1.5 V
3
1.5 V
1.350 V
1.5 V
6
1.35 V
3
3
3
6
SW3B_VOLT
SW3B_SEQ
1.5 V
1.5 V
3
1.5 V
1.350 V
1.5 V
6
1.35 V
3
3
3
6
1.825 V
7
SW4_VOLT
1.8 V
3.15 V
6
3.15 V
1.825 V
7
1.8 V
4
SW4_SEQ
3
-
SWBST_VOLT
SWBST_SEQ
VREFDDR_SEQ
VGEN1_VOLT
VGEN1_SEQ
VGEN2_VOLT
VGEN2_SEQ
VGEN3_VOLT
VGEN3_SEQ
VGEN4_VOLT
VGEN4_SEQ
-
5.0 V
13
-
5.0 V
10
5.0 V
10
5.0 V
Off
-
-
3
3
3
6
6
3
-
1.5 V
9
1.5 V
1.2 V
-
1.2 V
-
1.2 V
5
-
-
1.5 V
1.5 V
10
1.5 V
1.5 V
8
1.5 V
8
1.5 V
Off
2
-
-
2.5 V
11
2.5 V
1.8 V
8
1.8 V
8
2.8 V
5
-
1.8 V
3
-
1.8 V
-
1.8 V
7
3.0 V
4
3.0 V
4
1.8 V
4
PF0100Z
NXP Semiconductors
17
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 9. Start-up configuration (continued)
Default
Pre-programmed OTP configuration
configuration
Registers
All devices
F0
2.8 V
F6
F8
F9
FA
2.5 V
8
VGEN5_VOLT
2.5 V
3
2.8 V
2.5 V
8
3.3 V
5
VGEN5_SEQ
12
-
2.8 V
VGEN6_VOLT
2.8 V
3
3.3 V
2.8 V
7
2.8 V
7
3.0 V
1
VGEN6_SEQ
8
6
PU CONFIG, SEQ_CLK_SPEED
PU CONFIG, SWDVS_CLK
PU CONFIG, PWRON
SW1AB CONFIG
SW1C CONFIG
SW2 CONFIG
1.0 ms
6.25 mV/μs
2.0 ms
1.5625 mV/μs
2.0 ms
25 mV/16 μs
0.5 ms
6.25 mV/μs
0.5 ms
6.25 mV/μs
0.5 ms
6.25 mV/μs
Level sensitive
SW1AB Single Phase, SW1C Independent Mode, 2.0 MHz
SW1ABC Single Phase, 2.0 MHz
2.0 MHz
2.0 MHz
SW3A CONFIG
SW3B CONFIG
SW4 CONFIG
SW3AB Single Phase, 2.0 MHz
2.0 MHz
No VTT, 2.0 MHz
PG EN
RESETBMCU in Default Mode
PF0100Z
18
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
LICELL
VIN
UVDET
tr1
td1
1V
td2
tr2
VSNVS
PWRON
SW1A/B
SW1C
td3
tr3
td4
tr3
SW2
VGEN2
SW3A/B
td4
tr3
SW4
VREFDDR
VGEN4
VGEN5
td5
tr4
VGEN6
RESETBMCU
*VSNVS starts from 1.0 V if LICELL is valid before VIN.
Figure 6. Default start-up sequence
Table 10. Default start-up sequence timing
Parameter
Description
Min.
Typ.
Max.
Unit
Notes
(23)
tD1
tR1
tD2
tR2
Turn-on delay of VSNVS
Rise time of VSNVS
–
–
–
–
5.0
3.0
–
–
–
–
ms
ms
ms
ms
User determined delay
Rise time of PWRON
1.0
(24)
Turn-on delay of first regulator
–
–
–
–
–
2.0
2.5
4.0
7.0
0.2
–
–
–
–
–
SEQ_CLK_SPEED[1:0] = 00
SEQ_CLK_SPEED[1:0] = 01
(25)
(26)
tD3
ms
ms
SEQ_CLK_SPEED[1:0] = 10
SEQ_CLK_SPEED[1:0] = 11
Rise time of regulators
tR3
PF0100Z
NXP Semiconductors
19
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 10. Default start-up sequence timing (continued)
Parameter
Description
Min.
Typ.
Max.
Unit
Notes
Delay between regulators
–
–
–
–
0.5
1.0
2.0
4.0
–
–
–
–
SEQ_CLK_SPEED[1:0] = 00
SEQ_CLK_SPEED[1:0] = 01
tD4
ms
SEQ_CLK_SPEED[1:0] = 10
SEQ_CLK_SPEED[1:0] = 11
Rise time of RESETBMCU
tR4
tD5
–
–
0.2
2.0
–
–
ms
ms
Turn-on delay of RESETBMCU
Notes
23. Assumes LICELL voltage is valid before VIN is applied. If LICELL is not valid before VIN is applied then VSNVS turn-on delay may extend to a
maximum of 24 ms.
24. Depends on the external signal driving PWRON.
25. Default configuration.
26. Rise time is a function of slew rate of regulators and nominal voltage selected.
6.1.2 One time programmability (OTP)
OTP allows the programming of start-up configurations for a variety of applications. Before permanently programming the IC by
programming fuses, a configuration may be prototyped by using the “try before buy” (TBB) feature. Further, an error correction code (ECC)
algorithm is available to correct a single bit error and to detect multiple bit errors when fuses are programmed.
The following parameters which can be configured by OTP are listed.
• General: I2C slave address, PWRON pin configuration, start-up sequence and timing
• Buck regulators: Output voltage, dual/single phase or independent mode configuration, switching frequency, and soft start ramp
rate
• Boost regulator and LDOs: Output voltage
NOTE: When prototyping or programming fuses, the user must ensure register settings are consistent with the hardware configuration.
This is most important for the buck regulators, where the quantity, size, and value of the inductors depend on the configuration (single/
dual phase or independent mode) and the switching frequency. Additionally, if an LDO is powered by a buck regulator, it is gated by the
buck regulator in the start-up sequence.
6.1.2.1
Start-up sequence and timing
Each regulator has 5-bits allocated to program its start-up time slot from a turn on event; therefore, each can be placed from position one
to thirty-one in the start-up sequence. The all zeros code indicates a regulator is not part of the start-up sequence and remains off. See
Table 11. The delay between each position is equal; however, four delay options are available. See Table 12. The start-up sequence
terminates at the last programmed regulator.
Table 11. Start-up sequence
SWxx_SEQ[4:0]/
VGENx_SEQ[4:0]/
Sequence
VREFDDR_SEQ[4:0]
00000
Off
00001
SEQ_CLK_SPEED[1:0] * 1
00010
SEQ_CLK_SPEED[1:0] * 2
*
*
*
*
*
*
*
*
11111
SEQ_CLK_SPEED[1:0] * 31
PF0100Z
20
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 12. Start-up Sequence Clock Speed
SEQ_CLK_SPEED[1:0]
Time (μs)
00
01
10
11
500
1000
2000
4000
6.1.2.2
PWRON pin configuration
The PWRON pin can be configured as either a level sensitive input (PWRON_CFG = 0), or as an edge sensitive input (PWRON_CFG = 1).
As a level sensitive input, an active high signal turns on the part and an active low signal turns off the part, or puts it into sleep mode. As
an edge sensitive input, such as when connected to a mechanical switch, a falling edge turns on the part and if the switch is held low for
greater than or equal to 4.0 seconds, the part turns off or enters sleep mode.
Table 13. PWRON configuration
PWRON_CFG
Mode
PWRON pin HIGH = ON
PWRON pin LOW = OFF or sleep mode
0
PWRON pin pulled LOW momentarily = ON
PWRON pin LOW for 4.0 seconds = OFF or sleep mode
1
2
6.1.2.3
I C address configuration
The I2C device address can be programmed from 0x08 to 0x0F. This allows flexibility to change the I2C address to avoid bus conflicts.
Address bit, I2C_SLV_ADDR[3] in OTP_I2C_ADDR register is hard coded to “1” while the lower three LSBs of the I2C address
(I2C_SLV_ADDR[2:0]) are programmable as shown in Table 14.
Table 14. I2C address configuration
I2C_SLV_ADDR[3]
hard coded
I2C device address
(Hex)
I2C_SLV_ADDR[2:0]
1
1
1
1
1
1
1
1
000
001
010
011
100
101
110
111
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
6.1.2.4
Soft start ramp rate
The start-up ramp rate or soft start ramp rate can be chosen from the same options as shown in 6.4.4.2.1 Dynamic voltage scaling, page
34.
PF0100Z
NXP Semiconductors
21
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.1.3 OTP prototyping
Before permanently programming fuses, it is possible to test the desired configuration by using the “try before buy” feature. With this
feature, the configuration is loaded from the OTP registers. These registers merely serve as temporary storage for the values to be written
to the fuses, for the values read from the fuses, or for the values read from the default configuration. To avoid confusion, these registers
are referred to as the TBBOTP registers. The portion of the register map concerning OTP is shown in Table 136 and Table 137.
The contents of the TBBOTP registers are initialized to zero when a valid VIN is first applied. The values then loaded into the TBBOTP
registers depend on the setting of the VDDOTP pin and on the value of the TBB_POR and FUSE_POR bits. Refer to Table 15.
• If VDDOTP = VCOREDIG (1.5 V), the values are loaded from the default configuration.
• If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR = 1, the values are loaded from the fuses. In the MMPF0100Z, FUSE_POR1,
FUSE_POR2, and FUSE_POR3 are XOR’ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR must be 1 for fuses to be loaded.
This is achieved by setting any one or all of the FUSE_PORx bits. The XOR function is removed in the MMPF0100AZ. It is required
to set all of the FUSE_PORx bits to be able to load the fuses.
• If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR = 0, the TBBOTP registers remain initialized at zero.
The initial value of TBB_POR is always “0”; only when VDDOTP = 0.0 V and TBB_POR is set to “1” are the values from the TBBOTP
registers maintained and not loaded from a different source.
The contents of the TBBOTP registers are modified by I2C. To communicate with I2C, VIN must be valid and VDDIO, to which SDA and
SCL are pulled up, must be powered by a 1.7 V to 3.6 V supply. VIN, or the coin cell voltage must be valid to maintain the contents of the
registers. To power on with the contents of the TBBOTP registers, the following conditions must exist; VIN is valid, VDDOTP = 0.0 V,
TBB_POR = 1, and there is a valid turn-on event. Refer to the application note AN4536 for an example of prototyping.
6.1.4 Reading OTP fuses
As described in the previous section, the contents of the fuses are loaded to the TBBOTP registers when the following conditions are met;
VIN is valid, VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR = 1. If ECC were enabled at the time the fuses were programmed, the error
corrected values can be loaded into the TBBOTP registers if desired. Once the fuses are loaded and a turn-on event occurs, the PMIC
powers on with the configuration programmed in the fuses. For more details on reading the OTP fuses, see application note AN4536.
6.1.5 Programming OTP fuses
The programmable parameters are shown in the TBBOTP registers in the Table 136. Extended page 1, page 106 of the register map. The
PF0100AZ offers ECC, the control registers for which functions are located in Table 137. Extended page 2, page 110 of the register map.
There are ten banks of twenty-six fuses each which can be programmed. For more details on programming the OTP fuses, see application
note AN4536.
Table 15. Source of start-up sequence
VDDOTP(V)
TBB_POR FUSE_POR
Start-up sequence
0
0
0
0
1
x
0
1
x
x
None
OTP fuses
0
TBBOTP registers
Factory defined
1.5
PF0100Z
22
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.2
16 MHz and 32 kHz clocks
There are two clocks: a trimmed 16 MHz, RC oscillator and an untrimmed 32 kHz, RC oscillator. The 16 MHz oscillator is specified within
-8.0%/+8.0%. The 32 kHz untrimmed clock is only used in the following conditions:
• VIN < UVDET
• All regulators are in sleep mode
• All regulators are in PFM switching mode
A 32 kHz clock, derived from the 16 MHz trimmed clock, is used when accurate timing is needed under the following conditions:
• During start-up, VIN > UVDET
• PWRON_CFG = 1, for power button debounce timing
In addition, when the 16 MHz is active in the on mode, the debounce times in Table 26 are referenced to the 32 kHz derived from the
16 MHz clock. The exceptions are the LOWVINI and PWRONI interrupts, which are referenced to the 32 kHz untrimmed clock.
Table 16. 16 MHz clock specifications
PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 2.8 V to 4.5 V, LICELL = 1.8 V to 3.3 V and typical external
component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.
Symbol
Parameters
Min.
Typ.
Max.
Units
Notes
VIN16MHz
f16MHZ
f2MHZ
Operating voltage From VIN
16 MHz clock frequency
2.0 MHz clock frequency
2.8
–
16
–
4.5
V
14.7
1.84
17.2
2.15
MHz
MHz
(27)
Notes
27. The 2.0 MHz clock is derived from the 16 MHz clock.
6.2.1 Clock adjustment
The 16 MHz clock and hence the switching frequency of the regulators, can be adjusted to improve the noise integrity of the system. By
changing the factory trim values of the 16 MHz clock, the user may add an offset as small as 3% of the nominal frequency. Contact your
NXP representative for detailed information on this feature.
6.3
Bias and references block description
6.3.1 Internal core voltage references
All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at VCOREREF. The bandgap and
the rest of the core circuitry are supplied from VCORE. The performance of the regulators is directly dependent on the performance of the
bandgap. No external DC loading is allowed on VCORE, VCOREDIG, or VCOREREF. VCOREDIG is kept powered as long as there is a
valid supply and/or valid coin cell. Table 17 shows the main characteristics of the core circuitry.
Table 17. Core voltages electrical specifications(29)
PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 2.8 V to 4.5 V, LICELL = 1.8 V to 3.3 V, and typical external
component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.
Symbol
Parameters
Min.
Typ.
Max.
Units
Notes
VCOREDIG (digital core supply)
Output voltage
On mode (28)
Coin cell mode and off
VCOREDIG
–
–
1.5
1.3
–
–
V
VCORE (analog core supply)
Output voltage
On mode and charging (28)
VCORE
–
–
2.775
0.0
–
–
V
Off and Coin cell mode
PF0100Z
NXP Semiconductors
23
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 17. Core voltages electrical specifications(29) (continued)
PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 2.8 V to 4.5 V, LICELL = 1.8 V to 3.3 V, and typical external
component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.
Symbol
Parameters
Min.
Typ.
Max.
Units
Notes
VCOREREF (bandgap / regulator reference)
VCOREREF
Output voltage (28)
–
–
–
1.2
0.5
–
–
–
V
%
%
VCOREREFACC
Absolute accuracy
VCOREREFTACC Temperature drift
0.25
Notes
28. 3.0 V < VIN < 4.5 V, no external loading on VCOREDIG, VCORE, or VCOREREF. Extended operation down to UVDET, but no system malfunction.
29. For information only
6.3.1.1
External components
Table 18. External components for core voltages
Regulator
Capacitor value (μF)
VCOREDIG
VCORE
1.0
1.0
VCOREREF
0.22
6.3.2 VREFDDR voltage reference
VREFDDR is an internal PMOS half supply voltage follower capable of supplying up to 10 mA. The output voltage is at one half the input
voltage. Its typically used as the reference voltage for DDR memories. A filtered resistor divider is utilized to create a low frequency pole.
This divider uses a voltage follower to drive the load.
VINREFDDR
VINREFDDR
CHALF1
100 nf
VHALF
_
+
CHALF2
100 nf
Discharge
VREFDDR
VREFDDR
CREFDDR
1.0 uf
Figure 7. VREFDDR block diagram
6.3.2.1
VREFDDR control register
The VREFDDR voltage reference is controlled by a single bit in VREFDDCRTL register in Table 19.
PF0100Z
24
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 19. Register VREFDDCRTL - ADDR 0x6A
Name
UNUSED
Bit #
R/W Default
Description
3:0
–
R/W
–
0x00
0x00
0x00
unused
Enable or disables VREFDDR output voltage
0 = VREFDDR disabled
VREFDDREN
UNUSED
4
1 = VREFDDR enabled
7:5
unused
6.3.2.1.1
External components
Table 20. VREFDDR external components (30)
Capacitor
Capacitance (μF)
VINREFDDR(31) to VHALF
VHALF to GND
0.1
0.1
1.0
VREFDDR
Notes
30. Use X5R or X7R capacitors.
31. VINREFDDR to GND, 1.0 μF minimum capacitance is provided by buck regulator output.
6.3.2.1.2
VREFDDR specifications
Table 21. VREFDDR electrical characteristics
PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V and typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V, and
25 °C, unless otherwise noted.
Symbol
VREFDDR
VINREFDDR
IREFDDR
Parameter
Min.
Typ.
Max.
Unit
Notes
Operating input voltage range
Operating load current range
Current limit
1.2
0.0
–
–
1.8
10
V
mA
IREFDDRLIM
10.5
–
15
25
–
mA
IREFDDR when VREFDDR is forced to VINREFDDR/4
(32)
IREFDDRQ
Quiescent current
8.0
μA
Active Mode – DC
Output voltage
VINREFDDR
2
/
VREFDDR
–
–
V
%
1.2 V < VINREFDDR < 1.8 V
0.0 mA < IREFDDR < 10 mA
Output voltage tolerance
1.2 V < VINREFDDR < 1.8 V
0.6 mA ≤ IREFDDR ≤ 10 mA
VREFDDRTOL
T
T
A = -40 °C to 85 °C
A = -40 °C to 105 °C (PF0100AZ only)
–1.0
-1.2
–
–
1.0
1.2
Load regulation
VREFDDRLOR
–
0.40
–
mV/mA
1.0 mA < IREFDDR < 10 mA
1.2 V < VINREFDDR < 1.8 V
PF0100Z
NXP Semiconductors
25
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 21. VREFDDR electrical characteristics (continued)
PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V and typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V, and
25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
100
10
Unit
Notes
Active mode – AC
Turn-on Time
Enable to 90% of end value
INREFDDR = 1.2 V, 1.8 V
REFDDR = 0.0 mA
tONREFDDR
–
–
–
–
μs
V
I
Turn-off time
Disable to 10% of initial value
INREFDDR = 1.2 V, 1.8 V
REFDDR = 0.0 mA
tOFFREFDDR
ms
V
I
Start-up overshoot
VREFDDROSH
–
–
1.0
5.0
6.0
–
%
VINREFDDR = 1.2 V, 1.8 V
I
REFDDR = 0.0 mA
Transient load response
INREFDDR = 1.2 V, 1.8 V
VREFDDRTLR
Notes
mV
V
32. When VREFDDR is off there is a quiescent current of 1.5 μA typical.
PF0100Z
26
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4
Power generation
6.4.1 Modes of operation
The operation of the PF0100Z can be reduced to five states, or modes: on, off, sleep, standby, and coin cell. Figure 8 shows the state
diagram of the PF0100Z, along with the conditions to enter and exit from each state.
Coin Cell
VIN < UVDET
VIN < UVDET
VIN > UVDET
PWRON = 0 held >= 4.0 sec
Any SWxOMODE bits=1
& PWRONRSTEN = 1
(PWRON_CFG=1)
Thermal shutdown
OFF
PWRON=1
& VIN > UVDET
(PWRON_CFG = 0)
Or
VIN < UVDET
Sleep
PWRON = 0
Any SWxOMODE bits=1
(PWRON_CFG=0)
Or
PWRON=0 held >= 4.0 sec
Any SWxOMODE bits=1
& PWRONRSTEN = 1
(PWRON_CFG=1)
PWRON= 0 < 4.0 sec
& VIN > UVDET
(PWRON_CFG=1)
PWRON = 0
All SWxOMODE bits= 0
(PWRON_CFG = 0)
Or
VIN < UVDET
PWRON = 0
Any SWxOMODE bits=1
(PWRON_CFG=0)
Or
PWRON=0 held >= 4.0 sec
Any SWxOMODE bits=1
& PWRONRSTEN = 1
(PWRON_CFG=1)
PWRON = 0 held >= 4.0 sec
All SWxOMODE bits= 0
& PWRONRSTEN = 1
(PWRON_CFG = 1)
PWRON=1
& VIN > UVDET
(PWRON_CFG =0)
Or
PWRON= 0 < 4.0 sec
& VIN > UVDET
(PWRON_CFG=1)
ON
Thermal shudown
PWRON = 0
All SWxOMODE bits= 0
(PWRON_CFG = 0)
Or
STANDBY asserted
STANDBY de-asserted
PWRON = 0 held >= 4.0 sec
All SWxOMODE bits= 0
& PWRONRSTEN = 1
(PWRON_CFG = 1)
Thermal shutdown
Standby
Figure 8. State diagram
To complement the state diagram in Figure 8, a description of the states is provided in following sections. Note that VIN must exceed the
rising UVDET threshold to allow a power up. Refer to Table 28 for the UVDET thresholds. Additionally, I2C control is not possible in the
coin cell mode and the interrupt signal, INTB, is only active in sleep, standby, and on states.
6.4.1.1
On mode
The PF0100Z enters the on mode after a turn-on event. RESETBMCU is de-asserted, high, in this mode of operation.
6.4.1.2
Off mode
The PF0100Z enters the off mode after a turn-off event. A thermal shutdown event also forces the PF0100Z into the off mode. Only
VCOREDIG and VSNVS are powered in the mode of operation. To exit the off mode, a valid turn-on event is required. RESETBMCU is
asserted, low, in this mode.
PF0100Z
NXP Semiconductors
27
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.1.3
Standby mode
• Depending on STANDBY pin configuration, standby is entered when the STANDBY pin is asserted. This is typically used for low-
power mode of operation.
• When STANDBY is de-asserted, standby mode is exited.
A product may be designed to go into a low-power mode after periods of inactivity. The STANDBY pin is provided for board level control
of going in and out of such deep sleep modes (DSM).
When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing the
operating mode of the regulators, or disabling some regulators. The configuration of the regulators in standby is pre-programmed through
the I2C interface.
Note that the STANDBY pin is programmable for active high or active low polarity, and decoding of a Standby event takes into account
the programmed input polarity, as shown in Table 22. When the PF0100Z is powered up first, regulator settings for the standby mode are
mirrored from the regulator settings for the on mode. To change the STANDBY pin polarity to active low, set the STANDBYINV bit via
software first, and then change the regulator settings for standby mode as required. For simplicity, STANDBY is generally referred to as
active high throughout this document.
Table 22. Standby pin and polarity control
STANDBY (pin)(34)
STANDBYINV (I2C bit)(35)
STANDBY control (33)
0
0
1
1
0
1
0
1
0
1
1
0
Notes
33. STANDBY = 0: System is not in standby, STANDBY = 1: System is in standby
34. The state of the STANDBY pin only has influence in on mode.
35. Bit 6 in power control register (ADDR - 0x1B)
Since STANDBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond
to the pin level changes. A programmable delay is provided to hold off the system response to a Standby event. This allows the processor
and peripherals some time after a standby instruction was received to terminate processes to facilitate seamless entering into standby
mode.
When enabled (STBYDLY = 01, 10, or 11) per Table 23, STBYDLY delays the standby initiated response for the entire IC, until the
STBYDLY counter expires. An allowance should be made for three additional 32 k cycles required to synchronize the standby event.
Table 23. STANDBY delay - initiated response
STBYDLY[1:0](36)
Function
00
01
10
11
No delay
One 32 k period (default)
Two 32 k periods
Three 32 k periods
Notes
36. Bits [5:4] in Power Control Register (ADDR - 0x1B)
6.4.1.4
Sleep mode
• Depending on the PWRON pin configuration, sleep mode is entered when PWRON is de-asserted and SWxOMODE bit is set.
• To exit sleep mode, assert the PWRON pin.
In the sleep mode, the regulator uses the set point as programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/
B, and SW4. The activated regulators maintain settings for this mode and voltage until the next turn-on event. Table 24 shows the control
bits in sleep mode. During sleep mode, interrupts are active and the INTB pin reports any unmasked fault event.
PF0100Z
28
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 24. Regulator mode control
SWxOMODE
Off operational mode (sleep) (37)
0
1
Off
PFM
Notes
37. For sleep mode, an activated switching regulator, should use the off mode
set point as programmed by SW1xOFF[5:0] for SW1A/B/C and
SWxOFF[6:0] for SW2, SW3A/B, and SW4.
6.4.1.5
Coin cell mode
In the coin cell state, the coin cell is the only valid power source (VIN = 0.0 V) to the PMIC. No turn-on event is accepted in the coin cell
state. Transition to the OFF state requires that VIN surpasses UVDET threshold. RESETBMCU is held low in this mode.
If the coin cell is depleted, a complete system reset occurs. At the next application of power and the detection of a turn-on event, the
system is re-initialized with all I2C bits including those reset on COINPORB, which are restored to their default states.
6.4.2 State machine flow summary
Table 25 provides a summary matrix of the PF0100Z flow diagram to show the conditions needed to transition from one state to another.
Table 25. State machine flow summary
Next state
STATE
OFF
Coin cell
VIN < UVDET
X
Sleep
Standby
ON
PWRON_CFG = 0
PWRON = 1 & VIN > UVDET
or
OFF
Coin cell
Sleep
X
X
X
X
X
X
X
PWRON_CFG = 1
PWRON = 0 < 4.0 s
& VIN > UNDET
VIN > UVDET
X
Thermal Shutdown
PWRON_CFG = 0
PWRON = 1 & VIN > UVDET
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
Any SWxOMODE = 1 &
PWRONRSTEN = 1
VIN < UVDET
PWRON_CFG = 1
PWRON = 0 < 4.0 s &
V
IN > UNDET
Thermal Shutdown
PWRON_CFG = 0
PWRON = 0
Any SWxOMODE = 1
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
Any SWxOMODE = 1 &
PWRONRSTEN = 1
PWRON_CFG = 0
PWRON = 0
All SWxOMODE = 0
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
All SWxOMODE = 0 &
PWRONRSTEN = 1
Standby
VIN < UVDET
X
Standby de-asserted
Thermal Shutdown
PWRON_CFG = 0
PWRON = 0
Any SWxOMODE = 1
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
Any SWxOMODE = 1 &
PWRONRSTEN = 1
PWRON_CFG = 0
PWRON = 0
All SWxOMODE = 0
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
All SWxOMODE = 0 &
PWRONRSTEN = 1
Standby
asserted
ON
VIN < UVDET
X
PF0100Z
NXP Semiconductors
29
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.2.1
Turn on events
From off and sleep modes, the PMIC is powered on by a turn-on event. The type of turn-on event depends on the configuration of PWRON.
PWRON may be configured as an active high when PWRON_CFG = 0, or as the input of a mechanical switch when PWRON_CFG = 1.
VIN must be greater than UVDET for the PMIC to turn-on. When PWRON is configured as an active high and PWRON is high (pulled up
to VSNVS) before VIN is valid, a VIN transition from 0.0 V to a voltage greater than UVDET is also a turn-on event. See the state diagram,
Figure 8, and the Table 25 for more details. Any regulator enabled in the sleep mode remains enabled when transitioning from sleep to
on, the regulator does not turn off and then on again to match the start-up sequence. The following is a more detailed description of the
PWRON configurations:
• If PWRON_CFG = 0, the PWRON signal is high and VIN > UVDET, the PMIC turns on; the interrupt and sense bits, PWRONI and
PWRONS respectively, are set.
• If PWRON_CFG = 1, VIN > UVDET and PWRON transitions from high to low, the PMIC turns on; the interrupt and sense bits,
PWRONI and PWRONS respectively, are set.
The sense bit shows the real time status of the PWRON pin. In this configuration, the PWRON input can be a mechanical switch
debounced through a programmable debouncer, PWRONDBNC[1:0], to avoid a response to a very short (unintentional) key press. The
interrupt is generated for both the falling and the rising edge of the PWRON pin. By default, a 30 ms interrupt debounce is applied to both
falling and rising edges. The falling edge debounce timing can be extended with PWRONDBNC[1:0] as defined in Table 26. The interrupt
is cleared by software, or when cycling through the off mode.
Table 26. PWRON hardware debounce bit settings
Turn on
debounce (ms)
Falling edge INT
debounce (ms)
Rising edge INT
debounce (ms)
Bits
State
00
01
10
11
0.0
31.25
125
31.25
31.25
125
31.25
31.25
31.25
31.25
PWRONDBNC[1:0]
Notes
750
750
38. The sense bit, PWRONS, is not debounced and follows the state of the PWRON pin.
6.4.2.2
Turn off events
PWRON pin
6.4.2.2.1
The PWRON pin is used to power off the PF0100Z. The PWRON pin can be configured with OTP to power off the PMIC under the following
two conditions:
1. PWRON_CFG bit = 0, SWxOMODE bit = 0 and PWRON pin is low.
2. PWRON_CFG bit = 1, SWxOMODE bit = 0, PWRONRSTEN = 1 and PWRON is held low for longer than 4.0 seconds.
Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.
6.4.2.2.2
Thermal protection
If the die temperature surpasses a given threshold, the thermal protection circuit powers off the PMIC to avoid damage. A turn-on event
does not power on the PMIC while it is in thermal protection. The part remains in off mode until the die temperature decreases below a
given threshold. There are no specific interrupts related to this other than the warning interrupt. See 4.2.1 Power dissipation, page 10 for
more detailed information.
6.4.2.2.3
Undervoltage detection
When the voltage at VIN drops below the undervoltage falling threshold, UVDET, the state machine transitions to the coin cell mode.
PF0100Z
30
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.3 Power tree
The PF0100Z PMIC features six buck regulators, one boost regulator, six general purpose LDOs, one switch/LDO combination, and a
DDR voltage reference to supply voltages for the application processor and peripheral devices. The buck regulators as well as the boost
regulator are supplied directly from the main input supply (VIN). The inputs to all of the buck regulators must be tied to VIN, whether they
are powered on or off. The six general use LDO regulators are directly supplied from the main input supply or from the switching regulators
depending on the application requirements. Since VREFDDR is intended to provide DDR memory reference voltage, it should be supplied
by any rail supplying voltage to DDR memories; the typical application recommends the use of SW3 as the input supply for VREFDDR.
VSNVS is supplied by either the main input supply or the coin cell. Refer to Table 27 for a summary of all power supplies provided by the
PF0100Z.
Table 27. Power tree summary
Supply
Output voltage (V)
Step size (mV)
Maximum load current (mA)
SW1A/B
SW1C
0.3 - 1.875
0.3 - 1.875
25
25
2500
2000
2000 (40)
1250 (39)
1000
600
SW2
0.4 - 3.3
25/50
25/50
25/50
50
SW3A/B
SW4
0.4 - 3.3
0.5*SW3A_OUT, 0.4 - 3.3
5.00/5.05/5.10/5.15
0.80 – 1.55
0.80 – 1.55
1.8 – 3.3
SWBST
VGEN1
VGEN2
VGEN3
VGEN4
VGEN5
VGEN6
VSNVS
VREFDDR
50
100
50
250
100
100
100
100
NA
100
1.8 – 3.3
350
1.8 – 3.3
100
1.8 – 3.3
200
1.0 - 3.0
0.4
0.5*SW3A_OUT
NA
10
Notes
39. Current rating per independent phase, when SW3A/B is set in single or dual phase, current capability is up to 2500 mA.
40. SW2 capable of 2500 mA in NP/F9/FA versions
Figure 9 shows a simplified power map with various recommended options to supply the different block within the PF0100Z, as well as
the typical application voltage domain on the i.MX 6X processor. Note that each application power tree is dependent upon the system’s
voltage and current requirements, therefore a proper input voltage should be selected for the regulators.
The minimum operating voltage for the main VIN supply is 2.8 V, for lower voltages proper operation is not guaranteed. However at initial
power up, the input voltage must surpass the rising UVDET threshold before proper operation is guaranteed. Refer to the representative
tables and text specifying each supply for information on performance metrics and operating ranges. Table 28 summarizes the UVDET
thresholds.
Table 28. UVDET threshold
UVDET threshold
VIN
Rising
Falling
3.1 V
2.65 V
PF0100Z
NXP Semiconductors
31
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
i.MX6X
MCU
SW1A
CORE
VDDARM_IN
(0.3 to 1.875 V), 1.25 A
SW1B
CORE
(0.3 to 1.875 V), 1.25 A
SW1C
SOC
(0.3 to 1.875 V), 2.0 A
VDDSOC_IN
VDDHIGH_IN
SW2
VDDHIGH
VIN
2.8 - 4.5 V
(0.4 to 3.3 V), 2.0 A
SW3A
DDR CORE
(0.4 to 3.3 V), 1.25 A
SW3B
DDR IO
VDD_DDR_IO
(0.4 to 3.3 V), 1.25 A
SW4
System/VTT
(0.4 to 3.3 V)
(0.5*VDDR)
1.0 A
SWBST
5.0 V, 0.6 A
LDO_3p0
VREFDDR
0.5*VDDR, 10 mA
SW3A/B
VIN
VSNVS
MUX /
VSNVS_IN
COIN
CHRG
1.0 to 3.0 V,
400 uA
Coincell
VGEN1
(0.80 to 1.55 V),
100 mA
USB_OTG
VIN
SW2
VINMAX = 3.4 V
VINMAX = 3.6 V
VINMAX = 4.5 V
VGEN2
(0.80 to 1.55 V),
250 mA
SW4
DDR3
VGEN3
(1.8 to 3.3 V),
100 mA
Peripherals
VIN
SW2
VGEN4
(1.8 to 3.3 V),
350 mA
SW4
VGEN5
(1.8 to 3.3 V),
100 mA
VIN
SW2
VGEN6
(1.8 to 3.3 V),
200 mA
SW4
Figure 9. PF0100Z typical power map
PF0100Z
32
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4 Buck regulators
Each buck regulator is capable of operating in PFM, APS, and PWM switching modes.
6.4.4.1
Current limit
Each buck regulator has a programmable current limit. In an overcurrent condition, the current is limited cycle-by-cycle. If the current limit
condition persists for more than 8.0 ms, a fault interrupt is generated.
6.4.4.2
General control
To improve system efficiency the buck regulators can operate in different switching modes. Changing between switching modes can occur
by any of the following means: I2C programming, exiting/entering the standby mode, exiting/entering sleep mode, and load current
variation. Available switching modes for buck regulators are presented in Table 29.
Table 29. Switching mode description
Mode
Description
OFF
PFM
PWM
APS
The regulator is switched off and the output voltage is discharged.
In this mode, the regulator is always in PFM mode, which is useful at light loads for optimized efficiency.
In this mode, the regulator is always in PWM mode operation regardless of load conditions.
In this mode, the regulator moves automatically between pulse skipping mode and PWM mode depending on load conditions.
During soft-start of the buck regulators, the controller transitions through the PFM, APS, and PWM switching modes. 3.0 ms (typical) after
the output voltage reaches regulation, the controller transitions to the selected switching mode. Depending on the particular switching
mode selected, additional ripple may be observed on the output voltage rail as the controller transitions between switching modes. Contact
your NXP representative for application considerations if you are using load switches in series with the buck regulator outputs. Table 30
summarizes the buck regulator programmability for normal and standby modes.
Table 30. Regulator mode control
SWxMODE[3:0]
Normal mode
Standby mode
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Off
Off
Off
PWM
Reserved
PFM
Reserved
Off
APS
Off
PWM
PWM
PWM
APS
Reserved
APS
Reserved
APS
Reserved
Reserved
Reserved
APS
Reserved
Reserved
Reserved
PFM
PWM
PFM
Reserved
Reserved
Reserved
Reserved
Transitioning between normal and standby modes can affect a change in switching modes as well as output voltage. The rate of the output
voltage change is controlled by the dynamic voltage scaling (DVS), explained in 6.4.4.2.1 Dynamic voltage scaling, page 34. For each
regulator, the output voltage options are the same for normal and standby modes.
PF0100Z
NXP Semiconductors
33
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
When in standby mode, the regulator outputs the voltage programmed in its standby voltage register and operates in the mode selected
by the SWxMODE[3:0] bits. Upon exiting standby mode, the regulator returns to its normal switching mode and its output voltage
programmed in its voltage register.
Any regulators whose SWxOMODE bit is set to “1” enters sleep mode if a PWRON turn-off event occurs, and any regulator whose
SWxOMODE bit is set to “0” is turned off. In sleep mode, the regulator outputs the voltage programmed in its off (sleep) voltage register
and operates in the PFM mode. The regulator exits the sleep mode when a turn-on event occurs. Any regulator whose SWxOMODE bit
is set to “1” remains on and changes to its normal configuration settings when exiting the sleep state to the on state. Any regulator whose
SWxOMODE bit is set to “0” powers up with the same delay in the start-up sequence as when powering on from off. At this point, the
regulator returns to its default ON state output voltage and switch mode settings.
Table 24 shows the control bits in sleep mode. When sleep mode is activated by the SWxOMODE bit, the regulator uses the set point as
programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/B, and SW4.
6.4.4.2.1
Dynamic voltage scaling
To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor.
1. Normal operation: The output voltage is selected by I2C bits SW1x[5:0] for SW1A/B/C and SWx[6:0] for SW2, SW3A/B, and SW4.
A voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 33 and Table 34.
2. Standby mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the lowest state
retention voltage of a given processor; it is selected by I2C bits SW1xSTBY[5:0] for SW1A/B/C and by bits SWxSTBY[6:0] for SW2,
SW3A/B, and SW4. Voltage transitions initiated by a standby event are governed by the SW1xDVSSPEED[1:0] and
SWxDVSSPEED[1:0] I2C bits shown in Table 33 and Table 34, respectively.
3. Sleep mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest state
retention voltage of a given processor; it is selected by I2C bits SW1xOFF[5:0] for SW1A/B/C and by bits SWxOFF[6:0] for SW2,
SW3A/B, and SW4. Voltage transitions initiated by a turn-off event are governed by the SW1xDVSSPEED[1:0] and
SWxDVSSPEED[1:0] I2C bits shown in Table 33 and Table 34, respectively.
Table 31, Table 32, Table 33, and Table 34 summarize the set point control and DVS time stepping applied to all regulators.
Table 31. DVS control logic for SW1A/B/C
STANDBY
Set point selected by
0
1
SW1x[5:0]
SW1xSTBY[5:0]
Table 32. DVS control logic for SW2, SW3A/B, and SW4
STANDBY
Set point selected by
0
1
SWx[6:0]
SWxSTBY[6:0]
Table 33. DVS speed selection for SW1A/B/C
SW1xDVSSPEED[1:0]
Function
00
01 (default)
10
25 mV step each 2.0 μs
25 mV step each 4.0 μs
25 mV step each 8.0 μs
25 mV step each 16 μs
11
PF0100Z
34
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 34. DVS Speed Selection for SW2, SW3A/B, and SW4
Function
SWx[6] = 0 or SWxSTBY[6] = 0
Function
SWx[6] = 1 or SWxSTBY[6] = 1
SWxDVSSPEED[1:0]
00
01 (default)
10
25 mV step each 2.0 μs
25 mV step each 4.0 μs
25 mV step each 8.0 μs
25 mV step each 16 μs
50 mV step each 4.0 μs
50 mV step each 8.0 μs
50 mV step each 16 μs
50 mV step each 32 μs
11
The regulators have a strong sourcing capability and sinking capability in PWM mode, therefore the fastest rising and falling slopes are
determined by the regulator in PWM mode. However, if the regulators are programmed in PFM or APS mode during a DVS transition, the
falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS transitions in
PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation.
The following diagram shows the general behavior for the regulators when initiated with I2C programming, or standby control. During the
DVS period the overcurrent condition on the regulator should be masked.
Requested
Set Point
Output Voltage
with light Load
Internally
Controlled Steps
Example
Output
Voltage
Actual Output
Voltage
Initial
Set Point
Actual
Output Voltage
Internally
Possible
Output Voltage
Window
Controlled Steps
Request for
Higher Voltage
Request for
Lower Voltage
Voltage
Change
Request
Initiated by I2C Programming, Standby Control
Figure 10. Voltage stepping with DVS
6.4.4.2.2
Regulator phase clock
The SWxPHASE[1:0] bits select the phase of the regulator clock as shown in Table 35. By default, each regulator is initialized at 90 ° out
of phase with respect to each other. For example, SW1x is set to 0 °, SW2 is set to 90 °, SW3A/B is set to 180 °, and SW4 is set to 270 °
by default at power up.
Table 35. Regulator phase clock selection
Phase of clock sent to regulator
SWxPHASE[1:0]
(degrees)
00
01
10
11
0
90
180
270
The SWxFREQ[1:0] register is used to set the desired switching frequency for each one of the buck regulators. Table 37 shows the
selectable options for SWxFREQ[1:0]. For each frequency, all phases will be available, this allows regulators operating at different
frequencies to have different relative switching phases. However, not all combinations are practical. For example, 2.0 MHz, 90 ° and
4.0 MHz, 180 ° are the same in terms of phasing. Table 36 shows the optimum phasing when using more than one switching frequency.
PF0100Z
NXP Semiconductors
35
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 36. Optimum phasing
Frequencies
Optimum phasing
1.0 MHz
2.0 MHz
0 °
180 °
1.0 MHz
4.0 MHz
0 °
180 °
2.0 MHz
4.0 MHz
0 °
180 °
1.0 MHz
2.0 MHz
4.0 MHz
0 °
90 °
90 °
Table 37. Regulator frequency configuration
SWxFREQ[1:0]
Frequency
00
01
10
11
1.0 MHz
2.0 MHz
4.0 MHz
Reserved
6.4.4.2.3
Programmable maximum current
The maximum current, ISWxMAX, of each buck regulator is programmable. This allows the use of smaller inductors where lower currents
are required. Programmability is accomplished by choosing the number of paralleled power stages in each regulator. The
SWx_PWRSTG[2:0] bits in Table 137. Extended page 2, page 110 of the register map control the number of power stages. See Table 38
for the programmable options. Bit[0] must always be enabled to ensure the stage with the current sensor is chosen. The default setting,
SWx_PWRSTG[2:0] = 111, represents the highest maximum current. The current limit for each option is also scaled by the percentage of
power stages that are enabled.
Table 38. Programmable current configuration
% of power stages
Regulators
Control bits
Rated current (A)
enabled
SW1AB_PWRSTG[2:0]
ISW1ABMAX
1.0
0
0
1
1
1
1
40%
80%
SW1AB
0
1
1
1
2.0
0
60%
1.5
1
100%
2.5
SW1C_PWRSTG[2:0]
ISW1CMAX
0.9
0
0
1
1
0
1
1
1
1
43%
58%
SW1C
1
1.2
0
86%
1.7
1
100%
2.0
SW2_PWRSTG[2:0]
ISW2MAX
0.75
0
0
1
1
0
1
0
1
1
1
1
1
38%
75%
SW2
1.5
63%
1.25
100%
2.0
PF0100Z
36
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 38. Programmable current configuration (continued)
% of power stages
enabled
Regulators
Control bits
Rated current (A)
SW3A_PWRSTG[2:0]
ISW3AMAX
0.5
0
0
1
1
0
1
1
1
1
40%
80%
SW3A
1
1.0
0
60%
0.75
1
100%
1.25
SW3B_PWRSTG[2:0]
ISW3BMAX
0.5
0
0
1
1
0
1
1
1
1
40%
80%
SW3B
1
1.0
0
60%
0.75
1
100%
1.25
SW4_PWRSTG[2:0]
ISW4MAX
0.5
0
0
1
1
0
1
0
1
1
1
1
1
50%
75%
SW4
0.75
75%
0.75
100%
1.0
6.4.4.3
SW1A/B/C
SW1/A/B/C are 2.5 A to 4.5 A buck regulators which can be configured in various phasing schemes, depending on the desired cost/
performance trade-offs. The following configurations are available:
• SW1A/B/C single phase with one inductor
• SW1A/B as a single phase with one inductor and SW1C in independent mode with one inductor
• SW1A/B as a dual phase with two inductors and SW1C in independent mode with one inductor
The desired configuration is programmed by OTP by using SW1_CONFIG[1:0] bits in the register map Table 136. Extended page 1, page
106, as shown in Table 39.
.
Table 39. SW1 configuration
SW1_CONFIG[1:0]
Description
A/B/C single phase
00
A/B single phase
C independent mode
01
A/B dual phase
C independent mode
10
11
Reserved
6.4.4.3.1
SW1A/B/C single phase
In this configuration, all phases A, B, and C, are connected together to a single inductor, thus, providing up to 4.50 A current capability for
high current applications. The feedback and all other controls are accomplished by use of pin SW1CFB and SW1C control registers,
respectively. Figure 11 shows the connection for SW1A/B/C in single phase mode.
During single phase mode operation, all three phases use the same configuration for frequency, phase, and DVS speed set in the
SW1CCONF register. However, the same configuration settings for frequency, phase, and DVS speed setting on SW1AB registers should
be used. The SW1FB pin should be left floating in this configuration.
PF0100Z
NXP Semiconductors
37
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VIN
SW1AIN
SW1AMODE
ISENSE
CINSW1A
Controller
SW1A/B/C
SW1ALX
Driver
LSW1
COSW1A
SW1AFAULT
Internal
I2C
Compensation
Z2
SW1FB
Z1
EA
VREF
DAC
VIN
SW1BIN
SW1BMODE
ISENSE
CINSW1B
Controller
I2C
Interface
SW1BLX
Driver
SW1BFAULT
SW1CMODE
VIN
SW1CIN
ISENSE
CINSW1C
Controller
SW1CLX
EP
Driver
SW1CFAULT
Internal
I2C
Compensation
Z2
SW1CFB
Z1
VREF
EA
DAC
Figure 11. SW1A/B/C single phase block diagram
6.4.4.3.2
SW1A/B single phase - SW1C independent mode
In this configuration, SW1A/B is connected as a single phase with a single inductor, while SW1C is used as an independent output, using
its own inductor and configurations parameters. This configuration allows reduced component count by using only one inductor for
SW1A/B. As mentioned before, SW1A/B and SW1C operate independently from one another, thus, they can be operated with a different
voltage set point for normal, standby, and sleep modes, as well as switching mode selection and on/off control. Figure 12 shows the
physical connection for SW1A/B in single phase and SW1C as an independent output.
PF0100Z
38
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VIN
SW1AIN
SW1ALX
SW1AMODE
ISENSE
CINSW1A
Controller
SW1A/B
Driver
LSW1A
COSW1A
SW1AFAULT
Internal
I2C
Compensation
Z2
SW1FB
Z1
EA
VREF
DAC
VIN
SW1BIN
SW1BMODE
ISENSE
CINSW1B
Controller
I2C
Interface
SW1BLX
Driver
SW1BFAULT
SW1CMODE
VIN
SW1CIN
ISENSE
CINSW1C
Controller
SW1C
SW1CLX
EP
Driver
LSW1C
COSW1C
SW1CFAULT
Internal
I2C
Compensation
Z2
SW1CFB
Z1
VREF
EA
DAC
Figure 12. SW1A/B single phase, SW1C independent mode block diagram
Both SW1ALX and SW1BLX nodes operate at the same DVS, frequency, and phase configured by the SW1ABCONF register, while
SW1CLX node operates independently, using the configuration in the SW1CCONF register.
6.4.4.3.3
SW1A/B dual phase - SW1C independent mode
In this mode, SW1A/B is connected in dual phase mode using one inductor per switching node, while SW1C is used as an independent
output using its own inductor and configuration parameters. This mode provides a smaller output voltage ripple on the SW1A/B output.
As mentioned before, SW1A/B and SW1C operate independently from one another, thus, they can be operated with a different voltage
set point for normal, standby, and sleep modes, as well as switching mode selection and on/off control. Figure 13 shows the physical
connection for SW1A/B in dual phase and SW1C as an independent output.
PF0100Z
NXP Semiconductors
39
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VIN
SW1AIN
SW1AMODE
ISENSE
CINSW1A
Controller
SW1AB
SW1ALX
Driver
LSW1A
COSW1A
SW1AFAULT
Internal
I2C
Compensation
Z2
SW1FB
Z1
EA
VREF
DAC
VIN
SW1BIN
SW1BMODE
ISENSE
CINSW1B
I2C
Interface
Controller
SW1BLX
LSW1B
Driver
COSW1B
SW1BFAULT
SW1CMODE
VIN
SW1CIN
ISENSE
CINSW1C
Controller
SW1C
SW1CLX
Driver
LSW1C
COSW1C
SW1CFAULT
EP
Internal
I2C
Compensation
Z2
SW1CFB
Z1
VREF
EA
DAC
Figure 13. SW1A/B dual phase, SW1C independent mode block diagram
In this mode of operation, SW1ALX and SW1BLX nodes operate automatically at 180 ° phase shift from each other and use the same
frequency and DVS configured by SW1ABCONF register, while SW1CLX node operate independently using the configuration in the
SW1CCONF register.
PF0100Z
40
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.3.4
SW1A/B/C setup and control registers
SW1A/B and SW1C output voltages are programmable from 0.300 V to 1.875 V in steps of 25 mV. The output voltage set point is
independently programmed for normal, standby, and sleep mode by setting the SW1x[5:0], SW1xSTBY[5:0], and SW1xOFF[5:0] bits
respectively. Table 40 shows the output voltage coding for SW1A/B or SW1C.
Note: Voltage set points of 0.6 V and below are not supported.
Table 40. SW1A/B/C output voltage configuration
SW1x[5:0]
SW1x[5:0]
Set point
SW1xSTBY[5:0]
SW1xOFF[5:0]
SW1x output (V)
Set point
SW1xSTBY[5:0]
SW1xOFF[5:0]
SW1x output (V)
0
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
0.3000
0.3250
0.3500
0.3750
0.4000
0.4250
0.4500
0.4750
0.5000
0.5250
0.5500
0.5750
0.6000
0.6250
0.6500
0.6750
0.7000
0.7250
0.7500
0.7750
0.8000
0.8250
0.8500
0.8750
0.9000
0.9250
0.9500
0.9750
1.0000
1.0250
1.0500
1.0750
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
1.1000
1.1250
1.1500
1.1750
1.2000
1.2250
1.2500
1.2750
1.3000
1.3250
1.3500
1.3750
1.4000
1.4250
1.4500
1.4750
1.5000
1.5250
1.5500
1.5750
1.6000
1.6250
1.6500
1.6750
1.7000
1.7250
1.7500
1.7750
1.8000
1.8250
1.8500
1.8750
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Table 41 provides a list of registers used to configure and operate SW1A/B/C and a detailed description on each one of these register is
provided in Table 42 through Table 51.
PF0100Z
NXP Semiconductors
41
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 41. SW1A/B/C register summary
Register
SW1ABVOLT
Address
Output
0x20
0x21
0x22
0x23
0x24
0x2E
0x2F
0x30
0x31
0x32
SW1AB output voltage set point in normal operation
SW1AB output voltage set point on standby
SW1AB output voltage set point on sleep
SW1ABSTBY
SW1ABOFF
SW1ABMODE
SW1ABCONF
SW1CVOLT
SW1CSTBY
SW1COFF
SW1AB switching mode selector register
SW1AB DVS, phase, frequency and ILIM configuration
SW1C output voltage set point in normal operation
SW1C output voltage set point in standby
SW1C output voltage set point in sleep
SW1CMODE
SW1CCONF
SW1C switching mode selector register
SW1C DVS, phase, frequency and ILIM configuration
Table 42. Register SW1ABVOLT - ADDR 0x20
Name
Bit #
R/W Default
Description
Sets the SW1AB output voltage during normal
operation mode. See Table 40 for all possible
configurations.
SW1AB
UNUSED
5:0
7:6
R/W
–
0x00
0x00
unused
Table 43. Register SW1ABSTBY - ADDR 0x21
Name
Bit #
R/W Default
Description
Sets the SW1AB output voltage during standby
mode. See Table 40 for all possible
configurations.
SW1ABSTBY
UNUSED
5:0
7:6
R/W
–
0x00
0x00
unused
Table 44. Register SW1ABOFF - ADDR 0x22
Name
Bit #
R/W Default
Description
Sets the SW1AB output voltage during sleep
mode. See Table 40 for all possible
configurations.
SW1ABOFF
UNUSED
5:0
7:6
R/W
–
0x00
0x00
unused
Table 45. Register SW1ABMODE - ADDR 0x23
Name
Bit #
R/W Default
Description
Sets the SW1AB switching operation mode.
See Table 30 for all possible configurations.
SW1ABMODE
UNUSED
3:0
4
R/W
–
0x80
0x00
UNUSED
Set status of SW1AB when in sleep mode
SW1ABOMODE
UNUSED
5
R/W
–
0x00
0x00
0 = OFF
1 = PFM
7:6
unused
PF0100Z
42
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 46. Register SW1ABCONF - ADDR 0x24
Name
Bit #
R/W Default
Description
SW1AB current limit level selection
0 = High level current limit
SW1ABILIM
0
R/W
0x00
1 = Low level current limit
UNUSED
1
R/W
R/W
0x00
0x00
Unused
SW1A/B switching frequency selector.
See Table 37.
SW1ABFREQ
3:2
SW1A/B phase clock selection.
See Table 35.
SW1ABPHASE
5:4
7:6
R/W
R/W
0x00
0x00
SW1A/B DVS speed selection.
See Table 33.
SW1ABDVSSPEED
Table 47. Register SW1CVOLT - ADDR 0x2E
Name
Bit #
R/W Default
Description
Sets the SW1C output voltage during normal
operation mode. See Table 40 for all possible
configurations.
SW1C
UNUSED
5:0
7:6
R/W
–
0x00
0x00
unused
Table 48. Register SW1CSTBY - ADDR 0x2F
Name
Bit #
R/W Default
Description
Sets the SW1C output voltage during standby
mode. See Table 40 for all possible
configurations.
SW1CSTBY
UNUSED
5:0
7:6
R/W
–
0x00
0x00
unused
Table 49. Register SW1COFF - ADDR 0x30
Name
Bit #
R/W Default
Description
Sets the SW1C output voltage during sleep
mode. See Table 40 for all possible
configurations.
SW1COFF
UNUSED
5:0
7:6
R/W
–
0x00
0x00
unused
Table 50. Register SW1CMODE - ADDR 0x31
Name
Bit #
R/W Default
Description
Sets the SW1C switching operation mode.
See Table 29 for all possible configurations.
SW1CMODE
UNUSED
3:0
4
R/W
–
0x80
0x00
unused
Set status of SW1C when in sleep mode
SW1COMODE
UNUSED
5
R/W
–
0x00
0x00
0 = OFF
1 = PFM
7:6
unused
PF0100Z
NXP Semiconductors
43
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 51. Register SW1CCONF - ADDR 0x32
Name
Bit #
R/W Default
Description
SW1C current limit level selection
0 = High level current limit
1 = Low level current limit
SW1CILIM
0
R/W
0x00
UNUSED
1
R/W
R/W
0x00
0x00
Unused
SW1C switching frequency selector.
See Table 37.
SW1CFREQ
3:2
SW1C phase clock selection.
See Table 35.
SW1CPHASE
5:4
7:6
R/W
R/W
0x00
0x00
SW1C DVS speed selection.
See Table 33.
SW1CDVSSPEED
6.4.4.3.5
SW1A/B/C external components
Table 52. SW1A/B/C external component recommendations
Mode
Components
Description
A/B/C single
phase
A/B single - C
independent mode independent mode
A/B dual - C
(41)
CINSW1A
SW1A input capacitor
4.7 μF
0.1 μF
4.7 μF
0.1 μF
4.7 μF
0.1 μF
6 x 22 μF
–
4.7 μF
0.1 μF
4.7 μF
0.1 μF
(41)
CIN1AHF
SW1A decoupling input capacitor
SW1B input capacitor
(41)
CINSW1B
4.7 μF
4.7 μF
(41)
CIN1BHF
SW1B decoupling input capacitor
SW1C input capacitor
0.1 μF
0.1 μF
(41)
CINSW1C
4.7 μF
4.7 μF
(41)
CIN1CHF
SW1C decoupling input capacitor
SW1A/B output capacitor
SW1C output capacitor
0.1 μF
0.1 μF
(41)
COSW1AB
4 x 22 μF
2 x 22 μF
4 x 22 μF
2 x 22 μF
(41)
COSW1C
1.0 μH
1.0 μH
1.0 μH
LSW1A
SW1A inductor
SW1B inductor
SW1C inductor
DCR = 12 mΩ
ISAT = 6.0 A
DCR = 12 mΩ
ISAT = 4.5 A
DCR = 60 mΩ
ISAT = 2.4 A
1.0 μH
DCR = 60 mΩ
ISAT = 2.4 A
LSW1B
–
–
–
1.0 μH
DCR = 60 mΩ
ISAT = 2.4 A
1.0 μH
DCR = 60 mΩ
ISAT = 2.4 A
LSW1C
Notes
41. Use X5R or X7R capacitors.
PF0100Z
44
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.3.6
SW1A/B/C specifications
Table 53. SW1A/B/C electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V,
ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical
values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless
otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
SW1A/B/C (single phase)
VINSW1A
VINSW1B
VINSW1C
Operating input voltage
2.8
–
–
4.5
–
V
V
VSW1ABC
Nominal output voltage
Output voltage accuracy
Table 40
•
PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1ABC < 4.5 A
-25
-3.0%
–
–
25
3.0%
0.625 V ≤ VSW1ABC ≤ 1.450 V
1.475 V ≤ VSW1ABC ≤ 1.875 V
mV
%
VSW1ABCACC
•
PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW1ABC < 150 mA
-65
-45
-3.0%
–
–
–
65
45
3.0%
0.625 V < VSW1ABC < 0.675 V
0.7 V < VSW1ABC < 0.85 V
0.875 V < VSW1ABC < 1.875 V
Rated output load current,
ISW1ABC
–
–
4500
mA
A
2.8 V < VIN < 4.5 V, 0.625 V < VSW1ABC < 1.875 V
Current limiter peak current detection
•
Current through inductor
SW1ABILIM = 0
ISW1ABCLIM
7.1
5.3
10.5
7.9
13.7
10.3
SW1ABILIM = 1
Start-up overshoot
VSW1ABCOSH
–
–
66
mV
µs
ISW1ABC = 0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1ABC = 1.875 V
Turn-on time
Enable to 90% of end value
ISW1x = 0 mA
tONSW1ABC
–
–
500
DVS clk = 25 mV/4.0 μs, VIN = VINSW1x = 4.5 V,
V
SW1ABC = 1.875 V
Switching frequency
SW1xFREQ[1:0] = 00
SW1xFREQ[1:0] = 01
SW1xFREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
fSW1ABC
MHz
Efficiency
•
VIN = 3.6 V, fSW1ABC = 2.0 MHz, LSW1ABC = 1.0 μH
–
–
–
–
–
–
77
82
86
84
80
70
–
–
–
–
–
–
PFM, 0.9 V, 1.0 mA
PFM, 1.2 V, 50 mA
APS, PWM, 1.2 V, 850 mA
APS, PWM, 1.2 V, 1275 mA
APS, PWM, 1.2 V, 2125 mA
APS, PWM, 1.2 V, 4500 mA
ηSW1ABC
%
ΔVSW1ABC
VSW1ABCLIR
VSW1ABCLOR
Output ripple
–
–
–
10
–
–
mV
mV
mV
Line regulation (APS, PWM)
DC load regulation (APS, PWM)
Transient load regulation
20
20
–
•
Transient load = 0 A to 2.25 A, di/dt = 100 mA/μs
Overshoot
Undershoot
VSW1ABCLOTR
mV
–
–
–
–
50
50
PF0100Z
NXP Semiconductors
45
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 53. SW1A/B/C electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V,
ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical
values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless
otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
SW1A/B/C (single phase) (continued)
Quiescent current
ISW1ABCQ
–
–
18
145
–
–
µA
W
PFM mode
APS mode
RSW1ABCDIS
Discharge resistance
–
600
–
SW1A/B (single/dual phasE)
VINSW1A
VINSW1B
Operating input voltage
2.8
–
–
4.5
–
V
V
VSW1AB
Nominal output voltage
Output voltage accuracy
Table 40
•
PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1AB < 2.5 A
-25
-3.0%
-
-
25
3.0%
0.625 V ≤ VSW1AB ≤ 1.450 V
1.475 V ≤ VSW1AB ≤ 1.875 V
mV
%
VSW1ABACC
•
PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW1AB < 150 mA
-65
-45
-3.0%
–
–
–
-65
-45
3.0%
0.625 V < VSW1AB < 0.675 V
0.7 V < VSW1AB < 0.85 V
0.875 V < VSW1AB < 1.875 V
Rated output load current,
(43)
(43)
ISW1AB
–
–
2500
mA
2.8 V < VIN < 4.5 V, 0.625 V < VSW1AB < 1.875 V
Current limiter peak current detection
•
SW1A/B single phase (current through inductor)
SW1ABILIM = 0
4.5
3.3
6.5
4.9
8.5
6.4
SW1ABILIM = 1
ISW1ABLIM
A
•
SW1A/B dual phase (current through inductor per phase)
SW1ABILIM = 0
2.2
1.6
3.2
2.4
4.3
3.2
SW1ABILIM = 1
Start-up overshoot
VSW1ABOSH
–
–
–
–
66
mV
µs
ISW1AB = 0.0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V
Turn-on time
Enable to 90% of end value
tONSW1AB
500
I
SW1AB = 0.0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V
Switching frequency
–
–
–
1.0
2.0
4.0
–
–
–
SW1ABFREQ[1:0] = 00
SW1ABFREQ[1:0] = 01
SW1ABFREQ[1:0] = 10
fSW1AB
MHz
Efficiency (single phase)
•
VIN = 3.6 V, fSW1AB = 2.0 MHz, LSW1AB = 1.0 μH
–
–
–
–
–
–
82
84
86
87
83
75
–
–
–
–
–
–
PFM, 0.9 V, 1.0 mA
PFM, 1.2 V, 50 mA
APS, PWM, 1.2 V, 500 mA
APS, PWM, 1.2 V, 750 mA
APS, PWM, 1.2 V, 1250 mA
APS, PWM, 1.2 V, 2500 mA
ηSW1AB
%
ΔVSW1AB
Output ripple
–
–
10
–
–
mV
mV
VSW1ABLIR
Line regulation (APS, PWM)
20
PF0100Z
46
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 53. SW1A/B/C electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V,
ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical
values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless
otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
SW1A/B (single/dual phase) (continued)
VSW1ABLOR
DC load regulation (APS, PWM)
–
–
20
mV
Transient load regulation
•
Transient load = 0 A to 1.25 A, di/dt = 100 mA/μs
Overshoot
Undershoot
VSW1ABLOTR
mV
–
–
–
–
50
50
Quiescent current
PFM mode
ISW1ABQ
–
–
18
235
–
–
µA
APS mode
SW1A P-MOSFET RDS(on)
VINSW1A = 3.3 V
RONSW1AP
RONSW1AN
ISW1APQ
–
–
–
–
–
–
–
215
258
–
245
326
7.5
mΩ
mΩ
µA
SW1A N-MOSFET RDS(on)
VINSW1A = 3.3 V
SW1A P-MOSFET leakage current
VINSW1A = 4.5 V
SW1A N-MOSFET leakage current
VINSW1A = 4.5 V
ISW1ANQ
–
2.5
µA
SW1B P-MOSFET RDS(on)
VINSW1B = 3.3 V
RONSW1BP
RONSW1BN
ISW1BPQ
215
258
–
245
326
7.5
mΩ
mΩ
µA
SW1B N-MOSFET RDS(on)
VINSW1B = 3.3 V
SW1B P-MOSFET leakage current
VINSW1B = 4.5 V
SW1B N-MOSFET leakage current
VINSW1B = 4.5 V
ISW1BNQ
–
–
–
2.5
–
µA
W
RSW1ABDIS
Discharge Resistance
600
SW1C (independent)
VINSW1C
VSW1C
Operating input voltage
2.8
–
–
4.5
–
V
V
Nominal output voltage
Table 40
Output voltage accuracy
•
PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1C < 2.0 A
-25
-3.0%
–
–
25
3.0%
0.625 V ≤ VSW1C ≤ 1.450 V
1.475 V ≤ VSW1C ≤ 1.875 V
VSW1CACC
mV
•
PFM, steady state 2.8 V < VIN < 4.5 V, 0 < ISW1C < 50 mA
-65
-45
-3.0%
–
–
–
65
45
3.0%
0.625 V < VSW1C < 0.675 V
0.7 V < VSW1C < 0.85 V
0.875 V < VSW1C < 1.875 V
Rated output load current
ISW1C
–
–
2000
mA
A
2.8 V < VIN < 4.5 V, 0.625 V < VSW1C < 1.875 V
Current limiter peak current detection
•
Current through inductor
SW1CILIM = 0
ISW1CLIM
2.6(42)
1.95
4.0
3.0
5.2
3.9
SW1CILIM = 1
PF0100Z
NXP Semiconductors
47
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 53. SW1A/B/C electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V,
ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical
values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless
otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
66
Unit
mV
µs
Notes
SW1C (independent) (continued)
Start-up overshoot
VSW1COSH
–
–
–
–
ISW1C = 0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW1C = 4.5 V, VSW1C = 1.875 V
Turn-on time
Enable to 90% of end value
SW1C = 0 mA
tONSW1C
500
I
DVS clk = 25 mV/4 μs, VIN = VINSW1C = 4.5 V, VSW1C = 1.875 V
Switching frequency
SW1CFREQ[1:0] = 00
SW1CFREQ[1:0] = 01
SW1CFREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
fSW1C
MHz
Efficiency
•
VIN = 3.6 V, fSW1C = 2.0 MHz, LSW1C = 1.0 μH
–
–
–
–
–
–
77
78
86
84
78
68
–
–
–
–
–
–
PFM, 0.9 V, 1.0 mA
PFM, 1.2 V, 50 mA
APS, PWM, 1.2 V, 400 mA
APS, PWM, 1.2 V, 600 mA
APS, PWM, 1.2 V, 1000 mA
APS, PWM, 1.2 V, 2000 mA
ηSW1C
%
ΔVSW1C
VSW1CLIR
VSW1CLOR
Output ripple
–
–
–
10
–
–
mV
mV
mV
Line regulation (APS, PWM)
DC load regulation (APS, PWM)
Transient load regulation
20
20
–
•
Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/μs
Overshoot
Undershoot
VSW1CLOTR
mV
µA
–
–
–
–
50
50
Quiescent current
PFM mode
ISW1CQ
–
–
22
145
–
–
APS mode
SW1C P-MOSFET RDS(on)
at VINSW1C = 3.3 V
RONSW1CP
RONSW1CN
ISW1CPQ
–
–
–
184
211
–
206
260
10.5
mΩ
mΩ
µA
SW1C N-MOSFET RDS(on)
at VINSW1C = 3.3 V
SW1C P-MOSFET leakage current
VINSW1C = 4.5 V
SW1C N-MOSFET leakage current
VINSW1C = 4.5 V
ISW1CNQ
–
–
–
3.5
–
µA
W
RSW1CDIS
Discharge resistance
600
Notes
42. Supports the Coremark and 3D MM benchmark maximum current value of 2500 mA of the VDD_SOC_IN domain in the i.MX 6Dual/Quad
processors.
43. Current rating of SW1AB supports the power virus mode of operation of the i.MX 6X processor.
PF0100Z
48
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
SW1ABC single phase
Load current (mA)
SW1AB single phase
100
90
80
70
60
50
40
30
20
10
0
PFM - Vout = 1.2V
APS - Vout = 1.2V
PWM - Vout = 1.2v
0.1
1
10
100
1000
Load current (mA)
SW1C independent mode
100
90
80
70
60
50
40
30
20
10
0
PFM - Vout = 1.2V
APS - Vout = 1.2V
PWM - Vout = 1.2v
1
10
100
1000
Load current (mA)
Figure 14. SW1AB and SW1C efficiency waveforms
PF0100Z
NXP Semiconductors
49
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.4
SW2
SW2 is a single phase, 2.0 A rated buck regulator (2.5 A in NP/F9/FA versions). Table 29 describes the modes, and Table 30 show the
options for the SWxMODE[3:0] bits. Figure 15 shows the block diagram and the external component connections for SW2 regulator.
VIN
SW2IN
SW2MODE
ISENSE
CINSW2
Controller
SW2
SW2LX
EP
Driver
LSW2
COSW2
SW2FAULT
I2C
Interface
Internal
I2C
Compensation
Z2
SW2FB
Z1
VREF
EA
DAC
Figure 15. SW2 block diagram
6.4.4.4.1
SW2 setup and control registers
SW2 output voltage is programmable from 0.400 V to 3.300 V; however, bit SW2[6] in register SW2VOLT is read-only during normal
operation. Its value is determined by the default configuration, or may be changed by using the OTP registers. Therefore, once SW2[6] is
set to “0”, the output is limited to the lower output voltages from 0.400 V to 1.975 V with 25 mV increments, as determined by bits SW2[5:0].
Likewise, once bit SW2[6] is set to “1”, the output voltage is limited to the higher output voltage range from 0.800 V to 3.300 V with 50 mV
increments, as determined by bits SW2[5:0].
To optimize the performance of the regulator, it is recommended that only voltages from 2.000 V to 3.300 V be used in the high range,
and the lower range be used for voltages from 0.400 V to 1.975 V.
The output voltage set point is independently programmed for normal, standby, and sleep mode by setting the SW2[5:0], SW2STBY[5:0]
and SW2OFF[5:0] bits, respectively. However, the initial state of bit SW2[6] is copied into bits SW2STBY[6], and SW2OFF[6] bits.
Therefore, the output voltage range remains the same in all three operating modes. Table 54 shows the output voltage coding valid for
SW2.
Note: Voltage set points of 0.6 V and below are not supported.
Table 54. SW2 output voltage configuration
Low output voltage range(44)
High output voltage range
Set Point
SW2[6:0]
SW2 Output
Set Point
SW2[6:0]
SW2 Output
0
1
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0.4000
0.4250
0.4500
0.4750
0.5000
0.5250
0.5500
0.5750
0.6000
0.6250
0.6500
0.6750
0.7000
64
65
66
67
68
69
70
71
72
73
74
75
76
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
0.8000
0.8500
0.9000
0.9500
1.0000
1.0500
1.1000
1.1500
1.2000
1.2500
1.3000
1.3500
1.4000
2
3
4
5
6
7
8
9
10
11
12
PF0100Z
50
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 54. SW2 output voltage configuration (continued)
Low output voltage range(44)
High output voltage range
Set Point
SW2[6:0]
SW2 Output
Set Point
SW2[6:0]
SW2 Output
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0.7250
0.7500
0.7750
0.8000
0.8250
0.8500
0.8750
0.9000
0.9250
0.9500
0.9750
1.0000
1.0250
1.0500
1.0750
1.1000
1.1250
1.1500
1.1750
1.2000
1.2250
1.2500
1.2750
1.3000
1.3250
1.3500
1.3750
1.4000
1.4250
1.4500
1.4750
1.5000
1.5250
1.5500
1.5750
1.6000
1.6250
1.6500
1.6750
1.7000
1.7250
77
78
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1.4500
1.5000
1.5500
1.6000
1.6500
1.7000
1.7500
1.8000
1.8500
1.9000
1.9500
2.0000
2.0500
2.1000
2.1500
2.2000
2.2500
2.3000
2.3500
2.4000
2.4500
2.5000
2.5500
2.6000
2.6500
2.7000
2.7500
2.8000
2.8500
2.9000
2.9500
3.0000
3.0500
3.1000
3.1500
3.2000
3.2500
3.3000
Reserved
Reserved
Reserved
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
PF0100Z
NXP Semiconductors
51
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 54. SW2 output voltage configuration (continued)
Low output voltage range(44)
High output voltage range
Set Point
SW2[6:0]
SW2 Output
Set Point
SW2[6:0]
SW2 Output
54
55
56
57
58
59
60
61
62
63
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1.7500
1.7750
1.8000
1.8250
1.8500
1.8750
1.9000
1.9250
1.9500
1.9750
118
119
120
121
122
123
124
125
126
127
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes
44. For voltages less than 2.0 V, only use set points 0 to 63.
Setup and control of SW2 is done through I2C registers listed in Table 55, and a detailed description of each one of the registers is provided
in Tables 56 to Table 60.
Table 55. SW2 register summary
Register
SW2VOLT
Address
Description
0x35
0x36
0x37
0x38
0x39
Output voltage set point on normal operation
Output voltage set point on standby
Output voltage set point on sleep
SW2STBY
SW2OFF
SW2MODE
SW2CONF
Switching mode selector register
DVS, phase, frequency, and ILIM configuration
Table 56. Register SW2VOLT - ADDR 0x35
Name
Bit #
R/W Default
Description
Sets the SW2 output voltage during normal operation
mode. See Table 54 for all possible configurations.
SW2
SW2
5:0
R/W
0x00
Sets the operating output voltage range for SW2. Set
during OTP or TBB configuration only. See Table 54
for all possible configurations.
6
7
R
–
0x00
0x00
UNUSED
unused
Table 57. Register SW2STBY - ADDR 0x36
Name
SW2STBY
Bit #
R/W Default
Description
Sets the SW2 output voltage during standby mode.
See Table 54 for all possible configurations.
5:0
R/W
0x00
Sets the operating output voltage range for SW2 on
standby mode. This bit inherits the value configured
on bit SW2[6] during OTP or TBB configuration. See
Table 54 for all possible configurations.
SW2STBY
UNUSED
6
7
R
–
0x00
0x00
unused
PF0100Z
52
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 58. Register SW2OFF - ADDR 0x37
Name
SW2OFF
Bit #
R/W Default
Description
Sets the SW2 output voltage during sleep mode. See
Table 54 for all possible configurations.
5:0
R/W
0x00
Sets the operating output voltage range for SW2 on
sleep mode. This bit inherits the value configured on
bit SW2[6] during OTP or TBB configuration. See
Table 54 for all possible configurations.
SW2OFF
UNUSED
6
7
R
–
0x00
0x00
unused
Table 59. Register SW2MODE - ADDR 0x38
Name
SW2MODE
Bit #
R/W Default
Description
Sets the SW2 switching operation mode.
See Table 29 for all possible configurations.
3:0
4
R/W
–
0x80
0x00
UNUSED
unused
Set status of SW2 when in sleep mode
SW2OMODE
UNUSED
5
R/W
–
0x00
0x00
0 = OFF
1 = PFM
7:6
unused
Table 60. Register SW2CONF - ADDR 0x39
Name
Bit #
R/W Default
Description
SW2 current limit level selection (45)
0 = High level current limit
SW2ILIM
0
R/W
0x00
1 = Low level current limit
UNUSED
1
R/W
R/W
0x00
0x00
unused
SW2 switching frequency selector.
See Table 37.
SW2FREQ
3:2
SW2 phase clock selection.
See Table 35.
SW2PHASE
5:4
7:6
R/W
R/W
0x00
0x00
SW2 DVS speed selection.
See Table 34.
SW2DVSSPEED
Notes
45. SW2ILIM = 0 must be used in NP/F9/FA versions if 2.5 A output load current is desired
6.4.4.4.2
SW2 external components
Table 61. SW2 external component recommendations
Components
Description
SW2 input capacitor
Values
(46)
CINSW2
4.7 μF
0.1 μF
(46)
CIN2HF
SW2 decoupling input capacitor
SW2 output capacitor
(46)
COSW2
2 x 22 μF
1.0 μH
LSW2
SW2 inductor
DCR = 50 mΩ
ISAT = 2.65 A
Notes
46. Use X5R or X7R capacitors.
PF0100Z
NXP Semiconductors
53
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.4.3
SW2 specifications
Table 62. SW2 electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V,
ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values
are characterized at VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], and 25 °C, unless otherwise
noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Switch mode supply SW2
(47)
VINSW2
VSW2
Operating input voltage
2.8
–
–
4.5
–
V
V
Nominal output voltage
Table 54
Output voltage accuracy
•
•
PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW2 < 2.0 A
-25
-3.0%
-6.0%
–
–
–
25
3.0%
6.0%
0.625 V < VSW2 < 0.85 V
0.875 V < VSW2 < 1.975 V
2.0 V < VSW2 < 3.3 V
mV
%
VSW2ACC
PFM, 2.8 V < VIN < 4.5 V, 0 < ISW2 ≤ 50 mA
-65
-45
-3.0%
-3.0%
–
–
–
–
65
45
3.0%
3.0%
0.625 V < VSW2 < 0.675 V
0.7 V < VSW2 < 0.85 V
0.875 V < VSW2 < 1.975 V
2.0 V < VSW2 < 3.3 V
Rated output load current
(48)
(49)
ISW2
• 2.8 V < VIN < 4.5 V, 0.625 V < VSW2 < 3.3 V
• 2.8 V < VIN < 4.5 V, 1.2 V < VSW2 < 3.3 V, SW2LIM = 0
–
–
–
–
2000
2500
mA
A
Current limiter peak current detection
•
Current through inductor
SW2ILIM = 0
SW2ILIM = 1
ISW2LIM
VSW2OSH
tONSW2
2.8
2.1
4.0
3.0
5.2
3.9
Start-up overshoot
–
–
–
–
66
mV
µs
ISW2 = 0.0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW2 = 4.5 V
Turn-on time
Enable to 90% of end value
550
I
SW2 = 0.0 mA
DVS clk = 50 mV/8 μs, VIN = VINSW2 = 4.5 V
Switching frequency
SW2FREQ[1:0] = 00
SW2FREQ[1:0] = 01
SW2FREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
fSW2
MHz
Efficiency
•
VIN = 3.6 V, fSW2 = 2.0 MHz, LSW2 = 1.0 μH
–
–
–
–
–
–
94
95
96
94
92
88
–
–
–
–
–
–
PFM, 3.15 V, 1.0 mA
PFM, 3.15 V, 50 mA
APS, PWM, 3.15 V, 400 mA
APS, PWM, 3.15 V, 600 mA
APS, PWM, 3.15 V, 1000 mA
APS, PWM, 3.15 V, 2000 mA
ηSW2
%
ΔVSW2
VSW2LIR
VSW2LOR
Output ripple
–
–
–
10
–
–
mV
mV
mV
Line regulation (APS, PWM)
DC load regulation (APS, PWM)
Transient load regulation
20
20
–
•
Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/μs
Overshoot
Undershoot
VSW2LOTR
mV
–
–
–
–
50
50
PF0100Z
54
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 62. SW2 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V,
ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values
are characterized at VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], and 25 °C, unless otherwise
noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Switch mode supply SW2 (continued)
Quiescent current
–
–
–
23
145
305
–
–
–
PFM mode
APS mode (low output voltage settings)
APS mode (high output voltage settings)
ISW2Q
µA
SW2 P-MOSFET RDS(on)
at VIN = VINSW2 = 3.3 V
RONSW2P
RONSW2N
ISW2PQ
–
–
–
190
212
–
209
255
12
mΩ
mΩ
µA
SW2 N-MOSFET RDS(on)
at VIN = VINSW2 = 3.3 V
SW2 P-MOSFET leakage current
VIN = VINSW2 = 4.5 V
SW2 N-MOSFET leakage current
VIN = VINSW2 = 4.5 V
ISW2NQ
–
–
–
4.0
–
µA
W
RSW2DIS
Discharge resistance
600
Notes
47. When output is set to > 2.6 V the output will follow the input down when VIN gets near 2.8 V.
48. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation:
(VINSW2 - VSW2) = ISW2* (DCR of Inductor +RONSW2P + PCB trace resistance).
49. Applies to NP/F9/FA versions
100
90
80
70
60
50
40
30
20
PFM- Vout = 3.15V
APS - Vout = 3.15V
PWM- Vout = 3.15V
10
0
0.1
1
10
100
1000
Load current (mA)
Figure 16. SW2 efficiency waveforms
PF0100Z
NXP Semiconductors
55
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.5
SW3A/B
SW3A/B are 1.25 A to 2.5 A rated buck regulators, depending on the configuration. Table 29 describes the available switching modes and
Table 30 show the actual configuration options for the SW3xMODE[3:0] bits.
SW3A/B can be configured in various phasing schemes, depending on the desired cost/performance trade-offs. The following
configurations are available:
• A single phase
• A dual phase
• Independent regulators
The desired configuration is programmed in OTP by using the SW3_CONFIG[1:0] bits.Table 63 shows the options for the SW3CFG[1:0]
bits.
Table 63. SW3 configuration
SW3_CONFIG[1:0]
Description
00
01
10
11
A/B single phase
A/B single phase
A/B dual phase
A/B independent
6.4.4.5.1
SW3A/B single phase
In this configuration, SW3ALX and SW3BLX are connected in single phase with a single inductor a shown in Figure 17. This configuration
reduces cost and component count. Feedback is taken from the SW3AFB pin and the SW3BFB pin must be left open. Although control is
from SW3A, registers of both regulators, SW3A and SW3B, must be identically set.
VIN
SW3AIN
SW3ALX
SW3AMODE
ISENSE
CINSW3A
Controller
SW3
Driver
LSW3A
COSW3A
SW3AFAULT
Internal
I2C
Compensation
Z2
SW3AFB
SW3BIN
I2C
Interface
Z1
VREF
EA
DAC
VIN
SW3BMODE
ISENSE
CINSW3B
Controller
SW3BLX
Driver
SW3BFAULT
EP
I2C
Internal
Compensation
Z2
VREF
SW3BFB
Z1
DAC
EA
Figure 17. SW3A/B single phase block diagram
PF0100Z
56
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.5.2
SW3A/B dual phase
SW3A/B can be connected in dual phase configuration using one inductor per switching node, as shown in Figure 18. This mode allows
a smaller output voltage ripple. Feedback is taken from pin SW3AFB and pin SW3BFB must be left open. Although control is from SW3A,
registers of both regulators, SW3A and SW3B, must be identically set. In this configuration, the regulators switch 180 degrees apart.
VIN
SW3AIN
SW3ALX
SW3AMODE
ISENSE
CINSW3A
Controller
SW3
Driver
LSW3A
COSW3A
SW3AFAULT
Internal
I2C
Compensation
Z2
I2C
Interface
SW3AFB
SW3BIN
Z1
VREF
EA
DAC
VIN
SW3BMODE
ISENSE
CINSW3B
Controller
SW3BLX
EP
Driver
LSW3B
COSW3B
SW3BFAULT
I2C
Internal
Compensation
Z2
VREF
SW3BFB
Z1
DAC
EA
Figure 18. SW3A/B dual phase block diagram
6.4.4.5.3
SW3A - SW3B independent outputs
SW3A and SW3B can be configured as independent outputs as shown in Figure 19, providing flexibility for applications requiring more
voltage rails with less current capability. Each output is configured and controlled independently by its respective I2C registers as shown
in Table 65.
PF0100Z
NXP Semiconductors
57
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VIN
SW3AIN
SW3AMODE
ISENSE
CINSW3A
Controller
SW3A
SW3ALX
Driver
LSW3A
COSW3A
SW3AFAULT
Internal
I2C
Compensation
Z2
SW3AFB
Z1
VREF
EA
DAC
VIN
I2C
Interface
SW3BIN
SW3BMODE
ISENSE
CINSW3B
Controller
SW3B
SW3BLX
Driver
LSW3B
COSW3B
SW3BFAULT
EP
Internal
I2C
Compensation
Z2
SW3BFB
Z1
VREF
EA
DAC
Figure 19. SW3A/B independent output block diagram
6.4.4.5.4
SW3A/B setup and control registers
SW3A/B output voltage is programmable from 0.400 V to 3.300 V; however, bit SW3x[6] in register SW3xVOLT is read-only during normal
operation. Its value is determined by the default configuration, or may be changed by using the OTP registers. Therefore, once SW3x[6]
is set to “0”, the output is limited to the lower output voltages from 0.40 V to 1.975 V with 25 mV increments, as determined by bits
SW3x[5:0]. Likewise, once bit SW3x[6] is set to "1", the output voltage is limited to the higher output voltage range from 0.800 V to 3.300 V
with 50 mV increments, as determined by bits SW3x[5:0].
In order to optimize the performance of the regulator, it is recommended that only voltages from 2.00 to 3.300 V be used in the high range
and the lower range be used for voltages from 0.400 V to 1.975 V.
The output voltage set point is independently programmed for normal, standby, and sleep mode by setting the SW3x[5:0],
SW3xSTBY[5:0], and SW3xOFF[5:0] bits respectively; however, the initial state of the SW3x[6] bit is copied into the SW3xSTBY[6] and
SW3xOFF[6] bits. Therefore, the output voltage range remains the same on all three operating modes. Table 64 shows the output voltage
coding valid for SW3x.
Note: Voltage set points of 0.6 V and below are not supported.
Table 64. SW3A/B output voltage configuration
Low output voltage range(50)
High output voltage range
Set point
SW3x[6:0]
SW3x output
Set point
SW3x[6:0]
sw3x output
0
1
2
3
4
0000000
0000001
0000010
0000011
0000100
0.4000
0.4250
0.4500
0.4750
0.5000
64
65
66
67
68
1000000
1000001
1000010
1000011
1000100
0.8000
0.8500
0.9000
0.9500
1.0000
PF0100Z
58
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 64. SW3A/B output voltage configuration (continued)
Low output voltage range(50)
High output voltage range
Set point
SW3x[6:0]
SW3x output
Set point
SW3x[6:0]
sw3x output
5
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0.5250
0.5500
0.5750
0.6000
0.6250
0.6500
0.6750
0.7000
0.7250
0.7500
0.7750
0.8000
0.8250
0.8500
0.8750
0.9000
0.9250
0.9500
0.9750
1.0000
1.0250
1.0500
1.0750
1.1000
1.1250
1.1500
1.1750
1.2000
1.2250
1.2500
1.2750
1.3000
1.3250
1.3500
1.3750
1.4000
1.4250
1.4500
1.4750
1.5000
1.5250
69
70
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1.0500
1.1000
1.1500
1.2000
1.2500
1.3000
1.3500
1.4000
1.4500
1.5000
1.5500
1.6000
1.6500
1.7000
1.7500
1.8000
1.8500
1.9000
1.9500
2.0000
2.0500
2.1000
2.1500
2.2000
2.2500
2.3000
2.3500
2.4000
2.4500
2.5000
2.5500
2.6000
2.6500
2.7000
2.7500
2.8000
2.8500
2.9000
2.9500
3.0000
3.0500
6
7
71
8
72
9
73
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
PF0100Z
NXP Semiconductors
59
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 64. SW3A/B output voltage configuration (continued)
Low output voltage range(50)
High output voltage range
Set point
SW3x[6:0]
SW3x output
Set point
SW3x[6:0]
sw3x output
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1.5500
1.5750
1.6000
1.6250
1.6500
1.6750
1.7000
1.7250
1.7500
1.7750
1.8000
1.8250
1.8500
1.8750
1.9000
1.9250
1.9500
1.9750
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
3.1000
3.1500
3.2000
3.2500
3.3000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes
50. For voltages less than 2.0 V, only use set points 0 to 63.
Table 65 provides a list of registers used to configure and operate SW3A/B. A detailed description on each of these register is provided
on Tables 66 through Table 75.
Table 65. SW3AB register summary
Register
SW3AVOLT
Address
Output
0x3C
0x3D
0x3E
0x3F
0x40
0x43
0x44
0x45
0x46
0x47
SW3A output voltage set point on normal operation
SW3A output voltage set point on standby
SW3A output voltage set point on sleep
SW3ASTBY
SW3AOFF
SW3AMODE
SW3ACONF
SW3BVOLT
SW3BSTBY
SW3BOFF
SW3A switching mode selector register
SW3A DVS, phase, frequency and ILIM configuration
SW3B output voltage set point on normal operation
SW3B output voltage set point on standby
SW3B output voltage set point on sleep
SW3BMODE
SW3BCONF
SW3B switching mode selector register
SW3B DVS, phase, frequency and ILIM configuration
PF0100Z
60
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 66. Register SW3AVOLT - ADDR 0x3C
Name
Bit #
R/W Default
Description
Sets the SW3A output voltage (Independent) or
SW3A/B output voltage (single/dual phase),
during normal operation mode. See Table 64 for
all possible configurations.
SW3A
SW3A
5:0
R/W
0x00
Sets the operating output voltage range for SW3A
(independent) or SW3A/B (single/dual phase).
Set during OTP or TBB configuration only. See
Table 64 for all possible configurations.
6
7
R
–
0x00
0x00
UNUSED
unused
Table 67. Register SW3ASTBY - ADDR 0x3D
Name
Bit #
R/W Default
Description
Sets the SW3A output voltage (independent) or
SW3A/B output voltage (single/dual phase),
during standby mode. See Table 64 for all
possible configurations.
SW3ASTBY
5:0
R/W
0x00
Sets the operating output voltage range for SW3A
(independent) or SW3A/B (single/dual phase) on
standby mode. This bit inherits the value
configured on bit SW3A[6] during OTP or TBB
configuration. See Table 64 for all possible
configurations.
SW3ASTBY
UNUSED
6
7
R
–
0x00
0x00
unused
Table 68. Register SW3AOFF - ADDR 0x3E
Name
Bit #
R/W Default
Description
Sets the SW3A output voltage (independent) or
SW3A/B output voltage (single/dual phase),
during sleep mode. See Table 64 for all possible
configurations.
SW3AOFF
5:0
R/W
0x00
Sets the operating output voltage range for SW3A
(independent) or SW3A/B (single/dual phase) on
sleep mode. This bit inherits the value configured
on bit SW3A[6] during OTP or TBB configuration.
See Table 64 for all possible configurations.
SW3AOFF
UNUSED
6
7
R
–
0x00
0x00
unused
Table 69. Register SW3AMODE - ADDR 0x3F
Name
Bit #
R/W Default
Description
Sets the SW3A (Independent) or SW3A/B (single/
dual phase) switching operation mode.
See Table 29 for all possible configurations.
SW3AMODE
UNUSED
3:0
4
R/W
–
0x80
0x00
unused
Set status of SW3A (independent) or SW3A/B
(single/dual phase) when in sleep mode.
SW3AOMODE
UNUSED
5
R/W
–
0x00
0x00
0 = OFF
1 = PFM
7:6
unused
PF0100Z
NXP Semiconductors
61
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 70. Register SW3ACONF - ADDR 0x40
Name
Bit #
R/W Default
Description
SW3A current limit level selection
0 = High level current limit
1 = Low level current limit
SW3AILIM
0
R/W
0x00
UNUSED
1
R/W
R/W
0x00
0x00
unused
SW3A switching frequency selector. See
Table 37.
SW3AFREQ
3:2
SW3APHASE
5:4
7:6
R/W
R/W
0x00
0x00
SW3A phase clock selection. See Table 35.
SW3A DVS speed selection. See Table 34.
SW3ADVSSPEED
Table 71. Register SW3BVOLT - ADDR 0x43
Name
Bit #
R/W Default
Description
Sets the SW3B output voltage (independent)
during normal operation mode. See Table 64 for
all possible configurations.
SW3B
SW3B
5:0
R/W
0x00
Sets the operating output voltage range for SW3B
(independent). Set during OTP or TBB
configuration only. See Table 64 for all possible
configurations.
6
7
R
–
0x00
0x00
UNUSED
unused
Table 72. Register SW3BSTBY - ADDR 0x44
Name
Bit #
R/W Default
Description
Sets the SW3B output voltage (Independent)
during standby mode. See Table 64 for all
possible configurations.
SW3BSTBY
5:0
R/W
0x00
Sets the operating output voltage range for SW3B
(independent) on standby mode. This bit inherits
the value configured on bit SW3B[6] during OTP
or TBB configuration. See Table 64 for all
possible configurations.
SW3BSTBY
UNUSED
6
7
R
–
0x00
0x00
unused
Table 73. Register SW3BOFF - ADDR 0x45
Name
Bit #
R/W Default
Description
Sets the SW3B output voltage (independent)
during sleep mode. See Table 64 for all possible
configurations.
SW3BOFF
5:0
R/W
0x00
Sets the operating output voltage range for SW3B
(independent) on sleep mode. This bit inherits the
value configured on bit SW3B[6] during OTP or
TBB configuration. See Table 64 for all possible
configurations.
SW3BOFF
UNUSED
6
7
R
–
0x00
0x00
unused
PF0100Z
62
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 74. Register SW3BMODE - ADDR 0x46
Name
Bit #
R/W Default
Description
Sets the SW3B (Independent) switching
operation mode. See Table 29 for all possible
configurations.
SW3BMODE
UNUSED
3:0
4
R/W
–
0x80
0x00
unused
Set status of SW3B (Independent) when in sleep
mode.
SW3BOMODE
UNUSED
5
R/W
–
0x00
0x00
0 = OFF
1 = PFM
7:6
unused
Table 75. Register SW3BCONF - ADDR 0x47
Name
Bit #
R/W Default
Description
SW3B current limit level selection
0 = High level current limit
1 = Low level current limit
SW3BILIM
0
R/W
0x00
UNUSED
1
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
unused
SW3BFREQ
SW3BPHASE
SW3BDVSSPEED
3:2
5:4
7:6
SW3B switching frequency selector. See Table 37.
SW3B phase clock selection. See Table 35.
SW3B DVS speed selection. See Table 34.
6.4.4.5.5
SW3A/B external components
Table 76. SW3A/B external component requirements
Mode
SW3A/B single
phase
SW3A/B dual
phase
SW3A independent
SW3B independent
Components
Description
(51)
CINSW3A
SW3A input capacitor
4.7 μF
0.1 μF
4.7 μF
0.1 μF
4 x 22 μF
–
4.7 μF
0.1 μF
4.7 μF
0.1 μF
(51)
CIN3AHF
SW3A decoupling input capacitor
SW3B input capacitor
(51)
CINSW3B
4.7 μF
4.7 μF
(51)
CIN3BHF
SW3B decoupling input capacitor
SW3A output capacitor
0.1 μF
0.1 μF
(51)
COSW3A
2 x 22 μF
2 x 22 μF
2 x 22 μF
2 x 22 μF
(51)
COSW3B
SW3B output capacitor
1.0 μH
1.0 μH
1.0 μH
LSW3A
SW3A inductor
SW3B inductor
DCR = 50 mΩ
ISAT = 3.9 A
DCR = 60 mΩ
ISAT = 3.0 A
DCR = 60 mΩ
ISAT = 3.0 A
1.0 μH
DCR = 60 mΩ
ISAT = 3.0 A
1.0 μH
DCR = 60 mΩ
ISAT = 3.0 A
LSW3B
Notes
–
51. Use X5R or X7R capacitors.
PF0100Z
NXP Semiconductors
63
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.5.6
SW3A/B specifications
Table 77. SW3A/B electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V,
ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single/dual phase and independent
mode, unless otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA,
SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Switch mode supply SW3a/B
(52)
VINSW3x
VSW3x
Operating input voltage
2.8
-
–
4.5
-
V
V
Nominal output voltage
Table 64
Output voltage accuracy
•
•
PWM, APS 2.8 V < VIN < 4.5 V, 0 < ISW3x < ISW3xMAX
-25
-3.0%
-6.0%
–
–
–
25
3.0%
6.0%
0.625 V < VSW3x < 0.85 V
0.875 V < VSW3x < 1.975 V
2.0 V < VSW3x < 3.3 V
mV
%
VSW3xACC
PFM , steady state (2.8 V < VIN < 4.5 V, 0 < ISW3x < 50 mA)
-65
-45
-3.0%
-3.0%
–
–
–
–
65
45
3.0%
3.0%
0.625 V < VSW3x < 0.675 V
0.7 V < VSW3x < 0.85 V
0.875 V < VSW3x < 1.975 V
2.0 V < VSW3x < 3.3 V
Rated output load current
•
2.8 V < VIN < 4.5 V, 0.625 V < VSW3x < 3.3 V
(53)
ISW3x
mA
–
–
–
–
2500
1250
PWM, APS mode single/dual phase
PWM, APS mode independent (per phase)
Current limiter peak current detection
•
Single phase (current through inductor)
SW3xILIM = 0
SW3xILIM = 1
3.5
2.7
5.0
3.8
6.5
4.9
ISW3xLIM
A
•
Independent mode or dual phase (current through inductor per
phase)
SW3xILIM = 0
SW3xILIM = 1
1.8
1.3
2.5
1.9
3.3
2.5
Start-up overshoot
VSW3xOSH
–
–
–
–
66
mV
µs
ISW3x = 0.0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V
Turn-on time
Enable to 90% of end value
tONSW3x
500
I
SW3x = 0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V
Switching frequency
SW3xFREQ[1:0] = 00
SW3xFREQ[1:0] = 01
SW3xFREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
fSW3x
MHz
Efficiency (single phase)
•
fSW3 = 2.0 MHz, LSW3x 1.0 μH
–
–
–
–
–
–
84
85
89
89
85
80
–
–
–
–
–
–
PFM, 1.5 V, 1.0 mA
PFM, 1.5 V, 50 mA
APS, PWM 1.5 V, 500 mA
APS, PWM 1.5 V, 750 mA
APS, PWM 1.5 V, 1250 mA
APS, PWM 1.5 V, 2500 mA
ηSW3AB
%
ΔVSW3x
Output ripple
–
10
–
mV
PF0100Z
64
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 77. SW3A/B electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V,
ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single/dual phase and independent
mode, unless otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA,
SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Switch mode supply SW3a/B (continued)
VSW3xLIR
VSW3xLOR
Line regulation (APS, PWM)
–
–
–
–
20
20
mV
mV
DC load regulation (APS, PWM)
Transient load regulation
•
Transient load = 0.0 mA to ISW3x/2, di/dt = 100 mA/μs
Overshoot
Undershoot
VSW3xLOTR
mV
–
–
–
–
50
50
Quiescent current
–
–
–
–
–
22
300
50
250
150
–
–
–
–
–
PFM mode (single/dual phase)
APS mode (single/dual phase)
PFM mode (independent mode)
APS mode (SW3A independent mode)
APS mode (SW3B independent mode)
ISW3xQ
µA
SW3A P-MOSFET RDS(on)
at VIN = VINSW3A = 3.3 V
RONSW3AP
RONSW3AN
ISW3APQ
–
–
–
–
–
–
–
215
258
–
245
326
7.5
mΩ
mΩ
µA
SW3A N-MOSFET RDS(on)
at VIN = VINSW3A = 3.3 V
SW3A P-MOSFET leakage current
VIN = VINSW3A = 4.5 V
SW3A N-MOSFET leakage current
VIN = VINSW3A = 4.5 V
ISW3ANQ
–
2.5
µA
SW3B P-MOSFET RDS(on)
at VIN = VINSW3B = 3.3 V
RONSW3BP
RONSW3BN
ISW3BPQ
215
258
–
245
326
7.5
mΩ
mΩ
µA
SW3B N-MOSFET RDS(on)
at VIN = VINSW3B = 3.3 V
SW3B P-MOSFET leakage current
VIN = VINSW3B = 4.5 V
SW3B N-MOSFET leakage current
VIN = VINSW3B = 4.5 V
ISW3BPQ
–
–
–
2.5
–
µA
W
RSW3xDIS
Discharge resistance
600
Notes
52. When output is set to > 2.6 V the output will follow the input down when VIN gets near 2.8 V.
53. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation:
(VINSW3x - VSW3x) = ISW3x* (DCR of Inductor +RONSW3xP + PCB trace resistance).
PF0100Z
NXP Semiconductors
65
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
100
90
80
70
60
50
40
30
20
10
0
PFM- Vout = 1.5V
APS - Vout = 1.5V
PWM- Vout = 1.5V
0.1
1
10
100
1000
Load current (mA)
Figure 20. SW3AB single phase efficiency waveforms
6.4.4.6
SW4
SW4 is a 1.0 A rated single phase buck regulator capable of operating in two modes. In its default mode, it operates as a normal buck
regulator with a programmable output between 0.400 V and 3.300 V. It is capable of operating in the three available switching modes:
PFM, APS, and PWM, described on Table 29 and configured by the SW4MODE[3:0] bits, as shown in Table 30.
If the system requires DDR memory termination, SW4 can be used in its VTT mode. In the VTT mode, its reference voltage tracks the
output voltage of SW3A, scaled by 0.5. Furthermore, when in VTT mode, only the PWM switching mode is allowed. The VTT mode can
be configured by use of VTT bit in the OTP_SW4_CONFIG register.
Figure 21 shows the block diagram and the external component connections for the SW4 regulator.
VIN
SW4IN
SW4MODE
ISENSE
CINSW4
Controller
SW4
SW4LX
EP
Driver
LSW4
COSW4
SW4FAULT
I2C
Interface
Internal
I2C
Compensation
Z2
SW4FB
Z1
VREF
EA
DAC
Figure 21. SW4 block diagram
6.4.4.6.1
SW4 setup and control registers
To set the SW4 in regulator or VTT mode, bit VTT of the register OTP_SW4_CONF register on Table 136. Extended page 1, page 106,
is programmed during OTP or TBB configuration; setting bit VTT to “1” enables SW4 to operate in VTT mode and “0” in Regulator mode.
See 6.1.2 One time programmability (OTP), page 20 for detailed information on OTP configuration.
In regulator mode, the SW4 output voltage is programmable from 0.400 V to 3.300 V; however, bit SW4[6] in the SW4VOLT register is
read-only during normal operation. Its value is determined by the default configuration, or may be changed by using the OTP registers.
Once SW4[6] is set to “0”, the output is limited to the lower output voltages, from 0.400 V to 1.975 V with 25 mV increments, as determined
by the SW4[5:0] bits. Likewise, once the SW4[6] bit is set to "1", the output voltage is limited to the higher output voltage range from 0.800 V
to 3.300 V with 50 mV increments, as determined by the SW4[5:0] bits.
PF0100Z
66
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
To optimize the performance of the regulator, it is recommended that only voltages from 2.000 V to 3.300 V be used in the high range and
that that the lower range be used for voltages from 0.400 V to 1.975 V.
The output voltage set point is independently programmed for normal, standby, and sleep mode by setting the SW4[5:0], SW4STBY[5:0],
and SW4OFF[5:0] bits, respectively. However, the initial state of the SW4[6] bit is copied into bits SW4STBY[6], and SW4OFF[6] bits, so
the output voltage range remains the same on all three operating modes. Table 78 shows the output voltage coding valid for SW4.
Note: Voltage set points of 0.6 V and below are not supported, except in VTT mode.
Table 78. SW4 output voltage configuration
Low output voltage range(54)
High output voltage range
Set Point
SW4[6:0]
SW4 output
Set Point
SW4[6:0]
SW4 output
0
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0.4000
0.4250
0.4500
0.4750
0.5000
0.5250
0.5500
0.5750
0.6000
0.6250
0.6500
0.6750
0.7000
0.7250
0.7500
0.7750
0.8000
0.8250
0.8500
0.8750
0.9000
0.9250
0.9500
0.9750
1.0000
1.0250
1.0500
1.0750
1.1000
1.1250
1.1500
1.1750
1.2000
1.2250
1.2500
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
0.8000
0.8500
0.9000
0.9500
1.0000
1.0500
1.1000
1.1500
1.2000
1.2500
1.3000
1.3500
1.4000
1.4500
1.5000
1.5500
1.6000
1.6500
1.7000
1.7500
1.8000
1.8500
1.9000
1.9500
2.0000
2.0500
2.1000
2.1500
2.2000
2.2500
2.3000
2.3500
2.4000
2.4500
2.5000
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
PF0100Z
NXP Semiconductors
67
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 78. SW4 output voltage configuration (continued)
Low output voltage range(54)
High output voltage range
Set Point
SW4[6:0]
SW4 output
Set Point
SW4[6:0]
SW4 output
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1.2750
1.3000
1.3250
1.3500
1.3750
1.4000
1.4250
1.4500
1.4750
1.5000
1.5250
1.5500
1.5750
1.6000
1.6250
1.6500
1.6750
1.7000
1.7250
1.7500
1.7750
1.8000
1.8250
1.8500
1.8750
1.9000
1.9250
1.9500
1.9750
99
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
2.5500
2.6000
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
2.6500
2.7000
2.7500
2.8000
2.8500
2.9000
2.9500
3.0000
3.0500
3.1000
3.1500
3.2000
3.2500
3.3000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes
54. For voltages less than 2.0 V, only use set points 0 to 63.
Full setup and control of SW4 is done through the I2C registers listed on Table 79, and a detailed description of each one of the registers
is provided in Tables 80 to Table 84.
Table 79. SW4 register summary
Register
SW4VOLT
Address
Description
0x4A
0x4B
0x4C
0x4D
0x4E
Output voltage set point on normal operation
Output voltage set point on standby
Output voltage set point on sleep
SW4STBY
SW4OFF
SW4MODE
SW4CONF
Switching mode selector register
DVS, phase, frequency and ILIM configuration
PF0100Z
68
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 80. Register SW4VOLT - ADDR 0x4A
Name
Bit #
R/W Default
Description
Sets the SW4 output voltage during normal
operation mode. See Table 78 for all possible
configurations.
SW4
SW4
5:0
R/W
0x00
Sets the operating output voltage range for SW4.
Set during OTP or TBB configuration only. See
Table 78 for all possible configurations.
6
7
R
–
0x00
0x00
UNUSED
unused
Table 81. Register SW4STBY - ADDR 0x4B
Name
Bit #
R/W Default
Description
Sets the SW4 output voltage during standby
mode. See Table 78 for all possible
configurations.
SW4STBY
5:0
R/W
0x00
Sets the operating output voltage range for SW4
on standby mode. This bit inherits the value
configured on bit SW4[6] during OTP or TBB
configuration. See Table 78 for all possible
configurations.
SW4STBY
UNUSED
6
7
R
–
0x00
0x00
unused
Table 82. Register SW4OFF - ADDR 0x4C
Name
SW4OFF
Bit #
R/W Default
Description
Sets the SW4 output voltage during sleep mode.
See Table 78 for all possible configurations.
5:0
R/W
0x00
Sets the operating output voltage range for SW4
on sleep mode. This bit inherits the value
configured on bit SW4[6] during OTP or TBB
configuration. See Table 78 for all possible
configurations.
SW4OFF
UNUSED
6
7
R
–
0x00
0x00
unused
Table 83. Register SW4MODE - ADDR 0x4D
Name
SW4MODE
Bit #
R/W Default
Description
Sets the SW4 switching operation mode.
See Table 29 for all possible configurations.
3:0
4
R/W
–
0x80
0x00
UNUSED
unused
Set status of SW4 when in sleep mode
SW4OMODE
UNUSED
5
R/W
–
0x00
0x00
0 = OFF
1 = PFM
7:6
unused
PF0100Z
NXP Semiconductors
69
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 84. Register SW4CONF - ADDR 0x4E
Name
Bit #
R/W Default
Description
SW4 current limit level selection
0 = High level Current limit
1 = Low level Current limit
SW4ILIM
0
R/W
0x00
UNUSED
1
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
unused
SW4FREQ
3:2
5:4
7:6
SW4 switching frequency selector. See Table 37.
SW4 phase clock selection. See Table 35.
SW4 DVS speed selection. See Table 34.
SW4PHASE
SW4DVSSPEED
6.4.4.6.2
SW4 external components
Table 85. SW4 external component requirements
Components
Description
SW4 input capacitor
Values
(55)
CINSW4
4.7 μF
0.1 μF
(55)
CIN4HF
SW4 decoupling input capacitor
SW4 output capacitor
(55)
COSW4
2 x 22 μF
1.0 μH
LSW4
SW4 inductor
DCR = 60 mΩ
ISAT = 3.0 A
Notes
55. Use X5R or X7R capacitors.
6.4.4.6.3
SW4 specifications
Table 86. SW4 electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V,
ISW4 = 100 mA, SW4_PWRSTG[2:0] = [101], typical external component values, fSW4 = 2.0 MHz, single/dual phase and independent
mode, unless otherwise noted. Typical values are characterized at VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA,
SW4_PWRSTG[2:0] = [101], and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Switch Mode Supply SW4
(56)
VINSW4
Operating input voltage
2.8
–
4.5
V
V
Nominal output voltage
Normal operation
VTT mode
VSW4
–
–
Table 78
VSW3AFB/2
–
–
Output voltage accuracy
•
PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 1.0 A
-25
-3.0%
-6.0%
–
–
–
25
3.0%
6.0%
0.625 V < VSW4 < 0.85 V
0.875 V < VSW4 < 1.975 V
2.0 V < VSW4 < 3.3 V
mV
%
•
PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 50 mA
VSW4ACC
-65
-45
-3.0%
-3.0%
–
–
–
–
65
45
3.0%
3.0%
0.625 V < VSW4 < 0.675 V
0.7 V < VSW4 < 0.85 V
0.875 V < VSW4 < 1.975 V
2.0 V < VSW4 < 3.3 V
•
VTT mode , 2.8 V < VIN < 4.5 V, 0 < ISW4 < 1.0 A
-40
–
40
PF0100Z
70
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 86. SW4 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V,
ISW4 = 100 mA, SW4_PWRSTG[2:0] = [101], typical external component values, fSW4 = 2.0 MHz, single/dual phase and independent
mode, unless otherwise noted. Typical values are characterized at VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA,
SW4_PWRSTG[2:0] = [101], and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
mA
A
Notes
Switch mode supply SW4 (continued)
Rated output load current
ISW4
(57)
–
–
1000
2.8 V < VIN < 4.5 V, 0.625 V < VSW4 < 3.3 V
Current limiter peak current detection
Current through inductor
SW4ILIM = 0
ISW4LIM
VSW4OSH
tONSW4
1.4
1.0
2.0
1.5
3.0
2.4
SW4ILIM = 1
Start-up overshoot
–
–
–
–
66
mV
µs
ISW4 = 0.0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW4 = 4.5 V
Turn-on time
Enable to 90% of end value
500
I
SW4 = 0.0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW4 = 4.5 V
Switching frequency
SW4FREQ[1:0] = 00
SW4FREQ[1:0] = 01
SW4FREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
fSW4
MHz
Efficiency
•
fSW4 = 2.0 MHz, LSW4 = 1.0 μH
–
–
–
–
–
81
78
87
88
84
–
–
–
–
–
PFM, 1.8 V, 1.0 mA
PFM, 1.8 V, 50 mA
APS, PWM 1.8 V, 200 mA
APS, PWM 1.8 V, 500 mA
APS, PWM 1.8 V, 1000 mA
ηSW4
%
PWM 0.75 V, 200 mA
PWM 0.75 V, 500 mA
PWM 0.75 V, 1000 mA
–
–
–
78
76
66
–
–
–
ΔVSW4
VSW4LIR
VSW4LOR
Output ripple
–
–
–
10
–
–
mV
mV
mV
Line regulation (APS, PWM)
DC load regulation (APS, PWM)
Transient load regulation
20
20
–
•
Transient load = 0.0 mA to 500 mA, di/dt = 100 mA/μs
Overshoot
Undershoot
VSW4LOTR
–
–
–
–
mV
µA
50
50
Quiescent current
PFM mode
ISW4Q
–
–
22
145
–
–
APS mode
SW4 P-MOSFET RDS(on)
at VIN = VINSW4 = 3.3 V
RONSW4P
RONSW4N
ISW4PQ
–
–
–
–
236
293
–
274
378
6.0
mΩ
mΩ
µA
SW4 N-MOSFET RDS(on)
at VIN = VINSW4 = 3.3 V
SW4 P-MOSFET leakage current
VIN = VINSW4 = 4.5 V
SW4 N-MOSFET leakage current
VIN = VINSW4 = 4.5 V
ISW4NQ
–
2.0
µA
PF0100Z
NXP Semiconductors
71
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 86. SW4 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V,
ISW4 = 100 mA, SW4_PWRSTG[2:0] = [101], typical external component values, fSW4 = 2.0 MHz, single/dual phase and independent
mode, unless otherwise noted. Typical values are characterized at VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA,
SW4_PWRSTG[2:0] = [101], and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
RSW4DIS
Discharge Resistance
–
600
–
W
Notes
56. When the output is set to > 2.6 V, the output follows the input down when VIN gets near 2.8 V.
57. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation:
(VINSW4 - VSW4) = ISW4* (DCR of Inductor +RONSW4P + PCB trace resistance).
100
90
80
70
60
50
40
30
PFM- Vout = 1.8V
20
APS - Vout = 1.8V
PWM- Vout = 1.8V
PWM- Vout = 0.75V
10
0
0.1
1
10
100
1000
Load current (mA)
Figure 22. SW4 efficiency waveforms
6.4.5 Boost regulator
SWBST is a boost regulator with a programmable output from 5.0 V to 5.15 V. SWBST can supply the VUSB regulator for the USB PHY
in OTG mode, as well as the VBUS voltage. Note that the parasitic leakage path for a boost regulator causes the SWBSTOUT and
SWBSTFB voltage to be a Schottky drop below the input voltage whenever SWBST is disabled. The switching NMOS transistor is
integrated on-chip. Figure 23 shows the block diagram and component connection for the boost regulator.
PF0100Z
72
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VIN
CINBST
SWBSTIN
SWBSTLX
LBST
DBST
SWBSTMODE
VOBST
Driver
I2C
Interface
OC
SWBSTFAULT
Controller
RSENSE
EP
VREFSC
VREFUV
SC
UV
SWBSTFB
Internal
Compensation
COSWBST
Z2
Z1
EA
VREF
Figure 23. Boost Regulator Architecture
6.4.5.1
SWBST setup and control
Boost regulator control is done through a single register SWBSTCTL described in Table 87. SWBST is included in the power-up sequence
if its OTP power-up timing bits, SWBST_SEQ[4:0], are not all zeros.
Table 87. Register SWBSTCTL - ADDR 0x66
Name
Bit #
R/W
Default
Description
Set the output voltage for SWBST
00 = 5.000 V
SWBST1VOLT
1:0
R/W
0x00
01 = 5.050 V
10 = 5.100 V
11 = 5.150 V
Set the switching mode on normal operation
00 = OFF
SWBST1MODE
UNUSED
3:2
4
R
–
0x02
0x00
0x02
0x00
01 = PFM
10 = Auto (Default)(58)
11 = APS
unused
Set the switching mode on standby
00 = OFF
SWBST1STBYMODE
6:5
7
R/W
–
01 = PFM
10 = Auto (Default)(58)
11 = APS
UNUSED
Notes
unused
58. In auto mode, the controller automatically switches between PFM and APS modes depending on the load current.
The SWBST regulator starts up by default in the auto mode, if SWBST is part of the startup sequence.
PF0100Z
NXP Semiconductors
73
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.5.2
SWBST external components
Table 88. SWBST external component requirements
Components
Description
Values
(59)
CINBST
SWBST input capacitor
SWBST decoupling input capacitor
SWBST output capacitor
SWBST inductor
10 μF
0.1 μF
(59)
CINBSTHF
(59)
COBST
LSBST
DBST
2 x 22 μF
2.2 μH
SWBST boost diode
1.0 A, 20 V Schottky
Notes
59. Use X5R or X7R capacitors.
6.4.5.3
SWBST specifications
Table 89. SWBST electrical specifications
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V,
ISWBST = 100 mA, typical external component values, fSWBST = 2.0 MHz, otherwise noted. Typical values are characterized at
VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted.
Symbol
Parameters
Min.
Typ.
Max.
Units
Notes
Switch mode supply SWBST
VINSWBST
VSWBST
Input voltage range
2.8
–
–
4.5
–
V
V
Nominal output voltage
Table 87
Output voltage accuracy
VSWBSTACC
-4.0
–
–
–
3.0
%
2.8 V ≤ VIN ≤ 4.5 V
0 < ISWBST < ISWBSTMAX
Output ripple
2.8 V ≤ VIN ≤ 4.5 V
0 < ISWBST < ISWBSTMAX, excluding reverse recovery of Schottky
ΔVSWBST
120
mV Vp-p
diode
DC load regulation
VSWBSTLOR
–
–
0.5
50
–
–
mV/mA
mV
0 < ISWBST < ISWBSTMAX
DC line regulation
VSWBSTLIR
2.8 V ≤ VIN ≤ 4.5 V, ISWBST = ISWBSTMAX
Continuous load current
2.8 V ≤ VIN ≤ 3.0 V
3.0 V ≤ VIN ≤ 4.5 V
ISWBST
–
–
–
–
500
600
mA
Quiescent current
auto
ISWBSTQ
–
222
289
μA
RDSONBST
ISWBSTLIM
MOSFET on resistance
Peak current limit
–
206
306
mΩ
(60)
1400
2200
3200
mA
Start-up overshoot
ISWBST = 0.0 mA
VSWBSTOSH
–
–
–
–
500
300
mV
mV
Transient load response
VSWBSTTR
ISWBST from 1.0 mA to 100 mA in 1.0 µs
Maximum transient amplitude
Transient load response
VSWBSTTR
–
–
300
mV
ISWBST from 100 mA to 1.0 mA in 1.0 µs
Maximum transient amplitude
PF0100Z
74
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 89. SWBST electrical specifications (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V,
ISWBST = 100 mA, typical external component values, fSWBST = 2.0 MHz, otherwise noted. Typical values are characterized at
VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted.
Symbol
Parameters
Min.
Typ.
Max.
Units
Notes
Switch mode supply SWBST (continued)
Transient load response
tSWBSTTR
–
–
500
µs
ISWBST from 1.0 mA to 100 mA in 1.0 µs
Time to settle 80% of transient
Transient load response
tSWBSTTR
–
–
–
20
ms
µA
ISWBST from 100 mA to 1.0 mA in 1.0 µs
Time to settle 80% of transient
NMOS Off leakage
ISWBSTHSQ
1.0
5.0
SWBSTIN = 4.5 V, SWBSTMODE [1:0] = 00
Turn-on time
tONSWBST
fSWBST
–
–
–
–
2.0
–
ms
MHz
%
Enable to 90% of VSWBST, ISWBST = 0.0 mA
Switching frequency
2.0
86
Efficiency
ηSWBST
–
ISWBST = ISWBSTMAX
Notes
60. Only in auto mode.
6.4.6 LDO regulators description
This section describes the LDO regulators provided by the PF0100Z. All regulators use the main bandgap as reference. Refer to 6.3 Bias
and references block description, page 23 for further information on the internal reference voltages.
A low-power mode is automatically activated by reducing bias currents when the load current is less than I_Lmax/5. However, the lowest
bias currents may be attained by forcing the part into its low-power mode by setting the VGENxLPWR bit. The use of this bit is only
recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded. When a regulator is
disabled, the output is discharged by an internal pull-down. The pull-down is also activated when RESETBMCU is low.
VINx
VINx
VREF
_
+
VGENxEN
VGENxLPWR
VGENx
VGENx
I2C
Interface
CGENx
VGENx
Discharge
Figure 24. General LDO block diagram
PF0100Z
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.6.1
Transient response waveforms
Idealized stimulus and response waveforms for transient line and transient load tests are depicted in Figure 25. Note that the transient line
and load response refers to the overshoot, or undershoot only, excluding the DC shift.
IL = IMAX/10
IL = IMAX
Overshoot
IMAX
ILOAD
VOUT
IMAX/10
Undershoot
1.0 us
1.0 us
Transient Load Stimulus
VOUT Transient Load Response
VINx_FINAL
VINx_INITIAL
Overshoot
VINx_INITIAL
VOUT
VINx
VINx_FINAL
Undershoot
10 us
10 us
Transient Line Stimulus
VOUT Transient Line Response
Figure 25. Transient waveforms
6.4.6.2
Short-circuit protection
All general purpose LDOs have short-circuit protection capability. The short-circuit protection (SCP) system includes debounced fault
condition detection, regulator shutdown, and processor interrupt generation, to contain failures and minimize the chance of product
damage. If a short-circuit condition is detected, the LDO is disabled by resetting its VGENxEN bit, while at the same time, an interrupt
VGENxFAULTI is generated to flag the fault to the system processor. The VGENxFAULTI interrupt is maskable through the
VGENxFAULTM mask bit.
The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, the regulators do not automatically disable upon a short-
circuit detection. However, the current limiter continues to limit the output current of the regulator. By default, the REGSCPEN is not set;
therefore, at start-up none of the regulators are disabled if an overloaded condition occurs. A fault interrupt, VGENxFAULTI, is generated
in an overload condition regardless of the state of the REGSCPEN bit. See Table 90 for SCP behavior configuration.
Table 90. Short-circuit behavior
REGSCPEN[0]
Short-circuit behavior
0
1
Current limit
Shutdown
PF0100Z
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.6.3
LDO regulator control
Each LDO is fully controlled through its respective VGENxCTL register. This register enables the user to set the LDO output voltage
according to Table 91 for VGEN1 and VGEN2; and uses the voltage set point on Table 92 for VGEN3 through VGEN6.
Table 91. VGEN1, VGEN2 output voltage configuration
Set point
VGENx[3:0]
VGENx output (V)
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0.800
0.850
0.900
0.950
1.000
1.050
1.100
1.150
1.200
1.250
1.300
1.350
1.400
1.450
1.500
1.550
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Table 92. VGEN3/ 4/ 5/ 6 output voltage configuration
Set point
VGENx[3:0]
VGENx output (V)
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Besides the output voltage configuration, the LDOs can be enabled or disabled at anytime during normal mode operation, as well as be
programmed to stay “ON” or be disabled when the PMIC enters standby mode. Each regulator has associated I2C bits for this. Table 93
presents a summary of all valid combinations of the control bits on VGENxCTL register and the expected behavior of the LDO output.
PF0100Z
NXP Semiconductors
77
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 93. LDO control
VGENxEN
VGENxLPWR
VGENxSTBY STANDBY(61)
VGENxOUT
0
1
1
1
1
1
X
0
1
X
0
1
X
0
0
1
1
1
X
X
X
0
Off
On
Low Power
On
1
Off
1
Low Power
Notes
61. STANDBY refers to a standby event as described earlier.
For more detail information, Table 94 through Table 99 provide a description of all registers necessary to operate all six general purpose
LDO regulators.
Table 94. Register VGEN1CTL - ADDR 0x6C
Name
Bit #
R/W Default
Description
Sets VGEN1 output voltage.
See Table 91 for all possible configurations.
VGEN1
3:0
R/W
–
0x80
0x00
0x00
Enables or disables VGEN1 output
VGEN1EN
4
5
0 = OFF
1 = ON
Set VGEN1 output state when in standby. Refer
to Table 93.
VGEN1STBY
R/W
Enable low-power mode for VGEN1. Refer to
Table 93.
VGEN1LPWR
UNUSED
6
7
R/W
–
0x00
0x00
unused
Table 95. Register VGEN2CTL - ADDR 0x6D
Name
Bit #
R/W Default
Description
Sets VGEN2 output voltage.
See Table 91 for all possible configurations.
VGEN2
3:0
R/W
–
0x80
0x00
0x00
Enables or disables VGEN2 output
VGEN2EN
4
5
0 = OFF
1 = ON
Set VGEN2 output state when in standby. Refer
to Table 93.
VGEN2STBY
R/W
Enable low-power mode for VGEN2. Refer to
Table 93.
VGEN2LPWR
UNUSED
6
7
R/W
–
0x00
0x00
unused
PF0100Z
78
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 96. Register VGEN3CTL - ADDR 0x6E
Name
Bit #
R/W Default
Description
Sets VGEN3 output voltage.
See Table 92 for all possible configurations.
VGEN3
3:0
R/W
–
0x80
0x00
0x00
Enables or disables VGEN3 output
VGEN3EN
4
5
0 = OFF
1 = ON
Set VGEN3 output state when in standby. Refer
to Table 93.
VGEN3STBY
R/W
Enable low-power mode for VGEN3. Refer to
Table 93.
VGEN3LPWR
UNUSED
6
7
R/W
–
0x00
0x00
unused
Table 97. Register VGEN4CTL - ADDR 0x6F
Name
Bit #
R/W Default
Description
Sets VGEN4 output voltage.
See Table 92 for all possible configurations.
VGEN4
3:0
R/W
–
0x80
0x00
0x00
Enables or disables VGEN4 output
VGEN4EN
4
5
0 = OFF
1 = ON
Set VGEN4 output state when in standby. Refer
to Table 93.
VGEN4STBY
R/W
Enable low-power mode for VGEN4. Refer to
Table 93.
VGEN4LPWR
UNUSED
6
7
R/W
–
0x00
0x00
unused
Table 98. Register VGEN5CTL - ADDR 0x70
Name
Bit #
R/W Default
Description
Sets VGEN5 output voltage.
See Table 92 for all possible configurations.
VGEN5
3:0
R/W
–
0x80
0x00
0x00
Enables or disables VGEN5 output
VGEN5EN
4
5
0 = OFF
1 = ON
Set VGEN5 output state when in standby. Refer
to Table 93.
VGEN5STBY
R/W
Enable low-power mode for VGEN5. Refer to
Table 93.
VGEN5LPWR
UNUSED
6
7
R/W
–
0x00
0x00
unused
PF0100Z
NXP Semiconductors
79
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 99. Register VGEN6CTL - ADDR 0x71
Name
Bit #
R/W Default
Description
Sets VGEN6 output voltage.
See Table 92 for all possible configurations.
VGEN6
3:0
R/W
–
0x80
0x00
0x00
Enables or disables VGEN6 output
VGEN6EN
4
5
0 = OFF
1 = ON
Set VGEN6 output state when in standby. Refer
to Table 93.
VGEN6STBY
R/W
Enable low-power mode for VGEN6. Refer to
Table 93.
VGEN6LPWR
UNUSED
6
7
R/W
–
0x00
0x00
unused
6.4.6.4
External components
Table 100 lists the typical component values for the general purpose LDO regulators.
Table 100. LDO external components
Regulator
Output capacitor (μF)(62)
VGEN1
VGEN2
VGEN3
VGEN4
VGEN5
VGEN6
2.2
4.7
2.2
4.7
2.2
2.2
Notes
62. Use X5R/X7R ceramic capacitors.
6.4.6.5
LDO specifications
VGEN1
6.4.6.5.1
Table 101. VGEN1 electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN1 = 3.0 V,
VGEN1[3:0] = 1111, IGEN1 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, IN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
VGEN1
Parameter
Min.
Typ.
Max.
Unit
Notes
VIN1
VGEN1NOM
IGEN1
Operating input voltage
Nominal output voltage
Operating load current
1.75
–
–
Table 91
–
3.40
–
V
V
0.0
100
mA
VGEN1 DC
Output voltage tolerance
1.75 V < VIN1 < 3.4 V
VGEN1TOL
-3.0
–
3.0
%
0.0 mA < IGEN1 < 100 mA
VGEN1[3:0] = 0000 to 1111
PF0100Z
80
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 101. VGEN1 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN1 = 3.0 V,
VGEN1[3:0] = 1111, IGEN1 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, IN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Load regulation
VGEN1LOR
–
0.15
–
mV/mA
(VGEN1 at IGEN1 = 100 mA) - (VGEN1 at IGEN1 = 0.0 mA)
For any 1.75 V < VIN1 < 3.4 V
Line regulation
VGEN1LIR
IGEN1LIM
IGEN1OCP
–
0.30
167
–
–
mV/mA
mA
(VGEN1 at VIN1 = 3.4 V) - (VGEN1 at VIN1 = 1.75 V)
For any 0.0 mA < IGEN1 < 100 mA
Current limit
122
115
200
200
IGEN1 when VGEN1 is forced to VGEN1NOM/2
Overcurrent protection threshold
mA
IGEN1 required to cause the SCP function to disable LDO when
REGSCPEN = 1
Quiescent current
IGEN1Q
–
14
–
μA
No load, Change in IVIN and IVIN1
When VGEN1 enabled
VGEN1 AC and transient
PSRR
•
IGEN1 = 75 mA, 20 Hz to 20 kHz
(63)
PSRRVGEN1
dB
50
37
60
45
–
–
VGEN1[3:0] = 0000 - 1101
VGEN1[3:0] = 1110, 1111
Output noise density
VIN1 = 1.75 V, IGEN1 = 75 mA
100 Hz – <1.0 kHz
NOISEVGEN1
–
–
–
-108
-118
-124
-100
-108
-112
dBV/ √Hz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
Turn-on slew rate
•
10% to 90% of end value
•
1.75 V ≤ VIN1 ≤ 3.4 V, IGEN1 = 0.0 mA
VGEN1[3:0] = 0000 to 0111
VGEN1[3:0] = 1000 to 1111
SLWRVGEN1
mV/μs
μs
–
–
–
–
12.5
16.5
Turn-on time
Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V
GEN1 = 0.0 mA
GEN1tON
60
–
500
I
Turn-off time
Disable to 10% of initial value, VIN1 = 1.75 V
GEN1tOFF
GEN1OSHT
–
–
–
10
ms
%
IGEN1 = 0.0 mA
Start-up overshoot
1.0
2.0
VIN1 = 1.75 V, 3.4 V, IGEN1 = 0.0 mA
Transient load response
•
VIN1 = 1.75 V, 3.4 V
VGEN1LOTR
–
–
3.0
%
IGEN1 = 10 mA to 100 mA in 1.0 μs. Peak of overshoot or
undershoot of VGEN1 with respect to final value
Refer to Figure 25
•
PF0100Z
NXP Semiconductors
81
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 101. VGEN1 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN1 = 3.0 V,
VGEN1[3:0] = 1111, IGEN1 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, IN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Transient line response
IGEN1 = 75 mA
•
VIN1INITIAL = 1.75 V to VIN1FINAL = 2.25 V for
VGEN1[3:0] = 0000 to 1101
VGEN1LITR
–
5.0
8.0
mV
VIN1INITIAL = VGEN1+0.3 V to VIN1FINAL = VGEN1+0.8 V for
VGEN1[3:0] = 1110, 1111
•
Refer to Figure 25
Notes
63. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test.
6.4.6.5.2
VGEN2
Table 102. VGEN2 electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN1 = 3.0 V,
VGEN2[3:0] = 1111, IGEN2 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6V, VIN1 = 3.0 V, VGEN2[3:0] = 1111, IGEN2 = 10mA and 25°C, unless otherwise noted.
Symbol
VGEN2
Parameter
Min.
Typ.
Max.
Unit
Notes
VIN1
VGEN2NOM
IGEN2
Operating input voltage
Nominal output voltage
Operating load current
1.75
–
–
Table 91
–
3.40
–
V
V
0.0
250
mA
VGEN2 active mode - DC
Output voltage tolerance
1.75 V < VIN1 < 3.4 V
0.0 mA < IGEN2 < 250 mA
VGEN2TOL
-3.0
–
3.0
%
VGEN2[3:0] = 0000 to 1111
Load regulation
VGEN2LOR
–
–
0.05
0.50
–
–
mV/mA
mV/mA
(VGEN2 at IGEN2 = 250 mA) - (VGEN2 at IGEN2 = 0.0 mA)
For any 1.75 V < VIN1 < 3.4 V
Line regulation
VGEN2LIR
(VGEN2 at VIN1 = 3.4 V) - (VGEN2 at VIN1 = 1.75 V)
For any 0.0 mA < IGEN2 < 250 mA
Current limit
IGEN2 when VGEN2 is forced to VGEN2NOM/2
PF0100Z
PF0100AZ
IGEN2LIM
mA
333
305
417
417
510
510
Overcurrent protection threshold
IGEN2 required to cause the SCP function to disable LDO when
IGEN2OCP
mA
REGSCPEN = 1
PF0100Z
PF0100AZ
300
290
–
–
500
500
Quiescent current
IGEN2Q
–
16
–
μA
No load, Change in IVIN and IVIN1
When VGEN2 enabled
PF0100Z
82
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 102. VGEN2 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN1 = 3.0 V,
VGEN2[3:0] = 1111, IGEN2 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6V, VIN1 = 3.0 V, VGEN2[3:0] = 1111, IGEN2 = 10mA and 25°C, unless otherwise noted.
Symbol
VGEN2 AC and transient
PSRR (64)
Parameter
Min.
Typ.
Max.
Unit
Notes
•
IGEN2 = 187.5 mA, 20 Hz to 20 kHz
PSRRVGEN2
dB
50
37
60
45
–
–
VGEN2[3:0] = 0000 - 1101
VGEN2[3:0] = 1110, 1111
Output noise density
•
VIN1 = 1.75 V, IGEN2 = 187.5 mA
NOISEVGEN2
–
–
–
-108
-118
-124
-100
-108
-112
dBV/√Hz
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
Turn-on slew rate
•
10% to 90% of end value
•
1.75 V ≤ VIN1 ≤ 3.4 V, IGEN2 = 0.0 mA
VGEN2[3:0] = 0000 to 0111
VGEN2[3:0] = 1000 to 1111
SLWRVGEN2
mV/μs
μs
–
–
–
–
12.5
16.5
Turn-on time
Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V
GEN2 = 0.0 mA
GEN2tON
60
–
500
I
Turn-off time
Disable to 10% of initial value, VIN1 = 1.75 V
GEN2tOFF
GEN2OSHT
–
–
–
10
ms
%
IGEN2 = 0.0 mA
Start-up overshoot
1.0
2.0
VIN1 = 1.75 V, 3.4 V, IGEN2 = 0.0 mA
Transient load response
VIN1 = 1.75 V, 3.4 V
I
GEN2 = 25 mA to 250 mA in 1.0 μs
VGEN2LOTR
–
–
–
3.0
8.0
%
Peak of overshoot or undershoot of VGEN2 with respect to final
value
Refer to Figure 25
Transient line response
IGEN2 = 187.5 mA
VIN1INITIAL = 1.75 V to VIN1FINAL = 2.25 V for
VGEN2[3:0] = 0000 to 1101
VGEN2LITR
5.0
mV
VIN1INITIAL = VGEN2+0.3 V to VIN1FINAL = VGEN2+0.8 V for
VGEN2[3:0] = 1110, 1111
Refer to Figure 25
Notes
64. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test.
PF0100Z
NXP Semiconductors
83
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.6.5.3
VGEN3
Table 103. VGEN3 electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN2 = 3.6 V,
VGEN3[3:0] = 1111, IGEN3 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN2 = 3.6 V, VGEN3[3:0] = 1111, IGEN3 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
VGEN3
Parameter
Min.
Typ.
Max.
Unit
Notes
Operating input voltage
2.8
VGEN3NO
M+ 0.250
VIN2
V
1.8 V ≤ VGEN3NOM ≤ 2.5 V
2.6 V ≤ VGEN3NOM ≤ 3.3 V
–
–
3.6
3.6
(65)
VGEN3NOM
IGEN3
Nominal output voltage
Operating load current
–
Table 92
–
–
V
0.0
100
mA
VGEN3 DC
Output voltage tolerance
VIN2MIN < VIN2 < 3.6 V
0.0 mA < IGEN3 < 100 mA
VGEN3[3:0] = 0000 to 1111
VGEN3TOL
-3.0
–
–
3.0
–
%
Load regulation
VGEN3LOR
0.07
mV/mA
(VGEN3 at IGEN3 = 100 mA) - (VGEN3 at IGEN3 = 0.0 mA)
For any VIN2MIN < VIN2 < 3.6 V
Line regulation
VGEN3LIR
IGEN3LIM
IGEN3OCP
–
0.8
167
–
–
mV/mA
mA
(VGEN3 at VIN2 = 3.6 V) - (VGEN3 at VIN2MIN
For any 0.0 mA < IGEN3 < 100 mA
)
Current limit
127
120
200
200
IGEN3 when VGEN3 is forced to VGEN3NOM/2
Overcurrent protection threshold
mA
IGEN3 required to cause the SCP function to disable LDO when
REGSCPEN = 1
Quiescent current
IGEN3Q
–
13
–
μA
No load, Change in IVIN and IVIN2
When VGEN3 enabled
VGEN3 AC and transient
PSRR
•
IGEN3 = 75 mA, 20 Hz to 20 kHz
(66)
PSRRVGEN3
dB
35
55
40
60
–
–
VGEN3[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV
VGEN3[3:0] = 0000 - 1000, VIN2 = VGEN3NOM + 1.0 V
Output noise density
•
VIN2 = VIN2MIN, IGEN3 = 75 mA
NOISEVGEN3
–
–
–
-114
-129
-135
-102
-123
-130
dBV/√Hz
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
Turn-on slew rate
•
10% to 90% of end value
•
VIN2MIN ≤ VIN2 ≤ 3.6 V, IGEN3 = 0.0 mA
SLWRVGEN3
–
–
–
–
–
–
–
–
22.0
26.5
30.5
34.5
mV/μs
VGEN3[3:0] = 0000 to 0011
VGEN3[3:0] = 0100 to 0111
VGEN3[3:0] = 1000 to 1011
VGEN3[3:0] = 1100 to 1111
Turn-on time
Enable to 90% of end value, VIN2 = VIN2MIN, 3.6 V
GEN3 = 0.0 mA
GEN3tON
60
–
500
μs
I
PF0100Z
84
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 103. VGEN3 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN2 = 3.6 V,
VGEN3[3:0] = 1111, IGEN3 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN2 = 3.6 V, VGEN3[3:0] = 1111, IGEN3 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
VGEN3 AC and transient (continued)
Turn-off time
GEN3tOFF
GEN3OSHT
–
–
–
10
ms
%
Disable to 10% of initial value, VIN2 = VIN2MIN
IGEN3 = 0.0 mA
Start-up overshoot
1.0
2.0
VIN2 = VIN2MIN, 3.6 V, IGEN3 = 0.0 mA
Transient load response
VIN2 = VIN2MIN, 3.6 V
VGEN3LOTR
–
–
3.0
8.0
%
I
GEN3 = 10 mA to 100 mA in 1.0 μs
Peak of overshoot or undershoot of VGEN3 with respect to final
value. Refer to Figure 25
Transient line response
IGEN3 = 75 mA
VIN2INITIAL = 2.8 V to VIN2FINAL = 3.3 V for
GEN3[3:0] = 0000 to 0111
VIN2INITIAL = VGEN3+0.3 V to VIN2FINAL = VGEN3+0.8 V for
VGEN3[3:0] = 1000 to 1010
VGEN3LITR
–
5.0
mV
VIN2INITIAL = VGEN3+0.25 V to VIN2FINAL = 3.6 V for
VGEN3[3:0] = 1011 to 1111
Refer to Figure 25
Notes
65. When the LDO Output voltage is set above 2.6 V, the minimum allowed input voltage needs to be at least the output voltage plus 0.25 V, for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
66. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VIN2MIN refers to the minimum allowed input voltage for a particular output voltage.
6.4.6.5.4
VGEN4
Table 104. VGEN4 electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN2 = 3.6 V,
VGEN4[3:0] = 1111, IGEN4 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN2 = 3.6 V, VGEN4[3:0] = 1111, IGEN4 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
VGEN4
Parameter
Min
Typ
Max
Unit
Notes
Operating input voltage
2.8
VGEN4NO
M+ 0.250
VIN2
–
–
3.6
3.6
V
1.8 V ≤ VGEN4NOM ≤ 2.5 V
2.6 V ≤ VGEN4NOM ≤ 3.3 V
(67)
VGEN4NOM
IGEN4
Nominal output voltage
Operating load current
–
Table 92
–
–
V
0.0
350
mA
VGEN4 DC
Output voltage tolerance
VIN2MIN < VIN2 < 3.6 V
0.0 mA < IGEN4 < 350 mA
VGEN4[3:0] = 0000 to 1111
VGEN4TOL
-3.0
–
–
3.0
–
%
Load regulation
VGEN4LOR
0.07
mV/mA
(VGEN4 at IGEN4 = 350 mA) - (VGEN4 at IGEN4 = 0.0 mA )
For any VIN2MIN < VIN2 < 3.6 V
PF0100Z
NXP Semiconductors
85
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 104. VGEN4 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN2 = 3.6 V,
VGEN4[3:0] = 1111, IGEN4 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN2 = 3.6 V, VGEN4[3:0] = 1111, IGEN4 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VGEN4 DC (continued)
Line regulation
VGEN4LIR
IGEN4LIM
IGEN4OCP
–
0.80
584.5
–
–
mV/mA
mA
(VGEN4 at 3.6 V) - (VGEN4 at VIN2MIN
For any 0.0 mA < IGEN4 < 350 mA
)
Current limit
435
420
700
700
IGEN4 when VGEN4 is forced to VGEN4NOM/2
Overcurrent protection threshold
mA
IGEN4 required to cause the SCP function to disable LDO when
REGSCPEN = 1
Quiescent current
IGEN4Q
–
13
–
μA
No load, change in IVIN and IVIN2
When VGEN4 enabled
VGEN4 AC and transient
PSRR
•
IGEN4 = 262.5 mA, 20 Hz to 20 kHz
(68)
PSRRVGEN4
dB
35
55
40
60
–
–
VGEN4[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV
VGEN4[3:0] = 0000 - 1000, VIN2 = VGEN4NOM + 1.0 V
Output noise density
•
VIN2 = VIN2MIN, IGEN4 = 262.5 mA
NOISEVGEN4
–
–
–
-114
-129
-135
-102
-123
-130
dBV/√Hz
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
Turn-on slew rate
•
10% to 90% of end value
•
VIN2MIN ≤ VIN2 ≤ 3.6 V, IGEN4 = 0.0 mA
SLWRVGEN4
–
–
–
–
–
–
–
–
22.0
26.5
30.5
34.5
mV/μs
VGEN4[3:0] = 0000 to 0011
VGEN4[3:0] = 0100 to 0111
VGEN4[3:0] = 1000 to 1011
VGEN4[3:0] = 1100 to 1111
Turn-on time
Enable to 90% of end value, VIN2 = VIN2MIN, 3.6 V
GEN4 = 0.0 mA
GEN4tON
60
–
500
μs
I
Turn-off time
Disable to 10% of initial value, VIN2 = VIN2MIN
GEN4tOFF
GEN4OSHT
–
–
–
10
ms
%
IGEN4 = 0.0 mA
Start-up overshoot
1.0
2.0
VIN2 = VIN2MIN, 3.6 V, IGEN4 = 0.0 mA
Transient load response
VIN2 = VIN2MIN, 3.6 V
VGEN4LOTR
–
–
3.0
%
I
GEN4 = 35 mA to 350 mA in 1.0 μs
Peak of overshoot or undershoot of VGEN4 with respect to final
value. Refer to Figure 25
PF0100Z
86
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 104. VGEN4 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN2 = 3.6 V,
VGEN4[3:0] = 1111, IGEN4 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN2 = 3.6 V, VGEN4[3:0] = 1111, IGEN4 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VGEN4 AC and transient (continued)
Transient line response
IGEN4 = 262.5 mA
VIN2INITIAL = 2.8 V to VIN2FINAL = 3.3 V for
VGEN4[3:0] = 0000 to 0111
VGEN4LITR
–
5.0
8.0
mV
VIN2INITIAL = VGEN4+0.3 V to VIN2FINAL = VGEN4+0.8 V for
VGEN4[3:0] = 1000 to 1010
VIN2INITIAL = VGEN4+0.25 V to VIN2FINAL = 3.6 V for
VGEN4[3:0] = 1011 to 1111
Refer to Figure 25
Notes
67. When the LDO output voltage is set above 2.6 V, the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
68. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VIN2MIN refers to the minimum allowed input voltage for a particular output voltage.
6.4.6.5.5
VGEN5
Table 105. VGEN5 electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN3 = 3.6 V,
VGEN5[3:0] = 1111, IGEN5 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN3 = 3.6 V, VGEN5[3:0] = 1111, IGEN5 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
VGEN5
Parameter
Min
Typ
Max
Unit
Notes
Operating input voltage
2.8
VGEN5NO
M+ 0.250
VIN3
–
–
4.5
4.5
V
1.8 V ≤ VGEN5NOM ≤ 2.5 V
2.6 V ≤ VGEN5NOM ≤ 3.3 V
(69)
VGEN5NOM
IGEN5
Nominal output voltage
Operating load current
–
Table 92
–
–
V
0.0
100
mA
VGEN5 active mode – DC
Output voltage tolerance
VIN3MIN < VIN3 < 4.5 V
0.0 mA < IGEN5 < 100 mA
VGEN5[3:0] = 0000 to 1111
VGEN5TOL
-3.0
–
–
3.0
–
%
Load regulation
VGEN5LOR
0.10
mV/mA
(VGEN5 at IGEN5 = 100 mA) - (VGEN5 at IGEN5 = 0.0 mA)
For any VIN3MIN < VIN3 < 4.5 mV
Line regulation
VGEN5LIR
IGEN5LIM
IGEN5OCP
–
0.50
167
–
–
mV/mA
mA
(VGEN5 at VIN3 = 4.5 V) - (VGEN5 at VIN3MIN
For any 0.0 mA < IGEN5 < 100 mA
)
Current limit
122
120
200
200
IGEN5 when VGEN5 is forced to VGEN5NOM/2
Overcurrent protection threshold
mA
IGEN5 required to cause the SCP function to disable LDO when
REGSCPEN = 1
PF0100Z
NXP Semiconductors
87
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 105. VGEN5 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN3 = 3.6 V,
VGEN5[3:0] = 1111, IGEN5 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN3 = 3.6 V, VGEN5[3:0] = 1111, IGEN5 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VGEN5 active mode – DC (continued)
Quiescent current
IGEN5Q
–
13
–
μA
No load, change in IVIN and IVIN3
When VGEN5 enabled
VGEN5 AC and transient
PSRR
•
IGEN5 = 75 mA, 20 Hz to 20 kHz
(70)
PSRRVGEN5
dB
35
52
40
60
–
–
VGEN5[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV
VGEN5[3:0] = 0000 - 1111, VIN3 = VGEN5NOM + 1.0 V
Output noise density
•
VIN3 = VIN3MIN, IGEN5 = 75 mA
NOISEVGEN5
–
–
–
-114
-129
-135
-102
-123
-130
dBV/√Hz
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
Turn-on slew rate
•
10% to 90% of end value
•
VIN3MIN ≤ VIN3 ≤ 4.5 mV, IGEN5 = 0.0 mA
SLWRVGEN5
–
–
–
–
–
–
–
–
22.0
26.5
30.5
34.5
mV/μs
VGEN5[3:0] = 0000 to 0011
VGEN5[3:0] = 0100 to 0111
VGEN5[3:0] = 1000 to 1011
VGEN5[3:0] = 1100 to 1111
Turn-on time
Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V
GEN5 = 0.0 mA
GEN5tON
60
–
500
μs
I
Turn-off time
Disable to 10% of initial value, VIN3 = VIN3MIN
GEN5tOFF
GEN5OSHT
–
–
–
10
ms
%
IGEN5 = 0.0 mA
Start-up overshoot
1.0
2.0
VIN3 = VIN3MIN, 4.5 V, IGEN5 = 0.0 mA
Transient load response
VIN3 = VIN3MIN, 4.5 V
I
GEN5 = 10 to 100 mA in 1.0 μs
VGEN5LOTR
–
–
3.0
8.0
%
Peak of overshoot or undershoot of VGEN5 with respect to final
value.
Refer to Figure 25
Transient line response
IGEN5 = 75 mA
VIN3INITIAL = 2.8 V to VIN3FINAL = 3.3 V for VGEN5[3:0] = 0000 to
0111
VGEN5LITR
-
5.0
mV
VIN3INITIAL = VGEN5+0.3 V to VIN3FINAL = VGEN5+0.8 V for
VGEN5[3:0] = 1000 to 1111
Refer to Figure 25
Notes
69. When the LDO output voltage is set above 2.6 V, the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
70. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage.
PF0100Z
88
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.6.5.6
VGEN6
Table 106. VGEN6 electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN3 = 3.6 V,
VGEN6[3:0] = 1111, IGEN6 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN3 = 3.6 V, VGEN6[3:0] = 1111, IGEN6 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
VGEN6
Parameter
Min
Typ
Max
Unit
Notes
Operating input voltage
2.8
VGEN6NO
M+ 0.250
VIN3
–
–
4.5
4.5
V
1.8 V ≤ VGEN6NOM ≤ 2.5 V
2.6 V ≤ VGEN6NOM ≤ 3.3 V
(71)
VGEN6NOM
IGEN6
Nominal output voltage
Operating load current
–
Table 92
–
–
V
0.0
200
mA
VGEN6 DC
Output voltage tolerance
VIN3MIN < VIN3 < 4.5 V
0.0 mA < IGEN6 < 200 mA
VGEN6[3:0] = 0000 to 1111
VGEN6TOL
-3.0
–
3.0
%
Load regulation
VGEN6LOR
–
–
0.10
0.50
–
–
mV/mA
mV/mA
(VGEN6 at IGEN6 = 200 mA) - (VGEN6 at IGEN6 = 0.0 mA)
For any VIN3MIN < VIN3 < 4.5 V
Line regulation
VGEN6LIR
(VGEN6 at VIN3 = 4.5 V) - (VGEN6 at VIN3MIN
)
For any 0.0 mA < IGEN6 < 200 mA
Current limit
IGEN6 when VGEN6 is forced to VGEN6NOM/2
PF0100Z
PF0100AZ
IGEN6LIM
mA
232
232
333
333
400
475
Overcurrent protection threshold
IGEN6 required to cause the SCP function to disable LDO when
IGEN6OCP
mA
REGSCPEN = 1
PF0100Z
PF0100AZ
220
220
–
–
400
475
Quiescent current
IGEN6Q
–
13
–
μA
No load, change in IVIN and IVIN3
When VGEN6 enabled
VGEN6 AC and transient
PSRR
•
IGEN6 = 150 mA, 20 Hz to 20 kHz
(72)
PSRRVGEN6
dB
35
52
40
60
–
–
VGEN6[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV
VGEN6[3:0] = 0000 - 1111, VIN3 = VGEN6NOM + 1.0 V
Output noise density
•
VIN3 = VIN3MIN, IGEN6 = 150 mA
NOISEVGEN6
–
–
–
-114
-129
-135
-102
-123
-130
dBV/√Hz
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
Turn-on slew rate
•
10% to 90% of end value
•
VIN3MIN ≤ VIN3 ≤ 4.5 V. IGEN6 = 0.0 mA
SLWRVGEN6
–
–
–
–
–
–
–
–
22.0
26.5
30.5
34.5
mV/μs
VGEN6[3:0] = 0000 to 0011
VGEN6[3:0] = 0100 to 0111
VGEN6[3:0] = 1000 to 1011
VGEN6[3:0] = 1100 to 1111
PF0100Z
NXP Semiconductors
89
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 106. VGEN6 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN3 = 3.6 V,
VGEN6[3:0] = 1111, IGEN6 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN3 = 3.6 V, VGEN6[3:0] = 1111, IGEN6 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VGEN6 AC and transient (continued)
Turn-on time
GEN6tON
60
–
500
μs
Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V
I
GEN6 = 0.0 mA
Turn-off time
Disable to 10% of initial value, VIN3 = VIN3MIN
GEN6tOFF
GEN6OSHT
–
–
–
10
ms
%
IGEN6 = 0.0 mA
Start-up overshoot
1.0
2.0
VIN3 = VIN3MIN, 4.5 V, IGEN6 = 0 mA
Transient load response
VIN3 = VIN3MIN, 4.5 V
VGEN6LOTR
–
–
–
3.0
8.0
%
I
GEN6 = 20 to 200 mA in 1.0 μs
Peak of overshoot or undershoot of VGEN6 with respect to final
value. Refer to Figure 25
Transient line response
IGEN6 = 150 mA
VIN3INITIAL = 2.8 V to VIN3FINAL = 3.3 V for
VGEN6[3:0] = 0000 to 0111
VGEN6LITR
5.0
mV
VIN3INITIAL = VGEN6+0.3 V to VIN3FINAL = VGEN6+0.8 V for
VGEN6[3:0] = 1000 to 1111
Refer to Figure 25
Notes
71. When the LDO output voltage is set above 2.6 V, the minimum allowed input voltage needs to be at least the output voltage plus 0.25 V for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
72. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage.
6.4.7 VSNVS LDO/switch
VSNVS powers the low-power, SNVS/RTC domain on the processor. It derives its power from either VIN, or coin cell, and cannot be
disabled. When powered by both, VIN takes precedence when above the appropriate comparator threshold. When powered by VIN,
VSNVS is an LDO capable of supplying seven voltages: 3.0, 1.8, 1.5, 1.3, 1.2, 1.1, and 1.0 V. The bits VSNVSVOLT[2:0] in register
VSNVS_CONTROL determine the output voltage. When powered by coin cell, VSNVS is an LDO capable of supplying 1.8, 1.5, 1.3, 1.2,
1.1, or 1.0 V as shown in Table 107. If the 3.0 V option is chosen with the coin cell, VSNVS tracks the coin cell voltage by means of a
switch, whose maximum resistance is 100 Ω. In this case, the VSNVS voltage is simply the coin cell voltage minus the voltage drop across
the switch, which is 40 mV at a rated maximum load current of 400 μA.
The default setting of the VSNVSVOLT[2:0] is 110, or 3.0 V, unless programmed otherwise in OTP. However, when the coin cell is applied
for the very first time, VSNVS outputs 1.0 V. Only when VIN is applied thereafter, VSNVS transitions to its default, or the programmed value
if different. Upon subsequent removal of VIN, with the coin cell attached, VSNVS changes configuration from an LDO to a switch for the
“110” setting, and remains as an LDO for the other settings, continuing to output the same voltages as when VIN is applied, providing
certain conditions are met as described in Table 107.
PF0100Z
90
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
PF0100Z
VIN
2.25 V (VTL0) -
4.5 V
LDO/SWITCH
Input
LICELL
Charger
VREF
Sense/
Selector
_
+
VSNVS
Z
Coin Cell
1.8 - 3.3 V
I2C Interface
Figure 26. VSNVS supply switch architecture
Table 107 provides a summary of the VSNVS operation at a different VIN input voltage and with or without coin cell connected to the
system.
Table 107. VSNVS modes of operation
VSNVSVOLT[2:0]
110
VIN
Mode
> VTH1
< VTL1
> VTH0
< VTL0
VIN LDO 3.0 V
Coin cell switch
VIN LDO
110
000 – 101
000 – 101
Coin cell LDO
6.4.7.0.1
VSNVS control
The VSNVS output level is configured through the VSNVSVOLT[2:0]bits on VSNVSCTL register as shown in table Table 108.
Table 108. Register VSNVSCTL - ADDR 0x6B
Name
Bit #
R/W Default
Description
Configures VSNVS output voltage.(73)
000 = 1.0 V
001 = 1.1 V
010 = 1.2 V
VSNVSVOLT
2:0
7:3
R/W
0x80
0x00
011 = 1.3 V
100 = 1.5 V
101 = 1.8 V
110 = 3.0 V
111 = RSVD
UNUSED
Notes
–
unused
73. Only valid when a valid input voltage is present.
6.4.7.0.2
VSNVS external components
Table 109. VSNVS external components
Capacitor
Value (μF)
VSNVS
0.47
PF0100Z
NXP Semiconductors
91
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.7.0.3
VSNVS specifications
Table 110. VSNVS electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VSNVS = 3.0 V,
I
SNVS = 5.0 μA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V,
VSNVS = 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise noted.
Symbol
VSNVS
Parameter
Min
Typ
Max
Unit
Notes
Operating input voltage
Valid coin cell range
Valid VIN
VINSNVS
1.8
2.25
–
–
3.3
4.5
V
Operating load current
ISNVS
5.0
–
400
μA
VINMIN < VIN < VINMAX
VSNVS DC, LDO
Output voltage
•
•
•
5.0 μA < ISNVS < 400 μA (off)
3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110
VTL0/VTH < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
-5.0%
-8.0%
3.0
1.0 - 1.8
7.0%
7.0%
5.0μA < ISNVS < 400 μA (on)
3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110
UVDET < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
VSNVS
V
-5.0%
-4.0%
3.0
1.0 - 1.8
5.0%
4.0%
5.0 μA < ISNVS < 400 μA (coin cell mode)
V
COIN-0.04
-8.0%
–
VCOIN
7.0%
2.84 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = 110
1.8 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = [000] - [101]
(77)
1.0 - 1.8
Dropout voltage
VSNVSDROP
–
–
50
mV
2.85 V < VIN < 2.9 V, VSNVSVOLT[2:0] = 110
5.0 μA < ISNVS < 400 μA
Current limit
PF0100Z
750
500
480
–
–
–
5900
5900
3600
V
V
V
IN > VTH1, VSNVSVOLT[2:0] = 110
IN > VTL0, VSNVSVOLT[2:0] = 000 to 101
IN < VTL0, VSNVSVOLT[2:0] = 000 to 101
ISNVSLIM
μA
PF0100AZ
V
V
V
IN > VTH1, VSNVSVOLT[2:0] = 110
IN > VTL0, VSNVSVOLT[2:0] = 000 to 101
IN < VTL0, VSNVSVOLT[2:0] = 000 to 101
1100
500
480
–
–
–
6750
6750
4500
VIN threshold (coin cell powered to VIN powered) VIN going high with
valid coin cell
VTH0
V
V
VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101
2.25
2.40
2.55
VIN threshold (VIN powered to coin cell powered) VIN going low with
valid coin cell
VTL0
VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101
2.20
5.0
2.35
–
2.50
–
VHYST1
VHYST0
VIN threshold hysteresis for VTH1-VTL1
mV
mV
VIN threshold hysteresis for VTH0-VTL0
5.0
–
–
Output voltage during crossover
VSNVSVOLT[2:0] = 110
(74)
VSNVSCROSS
2.7
–
–
V
VCOIN > 2.9 V
Switch to LDO: VIN > 2.825 V, ISNVS = 100 μA
LDO to Switch: VIN < 3.05 V, ISNVS = 100 μA
PF0100Z
92
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 110. VSNVS electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VSNVS = 3.0 V,
ISNVS = 5.0 μA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V,
VSNVS = 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise noted.
Symbol
VSNVS AC and transient
Turn-on time (load capacitor, 0.47 μF)
Parameter
Min
–
Typ
–
Max
24
Unit
ms
Notes
VIN = UVDET to 90% of VSNVS
(75), (76)
tONSNVS
VCOIN = 0.0 V, ISNVS = 5.0 μA
VSNVSVOLT[2:0] = 000 to 110
Start-up overshoot
VSNVSVOLT[2:0] = 000 to 110
VSNVSOSH
–
40
70
mV
ISNVS = 5.0 μA
dVIN/dt = 50 mV/μs
Transient line response ISNVS = 75% of ISNVSMAX
3.2 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110
–
–
32
22
–
–
VSNVSLITR
mV
V
2.45 V < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
Transient load response
VSNVSVOLT[2:0] = 110
3.1 V (UVDETL)< VIN ≤ 4.5 V
2.8
–
–
ISNVS = 75 to 750 μA
VSNVSLOTR
VSNVSVOLT[2:0] = 000 to 101
2.45 V < VIN ≤ 4.5 V
–
1.0
2.0
%
VTL0 > VIN, 1.8 V ≤ VCOIN ≤ 3.3 V
ISNVS = 40 μA to 400 μA
Refer to Figure 25
VSNVS DC, switch
Operating input voltage
Valid coin cell range
VINSNVS
ISNVS
1.8
5.0
–
–
–
–
3.3
400
100
V
Operating load current
μA
W
Internal switch RDS(on)
VCOIN = 2.6 V
RDSONSNVS
VIN threshold (VIN powered to coin cell powered)
VSNVSVOLT[2:0] = 110
(74)
VTL1
VTH1
2.725
2.775
2.90
2.95
3.00
3.1
V
V
VIN threshold (coin cell powered to VIN powered)
VSNVSVOLT[2:0] = 110
Notes
74. During crossover from VIN to LICELL, the VSNVS output voltage may drop to 2.7 V before going to the LICELL voltage. Though this is outside
the specified DC voltage level for the VDD_SNVS_IN pin of the i.MX 6, this momentary drop does not cause a malfunction. The i.MX 6’s RTC
continues to operate through the transition, and as a worst case may switch to the internal RC oscillator for a few clock cycles before switching
back to the external crystal oscillator.
75. The start-up of VSNVS is not monotonic. It first rises to 1.0 V and then settles to its programmed value within the specified tr1 time.
76. From coin cell insertion to VSNVS = 1.0 V, the delay time is typically 400 ms.
77. For 1.8 V ISNVS limited to 100 μA for VCOIN < 2.1 V
6.4.7.1
Coin cell battery backup
The LICELL pin provides for a connection of a coin cell backup battery or a “super” capacitor. If the voltage at VIN goes below the VIN
threshold (VTL1 and VTL0), contact-bounced, or removed, the coin cell maintained logic is powered by the voltage applied to LICELL. The
supply for internal logic and the VSNVS rail switch over to the LICELL pin when VIN goes below VTL1 or VTL0, even in the absence of a
voltage at the LICELL pin, resulting in clearing of memory and turning off VSNVS. Applications concerned about this behavior can tie the
LICELL pin to any system voltage between 1.8 V and 3.0 V. A small capacitor should be placed from LICELL to ground under all
circumstances.
PF0100Z
NXP Semiconductors
93
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.7.1.1
Coin cell charger control
The coin cell charger circuit functions as a current-limited voltage source, resulting in the CC/CV taper characteristic typically used for
rechargeable Lithium-Ion batteries. The coin cell charger is enabled via the COINCHEN bit, while the coin cell voltage is programmable
through the VCOIN[2:0] bits on register COINCTL in Table 112. The coin cell charger voltage is programmable. In the on state, the charger
current is fixed at ICOINHI. In sleep and standby modes, the charger current is reduced to a typical 10 μA. In the off state, coin cell charging
is not available as the main battery could be depleted unnecessarily. The coin cell charging is stopped when VIN is below UVDET.
Table 111. Coin cell charger voltage
VCOIN[2:0]
VCOIN (V)(78)
000
001
010
011
100
101
110
111
2.50
2.70
2.80
2.90
3.00
3.10
3.20
3.30
Notes
78. Coin cell voltages selected based on the
type of LICELL used on the system.
Table 112. Register COINCTL - ADDR 0x1A
Name
Bit #
R/W Default
Description
Coin cell charger output voltage selection.
VCOIN
2:0
R/W
0x00
See Table 111 for all options selectable through
these bits.
COINCHEN
UNUSED
3
R/W
–
0x00
0x00
Enable or disable the coin cell charger
unused
7:4
6.4.7.1.2
External components
Table 113. Coin cell charger external components
Component
Value
Units
LICELL bypass capacitor
100
nF
6.4.7.1.3
Coin cell specifications
Table 114. Coin cell charger specifications
Parameter
Typ
Unit
Voltage accuracy
100
60
mV
μA
%
Coin cell charge current in on mode ICOINHI
Current accuracy
30
PF0100Z
94
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
2
6.5
Control interface I C block description
The PF0100Z contains an I2C interface port which allows access by a processor, or any I2C master, to the register set. Via these registers
the resources of the IC can be controlled. The registers also provide status information about how the IC is operating. The SCL and SDA
lines should be routed away from noisy signals and planes to minimize noise pick up. To prevent reflections in the SCL and SDA traces
from creating false pulses, the rise and fall times of the SCL and SDA signals must be greater than 20 ns. This can be accomplished by
reducing the drive strength of the I2C master, via software. The i.MX6 I2C driver defaults to a 40 Ω drive strength. It is recommended to
use a drive strength of 80 Ω or higher to increase the edge times. Alternatively, this can be accomplished by using small capacitors from
SCL and SDA to ground. For example, use 5.1 pF capacitors from SCL and SDA to ground for bus pull-up resistors of 4.8 kΩ.
2
6.5.1 I C device ID
I2C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing for bus
conflict avoidance, fuse programmability is provided to allow configuration for the lower 3 address LSB(s). Refer to 6.1.2 One time
programmability (OTP), page 20 for more details. This product supports 7-bit addressing only; support is not provided for 10-bit or general
call addressing. Note, when the TBB bits for the I2C slave address are written, the next access to the chip, must then use the new slave
address; these bits take affect right away.
6.5.2 I2C operation
The I2C mode of the interface is implemented generally following the fast mode definition which supports up to 400 kbits/s operation
(exceptions to the standard are noted to be 7-bit only addressing and no support for General Call addressing.) Timing diagrams, electrical
specifications, and further details can be found in the I2C specification, which is available for download at:
http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf
I2C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB and each byte
will be sent out unless a STOP command or NACK is received prior to completion.
The following examples show how to write and read data to and from the IC. The host initiates and terminates all communication. The
host sends a master command packet after driving the start condition. The device responds to the host if the master command packet
contains the corresponding slave address. In the following examples, the device is shown always responding with an ACK to
transmissions from the host. If at any time a NACK is received, the host should terminate the current transaction and retry the transaction.
Host can
also drive
another
Start instead
Packet
Type
Device
Master Driven Data
Register Address
Address
(
byte 0 )
of Stop
7
0
7
0
0
7
0
START
STOP
Host SDA
R / W
A
C
K
A
C
K
A
C
K
Slave SDA
Figure 27. I2C write example
Host can also
Packet
Type
Device
Address
Register Address
Device Address
PMIC Driven Data
drive another
Start instead of
Stop
23
16
0
15
8
7
0
1
NA
CK
Host SDA
START
START
STOP
R/W
R/W
7
0
A
C
K
A
C
K
A
C
K
Slave SDA
Figure 28. I2C read example
PF0100Z
NXP Semiconductors
95
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.5.3 Interrupt handling
The system is informed about important events based on interrupts. Unmasked interrupt events are signaled to the processor by driving
the INTB pin low.
Each interrupt is latched so even if the interrupt source becomes inactive, the interrupt remains set until cleared. Each interrupt can be
cleared by writing a “1” to the appropriate bit in the interrupt status register; this also causes the INTB pin to go high. If there are multiple
interrupt bits set the INTB pin remains low until all are either masked or cleared. If a new interrupt occurs while the processor clears an
existing interrupt bit, the INTB pin remains low.
Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high, the INTB
pin does not go low. A masked interrupt can still be read from the interrupt status register. This gives the processor the option of polling
for status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the device to determine if any
interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked interrupt bit was already high, the
INTB pin goes low after unmasking.
The sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources. They are
read only, and not latched or clearable.
Interrupts generated by external events are debounced; therefore, the event needs to be stable throughout the debounce period before
an interrupt is generated. Nominal debounce periods for each event are documented in the INT summary Table 115. Due to the
asynchronous nature of the debounce timer, the effective debounce time can vary slightly.
6.5.4 Interrupt bit summary
Table 115 summarizes all interrupt, mask, and sense bits associated with INTB control. For more detailed behavioral descriptions, refer
to the related chapters.
Table 115. Interrupt, Mask and Sense Bits
Interrupt
LOWVINI
Mask
LOWVINM
Sense
LOWVINS
Purpose
Trigger
Debounce time (ms)
Low input voltage detect
Sense is 1 if below 2.80 V threshold
H to L
3.9(79)
Power on button event
H to L
L to H
31.25(79)
31.25
PWRONI
PWRONM
PWRONS
Sense is 1 if PWRON is high.
Thermal 110 °C threshold
Sense is 1 if above threshold
THERM110
THERM110M
THERM120M
THERM125M
THERM130M
SW1AFAULTM
SW1BFAULTM
SW1CFAULTM
SW2FAULTM
SW3AFAULTM
SW3BFAULTM
SW4FAULTM
THERM110S
THERM120S
THERM125S
THERM130S
SW1AFAULTS
SW1BFAULTS
SW1CFAULTS
SW2FAULTS
SW3AFAULTS
SW3BFAULTS
SW4FAULTS
Dual
Dual
3.9
3.9
3.9
3.9
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Thermal 120 °C threshold
Sense is 1 if above threshold
THERM120
Thermal 125 °C threshold
Sense is 1 if above threshold
THERM125
Dual
Thermal 130 °C threshold
Sense is 1 if above threshold
THERM130
Dual
Regulator 1A overcurrent limit
Sense is 1 if above current limit
SW1AFAULTI
SW1BFAULTI
SW1CFAULTI
SW2FAULTI
SW3AFAULTI
SW3BFAULTI
SW4FAULTI
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Regulator 1B overcurrent limit
Sense is 1 if above current limit
Regulator 1C overcurrent limit
Sense is 1 if above current limit
Regulator 2 overcurrent limit
Sense is 1 if above current limit
Regulator 3A overcurrent limit
Sense is 1 if above current limit
Regulator 3B overcurrent limit
Sense is 1 if above current limit
Regulator 4 overcurrent limit
Sense is 1 if above current limit
PF0100Z
96
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 115. Interrupt, Mask and Sense Bits (continued)
Interrupt
Mask
Sense
Purpose
Trigger
Debounce time (ms)
SWBST overcurrent limit
Sense is 1 if above current limit
SWBSTFAULTI
SWBSTFAULTM
SWBSTFAULTS
L to H
8.0
VGEN1 overcurrent limit
Sense is 1 if above current limit
VGEN1FAULTI
VGEN2FAULTI
VGEN3FAULTI
VGEN4FAULTI
VGEN5FAULTI
VGEN6FAULTI
VGEN1FAULTM
VGEN2FAULTM
VGEN3FAULTM
VGEN4FAULTM
VGEN5FAULTM
VGEN6FAULTM
OTP_ECCM
VGEN1FAULTS
VGEN2FAULTS
VGEN3FAULTS
VGEN4FAULTS
VGEN1FAULTS
VGEN6FAULTS
OTP_ECCS
L to H
L to H
L to H
L to H
L to H
L to H
L to H
8.0
8.0
8.0
8.0
8.0
8.0
8.0
VGEN2 overcurrent limit
Sense is 1 if above current limit
VGEN3 overcurrent limit
Sense is 1 if above current limit
VGEN4 overcurrent limit
Sense is 1 if above current limit
VGEN5 overcurrent limit
Sense is 1 if above current limit
VGEN6 overcurrent limit
Sense is 1 if above current limit
1 or 2 bit error detected in OTP registers
Sense is 1 if error detected
OTP_ECCI
Notes
79. Debounce timing for the falling edge can be extended with PWRONDBNC[1:0].
A full description of all interrupt, mask, and sense registers is provided in Tables 116 to 127.
Table 116. Register INTSTAT0 - ADDR 0x05
Name
PWRONI
Bit #
R/W
Default
Description
Power on interrupt bit
0
1
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
–
0
0
LOWVINI
Low-voltage interrupt bit
110 °C thermal interrupt bit
120 °C thermal interrupt bit
125 °C thermal interrupt bit
130 °C thermal interrupt bit
unused
THERM110I
THERM120I
THERM125I
THERM130I
UNUSED
2
0
3
0
4
0
5
0
7:6
00
Table 117. Register INTMASK0 - ADDR 0x06
Name
PWRONM
Bit #
R/W
Default
Description
0
1
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
–
1
1
Power on interrupt mask bit
Low-voltage interrupt mask bit
110 °C thermal interrupt mask bit
120 °C thermal interrupt mask bit
125 °C thermal interrupt mask bit
130 °C thermal interrupt mask bit
unused
LOWVINM
THERM110M
THERM120M
THERM125M
THERM130M
UNUSED
2
1
3
1
4
1
5
1
7:6
00
PF0100Z
NXP Semiconductors
97
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 118. Register INTSENSE0 - ADDR 0x07
Name
Bit #
R/W
Default
Description
Power on sense bit
PWRONS
0
R
0
0 = PWRON low
1 = PWRON high
Low-voltage sense bit
0 = VIN > 2.8 V
LOWVINS
1
2
3
4
R
R
R
R
0
0
0
0
1 = VIN ≤ 2.8 V
110 °C thermal sense bit
0 = Below threshold
1 = Above threshold
THERM110S
THERM120S
THERM125S
120 °C thermal sense bit
0 = Below threshold
1 = Above threshold
125 °C thermal sense bit
0 = Below threshold
1 = Above threshold
130 °C thermal sense bit
0 = Below threshold
1 = Above threshold
THERM130S
UNUSED
5
6
7
R
–
0
0
unused
Additional VDDOTP voltage sense pin
0 = VDDOTP grounded
VDDOTPS
R
00
1 = VDDOTP to VCOREDIG or greater
Table 119. Register INTSTAT1 - ADDR 0x08
Name
Bit #
R/W
Default
Description
SW1AFAULTI
SW1BFAULTI
SW1CFAULTI
SW2FAULTI
SW3AFAULTI
SW3BFAULTI
SW4FAULTI
UNUSED
0
1
2
3
4
5
6
7
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
–
0
0
0
0
0
0
0
0
SW1A overcurrent interrupt bit
SW1B overcurrent interrupt bit
SW1C overcurrent interrupt bit
SW2 overcurrent interrupt bit
SW3A overcurrent interrupt bit
SW3B overcurrent interrupt bit
SW4 overcurrent interrupt bit
unused
Table 120. Register INTMASK1 - ADDR 0x09
Name
Bit #
R/W
Default
Description
SW1AFAULTM
SW1BFAULTM
SW1CFAULTM
SW2FAULTM
SW3AFAULTM
SW3BFAULTM
SW4FAULTM
UNUSED
0
1
2
3
4
5
6
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
1
1
1
1
1
1
1
0
SW1A overcurrent interrupt mask bit
SW1B overcurrent interrupt mask bit
SW1C overcurrent interrupt mask bit
SW2 overcurrent interrupt mask bit
SW3A overcurrent interrupt mask bit
SW3B overcurrent interrupt mask bit
SW4 overcurrent interrupt mask bit
unused
PF0100Z
98
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 121. Register INTSENSE1 - ADDR 0x0A
Name
Bit #
R/W
Default
Description
SW1A overcurrent sense bit
0 = Normal operation
SW1AFAULTS
0
R
0
1 = Above current limit
SW1B overcurrent sense bit
0 = Normal operation
SW1BFAULTS
SW1CFAULTS
SW2FAULTS
SW3AFAULTS
SW3BFAULTS
1
2
3
4
5
R
R
R
R
R
0
0
0
0
0
1 = Above current limit
SW1C overcurrent sense bit
0 = Normal operation
1 = Above current limit
SW2 overcurrent sense bit
0 = Normal operation
1 = Above current limit
SW3A overcurrent sense bit
0 = Normal operation
1 = Above current limit
SW3B overcurrent sense bit
0 = Normal operation
1 = Above current limit
SW4 overcurrent sense bit
0 = Normal operation
SW4FAULTS
UNUSED
6
7
R
–
0
0
1 = Above current limit
unused
Table 122. Register INTSTAT3 - ADDR 0x0E
Name
Bit #
R/W
Default
Description
SWBSTFAULTI
UNUSED
0
6:1
7
R/W1C
–
0
0x00
0
SWBST overcurrent limit interrupt bit
unused
OTP_ECCI
R/W1C
OTP error interrupt bit
Table 123. Register INTMASK3 - ADDR 0x0F
Name
Bit #
R/W
Default
Description
SWBSTFAULTM
UNUSED
0
6:1
7
R/W
–
1
0x00
1
SWBST overcurrent limit interrupt mask bit
unused
OTP_ECCM
R/W
OTP error interrupt mask bit
Table 124. Register INTSENSE3 - ADDR 0x10
Name
Bit #
R/W
Default
Description
SWBST overcurrent limit sense bit
0 = Normal operation
SWBSTFAULTS
UNUSED
0
6:1
7
R
–
0
0x00
0
1 = Above current limit
unused
OTP error sense bit
0 = No error detected
1 = OTP error detected
OTP_ECCS
R
PF0100Z
NXP Semiconductors
99
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 125. Register INTSTAT4 - ADDR 0x11
Name
Bit #
R/W
Default
Description
VGEN1FAULTI
VGEN2FAULTI
VGEN3FAULTI
VGEN4FAULTI
VGEN5FAULTI
VGEN6FAULTI
UNUSED
0
1
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
–
0
0
VGEN1 overcurrent interrupt bit
VGEN2 overcurrent interrupt bit
VGEN3 overcurrent interrupt bit
VGEN4 overcurrent interrupt bit
VGEN5 overcurrent interrupt bit
VGEN6 overcurrent interrupt bit
unused
2
0
3
0
4
0
5
0
7:6
00
Table 126. Register INTMASK4 - ADDR 0x12
Name
Bit #
R/W
Default
Description
VGEN1FAULTM
VGEN2FAULTM
VGEN3FAULTM
VGEN4FAULTM
VGEN5FAULTM
VGEN6FAULTM
UNUSED
0
1
R/W
R/W
R/W
R/W
R/W
R/W
–
1
1
VGEN1 overcurrent interrupt mask bit
VGEN2 overcurrent interrupt mask bit
VGEN3 overcurrent interrupt mask bit
VGEN4 overcurrent interrupt mask bit
VGEN5 overcurrent interrupt mask bit
VGEN6 overcurrent interrupt mask bit
unused
2
1
3
1
4
1
5
1
7:6
00
Table 127. Register INTSENSE4 - ADDR 0x13
Name
Bit #
R/W
Default
Description
VGEN1 overcurrent sense bit
0 = Normal operation
VGEN1FAULTS
0
R
0
1 = Above current limit
VGEN2 overcurrent sense bit
0 = Normal operation
VGEN2FAULTS
VGEN3FAULTS
VGEN4FAULTS
VGEN5FAULTS
1
2
3
4
R
R
R
R
0
0
0
0
1 = Above current limit
VGEN3 overcurrent sense bit
0 = Normal operation
1 = Above current limit
VGEN4 overcurrent sense bit
0 = Normal operation
1 = Above current limit
VGEN5 overcurrent sense bit
0 = Normal operation
1 = Above current limit
VGEN6 overcurrent sense bit
0 = Normal operation
VGEN6FAULTS
UNUSED
5
R
–
0
1 = Above current limit
7:6
00
unused
PF0100Z
100
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.5.5 Specific registers
6.5.5.1
IC and version identification
The IC and other version details can be read via identification bits. These are hard-wired on chip and described in Tables 128 to 130.
Table 128. Register DEVICEID - ADDR 0x00
Name
DEVICEID
UNUSED
Bit #
R/W
Default
Description
Die version.
0000 = PF0100
3:0
7:4
R
–
0x00
0x01
Unused
Table 129. Register SILICON REV- ADDR 0x03
Name
Bit #
R/W
Default
Description
Represents the metal mask revision
Pass 0.0 = 0000
METAL_LAYER_REV
3:0
R
0x00
.
.
Pass 0.15 = 1111
Represents the full mask revision
Pass 1.0 = 0001
FULL_LAYER_REV
7:4
R
0x01
.
.
Pass 15.0 = 1111
Table 130. Register FABID - ADDR 0x04
Name
Bit #
R/W
Default
Description
Allows for characterizing different options within
the same reticule
FIN
1:0
R
0x00
FAB
3:2
7:0
R
R
0x00
0x00
Represents the wafer manufacturing facility
unused
Unused
6.5.5.2
Embedded memory
There are four register banks of general purpose embedded memory to store critical data. The data written to MEMA[7:0], MEMB[7:0],
MEMC[7:0], and MEMD[7:0] is maintained by the coin cell when the main battery is deeply discharged, removed, or contact-bounced. The
contents of the embedded memory are reset by COINPORB. The banks can be used for any system need for bit retention with coin cell
backup.
Table 131. Register MEMA ADDR 0x1C
Name
Bit #
R/W
Default
Description
MEMA
7:0
R/W
0
Memory bank A
Memory bank B
Table 132. Register MEMB ADDR 0x1D
Name
Bit #
R/W
Default
Description
MEMB
7:0
R/W
0
PF0100Z
NXP Semiconductors
101
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 133. Register MEMC ADDR 0x1E
Name
Bit #
R/W
Default
Description
Description
MEMC
7:0
R/W
0
Memory bank C
Memory bank D
Table 134. Register MEMD ADDR 0x1F
Name
Bit #
R/W
Default
MEMD
7:0
R/W
0
6.5.6 Register Bitmap
The register map is comprised of thirty-two pages, and its address and data fields are each eight bits wide. Only the first two pages can
be accessed. On each page, registers 0 to 0x7F are referred to as 'functional', and registers 0x80 to 0xFF as 'extended'. On each page,
the functional registers are the same, but the extended registers are different. To access registers in Table 136. Extended page 1, page
106, one must first write 0x01 to the page register at address 0x7F, and to access registers Table 137. Extended page 2, page 110, one
must first write 0x02 to the page register at address 0x7F. To access the Table 135. Functional page, page 103 from one of the extended
pages, no write to the page register is necessary.
Registers missing in the sequence are reserved; reading from them returns a value 0x00, and writing to them has no effect. The contents
of all registers are given in the tables defined in this chapter; each table is structure as follows:
Name: Name of the bit.
Bit #: The bit location in the register (7-0)
R/W: Read / Write access and control
• R is read-only access
• R/W is read and write access
• RW1C is read and write access with write 1 to clear
Reset: Reset signals are color coded based on the following legend.
Bits reset by SC and VCOREDIG_PORB
Bits reset by PWRON or loaded default or OTP configuration
Bits reset by DIGRESETB
Bits reset by PORB or RESETBMCU
Bits reset by VCOREDIG_PORB
Bits reset by POR or OFFB
Default: The value after reset, as noted in the default column of the memory map.
• Fixed defaults are explicitly declared as 0 or 1.
• “X” corresponds to Read / Write bits initialized at start-up, based on the OTP fuse settings or default if VDDOTP = 1.5 V. Bits are
subsequently I2C modifiable, when their reset has been released. “X” may also refer to bits which may have other dependencies.
For example, some bits may depend on the version of the IC, or a value from an analog block, for instance the sense bits for the
interrupts.
PF0100Z
102
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.5.6.1
Register map
Table 135. Functional page
BITS[7:0]
Register
Name
Add
R/W
Default
7
–
0
6
–
0
5
–
0
4
–
1
3
2
1
0
DEVICE ID [3:0]
00
DeviceID
R
8'b0001_0000
0
0
0
0
FULL_LAYER_REV[3:0]
METAL_LAYER_REV[3:0]
03
04
05
06
07
08
09
0A
SILICONREVID
FABID
R
R
8'b0001_0000
8'b0000_0000
X
X
X
X
X
0
X
X
X
–
–
–
–
FAB[1:0]
FIN[1:0]
0
0
0
0
0
0
0
–
–
THERM130I
THERM125I
THERM120I
THERM110I
LOWVINI
PWRONI
INTSTAT0
INTMASK0
INTSENSE0
INTSTAT1
INTMASK1
INTSENSE1
RW1C 8'b0000_0000
0
0
0
0
0
0
0
0
–
–
THERM130M
THERM125M
THERM120M
THERM110M
LOWVINM
PWRONM
R/W
R
8'b0011_1111
8'b00xx_xxxx
0
0
1
1
1
1
1
1
VDDOTPS
RSVD
THERM130S
THERM125S
THERM120S
THERM110S
LOWVINS
PWRONS
x
0
–
0
–
0
–
0
0
x
x
x
x
x
SW4FAULTI
SW3BFAULTI
0
SW3AFAULTI
0
SW2FAULTI
SW1CFAULTI
0
SW1BFAULTI
0
SW1AFAULTI
RW1C 8'b0000_0000
0
0
0
SW4FAULTM
SW3BFAULTM SW3AFAULTM
SW2FAULTM
SW1CFAULTM SW1BFAULTM
SW1AFAULTM
R/W
R
8'b0111_1111
8'b0xxx_xxxx
1
1
1
1
1
1
1
SW4FAULTS
x
SW3BFAULTS
x
SW3AFAULTS
x
SW2FAULTS
x
SW1CFAULTS
x
SW1BFAULTS
x
SW1AFAULTS
x
OTP_ECCI
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
SWBSTFAULTI
0E
0F
10
11
INTSTAT3
INTMASK3
INTSENSE3
INTSTAT4
RW1C 8'b0000_0000
0
0
OTP_ECCM
SWBSTFAULTM
R/W
R
8'b1000_0001
8'b0000_000x
1
1
OTP_ECCS
SWBSTFAULTS
0
–
0
x
VGEN6FAULTI VGEN5FAULTI VGEN4FAULTI VGEN3FAULTI VGEN2FAULTI
VGEN1FAULTI
0
RW1C 8'b0000_0000
0
0
0
0
0
VGEN6
FAULTM
VGEN5
FAULTM
VGEN4
FAULTM
VGEN3
FAULTM
VGEN2
FAULTM
VGEN1
FAULTM
–
0
–
0
–
0
–
0
12
13
INTMASK4
R/W
R
8'b0011_1111
8'b00xx_xxxx
1
1
1
1
1
1
VGEN6
FAULTS
VGEN5
FAULTS
VGEN4
FAULTS
VGEN3
FAULTS
VGEN2
FAULTS
VGEN1
FAULTS
INTSENSE4
x
x
x
x
x
x
–
0
–
0
–
0
–
0
COINCHEN
0
VCOIN[2:0]
0
1A
COINCTL
R/W
8'b0000_0000
0
0
PF0100Z
NXP Semiconductors
103
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 135. Functional page (continued)
BITS[7:0]
Register
Name
Add
1B
1C
1D
1E
1F
20
R/W
R/W
R/W
R/W
R/W
R/W
Default
7
6
5
0
0
0
0
0
x
x
x
4
1
0
0
0
0
x
3
2
1
0
REGSCPEN
0
STANDBYINV
0
STBYDLY[1:0]
PWRONBDBNC[1:0]
PWRONRSTEN
0
RESTARTEN
0
PWRCTL
8'b0001_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
0
0
0
0
0
x
x
x
1
0
0
0
0
0
x
MEMA[7:0]
MEMB[7:0]
MEMC[7:0]
MEMD[7:0]
MEMA
MEMB
0
0
0
0
0
0
0
0
0
0
x
x
x
0
0
0
0
x
x
x
MEMC
MEMD
0
–
0
–
0
–
0
–
0
0
–
0
–
0
–
0
–
0
SW1AB[5:0]
SW1ABVOLT
SW1ABSTBY
SW1ABOFF
SW1ABMODE
SW1ABCONF
R/W/M 8'b00xx_xxxx
SW1ABSTBY[5:0]
21
R/W
R/W
R/W
R/W
8'b00xx_xxxx
8'b00xx_xxxx
8'b0000_1000
8'bxx00_xx00
x
x
SW1ABOFF[5:0]
x
22
x
–
0
SW1ABOMODE
0
SW1ABMODE[3:0]
23
0
0
0
SW1ABDVSSPEED[1:0]
SW1BAPHASE[1:0]
SW1ABFREQ[1:0]
–
SW1ABILIM
0
24
x
x
0
0
x
x
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
SW1C[5:0]
2E
2F
30
31
32
SW1CVOLT
SW1CSTBY
SW1COFF
R/W
R/W
R/W
R/W
R/W
8'b00xx_xxxx
8'b00xx_xxxx
8'b00xx_xxxx
8'b0000_1000
8'bxx00_xx00
x
x
x
x
x
x
x
1
x
x
x
x
x
x
SW1CSTBY[5:0]
x
SW1COFF[5:0]
x
x
–
0
x
x
SW1CMODE[3:0]
0
SW1COMODE
0
SW1CMODE
SW1CCONF
0
x
0
SW1CILIM
0
SW1CDVSSPEED[1:0]
SW1CPHASE[1:0]
SW1CFREQ[1:0]
–
x
x
0
0
x
0
–
0
–
0
–
0
SW2[6:0]
35
36
37
SW2VOLT
SW2STBY
SW2OFF
R/W
R/W
R/W
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0xxx_xxxx
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
SW2STBY[6:0]
x
SW2OFF[6:0]
x
PF0100Z
104
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 135. Functional page (continued)
BITS[7:0]
Register
Name
Add
38
R/W
R/W
R/W
Default
7
–
0
6
–
0
5
4
–
0
3
1
x
2
0
x
1
0
SW2OMODE
0
SW2MODE[3:0]
SW2MODE
8'b0000_1000
8'bxx01_xx00
0
–
0
0
SW2ILIM
0
SW2DVSSPEED[1:0]
SW2PHASE[1:0]
SW2FREQ[1:0]
39
SW2CONF
x
x
0
1
–
0
–
0
–
0
SW3A[6:0]
3C
3D
3E
3F
40
SW3AVOLT
SW3ASTBY
SW3AOFF
R/W
R/W
R/W
R/W
R/W
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0000_1000
8'bxx10_xx00
x
x
x
0
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
SW3ASTBY[6:0]
x
SW3AOFF[6:0]
x
x
x
–
0
SW3AOMODE
0
SW3AMODE[3:0]
SW3AMODE
SW3ACONF
0
1
x
0
–
0
0
SW3AILIM
0
SW3ADVSSPEED[1:0]
SW3APHASE[1:0]
SW3AFREQ[1:0]
x
x
1
0
x
–
0
–
0
–
0
–
0
SW3B[6:0]
43
44
45
46
47
SW3BVOLT
SW3BSTBY
SW3BOFF
R/W
R/W
R/W
R/W
R/W
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0000_1000
8'bxx10_xx00
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
SW3BSTBY[6:0]
x
SW3BOFF[6:0]
x
x
–
0
x
x
–
0
SW3BOMODE
0
SW3BMODE[3:0]
SW3BMODE
SW3BCONF
1
0
–
0
0
SW3BILIM
0
SW3BDVSSPEED[1:0]
SW3BPHASE[1:0]
SW3BFREQ[1:0]
x
x
1
0
x
–
0
–
0
–
0
–
0
SW4[6:0]
4A
4B
4C
4D
4E
SW4VOLT
SW4STBY
SW4OFF
R/W
R/W
R/W
R/W
R/W
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0xxx_xxxx
8'b0000_1000
8'bxx11_xx00
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
SW4STBY[6:0]
x
SW4OFF[6:0]
x
x
–
0
x
x
–
0
SW4OMODE
0
SW4MODE[3:0]
SW4MODE
SW4CONF
1
0
–
0
0
SW4ILIM
0
SW4DVSSPEED[1:0]
SW4PHASE[1:0]
SW4FREQ[1:0]
x
x
1
1
x
PF0100Z
NXP Semiconductors
105
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 135. Functional page (continued)
BITS[7:0]
Register
Name
Add
R/W
Default
7
–
0
6
5
4
–
0
3
2
1
0
SWBST1STBYMODE[1:0]
SWBST1MODE[1:0]
SWBST1VOLT[1:0]
66
SWBSTCTL
R/W
8'b0xx0_10xx
x
x
1
0
x
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
–
VREFDDREN
–
0
–
0
–
0
–
–
0
6A
6B
6C
6D
6E
6F
70
71
VREFDDRCTL
VSNVSCTL
VGEN1CTL
VGEN2CTL
VGEN3CTL
VGEN4CTL
VGEN5CTL
VGEN6CTL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8'b000x_0000
8'b0000_0xxx
8'b000x_xxxx
8'b000x_xxxx
8'b000x_xxxx
8'b000x_xxxx
8'b000x_xxxx
8'b000x_xxxx
0
0
x
0
–
–
–
VSNVSVOLT[2:0]
x
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
VGEN1LPWR
VGEN1STBY
VGEN1EN
VGEN1[3:0]
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
VGEN2LPWR
VGEN2STBY
VGEN2EN
VGEN2[3:0]
VGEN3[3:0]
VGEN4[3:0]
VGEN5[3:0]
VGEN6[3:0]
0
0
x
VGEN3LPWR
VGEN3STBY
VGEN3EN
0
0
x
VGEN4LPWR
VGEN4STBY
VGEN4EN
0
0
x
VGEN5LPWR
VGEN5STBY
VGEN5EN
0
0
x
VGEN6LPWR
0
VGEN6STBY
0
VGEN6EN
x
–
0
–
0
–
0
PAGE[4:0]
0
7F
Page Register
R/W
8'b0000_0000
0
0
0
0
Table 136. Extended page 1
BITS[7:0]
Address Register Name TYPE
Default
7
–
0
6
–
0
5
4
3
–
x
2
–
x
1
–
x
0
OTP FUSE
READ EN
–
0
–
x
OTP FUSE READ
80
84
R/W
R/W
8'b000x_xxx0
EN
0
RL OTP
FUSE
RL TRIM
FUSE
START
0
RL PWBRTN FORCE PWRCTL RL PWRCTL
RL OTP
0
RL OTP ECC
0
OTP LOAD MASK
8'b0000_0000
0
0
0
0
0
–
x
–
x
–
x
–
x
–
x
–
x
–
x
–
x
–
x
ECC5_SE
ECC4_SE
ECC3_SE
ECC2_SE
ECC1_SE
8A
8B
8C
OTP ECC SE1
OTP ECC SE2
OTP ECC DE1
R
R
R
8'bxxx0_0000
8'bxxx0_0000
8'bxxx0_0000
0
0
0
0
0
ECC10_SE
ECC9_SE
ECC8_SE
ECC7_SE
ECC6_SE
0
ECC5_DE
0
0
ECC4_DE
0
0
ECC3_DE
0
0
ECC2_DE
0
0
ECC1_DE
0
PF0100Z
106
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 136. Extended page 1 (continued)
BITS[7:0]
Address Register Name TYPE
Default
7
–
x
6
–
x
5
–
x
4
3
ECC9_DE
0
2
ECC8_DE
0
1
ECC7_DE
0
0
ECC6_DE
0
ECC10_DE
0
8D
OTP ECC DE2
R
8'bxxx0_0000
–
0
–
0
–
0
–
0
SW1AB_VOLT[5:0]
x
A0
A1
A2
OTP SW1AB VOLT
OTP SW1AB SEQ
R/W
R/W
R/W
8'b00xx_xxxx
8'b000x_xxXx
8'b0000_xxxx
x
x
x
x
x
x
x
SW1AB_SEQ[4:0]
x
0
–
0
0
–
0
x
–
0
x
X
SW1_CONFIG[1:0]
SW1AB_FREQ[1:0]
OTP SW1AB
CONFIG
x
x
x
–
0
–
0
–
0
–
0
SW1C_VOLT[5:0]
x
A8
A9
AA
OTP SW1C VOLT
OTP SW1C SEQ
R/W
R/W
R/W
8'b00xx_xxxx
8'b000x_xxxx
8'b0000_00xx
x
x
x
x
x
x
x
SW1C_SEQ[4:0]
0
–
0
0
–
0
x
–
0
x
–
0
x
–
0
SW1C_FREQ[1:0]
OTP SW1C
CONFIG
x
x
–
0
–
0
–
0
SW2_VOLT[5:0]
x
AC
AD
AE
OTP SW2 VOLT
OTP SW2 SEQ
R/W
R/W
R/W
8'b0xxx_xxxx
8'b000x_xxxx
8'b0000_00xx
x
–
0
–
0
x
x
x
x
x
x
x
x
SW2_SEQ[4:0]
0
–
0
x
–
0
x
–
0
x
–
0
SW2_FREQ[1:0]
OTP SW2 CONFIG
x
–
0
–
0
–
0
SW3A_VOLT[6:0]
x
B0
B1
B2
OTP SW3A VOLT
OTP SW3A SEQ
R/W
R/W
R/W
8'b0xxx_xxxx
8'b000x_xxxx
8'b0000_xxxx
x
–
0
–
0
x
x
x
x
x
x
x
SW3A_SEQ[4:0]
x
0
–
0
x
–
0
x
x
SW3_CONFIG[1:0]
SW3A_FREQ[1:0]
OTP SW3A
CONFIG
x
x
x
–
0
–
0
–
0
SW3B_VOLT[6:0]
x
B4
B5
B6
OTP SW3B VOLT
OTP SW3B SEQ
R/W
R/W
R/W
8'b0xxx_xxxx
8'b000x_xxxx
8'b0000_00xx
x
–
0
–
0
x
x
x
x
x
x
x
SW3B_SEQ[4:0]
0
–
0
x
–
0
x
–
0
x
–
0
SW3B_CONFIG[1:0]
OTP SW3B
CONFIG
x
x
PF0100Z
NXP Semiconductors
107
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 136. Extended page 1 (continued)
BITS[7:0]
Address Register Name TYPE
Default
7
–
0
–
0
–
0
6
5
4
3
2
1
x
x
0
x
x
x
SW4_VOLT[6:0]
x
B8
B9
BA
OTP SW4 VOLT
OTP SW4 SEQ
R/W
R/W
R/W
8'b00xx_xxxx
8'b000x_xxxx
8'b000x_xxxx
0
–
0
–
0
x
–
0
–
0
x
x
SW4_SEQ[4:0]
x
VTT
x
x
–
x
x
–
x
SW4_FREQ[1:0]
OTP SW4 CONFIG
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
SWBST_VOLT[1:0]
BC
BD
OTP SWBST VOLT
OTP SWBST SEQ
R/W
R/W
8'b0000_00xx
8'b0000_xxxx
0
x
x
SWBST_SEQ[4:0]
x
0
x
x
x
–
0
–
0
–
0
–
0
–
0
VSNVS_VOLT[2:0]
x
C0
C4
OTP VSNVS VOLT
R/W
R/W
8'b0000_0xxx
8'b000x_x0xx
0
x
x
–
0
–
0
–
0
VREFDDR_SEQ[4:0]
0
OTP VREFDDR
SEQ
x
x
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
VGEN1_VOLT[3:0]
C8
C9
OTP VGEN1 VOLT
OTP VGEN1 SEQ
R/W
R/W
8'b0000_xxxx
8'b000x_xxxx
x
x
x
x
x
x
VGEN1_SEQ[4:0]
x
x
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
VGEN2_VOLT[3:0]
CC
CD
OTP VGEN2 VOLT
OTP VGEN2 SEQ
R/W
R/W
8'b0000_xxxx
8'b000x_xxxx
x
x
x
x
x
x
VGEN2_SEQ[4:0]
x
x
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
VGEN3_VOLT[3:0]
D0
D1
OTP VGEN3 VOLT
OTP VGEN3 SEQ
R/W
R/W
8'b0000_xxxx
8'b000x_xxxx
x
x
x
x
x
x
VGEN3_SEQ[4:0]
x
x
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
VGEN4_VOLT[3:0]
D4
D5
OTP VGEN4 VOLT
OTP VGEN4 SEQ
R/W
R/W
8'b0000_xxxx
8'b000x_xxxx
x
x
x
x
x
x
VGEN4_SEQ[4:0]
x
x
x
PF0100Z
108
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 136. Extended page 1 (continued)
BITS[7:0]
Address Register Name TYPE
Default
7
–
0
–
0
6
–
0
–
0
5
–
0
–
0
4
–
0
3
x
x
2
1
0
x
x
VGEN5_VOLT[3:0]
D8
D9
OTP VGEN5 VOLT
OTP VGEN5 SEQ
R/W
R/W
8'b0000_xxxx
8'b000x_xxxx
x
x
x
VGEN5_SEQ[4:0]
x
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
VGEN6_VOLT[3:0]
DC
DD
OTP VGEN6 VOLT
OTP VGEN6 SEQ
R/W
R/W
8'b0000_xxxx
8'b000x_xxxx
x
x
x
x
x
x
VGEN6_SEQ[4:0]
x
x
x
PWRON_
CFG1
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
SWDVS_CLK1[1:0]
SEQ_CLK_SPEED1[1:0]
E0
E1
E2
OTP PU CONFIG1
OTP PU CONFIG2
OTP PU CONFIG3
R/W
R/W
R/W
8'b000x_xxxx
8'b000x_xxxx
8'b000x_xxxx
x
x
x
x
x
PWRON_
CFG2
SWDVS_CLK2[1:0]
SEQ_CLK_SPEED2[1:0]
x
x
x
x
x
PWRON_
CFG3
SWDVS_CLK3[1:0]
SEQ_CLK_SPEED3[1:0]
x
x
x
x
x
PWRON_CFG
_XOR
–
–
0
–
SWDVS_CLK3_XOR
SEQ_CLK_SPEED_XOR
OTP PU CONFIG
XOR
E3
R
8'b000x_xxxx
8'b0000_00x0
0
0
–
x
x
x
x
x
SOFT_FUSE_
POR
TBB_POR
–
–
–
FUSE_POR1
–
(80)
E4
OTP FUSE POR1
R/W
0
RSVD
0
0
RSVD
0
0
–
0
–
0
0
–
0
–
0
0
–
0
–
0
0
–
0
–
0
x
0
–
0
–
0
FUSE_POR2
E5
E6
OTP FUSE POR1
OTP FUSE POR1
R/W
R/W
8'b0000_00x0
8'b0000_00x0
x
RSVD
0
RSVD
0
FUSE_POR3
x
FUSE_POR_X
OR
RSVD
RSVD
–
–
–
–
–
OTP FUSE POR
XOR
E7
E8
R
8'b0000_00x0
0
–
0
0
–
0
0
–
0
0
–
0
0
–
0
0
–
0
x
–
x
0
OTP_PG_EN
0
OTP PWRGD EN
R/W/M 8'b0000_000x
EN_ECC_
BANK5
EN_ECC_
BANK4
EN_ECC_
BANK3
EN_ECC_
BANK2
EN_ECC_
BANK1
–
0
–
0
–
0
–
0
–
0
–
0
F0
F1
OTP EN ECCO
OTP EN ECC1
R/W
R/W
8'b000x_xxxx
8'b000x_xxxx
x
x
x
x
x
EN_ECC_
BANK10
EN_ECC_
BANK9
EN_ECC_
BANK8
EN_ECC_
BANK7
EN_ECC_
BANK6
x
x
x
x
x
PF0100Z
NXP Semiconductors
109
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 136. Extended page 1 (continued)
BITS[7:0]
Address Register Name TYPE
Default
7
–
0
–
0
–
0
–
0
6
–
0
–
0
–
0
–
0
5
–
0
–
0
–
0
–
0
4
–
0
–
0
–
0
–
0
3
2
1
0
x
x
RSVD
F4
F5
F6
F7
OTP SPARE2_4
OTP SPARE4_3
OTP SPARE6_2
OTP SPARE7_1
R/W
R/W
R/W
R/W
8'b0000_xxxx
8'b0000_0xxx
8'b0000_00xx
8'b0000_0xxx
x
–
0
–
0
–
0
x
x
RSVD
x
x
–
0
–
x
RSVD
x
–
x
x
RSVD
x
–
0
–
0
–
0
–
0
–
0
–
0
–
0
OTP_DONE
x
FE
OTP DONE
R/W
R/W
8'b0000_000x
8'b0000_0xxx
I2C_SLV
ADDR[3]
–
0
–
0
–
0
–
0
I2C_SLV ADDR[2:0]
x
FF
OTP I2C ADDR
1
x
x
Notes
80. In the PF0100Z FUSE_POR1, FUSE_POR2, and FUSE_POR3 are XOR’ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR has to be 1 for
fuses to be loaded. This can be achieved by setting any one or all of the FUSE_PORx bits. In the PF0100AZ, the XOR function is removed. It is
required to set all of the FUSE_PORx bits to be able to load the fuses.
Table 137. Extended page 2
BITS[7:0]
Address
Register Name
TYPE
Default
7
6
5
4
3
2
1
0
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
SW1AB_PWRSTG[2:0]
1
81
82
83
84
85
86
SW1AB PWRSTG
PWRSTG RSVD
SW1C PWRSTG
SW2 PWRSTG
SW3A PWRSTG
SW3B PWRSTG
R/W
R
8'b1111_1111
8'b0000_0000
8'b1111_1111
8'b1111_1111
8'b1111_1111
8'b1111_1111
1
0
1
1
1
1
1
0
1
1
1
1
PWRSTGRSVD
0
RSVD
1
0
RSVD
1
0
RSVD
1
0
RSVD
1
0
RSVD
1
0
SW1C_PWRSTG[2:0]
R
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
SW2_PWRSTG[2:0]
R
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
SW3A_PWRSTG[2:0]
R
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
SW3B_PWRSTG[2:0]
1
R
FSLEXT_
THERM_
DISABLE
PWRGD_
SHDWN_
DISABLE
RSVD
RSVD
RSVD
SW4_PWRSTG[2:0]
87
88
SW4 PWRSTG
R
8'b0111_1111
8'b0000_0001
0
–
0
0
–
0
1
–
0
1
–
0
1
–
0
1
–
0
1
1
OTP_
SHDWN_EN
PWRGD_EN
PWRCTRL OTP
CTRL
R/W
0
1
PF0100Z
110
NXP Semiconductors
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 137. Extended page 2 (continued)
BITS[7:0]
Address
Register Name
TYPE
R/W
Default
7
6
5
4
3
2
1
0
0
0
0
0
0
0
I2C_WRITE_ADDRESS_TRAP[7:0]
I2C WRITE
ADDRESS TRAP
8D
8E
8F
90
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b00xx_xxxx
0
0
RSVD
0
0
RSVD
0
0
0
0
0
0
LET_IT_ ROLL
0
I2C_TRAP_PAGE[4:0]
0
I2C TRAP PAGE
I2C TRAP CNTR
IO DRV
R/W
I2C_WRITE_ADDRESS_COUNTER[7:0]
R/W
0
0
0
0
0
0
0
x
SDA_DRV[1:0]
SDWNB_DRV[1:0]
INTB_DRV[1:0]
RESETBMCU_DRV[1:0]
R/W
0
x
x
x
x
x
AUTO_ECC
_BANK5
AUTO_ECC AUTO_ECC_B AUTO_ECC AUTO_ECC_B
–
0
–
0
–
0
–
0
–
0
–
0
_BANK4
ANK3
_BANK2
ANK1
D0
D1
OTP AUTO ECC0
OTP AUTO ECC1
R/W
R/W
8'b0000_0000
8'b0000_0000
0
0
0
0
0
AUTO_ECC_B AUTO_ECC AUTO_ECC_B AUTO_ECCBA AUTO_ECC_B
ANK10
_BANK9
ANK8
NK7
ANK6
0
0
0
0
0
(81)
D8
D9
Reserved
Reserved
–
–
8'b0000_0000
8'b0000_0000
Reserved
(81)
Reserved
ECC1_EN_
TBB
ECC1_CALC_
CIN
ECC1_CIN_TBB[5:0]
E1
E2
E3
E4
E5
E6
E7
E8
OTP ECC CTRL1
OTP ECC CTRL2
OTP ECC CTRL3
OTP ECC CTRL4
OTP ECC CTRL5
OTP ECC CTRL6
OTP ECC CTRL7
OTP ECC CTRL8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ECC2_EN_
TBB
ECC2_CALC_
CIN
ECC2_CIN_TBB[5:0]
0
0
0
0
0
0
0
0
0
0
0
ECC3_EN_
TBB
ECC3_CALC_
CIN
ECC3_CIN_TBB[5:0]
0
0
0
0
ECC4_EN_
TBB
ECC4_CALC_
CIN
ECC4_CIN_TBB[5:0]
0
0
0
0
ECC5_EN_
TBB
ECC5_CALC_
CIN
ECC5_CIN_TBB[5:0]
0
0
0
0
ECC6_EN_
TBB
ECC6_CALC_
CIN
ECC6_CIN_TBB[5:0]
0
0
0
0
ECC7_EN_
TBB
ECC7_CALC_
CIN
ECC7_CIN_TBB[5:0]
0
0
0
0
ECC8_EN_
TBB
ECC8_CALC_
CIN
ECC8_CIN_TBB[5:0]
0
0
0
0
PF0100Z
NXP Semiconductors
111
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 137. Extended page 2 (continued)
BITS[7:0]
Address
Register Name
TYPE
Default
7
6
5
0
0
4
0
0
3
2
1
0
0
0
0
0
ECC9_EN_
TBB
ECC9_CALC_
CIN
ECC9_CIN_TBB[5:0]
E9
OTP ECC CTRL9
R/W
8'b0000_0000
0
0
0
0
ECC10_EN_T ECC10_CALC
ECC10_CIN_TBB[5:0]
BB
_CIN
EA
OTP ECC CTRL10
R/W
8'b0000_0000
0
0
0
0
ANTIFUSE1_E ANTIFUSE1_L ANTIFUSE1_R
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
BYPASS1
N
OAD
W
F1
F2
F3
F4
F5
F6
F7
F8
F9
OTP FUSE CTRL1
OTP FUSE CTRL2
OTP FUSE CTRL3
OTP FUSE CTRL4
OTP FUSE CTRL5
OTP FUSE CTRL6
OTP FUSE CTRL7
OTP FUSE CTRL8
OTP FUSE CTRL9
OTP FUSE CTRL10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
0
0
0
0
ANTIFUSE2_E ANTIFUSE2_L ANTIFUSE2_R
BYPASS2
N
OAD
W
0
0
0
0
ANTIFUSE3_E ANTIFUSE3_L ANTIFUSE3_R
BYPASS3
N
OAD
W
0
0
0
0
ANTIFUSE4_E ANTIFUSE4_L ANTIFUSE4_R
BYPASS4
N
OAD
W
0
0
0
0
ANTIFUSE5_E ANTIFUSE5_L ANTIFUSE5_R
BYPASS5
N
OAD
W
0
0
0
0
ANTIFUSE6_E ANTIFUSE6_L ANTIFUSE6_R
BYPASS6
N
OAD
W
0
0
0
0
ANTIFUSE7_E ANTIFUSE7_L ANTIFUSE7_R
BYPASS7
N
OAD
W
0
0
0
0
ANTIFUSE8_E ANTIFUSE8_L ANTIFUSE8_R
BYPASS8
N
OAD
W
0
0
0
0
ANTIFUSE9_E ANTIFUSE99_ ANTIFUSE9_R
BYPASS9
N
LOAD
W
0
0
0
0
ANTIFUSE10_ ANTIFUSE10_ ANTIFUSE10_
BYPASS10
0
EN
LOAD
RW
FA
0
0
0
Notes
81. Do not write in reserved registers.
PF0100Z
112
NXP Semiconductors
TYPICAL APPLICATIONS
7
Typical applications
7.1
Introduction
Figure 29 provides a typical application diagram of the PF0100Z PMIC together with its functional components. For details on component
references and additional components such as filters, refer to the individual sections.
7.1.1 Application diagram
VIN1
SW1AB Output
SW1FB
1.0uF
2.2uF
4.7uF
Vin
VIN1
4.7uF
PF0100
VGEN1
100mA
SW1AIN
SW1ALX
VGEN1
O/P
Drive
1.0uH
SW1A/B
Single/Dual
2500 mA
Buck
VGEN2
250mA
VGEN2
4 x22uF
SW1BLX
SW1BIN
O/P
Drive
VIN2
1.0uF
2.2uF
VIN2
4.7uF
4.7uF
Vin
Vin
VGEN3
100mA
SW1C Output
VGEN3
1.0uH
SW1CLX
SW1CIN
O/P
Drive
SW1C
2000 mA
Buck
VGEN4
350mA
2 x 22uF
4.7uF
VGEN4
VIN3
SW1CFB
VIN3
SW1VSSSNS
Core Control logic
1.0uF
2.2uF
VGEN5
100mA
SW2 Output
1.0uH
VGEN5
VGEN6
SW2LX
SW2IN
SW2IN
SW2FB
Initialization State Machine
SW2
2000 mA
Buck
O/P
Drive
VGEN6
200mA
2.2uF
2 x 22uF
4.7uF
Vin
SW3AFB
OTP
Supplies
Control
SW3A Output
2 x 22uF
Vin
4.7uF
SW3AIN
SW3ALX
VDDOTP
O/P
Drive
VDDOTP
VDDIO
1.0uH
1.0uH
VDDIO
SW3A/B
Single/Dual
DDR
2500 mA
Buck
CONTROL
SW3BLX
SW3BIN
I2C
Interface
0.1uF
O/P
Drive
2 x 22uF
SCL
SDA
To
MCU
4.7uF
Vin
Vin
SW3BFB
SW3B Output
DVS CONTROL
SW3VSSSNS
DVS Control
SW4FB
SW4 Output
2 x 22uF
4.7uF
2.2uH
SW4
1000 mA
Buck
SW4IN
O/P
Drive
1.0uH
I2C
Register
map
SW4LX
1uF
Trim-In-Package
VCOREDIG
VCOREREF
GNDREF1
Vin
10uF
220nF
1uF
SWBSTLX
SWBSTIN
SWBSTFB
Reference
Generation
SWBST
Output
Clocks and
resets
SWBST
600 mA
Boost
O/P
Drive
Vin
VCORE
2 x 22uF
GNDREF
2.2uF
1uF
VREFDDR
VSW3A
VINREFDDR
100nF
100nF
Vin
Clocks
32kHz and 16MHz
Package Pin Legend
VHALF
Output Pin
Input Pin
Bi-directional Pin
VIN
1uF
Best
of
Supply
Li Cell
Charger
LICELL
100nF
VSNVS
Coin Cell
Battery
VSW2
VSW2
VSW2
VSW2
0.47uF
To/From
AP
Figure 29. Typical application schematic
PF0100Z
NXP Semiconductors
113
TYPICAL APPLICATIONS
7.1.2 Bill of materials
The following table provides a complete list of the recommended components on a full featured system using the PF0100Z Device. Critical
components such as inductors, transistors, and diodes are provided with a recommended part number, but equivalent components may
be used.
Table 138. Bill of materials (82)
Value
PMIC
Qty
Description
Part#
Manufacturer
Component/pin
1
Power management IC
MMPF0100Z
NXP
Buck, SW1AB - (0.300-1.875 V), 2.5 A
4 x 4 x 2.1
1.0 μH
1.0 μH
1
–
XFL4020-102MEB
LPS5015_102ML
Coilcraft
Coilcraft
Output inductor
I
= 4.5 A for 10% drop, DCR
= 11.9 mΩ
= 50 mΩ
SAT
MAX
MAX
5 x 5 x 1.5
= 3.6 A for 10% drop, DCR
Output inductor
optional
I
SAT
2.5 x 2.0 x 1.2
= 4.5 A
Output inductor
(optional)
1.0 μH
–
I
DFE252012PD-1R0M
TOKO
SAT
DCR
= 42 mΩ
MAX
22 μF
4.7 μF
0.1 μF
4
2
1
10 V X5R 0805
10 V X5R 0603
10 V X5R 0402
LMK212BJ226MG-T
LMK107BJ475KA-T
C0402C104K8PAC
Taiyo Yuden
Taiyo Yuden
Kemet
Output capacitance
SW1AIN, SW1BIN
Input capacitance
Buck, SW1C- (0.300-1.875 V), 2.0 A
4 x 4 x 1.2
1.0 μH
1.0 μH
1
–
LPS4012-102NL
XFL3012-102ML
Coilcraft
Coilcraft
Output inductor
I
= 2.8 A for 10% drop, DCR
= 60 mΩ
= 42 mΩ
SAT
MAX
MAX
3 x 3 x1.2
= 2.5 A for 10% drop, DCR
Output inductor
optional
I
SAT
2.5 x 2.0 x 1.2
= 4.5 A
Output inductor
(optional)
1.0 μH
–
I
DFE252012PD-1R0M
TOKO
SAT
DCR
= 42 mΩ
MAX
22 μF
4.7 μF
0.1 μF
2
1
1
10 V X5R 0805
10 V X5R 0603
10 V X5R 0402
LMK212BJ226MG-T
LMK107BJ475KA-T
C0402C104K8PAC
Taiyo Yuden
Taiyo Yuden
Kemet
Output capacitance
Input capacitance
Input capacitance
Buck, SW1ABC - (0.300-1.875 V), 4.5 A
4.2 x 4.2 x 2
1.0 μH
1
FDSD0420D-1R0M
TOKO Inc.
Output inductor
I
= 5.1 A for 10% drop, DCR
= 29 mΩ
SAT
MAX
22 μF
4.7 μF
0.1 μF
6
2
1
10 V X5R 0805
10 V X5R 0603
10 V X5R 0402
LMK212BJ226MG-T
LMK107BJ475KA-T
C0402C104K8PAC
Taiyo Yuden
Taiyo Yuden
Kemet
Output capacitance
Input capacitance
Input capacitance
PF0100Z
114
NXP Semiconductors
TYPICAL APPLICATIONS
Table 138. Bill of materials (82) (continued)
Value
Qty
Description
Part#
Manufacturer
Component/pin
Buck, SW2 - (0.400-3.300 V), 2.0 A
4 x 4 x 1.2
1.0 μH
1.0 μH
1
–
LPS4012-102NL
XFL3012-102ML
Coilcraft
Output inductor
I
= 2.8 A for 10% drop, DCR
= 60 mΩ
= 42 mΩ
SAT
MAX
MAX
3x 3 x 1.2
= 2.5 A for 10% drop, DCR
Output inductor
optional
Coilcraft
TOKO
I
SAT
2.5 x 2.0 x 1.2
= 4.5 A
Output inductor
(optional)
1.0 μH
–
I
DFE252012PD-1R0M
SAT
DCR
= 42 mΩ
MAX
22 μF
4.7 μF
0.1 μF
2
1
1
10 V X5R 0805
10 V X5R 0603
10 V X5R 0402
LMK212BJ226MG-T
LMK107BJ475KA-T
C0402C104K8PAC
Taiyo Yuden
Taiyo Yuden
Kemet
Output capacitance
Input capacitance
Input capacitance
Buck, SW3AB - (0.400-3.300 V), 2.5 A
4 x 4 x 2.1
1.0 μH
1.0 μH
1
–
XFL4020-102MEB
LPS5015_102ML
Coilcraft
Coilcraft
Output inductor
I
= 4.5 A for 10% drop, DCR
= 11.9 mΩ
= 50 mΩ
SAT
MAX
MAX
5 x 5 x 1.5
= 3.6 A for 10% drop, DCR
Output inductor
optional
I
SAT
2.5 x 2.0 x 1.2
= 4.5 A
Output inductor
(optional)
1.0 μH
–
I
DFE252012PD-1R0M
TOKO
SAT
DCR
= 42 mΩ
MAX
22 μF
4.7 μF
0.1 μF
4
2
1
10 V X5R 0805
10 V X5R 0603
10 V X5R 0402
LMK212BJ226MG-T
LMK107BJ475KA-T
C0402C104K8PAC
Taiyo Yuden
Taiyo Yuden
Kemet
Output capacitance
SW3AIN, SW3BIN
Input capacitance
Buck, SW4 - (0.400-3.300V), 1A
2.5 x 2 x 1
1.0 μH
1.0 μH
1.0 μH
1
–
-
VLS252010ET-1R0N
DFE252012PD-1R0M
XPL2010_102ML
TDK
Output inductor
I
= 1.8 A for 30% drop, DCR
= 84 mΩ
= 89 mΩ
SAT
MAX
2.5 x 2.0 x 1.2
= 4.5 A
Output inductor
(optional)
I
TOKO
Coilcraft
SAT
DCR
= 42 mΩ
MAX
2.2 x 2.1 x 1
= 1.2 A for 10% drop, DCR
Output inductor
optional
I
SAT
MAX
22 μF
4.7 μF
0.1 μF
2
1
1
10 V X5R 0805
10 V X5R 0603
10 V X5R 0402
LMK212BJ226MG-T
LMK107BJ475KA-T
C0402C104K8PAC
Taiyo Yuden
Taiyo Yuden
Kemet
Output capacitance
Input capacitance
Input capacitance
PF0100Z
NXP Semiconductors
115
TYPICAL APPLICATIONS
Table 138. Bill of materials (82) (continued)
Value
Qty
Description
Part#
Manufacturer
Component/pin
BOOST, SWBST - 5.0 V, 600 mA
3 x 3 x 1.5
2.2 μH
2.2 μH
–
–
LPS3015-222ML
Coilcraft
Output Inductor
I
= 2.0 A for 10% drop, DCR
= 110 mΩ
MAX
SAT
2.5 x 2.0 x 1.2
= 3.3 A
Output inductor
(optional)
I
DFE252012PD-2R2M
TOKO
SAT
DCR
= 84 mΩ
MAX
22 μF
10 μF
2.2 μF
0.1 μF
1.0 A
2
1
1
1
1
10 V X5R 0805
10 V X5R 0805
6.3 V X5R 0402
10 V X5R 0402
20 V SOD-123FL
LMK212BJ226MG-T
C2012X5R1A106MT
C0402C225M9PACTU
C0402C104K8PAC
MBR120VLSFT1G
Taiyo Yuden
TDK
Output capacitance
Input capacitance
Input capacitance
Input capacitance
Schottky diode
Kemet
Kemet
ON Semiconductor
LDO, VGEN1 - (0.80-1.55), 100 mA
2.2 μF
1.0 μF
1
1
6.3 V X5R 0402
10 V X5R 0402
C0402C225M9PACTU
CC0402KRX5R6BB105
Kemet
Output capacitance
Input capacitance
Yageo America
LDO, VGEN2 - (0.80-1.55), 250 mA
4.7 μF 6.3 V X5R 0402
LDO, VGEN3 - (1.80-3.30), 100 mA
1
C0402X5R6R3-475MNP
Venkel
Output capacitance
2.2 μF
1.0 μF
1
1
6.3 V X5R 0402
10 V X5R 0402
C0402C225M9PACTU
CC0402KRX5R6BB105
Kemet
Output capacitance
Input capacitance
Yageo America
LDO, VGEN4 - (1.80-3.30), 350 mA
4.7 μF 6.3 V X5R 0402
LDO, VGEN5 - (1.80-3.30), 150 mA
1
C0402X5R6R3-475MNP
Venkel
Output capacitance
2.2 μF
1.0 μF
1
1
6.3 V X5R 0402
10 V X5R 0402
C0402C225M9PACTU
CC0402KRX5R6BB105
Kemet
Output capacitance
Input capacitance
Yageo America
LDO, VGEN6 - (1.80-3.30), 200 mA
2.2 μF 6.3 V X5R 0402
LDO/Switch VSNVS - (1.1-3.3), 200 mA
0.47 μF 6.3 V X5R 0402
Reference, VREFDDR - (0.20-1.65V), 10 mA
1
C0402C225M9PACTU
C1005X5R0J474K
Kemet
TDK
Output capacitance
Output capacitance
Output capacitance
1
1.0 μF
0.1 μF
1
2
10 V X5R 0402
10 V X5R 0402
CC0402KRX5R6BB105
C0402C104K8PAC
Yageo America
Kemet
VHALF,
VINREFDDR
Internal references, VCOREDIG, VCOREREF, VCORE
1.0 μF
1
1
1
10 V X5R 0402
10 V X5R 0402
10 V X5R 0402
CC0402KRX5R6BB105
CC0402KRX5R6BB105
GRM155R61A224KE19D
Yageo America
Yageo America
Murata
VCOREDIG
VCORE
1.0 μF
0.22 μF
Coin cell
0.1 μF
VCOREREF
1
10 V X5R 0402
C0402C104K8PAC
Kemet
LICELL
PF0100Z
116
NXP Semiconductors
TYPICAL APPLICATIONS
Table 138. Bill of materials (82) (continued)
Value
Qty
Description
Part#
Manufacturer
Component/pin
Miscellaneous
0.1 μF
1
1
1
1
1
1
10 V X5R 0402
10 V X5R 0402
1/16 W 0402
1/16 W 0402
1/16 W 0402
1/16 W 0402
CD402C104K8PAC
CC0402KRX5R6BB105
RK73H1ETTP1003F
RK73H1ETTP1003F
RK73H1ETTP1003F
RK73H1ETTP1003F
Kemet
VDDIO
VIN
1.0 μF
Yageo America
KOA SPEER
KOA SPEER
KOA SPEER
KOA SPEER
100 kΩ
PWRON
RESETBMCU
SDWN
100 kΩ
100 kΩ
100 kΩ
INTB
Notes
82. NXP does not assume liability, endorse, or warrant components from external manufacturers referenced in circuit drawings or tables. While NXP
offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.
7.2
PF0100Z layout guidelines
7.2.1 General board recommendations
1. It is recommended to use an eight layer board stack-up arranged as follows:
• High current signal
• GND
• Signal
• Power
• Power
• Signal
• GND
• High current signal
2. Allocate TOP and BOTTOM PCB Layers for POWER ROUTING (high current signals), copper-pour the unused area.
3. Use internal layers sandwiched between two GND planes for the SIGNAL routing.
7.2.2 Component placement
It is desirable to keep all component related to the power stage as close to the PMIC as possible, specially decoupling input and output
capacitors.
7.2.3 General routing requirements
1. Some recommended things to keep in mind for manufacturability:
•
•
•
•
Via in pads require a 4.5 mil minimum annular ring. Pad must be 9.0 mils larger than the hole
Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper
Minimum allowed spacing between line and hole pad is 3.5 mils
Minimum allowed spacing between line and line is 3.0 mils
2. Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from power,
clock, or high power signals, like the ones on the SWxIN, SWx, SWxLX, SWBSTIN, SWBST, and SWBSTLX pins. They could be
also shielded.
3. Shield feedback traces of the regulators and keep them as short as possible (trace them on the bottom so the ground and power
planes shield these traces).
4. Avoid coupling traces between important signal/low noise supplies (like REFCORE, VCORE, VCOREDIG) from any switching node
(i.e. SW1ALX, SW1BLX, SW1CLX, SW2LX, SW3ALX, SW3BLX, SW4LX, and SWBSTLX).
5. Make sure all components related to a specific block are referenced to the corresponding ground.
PF0100Z
NXP Semiconductors
117
TYPICAL APPLICATIONS
7.2.4 Parallel routing requirements
1. I2C signal routing
•
CLK is the fastest signal of the system, so it must be given special care.
•
To avoid contamination of these delicate signals by nearby high power or high frequency signals, it is a good practice to
shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole
signal trace length.
Figure 30. Recommended shielding for critical signals.
•
•
These signals can be placed on an outer layer of the board to reduce their capacitance with respect to the ground plane.
Care must be taken with these signals not to contaminate analog signals, as they are high frequency signals. Another good
practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals.
7.2.5 Switching regulator layout recommendations
1. Per design, the switching regulators in PF0100Z are designed to operate with only one input bulk capacitor. However, it is
recommended to add a high-frequency filter input capacitor (CIN_hf), to filter out any noise at the regulator input. This capacitor
should be in the range of 100 nF and should be placed right next to or under the IC, closest to the IC pins.
2. Make high-current ripple traces low-inductance (short, high W/L ratio).
3. Make high-current traces wide or copper islands.
4. Make high-current traces symetrical for dual–phase regulators (SW1, SW3).
PF0100Z
118
NXP Semiconductors
TYPICAL APPLICATIONS
VIN
SWxIN
CIN_HF
CIN
SWx
SWxLX
Diver Controller
L
COUT
SWxFB
Compensation
Figure 31. Generic buck regulator architecture
Inductor
SWxIN
C
C
IN_HF
IN
SWxLX
SWxFB
COUT
GND
Figure 32. Recommended layout for buck regulators
7.3
Thermal information
7.3.1 Rating data
The thermal rating data of the packages has been simulated with the results listed in Table 5.
Junction to ambient thermal resistance nomenclature: the JEDEC specification reserves the symbol RθJA or θJA (Theta-JA) strictly for
junction-to-ambient thermal resistance on a 1s test board in natural convection environment. RθJMA or θJMA (Theta-JMA) is used for both
junction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and 2s2p
test boards. It is anticipated the generic name, Theta-JA, continues to be commonly used.
The JEDEC standards can be consulted at http://www.jedec.org.
PF0100Z
NXP Semiconductors
119
TYPICAL APPLICATIONS
7.3.2 Estimation of junction temperature
An estimation of the chip junction temperature TJ can be obtained from the equation:
TJ = TA + (RθJA x PD)
with:
TA = Ambient temperature for the package in °C
RθJA = Junction to ambient thermal resistance in °C/W
PD = Power dissipation in the package in W
The junction to ambient thermal resistance is an industry standard value provideing a quick and easy estimation of thermal performance.
Unfortunately, there are two values in common usage: the value determined on a single layer board RθJA and the value obtained on a four
layer board RθJMA. Actual application PCBs show a performance close to the simulated four layer board value although this may be
somewhat degraded in case of significant power dissipated by other components placed close to the device.
At a known board temperature, the junction temperature TJ is estimated using the following equation
TJ = TB + (RθJB x PD) with
TB = Board temperature at the package perimeter in °C
RθJB = Junction to board thermal resistance in °C/W
PD = Power dissipation in the package in W
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.
See 6 Functional block requirements and behaviors, page 17 for more details on thermal management.
PF0100Z
120
NXP Semiconductors
PACKAGING
8
Packaging
8.1
Packaging dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and
perform a keyword search for the drawing’s document number. See the 4.2 Thermal characteristics, page 10 for specific thermal
characteristics for each package.
Table 139. Package drawing information
Package
Suffix
Package outline drawing number
98ASA00589D
56 QFN 8x8 mm - 0.5 mm pitch. WF-Type (wettable flank)
ES
PF0100Z
NXP Semiconductors
121
PACKAGING
PF0100Z
122
NXP Semiconductors
PACKAGING
PF0100Z
NXP Semiconductors
123
PACKAGING
PF0100Z
124
NXP Semiconductors
REFERENCE SECTION
9
Reference section
9.1
Reference documents
Table 140. PF0100Z reference documents
Reference
Description
AN4536
AN4622
MMPF0100 OTP Programming Instructions
MMPF0100 Layout Guidelines
PF0100Z
NXP Semiconductors
125
REVISION HISTORY
10 Revision history
10.1 Document changes
Revision
1.0
Date
Description of Changes
11/2012
•
Initial release
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Deleted unneeded rows from Ordering information and updated part number
Changed Note 2
Added Note 4 to Pin Definitions and assigned it to the applicable pin names
Corrected Functional Block diagram
Corrected pin name in section 7.1
Deleted unnecessary columns in Table 9
Added section 7.2.1 and fixed TOC
Corrected FF row in Table 136
Corrected schematics 10, 11, 12, 14, 16, 17, 18, 20, and 22
Corrected page one package isometric
Added warning to note 6
Changed graphics on figures 13, 15, 19, and 21
Deleted original note 64.
Deleted reference to ICOINLO in Coin Cell Charger Control
Updated figure 28
Corrected part number in BOM
2.0
1/2013
Corrected #4 in General Routing Requirements
Added AN4622 to Reference Documents
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Separated VSNS pin for HBM page 9
Reworded sentence in Programming OTP fuses
Added 2.0 MHz clock frequency
Changed min. for VREFDDR Current Limit
Changed min. for VGEN1 DC Current Limit
Changed min. for VGEN1 DC Overcurrent Protection Threshold
Changed max. for VGEN2 ACTIVE MODE - DC Current Limit
Changed min. for VGEN3 DC Current Limit
Changed min. for VGEN4 DC Current Limit
Changed min. for VGEN5 ACTIVE MODE - DC Current Limit
Changed min. for VGEN6 DC Current Limit
Changed min. for VGEN6 DC Overcurrent Protection Threshold
Changed max. for VSNVS DC, LDO VIN Threshold, VIN going high with valid coin cell
Changed max. for VSNVS DC, LDO VIN Threshold, VIN going low with valid coin cell
Added note to VSNVS AC AND TRANSIENT Turn-on Time, and deleted notation of conditions
Register D8 and D9 in table 137 marked as reserved.
Added Figure 4
3.0
2/2013
Updated table 8. Current consumption summary.
PF0100Z
126
NXP Semiconductors
REVISION HISTORY
Revision
Date
Description of Changes
•
•
•
•
•
•
•
•
Added new package name and drawing for PF0100AZ
Added Table 2 listing differences between PF0100Z and PF0100AZ
Corrected VDDOTP maximum rating
Corrected SWBSTFB maximum rating
Updated Table 8 to included PF0100AZ specifications
Updated Figure 4
Added note of FUSE_POR-XOR bit for PF0100AZ in OTP prototyping
Corrected 2.0 MHz clock minimum specification from 1.85 MHz to 1.84 MHz in 16 MHz and 32 kHz
clocks
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Corrected inductor Isat for SW1ABC single phase mode from 4.5 A to 6.0 A
Tightened accuracy specification in PFM mode for all the switching regulators
Corrected typical efficiency specifications for all switching regulators
Added note to clarify SWBST default operation in Auto mode
Added current limit specifications for VGEN2, VGEN6, and VSNVS for PF0100AZ
Corrected conditions for VSNVS turn-on time specifications
Changed VTH1 maximum specification from 3.05 V to 3.1 V
Updated Control interface I2C block description to include note about SCL/SDA drive strength
Corrected default values of bits in INTMASK0 register in Table 118
Corrected default value of 4 MSBs in Table 128
Corrected default value of bits in SILICONREVID register in Table 126
Updated Typical Application Schematic to add bypass capacitor on VDDIO pin
Added capacitor at VDDIO pin in Bill of Material table
Noted that voltage settings 0.6 V and below are not supported
VSNVS Turn On Delay (td1) spec corrected from 15 ms to 5.0 ms
Updated per GPCN 16220
4.0
4/2014
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Updated as per PB 16482
Increased ambient operating temperature of MMPF0100NPAZES device
Added additional specification line items for Standby current, Sleep current, and VREFDDR accuracy
for the extended temperature operation
5.0
10/2014
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Added new part number MMPF0100F8AZES
Updated Table 9
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Corrected the temperature range for the device MMPF0100F8AZES in Table 1
Updated Table 23
Updated Bill of Materials Table 138
6.0
7.0
11/2014
7/2015
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Added new part numbers MMPF0100F9AZES and MMPF0100FAAZES to Table 1
Updated Table 9
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Added MMPF0100F0AZES to Table 1
Updated Table 9
Updated Table 52
10/2015
8.0
Updated Table 137
10/2015
12/2015
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Fixed typo on page 1
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Removed MMPF0100NPZES from Orderable part variations. No longer manufactured.
Added MMPF0100F6AZES to Orderable part variations
Updated Table 9 for MMPF0100F6AZES
9.0
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Updated SW2 current capability from 2000 mA to 2500 mA for F9/FA versions
10.0
11.0
3/2016
5/2016
2
Changed Table 9 row - Default I C Address from 0x80 to 0x08 for F0, F9, and FA
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Added NP version to OTP's with SW2 current capability of 2500 mA
Added BOM for SW1ABC
12.0
8/2016
PF0100Z
NXP Semiconductors
127
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Document Number: MMPF0100Z
Rev. 12.0
8/2016
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