BSS84,215 [NXP]

BSS84 - P-channel vertical D-MOS logic level FET TO-236 3-Pin;
BSS84,215
型号: BSS84,215
厂家: NXP    NXP
描述:

BSS84 - P-channel vertical D-MOS logic level FET TO-236 3-Pin

PC 开关 光电二极管 晶体管
文件: 总11页 (文件大小:61K)
中文:  中文翻译
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BSS84  
P-channel enhancement mode vertical DMOS transistor  
Rev. 06 — 16 December 2008  
Product data sheet  
1. Product profile  
1.1 General description  
P-channel enhancement mode vertical Diffusion Metal-Oxide Semiconductor (DMOS)  
transistor in a small Surface-Mounted Device (SMD) plastic package.  
Table 1.  
Product overview  
Type number[1]  
Package  
NXP  
JEDEC  
BSS84  
SOT23  
TO-236AB  
BSS84/DG  
[1] /DG: halogen-free  
1.2 Features  
I Low threshold voltage  
I Direct interface to CMOS and  
Transistor-Transistor Logic (TTL)  
I No secondary breakdown  
I High-speed switching  
1.3 Applications  
I Line current interrupter in telephone sets I Relay, high-speed and line transformer  
drivers  
1.4 Quick reference data  
I VDS ≤ −50 V  
I RDSon 10 Ω  
I ID ≤ −130 mA  
I Ptot 250 mW  
 
 
 
 
 
 
BSS84  
NXP Semiconductors  
P-channel enhancement mode vertical DMOS transistor  
2. Pinning information  
Table 2.  
Pinning  
Pin  
1
Symbol  
Description  
gate  
Simplified outline  
Graphic symbol  
G
S
D
3
D
2
source  
drain  
3
1
2
G
SOT23 (TO-236AB)  
S
001aaa025  
3. Ordering information  
Table 3.  
Ordering information  
Type number[1] Package  
Name  
Description  
Version  
BSS84  
TO-236AB plastic surface-mounted package; 3 leads  
SOT23  
BSS84/DG  
[1] /DG: halogen-free  
4. Marking  
Table 4.  
Marking codes  
Type number[1]  
Marking code[2]  
BSS84  
13*  
BSS84/DG  
ZV*  
[1] /DG: halogen-free  
[2] * = -: made in Hong Kong  
* = p: made in Hong Kong  
* = t: made in Malaysia  
* = W: made in China  
BSS84_6  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 06 — 16 December 2008  
2 of 11  
 
 
 
 
 
 
BSS84  
NXP Semiconductors  
P-channel enhancement mode vertical DMOS transistor  
5. Limiting values  
Table 5.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol Parameter  
Conditions  
Min  
Max  
50  
Unit  
V
VDS  
VGS  
ID  
drain-source voltage  
25 °C Tj 150 °C  
-
-
-
gate-source voltage  
drain current  
±20  
V
Tsp = 25 °C; VGS = 10 V;  
130  
mA  
see Figure 1  
Tsp = 100 °C;  
-
-
75  
mA  
mA  
VGS = 10 V  
IDM  
peak drain current  
Tsp = 25 °C; tp 10 µs;  
520  
see Figure 1  
[1]  
Ptot  
Tstg  
Tj  
total power dissipation  
storage temperature  
junction temperature  
Tsp = 25 °C; see Figure 2  
-
250  
mW  
°C  
65  
65  
+150  
+150  
°C  
[1] Device mounted on a Printed-Circuit Board (PCB).  
mld251  
3
2
10  
t
=
p
10 µs  
100 µs  
1 ms  
(1)  
I
D
(mA)  
10  
10 ms  
100 ms  
DC  
10  
1  
2
1  
10  
10  
V
(V)  
DS  
Tsp = 25 °C  
(1) RDSon limitation  
Fig 1. Safe operating area; continuous and peak drain currents as a function of drain-source voltage  
BSS84_6  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 06 — 16 December 2008  
3 of 11  
 
 
 
 
BSS84  
NXP Semiconductors  
P-channel enhancement mode vertical DMOS transistor  
mld199  
300  
P
tot  
(mW)  
200  
100  
0
0
50  
100  
150  
T
200  
(°C)  
amb  
Fig 2. Power derating curve  
6. Thermal characteristics  
Table 6.  
Thermal characteristics  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max Unit  
[1]  
Rth(j-a)  
thermal resistance from  
junction to ambient  
see Figure 3  
-
-
500  
K/W  
[1] Mounted on a PCB, vertical in still air.  
mld250  
3
10  
R
(K/W)  
th(j-a)  
δ = 0.75  
0.5  
2
0.2  
0.1  
10  
0.05  
0.02  
0.01  
10  
t
p
P
δ =  
T
1
0
t
t
p
T
2
1  
10  
6  
5  
4  
3  
2  
1  
3
10  
10  
10  
10  
10  
10  
1
10  
10  
10  
t
(s)  
p
Fig 3. Transient thermal impedance from junction to ambient as a function of pulse duration  
BSS84_6  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 06 — 16 December 2008  
4 of 11  
 
 
 
BSS84  
NXP Semiconductors  
P-channel enhancement mode vertical DMOS transistor  
7. Characteristics  
Table 7.  
Characteristics  
Tj = 25 °C unless otherwise specified.  
Symbol Parameter  
Static characteristics  
Conditions  
Min  
Typ  
Max Unit  
V(BR)DSS  
drain-source breakdown ID = 10 µA; VGS = 0 V  
50  
-
-
V
voltage  
VGS(th)  
gate-source threshold  
voltage  
ID = 1 mA; VDS = VGS;  
see Figure 8  
Tj = 25 °C  
0.8  
-
-
2  
V
V
Tj = 55 °C  
-
1.8  
IDSS  
drain leakage current  
gate leakage current  
VDS = 40 V; VGS = 0 V  
Tj = 25 °C  
-
-
100 nA  
VDS = 50 V; VGS = 0 V  
Tj = 25 °C  
-
-
-
-
-
-
10  
60  
100  
100  
10  
µA  
µA  
nA  
nA  
Tj = 125 °C  
-
IGSS  
VGS = +20 V; VDS = 0 V  
VGS = 20 V; VDS = 0 V  
-
-
RDSon  
drain-source on-state  
resistance  
VGS = 10 V;  
ID = 130 mA;  
see Figure 5 and 7  
6
Dynamic characteristics  
|Yfs|  
transfer admittance  
VDS = 25 V;  
ID = 130 mA  
50  
-
-
mS  
Ciss  
Coss  
Crss  
input capacitance  
output capacitance  
VGS = 0 V; VDS = 25 V;  
f = 1 MHz; see Figure 9  
-
-
-
25  
15  
3.5  
45  
25  
12  
pF  
pF  
pF  
reverse transfer  
capacitance  
ton  
turn-on time  
VDS = 40 V; VGS = 0 V  
to 10 V; ID = 200 mA;  
see Figure 10 and 11  
-
-
3
7
-
-
ns  
ns  
toff  
turn-off time  
VDS = 40 V;  
VGS = 10 V to 0 V;  
ID = 200 mA;  
see Figure 10 and 11  
BSS84_6  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 06 — 16 December 2008  
5 of 11  
 
BSS84  
NXP Semiconductors  
P-channel enhancement mode vertical DMOS transistor  
mld197  
mld198  
600  
60  
V
= 10 V  
7.5 V  
GS  
6 V  
R
DSon  
I
V
= 2.5 V 3 V 4 V  
GS  
5 V  
D
()  
(mA)  
400  
40  
20  
0
5 V  
4 V  
200  
7.5 V  
10 V  
3 V  
2.5 V  
0
2
3
0
2  
4  
6  
8  
10  
12  
(V)  
1  
10  
10  
10  
V
I (mA)  
D
DS  
Tj = 25 °C  
Tj = 25 °C  
Fig 4. Output characteristics: drain current as a  
function of drain-source voltage; typical  
values  
Fig 5. Drain-source on-state resistance as a function  
of drain current; typical values  
mld196  
mld194  
1.8  
600  
(1)  
I
R
DSon  
D
(mA)  
R
DSon(25°C)  
(2)  
1.4  
400  
1.0  
0.6  
200  
0
0
2  
4  
6  
8  
10  
(V)  
50  
0
50  
100  
150  
T (°C)  
j
V
GS  
Tj = 25 °C; VDS = 10 V  
(1) ID = 130 mA; VGS = 10 V  
(2) ID = 20 mA; VGS = 2.4 V  
Fig 6. Transfer characteristics: drain current as a  
function of gate-source voltage; typical values  
Fig 7. Normalized drain-source on-state resistance  
factor as a function of junction temperature  
BSS84_6  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 06 — 16 December 2008  
6 of 11  
BSS84  
NXP Semiconductors  
P-channel enhancement mode vertical DMOS transistor  
mld195  
mld191  
1.2  
80  
C
(pF)  
V
GSth  
V
GSth(25°C)  
60  
40  
1.0  
C
iss  
0.8  
20  
0
C
oss  
C
rss  
0.6  
50  
0
10  
20  
30  
0
50  
100  
150  
V
(V)  
DS  
T (°C)  
j
ID = 1 mA; VDS = VGS  
VGS = 0 V; f = 1 MHz  
Fig 8. Gate-source threshold voltage as a function of  
junction temperature  
Fig 9. Input, output and reverse transfer  
capacitances as a function of drain-source  
voltage; typical values  
8. Test information  
10 %  
V
= 40 V  
DS  
INPUT  
90 %  
10 %  
OUTPUT  
0 V  
I
D
90 %  
10 V  
50 Ω  
t
t
off  
on  
mld189  
mbb690  
Fig 10. Switching time test circuit  
Fig 11. Input and output waveforms  
BSS84_6  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 06 — 16 December 2008  
7 of 11  
 
BSS84  
NXP Semiconductors  
P-channel enhancement mode vertical DMOS transistor  
9. Package outline  
Plastic surface-mounted package; 3 leads  
SOT23  
D
B
E
A
X
H
v
M
A
E
3
Q
A
A
1
c
1
2
e
1
b
p
w M  
B
L
p
e
detail X  
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
1
UNIT  
b
c
D
E
e
e
H
L
Q
v
w
A
p
p
1
E
max.  
1.1  
0.9  
0.48  
0.38  
0.15  
0.09  
3.0  
2.8  
1.4  
1.2  
2.5  
2.1  
0.45  
0.15  
0.55  
0.45  
mm  
0.1  
1.9  
0.95  
0.2  
0.1  
REFERENCES  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
JEDEC  
JEITA  
04-11-04  
06-03-16  
SOT23  
TO-236AB  
Fig 12. Package outline SOT23 (TO-236AB)  
BSS84_6  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 06 — 16 December 2008  
8 of 11  
 
BSS84  
NXP Semiconductors  
P-channel enhancement mode vertical DMOS transistor  
10. Revision history  
Table 8.  
Revision history  
Document ID  
BSS84_6  
Release date  
Data sheet status  
Change notice  
Supersedes  
20081216  
Product data sheet  
-
BSS84_5  
Modifications:  
BSS84_5  
Table 5 “Limiting values”: Ptot figure reference updated  
20081209  
20070717  
20030804  
19970618  
19950407  
Product data sheet  
Product data sheet  
Product specification  
Product specification  
Product specification  
-
-
-
-
-
BSS84_4  
BSS84_3  
BSS84_2  
BSS84_1  
-
BSS84_4  
BSS84_3  
BSS84_2  
BSS84_1  
BSS84_6  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 06 — 16 December 2008  
9 of 11  
 
BSS84  
NXP Semiconductors  
P-channel enhancement mode vertical DMOS transistor  
11. Legal information  
11.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
11.2 Definitions  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Terms and conditions of sale — NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
11.3 Disclaimers  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
11.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
12. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
BSS84_6  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 06 — 16 December 2008  
10 of 11  
 
 
 
 
 
 
BSS84  
NXP Semiconductors  
P-channel enhancement mode vertical DMOS transistor  
13. Contents  
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
1.1  
1.2  
1.3  
1.4  
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1  
2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Test information. . . . . . . . . . . . . . . . . . . . . . . . . 7  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9  
3
4
5
6
7
8
9
10  
11  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 10  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
11.1  
11.2  
11.3  
11.4  
12  
13  
Contact information. . . . . . . . . . . . . . . . . . . . . 10  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2008.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 16 December 2008  
Document identifier: BSS84_6  
 

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