首页 |元器件品牌

BUK754R0-55B [NXP]

TrenchMOS standard level FET; 的TrenchMOS标准水平FET
BUK754R0-55B
型号： BUK754R0-55B
厂家： NXP    NXP
描述：

TrenchMOS standard level FET
的TrenchMOS标准水平FET

晶体 晶体管 功率场效应晶体管 开关 脉冲 局域网
文件： 总15页 (文件大小：136K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
BUK75/764R0-55B  
TrenchMOS™ standard level FET  
Rev. 02 — 30 September 2002  
Product data  
1. Product profile  
1.1 Description  
N-channel enhancement mode field-effect power transistor in a plastic package using  
Philips High-Performance Automotive TrenchMOS™ technology.  
Product availability:  
BUK754R0-55B in SOT78 (TO-220AB)  
BUK764R0-55B in SOT404 (D2-PAK).  
1.2 Features  
■ Very low on-state resistance  
■ 175 °C rated  
■ Q101 compliant  
■ Standard level compatible.  
1.3 Applications  
■ Automotive systems  
■ 12 V and 24 V loads  
■ Motors, lamps and solenoids  
■ General purpose power switching.  
1.4 Quick reference data  
■ EDS(AL)S ≤ 1.2 J  
■ ID ≤ 75 A  
■ RDSon = 3.4 mΩ (typ)  
■ Ptot ≤ 300 W.  
2. Pinning information  
Table 1:  
Pinning - SOT78 and SOT404 simplified outlines and symbol  
Pin  
1
Description  
gate (g)  
Simplified outline  
Symbol  
mb  
mb  
d
[1]  
2
drain (d)  
3
source (s)  
g
mb  
mounting base,  
connected to  
drain (d)  
s
MBB076  
2
1
3
MBK116  
MBK106  
1
2 3  
SOT404 (D2-PAK)  
SOT78 (TO-220AB)  
[1] It is not possible to make connection to pin 2 of the SOT404 package.  
 
 
 
 
 
BUK75/764R0-55B  
Philips Semiconductors  
TrenchMOS™ standard level FET  
3. Limiting values  
Table 2: Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol Parameter  
Conditions  
Min  
Max  
55  
Unit  
V
VDS  
VDGR  
VGS  
ID  
drain-source voltage (DC)  
-
-
-
-
-
-
-
drain-gate voltage (DC)  
gate-source voltage (DC)  
drain current (DC)  
RGS = 20 kΩ  
55  
V
±20  
193  
75  
V
[1]  
[2]  
[2]  
Tmb = 25 °C; VGS = 10 V;  
Figure 2 and 3  
A
A
Tmb = 100 °C; VGS = 10 V; Figure 2  
75  
A
IDM  
peak drain current  
Tmb = 25 °C; pulsed; tp ≤ 10 µs;  
774  
A
Figure 3  
Ptot  
Tstg  
Tj  
total power dissipation  
storage temperature  
Tmb = 25 °C; Figure 1  
-
300  
W
−55  
−55  
+175  
+175  
°C  
°C  
operating junction temperature  
Source-drain diode  
[1]  
[2]  
IDR  
reverse drain current (DC)  
Tmb = 25 °C  
-
-
-
193  
75  
A
A
A
IDRM  
peak reverse drain current  
Tmb = 25 °C; pulsed; tp ≤ 10 µs  
774  
Avalanche ruggedness  
EDS(AL)S non-repetitive drain-source avalanche unclamped inductive load; ID = 75 A;  
energy DS ≤ 55 V; VGS = 10 V; RGS = 50 Ω;  
-
1.2  
J
V
starting Tmb = 25 °C  
[1] Current is limited by power dissipation chip rating  
[2] Continuous current is limited by package  
9397 750 10276  
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.  
Product data  
Rev. 02 — 30 September 2002  
2 of 15  
 
 
BUK75/764R0-55B  
Philips Semiconductors  
TrenchMOS™ standard level FET  
03na19  
200  
120  
I
D
(A)  
P
der  
(%)  
150  
80  
100  
50  
0
40  
Capped at 75 A due to package  
0
25  
50  
75  
100  
125  
150  
175  
T
200  
(ºC)  
0
50  
100  
150  
200  
(°C)  
T
mb  
mb  
VGS ≥ 10 V  
Ptot  
Pder  
=
× 100%  
-----------------------  
P
°
tot(25 C)  
Fig 1. Normalized total power dissipation as a  
function of mounting base temperature.  
Fig 2. Continuous drain current as a function of  
mounting base temperature.  
03ng55  
3
10  
t
= 10 µs  
p
I
Limit R  
DSon  
= V /I  
DS D  
D
(A)  
2
10  
100 µs  
1 ms  
Capped at 75 A due to package  
DC  
10 ms  
10  
100 ms  
1
-1  
10  
2
10  
1
10  
V
(V)  
DS  
Tmb = 25 °C; IDM single pulse.  
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.  
9397 750 10276  
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.  
Product data  
Rev. 02 — 30 September 2002  
3 of 15  
BUK75/764R0-55B  
Philips Semiconductors  
TrenchMOS™ standard level FET  
4. Thermal characteristics  
Table 3:  
Thermal characteristics  
Symbol Parameter  
Conditions  
Min Typ Max Unit  
Rth(j-mb) thermal resistance from junction to  
mounting base  
Figure 4  
-
-
0.5 K/W  
Rth(j-a)  
thermal resistance from junction to  
ambient  
SOT78  
vertical in still air  
-
-
60  
50  
-
-
K/W  
K/W  
SOT404  
mounted on a printed circuit board; minimum  
footprint  
4.1 Transient thermal impedance  
03ng56  
1
Z
th(j-mb)  
(K/W)  
δ = 0.5  
-1  
0.2  
10  
0.1  
0.05  
0.02  
-2  
10  
t
p
P
δ =  
T
single shot  
t
t
p
T
-3  
10  
-6  
10  
-5  
10  
-4  
10  
-3  
10  
-2  
10  
-1  
10  
1
t
(s)  
p
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.  
9397 750 10276  
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.  
Product data  
Rev. 02 — 30 September 2002  
4 of 15  
 
 
BUK75/764R0-55B  
Philips Semiconductors  
TrenchMOS™ standard level FET  
5. Characteristics  
Table 4: Characteristics  
Tj = 25 °C unless otherwise specified  
Symbol  
Static characteristics  
V(BR)DSS drain-source breakdown  
voltage  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
ID = 0.25 mA; VGS = 0 V  
Tj = 25 °C  
55  
50  
-
-
-
-
V
V
Tj = −55 °C  
VGS(th)  
gate-source threshold voltage ID = 1 mA; VDS = VGS  
Figure 9  
Tj = 25 °C  
;
2
1
-
3
-
4
V
V
V
Tj = 175 °C  
Tj = −55 °C  
-
-
4.4  
IDSS  
drain-source leakage current VDS = 55 V; VGS = 0 V  
Tj = 25 °C  
Tj = 175 °C  
-
-
-
0.02  
1
µA  
µA  
nA  
-
500  
100  
IGSS  
gate-source leakage current VGS = ±20 V; VDS = 0 V  
2
RDSon  
drain-source on-state  
resistance  
VGS = 10 V; ID = 25 A;  
Figure 7 and 8  
Tj = 25 °C  
-
-
3.4  
-
4.0  
8
mΩ  
mΩ  
Tj = 175 °C  
Dynamic characteristics  
Qg(tot)  
Qgs  
Qgd  
Ciss  
Coss  
Crss  
td(on)  
tr  
total gate charge  
VGS = 10 V; VDD = 44 V;  
ID = 25 A; Figure 14  
-
-
-
-
-
-
-
-
-
-
-
86  
-
nC  
nC  
nC  
pF  
pF  
pF  
ns  
gate-to-source charge  
gate-to-drain (Miller) charge  
input capacitance  
output capacitance  
reverse transfer capacitance  
turn-on delay time  
rise time  
18  
-
25  
-
VGS = 0 V; VDS = 25 V;  
f = 1 MHz; Figure 12  
5082  
1054  
289  
23  
6776  
1265  
396  
VDD = 30 V; RL = 1.2 Ω;  
VGS = 10 V; RG = 10 Ω  
-
-
-
-
-
51  
ns  
td(off)  
tf  
turn-off delay time  
fall time  
71  
ns  
41  
ns  
Ld  
internal drain inductance  
from drain lead 6 mm from  
package to centre of die  
4.5  
nH  
from contact screw on  
mounting base to centre of  
die SOT78  
-
-
-
3.5  
2.5  
7.5  
-
-
-
nH  
nH  
nH  
from upper edge of drain  
mounting base to centre of  
die SOT404  
Ls  
internal source inductance  
from source lead to source  
bond pad  
9397 750 10276  
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.  
Product data  
Rev. 02 — 30 September 2002  
5 of 15  
 
BUK75/764R0-55B  
Philips Semiconductors  
TrenchMOS™ standard level FET  
Table 4: Characteristics…continued  
Tj = 25 °C unless otherwise specified  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Source-drain diode  
VSD  
source-drain (diode forward) IS = 40 A; VGS = 0 V;  
-
0.85  
1.2  
V
voltage  
Figure 15  
trr  
reverse recovery time  
recovered charge  
IS = 20 A; dIS/dt = −100 A/µs  
VGS = −10 V; VDS = 30 V  
-
-
95  
-
-
ns  
Qr  
251  
nC  
9397 750 10276  
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.  
Product data  
Rev. 02 — 30 September 2002  
6 of 15  
BUK75/764R0-55B  
Philips Semiconductors  
TrenchMOS™ standard level FET  
03nh21  
03nh22  
7
300  
7
20  
10  
I
R
D
(A)  
6.5  
DSon  
6
(mΩ)  
250  
200  
150  
100  
50  
6
5
4
3
5.5  
5
4.5  
V
= 4 V  
GS  
6
0
5
10  
15  
20  
0
2
4
8
10  
(V)  
V
(V)  
GS  
V
DS  
Tj = 25 °C; tp = 300 µs  
Tj = 25 °C; ID = 25 A  
Fig 5. Output characteristics: drain current as a  
function of drain-source voltage; typical values.  
Fig 6. Drain-source on-state resistance as a function  
of gate-source voltage; typical values.  
03nh23  
03ne89  
7
2
R
DSon  
(mΩ)  
a
V
= 6 V  
GS  
6
5
4
3
1.5  
6.5  
7
1
0.5  
0
8
10  
-60  
0
60  
120  
180  
0
50  
100  
150  
200  
250  
300  
(A)  
T ( C)  
I
°
j
D
Tj = 25 °C  
RDSon  
a =  
----------------------------  
RDSon(25 C)  
°
Fig 7. Drain-source on-state resistance as a function  
of drain current; typical values.  
Fig 8. Normalized drain-source on-state resistance  
factor as a function of junction temperature.  
9397 750 10276  
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.  
Product data  
Rev. 02 — 30 September 2002  
7 of 15  
BUK75/764R0-55B  
Philips Semiconductors  
TrenchMOS™ standard level FET  
03aa32  
03aa35  
-1  
-2  
-3  
-4  
-5  
-6  
5
10  
I
V
D
(A)  
GS(th)  
(V)  
4
10  
max  
typ  
min  
typ  
max  
3
2
1
0
10  
10  
10  
10  
min  
-60  
0
60  
120  
180  
0
2
4
6
°
T ( C)  
V
(V)  
j
GS  
ID = 1 mA; VDS = VGS  
Tj = 25 °C; VDS = VGS  
Fig 9. Gate-source threshold voltage as a function of  
junction temperature.  
Fig 10. Sub-threshold drain current as a function of  
gate-source voltage.  
03nh19  
03nh24  
120  
fs  
(S)  
7000  
g
C
(pF)  
6000  
100  
C
iss  
5000  
80  
60  
40  
20  
0
4000  
C
oss  
3000  
2000  
C
1000  
0
rss  
-1  
10  
2
10  
0
20  
40  
60  
1
10  
I
(A)  
V
(V)  
D
DS  
Tj = 25 °C; VDS = 25 V  
VGS = 0 V; f = 1 MHz  
Fig 11. Forward transconductance as a function of  
drain current; typical values.  
Fig 12. Input, output and reverse transfer capacitances  
as a function of drain-source voltage; typical  
values.  
9397 750 10276  
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.  
Product data  
Rev. 02 — 30 September 2002  
8 of 15  
BUK75/764R0-55B  
Philips Semiconductors  
TrenchMOS™ standard level FET  
03nh20  
03nh18  
100  
10  
V
I
GS  
D
(A)  
(V)  
80  
8
V
= 14 (V)  
V
= 44 (V)  
DD  
60  
40  
20  
6
4
2
0
DD  
T = 175 ºC  
j
T = 25 ºC  
j
0
0
2
4
6
0
20  
40  
60  
80  
Q
100  
(nC)  
V
(V)  
GS  
G
VDS = 25 V  
Tj = 25 °C; ID = 25 A  
Fig 13. Transfer characteristics: drain current as a  
function of gate-source voltage; typical values.  
Fig 14. Gate-source voltage as a function of turn-on  
gate charge; typical values.  
03nh17  
100  
I
D
(A)  
80  
60  
40  
20  
T = 175 ºC  
j
T = 25 ºC  
j
0
0.0  
0.2  
0.4  
0.6  
0.8  
V
1.0  
(V)  
SD  
VGS = 0 V  
Fig 15. Reverse diode current as a function of reverse diode voltage; typical values.  
9397 750 10276  
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.  
Product data  
Rev. 02 — 30 September 2002  
9 of 15  
BUK75/764R0-55B  
Philips Semiconductors  
TrenchMOS™ standard level FET  
6. Package outline  
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB  
SOT78  
E
p
A
A
1
q
mounting  
base  
D
1
D
(1)  
L
L
2
1
Q
b
1
L
1
2
3
b
c
e
e
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
b
L
max.  
(1)  
2
e
A
b
D
E
L
D
L
1
A
c
UNIT  
p
q
Q
1
1
1
4.5  
4.1  
1.39  
1.27  
0.9  
0.7  
1.3  
1.0  
0.7  
0.4  
15.8  
15.2  
6.4  
5.9  
10.3  
9.7  
15.0  
13.5  
3.30  
2.79  
3.8  
3.6  
3.0  
2.7  
2.6  
2.2  
mm  
3.0  
2.54  
Note  
1. Terminals in this zone are not tinned.  
REFERENCES  
JEDEC  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
EIAJ  
SC-46  
00-09-07  
01-02-16  
SOT78  
3-lead TO-220AB  
Fig 16. SOT78 (TO-220AB).  
9397 750 10276  
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.  
Product data  
Rev. 02 — 30 September 2002  
10 of 15  
 
BUK75/764R0-55B  
Philips Semiconductors  
TrenchMOS™ standard level FET  
2
Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads  
(one lead cropped)  
SOT404  
A
A
E
1
mounting  
base  
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
D
E
A
A
b
UNIT  
c
D
e
L
H
Q
1
1
p
D
max.  
4.50  
4.10  
1.40  
1.27  
0.85  
0.60  
0.64  
0.46  
1.60  
1.20  
10.30  
9.70  
2.90 15.80 2.60  
2.10 14.80 2.20  
mm  
11  
2.54  
REFERENCES  
JEDEC  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
EIAJ  
99-06-25  
01-02-12  
SOT404  
Fig 17. SOT404 (D2-PAK)  
9397 750 10276  
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.  
Product data  
Rev. 02 — 30 September 2002  
11 of 15  
BUK75/764R0-55B  
Philips Semiconductors  
TrenchMOS™ standard level FET  
7. Soldering  
10.85  
10.60  
10.50  
1.50  
7.50  
7.40  
1.70  
2.15  
1.50  
2.25  
8.275  
8.35  
8.15  
4.60  
0.30  
4.85  
5.40  
7.95  
8.075  
3.00  
0.20  
1.20  
1.30  
1.55  
solder lands  
solder resist  
occupied area  
solder paste  
5.08  
MSD057  
Dimensions in mm.  
Fig 18. Reflow soldering footprint for SOT404.  
9397 750 10276  
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.  
Product data  
Rev. 02 — 30 September 2002  
12 of 15  
 
BUK75/764R0-55B  
Philips Semiconductors  
TrenchMOS™ standard level FET  
8. Revision history  
Table 5:  
Revision history  
CPCN  
Rev Date  
Description  
02 20020930  
-
Product data (9397 750 10276)  
Modifications:  
• Description in Section 1 changed from:  
N-channel enhancement mode field-effect power transistor in a plastic package using  
generation three TrenchMOS™ technology, featuring very low on-state resistance.  
to:  
N-channel enhancement mode field-effect power transistor in a plastic package using  
Philips High-Performance Automotive TrenchMOS™ technology.  
01 20020328  
-
Product data (9397 750 09492)  
9397 750 10276  
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.  
Product data  
Rev. 02 — 30 September 2002  
13 of 15  
 
BUK75/764R0-55B  
Philips Semiconductors  
TrenchMOS™ standard level FET  
9. Data sheet status  
Data sheet status[1]  
Product status[2]  
Definition  
Objective data  
Development  
This data sheet contains data from the objective specification for product development. Philips Semiconductors  
reserves the right to change the specification in any manner without notice.  
Preliminary data  
Product data  
Qualification  
Production  
This data sheet contains data from the preliminary specification. Supplementary data will be published at a  
later date. Philips Semiconductors reserves the right to change the specification without notice, in order to  
improve the design and supply the best possible product.  
This data sheet contains data from the product specification. Philips Semiconductors reserves the right to  
make changes at any time in order to improve the design, manufacturing and supply. Changes will be  
communicated according to the Customer Product/Process Change Notification (CPCN) procedure  
SNW-SQ-650A.  
[1]  
[2]  
Please consult the most recently issued data sheet before initiating or completing a design.  
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at  
URL http://www.semiconductors.philips.com.  
10. Definitions  
11. Disclaimers  
Short-form specification — The data in a short-form specification is  
extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Life support — These products are not designed for use in life support  
appliances, devices, or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors  
customers using or selling these products for use in such applications do so  
at their own risk and agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Limiting values definition — Limiting values given are in accordance with  
the Absolute Maximum Rating System (IEC 60134). Stress above one or  
more of the limiting values may cause permanent damage to the device.  
These are stress ratings only and operation of the device at these or at any  
other conditions above those given in the Characteristics sections of the  
specification is not implied. Exposure to limiting values for extended periods  
may affect device reliability.  
Right to make changes — Philips Semiconductors reserves the right to  
make changes, without notice, in the products, including circuits, standard  
cells, and/or software, described or contained herein in order to improve  
design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no  
licence or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are  
free from patent, copyright, or mask work right infringement, unless otherwise  
specified.  
Application information — Applications that are described herein for any  
of these products are for illustrative purposes only. Philips Semiconductors  
make no representation or warranty that such applications will be suitable for  
the specified use without further testing or modification.  
12. Trademarks  
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.  
Contact information  
For additional information, please visit http://www.semiconductors.philips.com.  
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.  
Fax: +31 40 27 24825  
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.  
14 of 15  
9397 750 10276  
Product data  
Rev. 02 — 30 September 2002  
 
 
 
 
 
BUK75/764R0-55B  
Philips Semiconductors  
TrenchMOS™ standard level FET  
Contents  
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1  
1.1  
1.2  
1.3  
1.4  
2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4  
Transient thermal impedance . . . . . . . . . . . . . . 4  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10  
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 14  
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
3
4
4.1  
5
6
7
8
9
10  
11  
12  
© Koninklijke Philips Electronics N.V. 2002.  
Printed in The Netherlands  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior  
written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or  
contract, is believed to be accurate and reliable and may be changed without notice. No  
liability will be accepted by the publisher for any consequence of its use. Publication  
thereof does not convey nor imply any license under patent- or other industrial or  
intellectual property rights.  
Date of release: 30 September 2002  
Document order number: 9397 750 10276  

相关型号：

BUK754R0-55B,127

 N-channel TrenchMOS standard level FET TO-220 3-Pin
NXP

BUK754R3-40B

 TrenchMOS standard level FET
NXP

BUK754R3-40B,127

 N-channel TrenchMOS standard level FET TO-220 3-Pin
NXP

BUK754R3-75C

 N-channel TrenchMOS standard level FET
NXP

BUK754R7-60E

 100A, 60V, 0.0046ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB, PLASTIC, SC-46, 3 PIN
NXP

BUK7556-30

 N-Channel Enhancement MOSFET
ETC

BUK755R2-40B

 N-channel TrenchMOS standard level FET
NXP

BUK755R2-40B,127

 N-channel TrenchMOS standard level FET TO-220 3-Pin
NXP

BUK755R4-100E

 120A, 100V, 0.0052ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB, PLASTIC, SC-46, 3 PIN
NXP

BUK755R4-100E,127

 N-channel TrenchMOS standard level FET TO-220 3-Pin
NXP

BUK7560-100A

 TrenchMOS standard level FET
NXP

BUK7560-100A,127

 BUK7560-100A
NXP
©2020 ICPDF网 联系我们和版权申明