BUK95180-100A [NXP]
Logic level FET; 逻辑电平FET
| 型号： | BUK95180-100A |
| 厂家： | 
NXP |
| 描述： | Logic level FET |
| 文件： | 总9页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK95180-100A
BUK96180-100A
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope available in
TO220AB and SOT404 . Using
’trench’ technology which features
very low on-state resistance. It is
intended for use in automotive and
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Ptot
Tj
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
100
11
54
V
A
W
˚C
175
RDS(ON)
general
purpose
switching
resistance
V
GS = 5 V
180
173
mΩ
mΩ
applications.
VGS = 10 V
PINNING
TO220AB & SOT404
PIN CONFIGURATION
SYMBOL
PIN DESCRIPTION
d
tab
mb
1
2
3
gate
drain
source
g
2
1
3
1
2
3
TO220AB
BUK95180-100A
SOT404
BUK96180-100A
tab/mb drain
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
ID
ID
IDM
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
-
-
-
-
-
-
-
-
100
100
15
11
7.7
44
V
V
V
A
A
A
W
˚C
RGS = 20 kΩ
-
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
Ptot
Tstg, Tj
54
175
- 55
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-mb
Rth j-a
Rth j-a
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient(TO220AB)
Thermal resistance junction to
ambient(SOT404)
-
-
2.8
K/W
in free air
60
50
-
-
K/W
K/W
Minimum footprint, FR4
board
May 2000
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK95180-100A
BUK96180-100A
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DSS
VGS(TO)
Drain-source breakdown
voltage
Gate threshold voltage
VGS = 0 V; ID = 0.25 mA;
100
89
1
0.5
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
µA
µA
nA
mΩ
mΩ
mΩ
mΩ
Tj = -55˚C
VDS = VGS; ID = 1 mA
1.5
-
-
0.05
-
2
165
-
152
170
2.0
-
2.3
10
500
100
180
450
173
200
Tj = 175˚C
Tj = -55˚C
IDSS
Zero gate voltage drain current VDS = 100 V; VGS = 0 V;
Tj = 175˚C
Tj = 175˚C
IGSS
RDS(ON)
Gate source leakage current
Drain-source on-state
resistance
VGS = ±10 V; VDS = 0 V
VGS = 5 V; ID = 5 A
V
V
GS = 10 V; ID = 5 A
GS = 4.5 V; ID = 5 A
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
464
60
37
619
72
50
pF
pF
pF
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; Rload =1.2Ω;
VGS = 5 V; RG = 10 Ω
-
-
-
-
9
112
18
20
157
27
ns
ns
ns
ns
25
38
Ld
Ld
Ld
Ls
Internal drain inductance
Internal drain inductance
Internal drain inductance
Internal source inductance
Measured from drain lead 6 mm
from package to centre of die
Measured from contact screw on
tab to centre of die(TO220AB)
Measured from upper edge of drain
tab to centre of die(SOT404)
Measured from source lead to
source bond pad
-
-
-
-
4.5
3.5
2.5
7.5
-
-
-
-
nH
nH
nH
nH
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IDR
Continuous reverse drain
current
-
-
11
A
IDRM
VSD
Pulsed reverse drain current
Diode forward voltage
-
-
-
-
44
1.2
-
A
V
V
IF = 5 A; VGS = 0 V
IF = 11 A; VGS = 0 V
0.85
1.1
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 11 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 30 V
-
-
49
0.13
-
-
ns
µC
May 2000
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK95180-100A
BUK96180-100A
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
1
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 5.5 A; VDD ≤ 25 V;
VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
-
-
1.5
mJ
!
Normalised Power Derating
100
ID/A
PD%
120
110
100
90
80
70
60
50
40
30
20
10
0
RDS(ON)=VSD/ID
10
DC
1
0.1
0
20
40
60
80 100 120 140 160 180
Tmb /
1
10
100
1000
C
VSD/V
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Normalised Current Derating
ID%
120
110
100
90
80
70
60
50
40
30
20
10
0
Zth/(K/W)
10
0.5
0.2
1
0.1
0.05
0.1
0.02
0
0.01
0.001
1E-07
1E-05
1E-03
1E-01
1E+01
0
20
40
60
80
100 120 140 160 180
t/s
Tmb /
C
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
1 For maximum permissible repetive avalanche current see fig.18.
May 2000
3
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK95180-100A
BUK96180-100A
VGS/V =
12
ID/A
25
10.0
5.0
ID/A
10
4.0
20
15
10
5
3.8
8
3.6
3.4
3.2
3.0
6
Tj/C= 175
25
4
2.8
2
2.6
2.4
2.2
0
0
0
2
4
6
8
0
2
4
6
8
10
VDS/V
VGS/V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
Fig.8. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
ID = f(VDS); parameter VGS
RDS(ON)/mOhm
240
16
gfs/S
3.2
3.4
3.0
14
12
10
8
220
200
180
160
140
120
100
3.6
3.8
4.0
5.0
6
4
2
0
2
4
6
8
10
12
0
2
4
6
8
10
12
14
ID/A
ID/A
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
Fig.9. Typical transconductance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
gfs = f(ID); conditions: VDS = 25 V
Rds(on) normalised to 25degC
a
240 RDS(ON) Ohm
3
2.5
2
230
220
210
200
190
180
170
160
150
1.5
1
3
4
5
6
7
8
9
10
0.5
-100
-50
0
50
100
150
200
VGS/V
Tmb / degC
Fig.7. Typical on-state resistance, Tj = 25 ˚C.
Fig.10. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V
RDS(ON) = f(VGS); conditions: ID = 25 A;
May 2000
4
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK95180-100A
BUK96180-100A
VGS(TO) / V
2.5
5
VGS / V
max.
2
4
3
2
1
0
typ.
1.5
min.
1
0.5
0
0
2
4
6
8
10
-100
-50
0
50
Tj / C
100
150
200
QG / nC
Fig.11. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.14. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 25 A; parameter VDS
Sub-Threshold Conduction
15
1E-01
IF/A
1E-02
1E-03
1E-04
1E-05
1E-05
10
5
2%
typ
98%
Tj/C= 150
25
0
0.0
0.2
0.4
0.6
VSDS/V
0.8
1.0
1.2
0
0.5
1
1.5
2
2.5
3
Fig.15. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.12. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
WDSS%
120
Capacitance / pF
1200
1000
800
600
400
200
0
110
100
90
80
70
60
50
40
30
20
10
0
Ciss
Coss
Crss
0.01
0.1
1
10
100
20
40
60
80
100
Tmb /
120
C
140
160
180
VDS/V
Fig.13. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.16. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 75 A
May 2000
5
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK95180-100A
BUK96180-100A
VDD
VDD
+
+
-
RD
L
VDS
VDS
-
VGS
0
VGS
0
-ID/100
RG
T.U.T.
T.U.T.
R 01
shunt
RGS
Fig.17. Avalanche energy test circuit.
Fig.19. Switching test circuit.
WDSS = 0.5 LID2 BVDSS/(BVDSS − VDD
)
100
IAV
10
Tj prior to avalanche 150oC
25oC
1
0.001
0.01
0.1
1
10
Avalanche Time, tAV (ms)
Fig.18. Maximum permissible repetitive avalanche
current(IAV) versus avalanche time(tAV) for unclamped
inductive loads.
May 2000
6
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK95180-100A
BUK96180-100A
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
4,5
max
10,3
max
1,3
3,7
2,8
5,9
min
15,8
max
3,0 max
not tinned
3,0
13,5
min
1,3
1 2 3
max
(2x)
0,9 max (3x)
0,6
2,4
2,54 2,54
Fig.20. SOT78 (TO220AB); pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT78 (TO220) envelopes.
3. Epoxy meets UL94 V0 at 1/8".
May 2000
7
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK95180-100A
BUK96180-100A
MECHANICAL DATA
2
Plastic single-ended surface mounted package (Philips version of D -PAK); 3 leads
(one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.40 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
98-12-14
99-06-25
SOT404
Fig.21. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
May 2000
8
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK95180-100A
BUK96180-100A
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.22. SOT404 : soldering pattern for surface mounting.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
May 2000
9
Rev 1.100
相关型号：
BUK9524-55127
TRANSISTOR 45 A, 55 V, 0.024 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB, FET General Purpose Power
NXP
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