GTL2005PW/DG,118_技术文档

GTL2005

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched

translator

Rev. 07 — 3 February 2009

Product data sheet

1. General description

The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a

GTL/GTL+ bus.

The direction pin (DIR) allows the part to function as either a GTL-to-TTL sampling

receiver or as a TTL-to-GTL interface.

The GTL2005 LVTTL interface is tolerant up to 5.5 V allowing direct access to TTL or 5 V

CMOS outputs.

The GTL2005 V_reflinearity degrades below 0.8 V (see Section 10.1). If the application

allows, use the GTL2014, otherwise more closely review noise margins.

fast t

PD

GTL2005

GTL2014

slow t

PD

GTL

GTL−

GTL+

002aab378

Fig 1. GTL2005/GTL2014 positioning

2. Features

I Operates as a quad GTL/GTL+ sampling receiver or as a LVTTL/TTL to GTL/GTL+

driver

I Quad bidirectional bus interface

I 3.0 V to 3.6 V operation with 5 V tolerant LVTTL I/O

I Live insertion/extraction permitted

I Latch-up protection exceeds 500 mA per JESD78

I ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per

JESD22-A115, and 1000 V CDM per JESD22-CC101

I Package offered: TSSOP14

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

3. Quick reference data

Table 1.

Quick reference data

V_CC= 3.3 V ± 0.3 V

Symbol

Parameter

Conditions

Min

Typ^[1]Max

Unit

C_i

input capacitance

control inputs;

V_I= 3.0 V or 0 V

-

2.3

3.4

6.0

3.5

5.0

7.0

pF

C_io

input/output capacitance

A port;

V_O= V_TTor 0 V

-

pF

B port;

V_O= 3.0 V or 0 V

GTL; V_ref= 0.8 V

t_PLH

t_PHL

t_PLH

t_PHL

propagation delay, Bn to An see Figure 7

-

2.1

1.9

4.1

4.4

2.3

2.6

5.9

ns

propagation delay, An to Bn see Figure 8

[1] All typical values are measured at V_CC= 3.3 V and T_amb= 25 °C.

4. Ordering information

Table 2.

Ordering information

T_amb= −40 °C to +85 °C

Type number Topside

mark

Package

Name

Description

Version

GTL2005PW

GTL2005 TSSOP14 plastic thin shrink small outline package; SOT402-1

14 leads; body width 4.4 mm

GTL2005_7

Product data sheet

Rev. 07 — 3 February 2009

2 of 19

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

5. Functional diagram

GTL2005

A0

B0

A1

B1

A2

B2

A3

B3

002aab151

VREF

DIR

Fig 2. Logic diagram of GTL2005

6. Pinning information

6.1 Pinning

1

2

3

4

5

6

7

14

13

12

11

10

9

DIR

A0

V

CC

B0

A1

B1

VREF

A2

GTL2005PW

GND

B2

A3

B3

GND

8

GND

002aab150

Fig 3. Pin conﬁguration for TSSOP14

GTL2005_7

Product data sheet

Rev. 07 — 3 February 2009

3 of 19

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

6.2 Pin description

Table 3.

Symbol

DIR

A0

Pin description

Description

1

direction control input

data inputs/outputs (A side, GTL)

2

A1

3

A2

5

A3

6

B0

13

data inputs/outputs (B side, TTL)

B1

12

B2

10

B3

9

VREF

GND

V_CC

4

GTL reference voltage

ground (0 V)

7, 8, 11

14

positive supply voltage

7. Functional description

Refer to Figure 2 “Logic diagram of GTL2005”.

7.1 Function table

Table 4.

Function table

H = HIGH voltage level; L = LOW voltage level.

Input

DIR

H

Input/output

B (TTL)

A (GTL)

Bn = An

inputs

L

An = Bn

GTL2005_7

Product data sheet

Rev. 07 — 3 February 2009

4 of 19

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

8. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

−0.5

-

−0.5^[2]

-

Max

+4.6

−50

Unit

V

DC supply voltage

DC input diode current

DC input voltage

V_I< 0 V

A port

mA

V

V_I

+7.0

+4.6

−50

B port

V

I_OK

V_O

DC output diode current

DC output voltage

V_O< 0 V

mA

V

output in OFF or

−0.5^[2]

+7.0

HIGH state; A port

output in OFF or

−0.5^[2]

+4.6

V

HIGH state; B port

I_OL

current into any output in

the LOW state

B port

A port

B port

-

128

80

mA

I_OH

current into any output in

the HIGH state

−64

[3]

T_stg

storage temperature range

−60

+150

°C

[1] Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only

and functional operation of the device at these or any other conditions beyond those indicated under

Section 9 “Recommended operating conditions” is not implied. Exposure to absolute-maximum-rated

conditions for extended periods may affect device reliability.

[2] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings

are observed.

[3] The performance capability of a high-performance integrated circuit in conjunction with its thermal

environment can create junction temperatures which are detrimental to reliability. The maximum junction

temperature of this integrated circuit should not exceed 150 °C.

GTL2005_7

Product data sheet

Rev. 07 — 3 February 2009

5 of 19

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

9. Recommended operating conditions

Table 6.

Symbol Parameter

Operating conditions ^[1]

Conditions

Min

3.0

Typ

3.3

0.9

1.2

1.5

²⁄₃V_TT

0.6

0.8

1.0

V_TT

3.3

-

Max

3.6

Unit

V

V_CC

V_TT

supply voltage

termination voltage

GTL−

0.85

1.14

1.35

0.5

0.95

1.26

1.65

1.8

V

GTL

V

GTL+

V

[2]

V_ref

reference voltage

overall

GTL−

V

0.5

0.63

0.84

1.10

3.6

V

GTL

0.76

0.87

0

V

GTL+

V

V_I

input voltage

A port

except A port

V

0

5.5

V

[3]

V_IH

V_IL

HIGH-level input voltage A port

except A port

A port

except A port

-

V

2

-

V

[3]

LOW-level input voltage

-

V

-

0.8

−12

40

V

I_OH

I_OL

HIGH-level output current B port

LOW-level output current A port

B port

-

mA

°C

-

12

T_amb

ambient temperature

operating in

free-air

−40

-

+85

[1] Unused inputs must be held HIGH or LOW to prevent them from ﬂoating.

[2] V_refis normally ²⁄₃V_TT, but based upon application and noise margin requirements can be set anywhere

within this range and does not need to follow GTL-/GTL/GTL+ speciﬁcation.

[3] Nominally ±50 mV around V_ref. See Figure 4, Figure 5, and Figure 6 for actual performance versus V_ref

,

V_CC, and temperature.

GTL2005_7

Product data sheet

Rev. 07 — 3 February 2009

6 of 19

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

10. Static characteristics

Table 7.

Static characteristics

Recommended operating conditions; voltages are referenced to GND (ground = 0 V); T_amb= −40 °C to +85 °C.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

[2]

V_OH

HIGH-level output

voltage

B port; V_CC= 3.0 V to 3.6 V;

V

_CC− 0.2

-

V

I

_OH= −100 µA

B port; V_CC= 3.0 V;

_OH= −12 mA

2.0

-

V

I

[2]

V_OL

LOW-level output

voltage

A port; V_CC= 3.0 V; I_OL= 40 mA

B port; V_CC= 3.0 V; I_OL= 4 mA

B port; V_CC= 3.0 V; I_OL= 8 mA

B port; V_CC= 3.0 V; I_OL= 12 mA

-

0.4

0.55

0.8

±1

V

I_I

input current

control inputs; V_CC= 3.6 V;

V_I= V_CCor GND

µA

A port; V_CC= 3.6 V;

V_I= V_TTor GND

-

±1

µA

B port; V_CC= 0 V or 3.6 V;

V_I= 5.5 V

10

B port; V_CC= 3.6 V; V_I= V_CC

B port; V_CC= 3.6 V; V_I= 0 V

-

±1

µA

−5

I_OFF

I_EX

output OFF current

A port; V_CC= 0 V;

±100

V_Ior V_O= 0 V to 4.5 V

high contention over B port; V_CC= 3.0 V; V_O= 5.5 V

-

50

125

µA

voltage leakage

current

I_CC

supply current

A or B port; V_CC= 3.6 V;

V_I= V_CCor GND; I_O= 0 mA

-

3

mA

[3]

∆I_CC

additional supply

current per input

B port or control inputs;

500

µA

V_CC= 3.6 V; V_I= V_CC− 0.6 V

C_i

input capacitance

control inputs; V_I= 3.0 V or 0 V

A port; V_O= V_TTor 0 V

-

2.3

3.4

6.0

3.5

5.0

7.0

pF

C_io

input/output

capacitance

B port; V_O= 3.0 V or 0 V

[1] All typical values are measured at V_CC= 3.3 V and T_amb= 25 °C.

[2] The input and output voltage ratings my be exceeded if the input and output current ratings are observed.

[3] This is the increase in supply current for each input that is at the speciﬁed TTL voltage level rather than V_CCor GND.

GTL2005_7

Product data sheet

Rev. 07 — 3 February 2009

7 of 19

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

10.1 Performance curves

002aab152

002aab153

1200

TH+

1200

TH+

V

and

V

TH−

(mV)

1000

V

TH+

V

TH−

800

600

400

800

600

400

V

ref

V

TH−

0.5

0.6

0.7

0.8

0.9

1.0

(V)

0.5

0.6

0.7

0.8

0.9

1.0

(V)

V

ref

a. V_CC= 3.0 V

b. V_CC= 3.3 V

002aab154

1200

V

TH+

and

V

TH−

(mV)

1000

V

TH+

800

600

400

V

ref

TH−

0.5

0.6

0.7

0.8

0.9

1.0

(V)

V

ref

c. V_CC= 3.6 V

Fig 4. GTL V_TH+and V_TH−versus V_ref; T_amb= −40 °C

GTL2005_7

Product data sheet

Rev. 07 — 3 February 2009

8 of 19

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

002aab155

002aab156

1200

TH+

1200

TH+

V

and

V

TH−

(mV)

1000

V

TH+

V

ref

V

ref

V

TH−

800

600

400

800

600

400

0.5

0.6

0.7

0.8

0.9

1.0

(V)

0.5

0.6

0.7

0.8

0.9

1.0

(V)

V

ref

a. V_CC= 3.0 V

b. V_CC= 3.3 V

002aab157

1200

V

TH+

and

V

TH−

(mV)

1000

V

TH+

V

ref

V

TH−

800

600

400

0.5

0.6

0.7

0.8

0.9

1.0

(V)

V

ref

c. V_CC= 3.6 V

Fig 5. GTL V_TH+and V_TH−versus V_ref; T_amb= +25 °C

GTL2005_7

Product data sheet

Rev. 07 — 3 February 2009

9 of 19

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

002aab158

002aab159

1200

TH+

1200

TH+

V

and

V

TH−

(mV)

1000

V

TH+

V

TH−

V

TH+

800

600

400

800

600

400

V

TH−

V

ref

V

ref

0.5

0.6

0.7

0.8

0.9

1.0

(V)

0.5

0.6

0.7

0.8

0.9

1.0

(V)

V

ref

a. V_CC= 3.0 V

b. V_CC= 3.3 V

002aab160

1200

V

TH+

and

V

TH−

(mV)

1000

V

TH+

800

600

400

V

TH−

V

ref

0.5

0.6

0.7

0.8

0.9

1.0

(V)

V

ref

c. V_CC= 3.6 V

Fig 6. GTL V_TH+and V_TH−versus V_ref; T_amb= +85 °C

GTL2005_7

Product data sheet

Rev. 07 — 3 February 2009

10 of 19

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

11. Dynamic characteristics

Table 8.

Dynamic characteristics

V_CC= 3.3 V ± 0.3 V

Symbol

Parameter

Conditions

see Figure 7

see Figure 8

Min

Typ^[1]

Max

Unit

GTL−; V_ref= 0.6 V

t_PLH

t_PHL

t_PLH

t_PHL

propagation delay, Bn to An

-

2.1

1.9

4.1

4.4

2.3

2.6

5.9

ns

propagation delay, An to Bn

GTL; V_ref= 0.8 V

t_PLH

t_PHL

t_PLH

t_PHL

propagation delay, Bn to An

see Figure 7

see Figure 8

-

2.1

1.9

4.1

4.4

2.3

2.6

5.9

ns

propagation delay, An to Bn

GTL+; V_ref= 1.0 V

t_PLH

t_PHL

t_PLH

t_PHL

propagation delay, Bn to An

see Figure 7

see Figure 8

-

2.1

1.9

4.2

3.8

2.3

2.6

5.7

5.4

ns

propagation delay, An to Bn

[1] All typical values are at V_CC= 3.3 V and T_amb= 25 °C.

11.1 Waveforms

V_M= 1.5 V at V_CC≥ 3.0 V; V_M= V_CC/2 at V_CC≤ 2.7 V for B ports and control pins;

V_M= V_reffor A ports.

3.0 V

0 V

input

1.5 V

t

PHL

PLH

t

p

V

3.0 V

0 V

OH

output

V

ref

V

M

V

OL

002aab141

002aab140

V_M= 1.5 V for B port and V_reffor A port

a. Pulse duration

B port to A port

b. Propagation delay times

Fig 7. Voltage waveforms

GTL2005_7

Product data sheet

Rev. 07 — 3 February 2009

11 of 19

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

3.0 V

input

V

ref

0 V

t

PHL

PLH

V

OH

OL

output

1.5 V

002aab163

PRR ≤ 10 MHz; Z_o= 50 Ω; t_r≤ 2.5 ns; t_f≤ 2.5 ns

Fig 8. Propagation delay, An to Bn

12. Test information

V

CC

V

O

I

PULSE

GENERATOR

DUT

R

500 Ω

C

L

50 pF

L

R

T

002aab006

Fig 9. Load circuitry for switching times

V

TT

V

CC

25 Ω

V

O

I

PULSE

GENERATOR

DUT

C

30 pF

L

R

T

002aab143

Fig 10. Load circuit for A (GTL) outputs

R_L— Load resistor

C_L— Load capacitance; includes jig and probe capacitance

R_T— Termination resistance; should be equal to Z_oof pulse generators.

GTL2005_7

Product data sheet

Rev. 07 — 3 February 2009

12 of 19

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

13. Package outline

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

D

E

A

X

c

y

H

v

M

A

E

Z

8

14

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

7

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.72

0.38

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT402-1

MO-153

Fig 11. Package outline SOT402-1 (TSSOP14)

GTL2005_7

Product data sheet

Rev. 07 — 3 February 2009

13 of 19

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

14. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

14.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

14.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

14.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

GTL2005_7

Product data sheet

Rev. 07 — 3 February 2009

14 of 19

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

14.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 12) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 9 and 10

Table 9.

SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

≥ 350

220

< 2.5

235

220

≥ 2.5

220

Table 10. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 12.

GTL2005_7

Product data sheet

Rev. 07 — 3 February 2009

15 of 19

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 12. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

15. Abbreviations

Table 11. Abbreviations

Acronym

CDM

CMOS

DUT

Description

Charged-Device Model

Complementary Metal-Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

Gunning Transceiver Logic

Human Body Model

GTL

HBM

I/O

Input/Output

LVTTL

MM

Low Voltage Transistor-Transistor Logic

Machine Model

TTL

Transistor-Transistor Logic

GTL2005_7

Product data sheet

Rev. 07 — 3 February 2009

16 of 19

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

16. Revision history

Table 12. Revision history

Document ID

GTL2005_7

Release date

20090203

Data sheet status

Change notice

Supersedes

Product data sheet

-

GTL2005_6

Modiﬁcations:

• Figure 2 “Logic diagram of GTL2005” modiﬁed: symbol for AND gate replaced and its direction

reversed

• updated soldering information

GTL2005_6

20070906

Product data sheet

-

GTL2005_5

GTL2005_4

GTL2005_5

20050406

Product data sheet

(9397 750 14285)

GTL2005_4

(9397 750 13104)

20040510

20000619

19990917

Product data

-

GTL2005_3

GTL2005_2

GTL2005_1

-

GTL2005_3

(9397 750 07222)

853-2171 23901

853-2171 22353

GTL2005_2

(9397 750 06695)

GTL2005_1

(9397 750 06497)

GTL2005_7

Product data sheet

Rev. 07 — 3 February 2009

17 of 19

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

17. Legal information

17.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

17.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

GTL2005_7

Product data sheet

Rev. 07 — 3 February 2009

18 of 19

GTL2005

NXP Semiconductors

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator

19. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7

7.1

8

Functional description . . . . . . . . . . . . . . . . . . . 4

Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended operating conditions. . . . . . . . 6

Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

Performance curves . . . . . . . . . . . . . . . . . . . . . 8

Dynamic characteristics . . . . . . . . . . . . . . . . . 11

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Test information. . . . . . . . . . . . . . . . . . . . . . . . 12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

9

10

10.1

11

11.1

12

13

14

Soldering of SMD packages . . . . . . . . . . . . . . 14

Introduction to soldering . . . . . . . . . . . . . . . . . 14

Wave and reﬂow soldering . . . . . . . . . . . . . . . 14

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 14

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 15

14.1

14.2

14.3

14.4

15

16

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17

17

Legal information. . . . . . . . . . . . . . . . . . . . . . . 18

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

17.1

17.2

17.3

17.4

18

19

Contact information. . . . . . . . . . . . . . . . . . . . . 18

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 3 February 2009

Document identifier: GTL2005_7


型号：	GTL2005PW/DG,118
厂家：	NXP
描述：	GTL2005 - Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator TSSOP 14-Pin 光电二极管接口集成电路
文件：	总19页 (文件大小：118K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GTL2005PW/DG,118 [NXP]

相关型号：

GTL2005PWDH

GTL2005PWDH-T

GTL2006

GTL2006PW

GTL2007

GTL2007PW

GTL2007PW,112

GTL2007PW,118

GTL2008

GTL2008PW

GTL2008PW,118

GTL2009