GTL2007_技术文档

GTL2007

13-bit GTL to LVTTL translator with power good control

Rev. 01 — 2 June 2005

Product data sheet

1. General description

The GTL2007 is a customized translator between dual Xeon processors, Platform Health

Management, South Bridge and Power Supply LVTTL and GTL signals.

The GTL2007 is derived from the GTL2006 with an enable function added that disables

the error output to the monitoring agent for platforms that monitor the individual error

conditions from each processor. This enable function can be used so that false error

conditions are not passed to the monitoring agent when the system is unexpectedly

powered down. This unexpected power-down could be from a power supply overload, a

CPU thermal trip, or some other event of which the monitoring agent is unaware.

A typical implementation would be to connect each enable line to the system power good

signal or the individual enables to the VRD power good for each processor.

The Nocona and Dempsey/Blackford Xeon processors specify a V_TTof 1.2 V and 1.1 V,

as well as a nominal V_refof 0.76 V and 0.73 V respectively. To allow for future voltage level

changes that may extend V_refto 0.63 of V_TT(minimum of 0.693 V with V_TTof 1.1 V) the

GTL2009 allows a minimum V_refof 0.66 V. Characterization results show that there is little

DC or AC performance variation between these levels.

The GTL2007 is the companion chip to the GTL2009 3-bit GTL Front-Side Bus frequency

comparator that is used in dual-processor Xeon applications.

2. Features

■ Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver

■ 3.0 V to 3.6 V operation

■ LVTTL I/O not 5 V tolerant

■ Series termination on the LVTTL outputs of 30 Ω

■ ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

■ Latch-up testing is done to JEDEC Standard JESD78 which exceeds 500 mA

■ Package offered: TSSOP28

GTL2007

Philips Semiconductors

13-bit GTL to LVTTL translator with power good control

3. Quick reference data

Table 1:

Quick reference data

T_amb= 25 °C

Symbol Parameter

Conditions

Min

Typ

5.5

2.0

Max Unit

t_PLH

t_PHL

C_io

propagation delay;

An-to-Bn or Bn-to-An

C_L= 50 pF; V_CC= 3.3 V

-

ns

pF

-

input/output capacitance; outputs disabled;

3.0

A-to-B

V_Iand V_O= 0 V or 3.0 V

input/output capacitance;

B-to-A

-

1.5

2.5

pF

4. Ordering information

Table 2:

Ordering information

T_amb= −40 °C to +85 °C

Type number Topside

mark

Package

Name

Description

Version

GTL2007PW

GTL2007

TSSOP28 plastic thin shrink small outline package;

28 leads; body width 4.4 mm

SOT361-1

Standard packing quantities and other packaging data are available at

www.semiconductors.philips.com/standardics/packaging.

9397 750 13264

Product data sheet

Rev. 01 — 2 June 2005

2 of 19

GTL2007

Philips Semiconductors

13-bit GTL to LVTTL translator with power good control

5. Functional diagram

GTL2007

1

2

GTL VREF

1AO

27

1BI

GTL inputs

LVTTL outputs

26

2BI

3

2AO

25

4

5

6

7BO1

5A

6A

LVTTL inputs/outputs

(open-drain)

GTL outputs

24

7BO2

23

LVTTL input EN1

GTL input 11BI

EN2

LVTTL input

GTL output

7

8

9

22

11BO

(1)

DELAY

LVTTL input/output

11A

9BI

(open-drain)

21

20

19

18

5BI

6BI

3BI

4BI

(1)

DELAY

GTL input

GTL inputs

10

11

3AO

4AO

LVTTL outputs

17

16

10BO1

10BO2

12

13

10AI1

10AI2

GTL outputs

LVTTL inputs

15

9AO LVTTL output

002aab210

(1) The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and

the LOW to HIGH on 5A/6A lags up to 100 ns from causing a LOW glitch on the 7BO1/7BO2 outputs.

Fig 1. Logic diagram of GTL2007

9397 750 13264

Product data sheet

Rev. 01 — 2 June 2005

3 of 19

GTL2007

Philips Semiconductors

13-bit GTL to LVTTL translator with power good control

6. Pinning information

6.1 Pinning

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VREF

1AO

2AO

5A

V

CC

1BI

3

2BI

4

7BO1

7BO2

EN2

11BO

5BI

5

6A

6

EN1

11BI

11A

7

GTL2007PW

8

9

9BI

6BI

10

11

12

13

14

3AO

4AO

10AI1

10AI2

GND

3BI

4BI

10BO1

10BO2

9AO

002aab209

Fig 2. Pin conﬁguration for TSSOP28

6.2 Pin description

Table 3:

Symbol

Pin description

Description

VREF

1AO

2AO

5A

1

GTL reference voltage

data output (LVTTL)

2

3

4

data input/output (LVTTL), open-drain

enable input (LVTTL)

data input (GTL)

6A

5

EN1

11BI

11A

6

7

8

data input/output (LVTTL), open-drain

data input (GTL)

9BI

9

3AO

4AO

10AI1

10AI2

GND

9AO

10BO2

10BO1

4BI

10

11

12

13

14

15

16

17

18

19

data output (LVTTL)

data input (LVTTL)

ground (0 V)

data output (LVTTL)

data output (GTL)

data input (GTL)

3BI

data input (GTL)

9397 750 13264

Product data sheet

Rev. 01 — 2 June 2005

4 of 19

GTL2007

Philips Semiconductors

13-bit GTL to LVTTL translator with power good control

Table 3:

Symbol

6BI

Pin description …continued

20

21

22

23

24

25

26

27

28

Description

data input (GTL)

data output (GTL)

enable input (LVTTL)

data output (GTL)

data input (GTL)

positive supply voltage

5BI

11BO

EN2

7BO2

7BO1

2BI

1BI

V_CC

7. Functional description

Refer to Figure 1 “Logic diagram of GTL2007” on page 3.

7.1 Function tables

Table 4:

GTL input signals

H = HIGH voltage level; L = LOW voltage level.

Input

Output^[1]

1BI/2BI/3BI/4BI/9BI

1AO/2AO/3AO/4AO/9AO

L

H

[1] 1AO, 2AO, 3AO, 4AO and 5A/6A condition changed by ENn power good signal as described in Table 5 and

Table 6.

Table 5:

EN1 power good signal

H = HIGH voltage level; L = LOW voltage level.

EN1

L

1AO and 2AO

H

5A

5BI disconnected

5BI connected

H

follows BI

Table 6:

EN2 power good signal

H = HIGH voltage level; L = LOW voltage level.

EN2

L

3AO and 4AO

H

6A

6BI disconnected

6BI connected

H

follows BI

9397 750 13264

Product data sheet

Rev. 01 — 2 June 2005

5 of 19

GTL2007

Philips Semiconductors

13-bit GTL to LVTTL translator with power good control

Table 7:

SMI signals

H = HIGH voltage level; L = LOW voltage level.

Input

9BI

L

Output

10AI1/10AI2

10BO1/10BO2

L

H

L

H

L

H

Table 8:

PROCHOT signals

H = HIGH voltage level; L = LOW voltage level.

Input

Input/output

Output

5BI/6BI

5A/6A (open-drain)

7BO1/7BO2

L

H^[1]

H

L^[2]

L

H

[1] The enable on 7BO1/7BO2 includes a delay that prevents the transient condition where 5BI/6BI go from

LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a low glitch on the

7BO1/7BO2 outputs.

[2] Open-drain input/output terminal is driven to logic LOW state by other driver.

Table 9:

NMI signals

H = HIGH voltage level; L = LOW voltage level.

Input

11BI

L

Input/output

Output

11A (open-drain)

11BO

H

L

L^[1]

H

L

[1] Open-drain input/output terminal is driven to logic LOW state by other driver.

9397 750 13264

Product data sheet

Rev. 01 — 2 June 2005

6 of 19

GTL2007

Philips Semiconductors

13-bit GTL to LVTTL translator with power good control

8. Application design-in information

V

TT

56 Ω

R

V

CC

1.5 kΩ to 1.2 kΩ

2R

1.5 kΩ

PLATFORM

HEALTH

V

CC

CPU1

MANAGEMENT

VREF

1AO

2AO

5A

V

CC

IERR_L

1BI

2BI

CPU1 1ERR_L

CPU1 THRMTRIP L

CPU1 PROCHOT L

CPU2 PROCHOT L

THRMTRIP L

FORCEPR_L

PROCHOT L

7BO1

7BO2

EN2

6A

EN1

11B1

NMI

CPU1 SMI L

11B0

GTL2007

11A

NMI_L

FORCEPR_L

PROCHOT L

IERR_L

5BI

6BI

9BI

3AO

4AO

10AI1

10AI2

GND

CPU2 IERR_L

CPU2 THRMTRIP L

CPU1 SMI L

3BI

THRMTRIP L

NMI

4BI

10BO1

10BO2

9AO

CPU2 SMI L

CPU2

SMI_BUFF_L

SOUTHBRIDGE NMI

SOUTHBRIDGE SMI_L

power supply

POWER GOOD

002aab211

Fig 3. Typical application

9397 750 13264

Product data sheet

Rev. 01 — 2 June 2005

7 of 19

GTL2007

Philips Semiconductors

13-bit GTL to LVTTL translator with power good control

9. Limiting values

Table 10: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). ^[1]

Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

−0.5

-

−0.5^[3]

-

Max

+4.6

−50

Unit

V

DC supply voltage

input clamping diode current

DC input voltage

V_I< 0 V

mA

V

V_I

A port (LVTTL)

B port (GTL)

V_O< 0 V

+4.6

−50

V

I_OK

V_O

output diode clamping current

DC output voltage

mA

V

output in OFF or HIGH state;

A port

−0.5^[3]

+4.6

output in OFF or HIGH state;

B port

−0.5^[3]

+4.6

V

I_OL

current into any output in the LOW state A port

B port

-

32

mA

°C

-

30

I_OH

current into any output in the HIGH state A port

storage temperature

-

−32

+150

+125

T_stg

−60

[2]

T_j(max)

maximum junction temperature

−

°C

[1] Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under Section 10 “Recommended operating conditions” is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.

[3] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

10. Recommended operating conditions

Table 11: Operating conditions

Symbol Parameter

Conditions

Min

Typ

Max

3.6

-

Unit

V

V_CC

V_TT

V_ref

V_I

supply voltage

3.0

3.3

termination voltage

reference voltage

input voltage

GTL

-

1.2

V

GTL

0.64

0.8

1.1

3.6

-

V

A port

0

3.3

V

B port

0

V_TT

V

V_IH

V_IL

HIGH-level input voltage

LOW-level input voltage

A port and ENn

B port

2

-

V

V_ref+ 0.050

-

V

A port and ENn

B port

-

0.8

V

-

V

_ref− 0.050

V

I_OH

I_OL

HIGH-level output current

LOW-level output current

A port

-

−16

16

mA

°C

A port

-

B port

-

15

T_amb

ambient temperature

operating in free-air

−40

+85

9397 750 13264

Product data sheet

Rev. 01 — 2 June 2005

8 of 19

GTL2007

Philips Semiconductors

13-bit GTL to LVTTL translator with power good control

11. Static characteristics

Table 12: Static characteristics

Recommended operating conditions; voltages are referenced to GND (ground = 0 V). T_amb= −40 °C to +85 °C

Symbol

Parameter

Conditions

Min

Typ ^[1]

Max

Unit

[2]

V_OH

HIGH-level output

voltage

A port; V_CC= 3.0 V to 3.6 V;

V_CC− 0.2 3.0

-

V

I_OH= −100 µA

[2]

A port; V_CC= 3.0 V; I_OH= −16 mA

A port; V_CC= 3.0 V; I_OL= 4 mA

A port; V_CC= 3.0 V; I_OL= 8 mA

A port; V_CC= 3.0 V; I_OL= 16 mA

B port; V_CC= 3.0 V; I_OL= 15 mA

A port; V_CC= 3.6 V; V_I= V_CC

2.1

2.3

0.15

0.3

0.6

0.13

-

V

V_OL

LOW-level output

voltage

-

0.4

0.55

0.8

0.4

±1

12

V

I_I

input current

µA

mA

A port; V_CC= 3.6 V; V_I= 0 V

-

B port; V_CC= 3.6 V; V_I= V_TTor GND

-

I_CC

supply current

A or B port; V_CC= 3.6 V;

8

V_I= V_CCor GND; I_O= 0 mA

[3]

∆I_CC

additional quiescent

current (per input)

A port or control inputs; V_CC= 3.6 V;

V_I= V_CC− 0.6 V

-

500

µA

C_io

input/output

capacitance

A port; V_O= 3.0 V or 0 V

B port; V_O= V_TTor 0 V

-

2.5

1.5

3.5

2.5

pF

[1] All typical values are measured at V_CC= 3.3 V and T_amb= 25 °C.

[2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[3] This is the increase in supply current for each input that is at the speciﬁed LVTTL voltage level rather than V_CCor GND.

9397 750 13264

Product data sheet

Rev. 01 — 2 June 2005

9 of 19

GTL2007

Philips Semiconductors

13-bit GTL to LVTTL translator with power good control

12. Dynamic characteristics

Table 13: Dynamic characteristics

V_CC= 3.3 V ± 0.3 V

Symbol

Parameter

Conditions

see Figure 4

see Figure 5

Min

Typ ^[1]

Max

Unit

V_ref= 0.73 V; V_TT= 1.1 V

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLZ

propagation delay, An to Bn

1

2

4

8

ns

5.5

6

10

11

13

21

18

propagation delay, nBI to nAO

propagation delay, 9BI to 10BOn

propagation delay, 11BI to 11BO

6

8

[2]

14

13

disable time from LOW level,

nBI to nA (I/O)

see Figure 6

t_PZL

enable time to LOW level,

nBI to nA (I/O)

2

12

16

ns

t_PLH

t_PHL

t_PLH

t_PHL

t_PLZ

propagation delay,

5BI to 7BO1 or 6BI to 7BO2

see Figure 7

see Figure 8

see Figure 9

4

7

12

350

10

7

ns

100

2

205

6.5

3

propagation delay,

EN1 to nAO or EN2 to nAO

2

disable time from LOW level,

1

EN1 to 5A (I/O) or EN2 to 6A (I/O)

t_PZL

enable time to LOW level,

2

7

10

ns

EN1 to 5A (I/O) or EN2 to 6A (I/O)

V_ref= 0.76 V; V_TT= 1.2 V

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLH

t_PHL

t_PLZ

propagation delay, An to Bn

see Figure 4

see Figure 5

1

2

4

8

ns

5.5

6

10

11

13

21

18

propagation delay, nBI to nAO

propagation delay, 9BI to 10BOn

propagation delay, 11BI to 11BO

6

8

[2]

14

13

disable time from LOW level,

nBI to nA (I/O)

see Figure 6

see Figure 7

t_PZL

enable time to LOW level,

nBI to nA (I/O)

2

12

16

ns

t_PLH

t_PHL

propagation delay,

5BI to 7BO1 or 6BI to 7BO2

4

7

12

ns

100

205

350

9397 750 13264

Product data sheet

Rev. 01 — 2 June 2005

10 of 19

GTL2007

Philips Semiconductors

13-bit GTL to LVTTL translator with power good control

Table 13: Dynamic characteristics …continued

V_CC= 3.3 V ± 0.3 V

Symbol

t_PLH

Parameter

Conditions

Min

2

Typ ^[1]

6.5

Max

10

7

Unit

ns

propagation delay,

EN1 to nAO or EN2 to nAO

see Figure 8

t_PHL

2

6.5

ns

t_PLZ

disable time from LOW level,

see Figure 9

1

3

ns

EN1 to 5A (I/O) or EN2 to 6A (I/O)

t_PZL

enable time to LOW level,

2

7

10

ns

EN1 to 5A (I/O) or EN2 to 6A (I/O)

[1] All typical values are at V_CC= 3.3 V and T_amb= 25 °C.

[2] Includes ~7.6 ns RC rise time of test load pull-up on 11A, 1.5 kΩ pull-up and 21 pF load on 11A has about 23 ns RC rise time.

12.1 Waveforms

V_M= 1.5 V at V_CC≥ 3.0 V for A ports; V_M= V_reffor B ports.

3.0 V

input

1.5 V

0 V

V

t

PHL

PLH

t

pulse

V

OH

H

output

V

ref

V

M

V

0 V

OL

002aab000

002aaa999

V_M= 3.0 V for A port and V_TTfor B port

a. Pulse duration

A port to B port

b. Propagation delay times

Fig 4. Voltage waveforms

9397 750 13264

Product data sheet

Rev. 01 — 2 June 2005

11 of 19

GTL2007

Philips Semiconductors

13-bit GTL to LVTTL translator with power good control

V

1

V

1

TT

input

V

input

V

ref

/ V

3

/ V

3 TT

TT

t

PLZ

PZL

t

PHL

PLH

V

CC

OH

OL

output

1.5 V

output

1.5 V

V

OL

+ 0.3 V

V

002aab001

002aab002

PRR ≤ 10 MHz; Z_O= 50 Ω; t_r≤ 2.5 ns; t_f≤ 2.5 ns

Fig 5. Propagation delay, nBI to nAO

Fig 6. nBI to nA (I/O)

V

1

3.0 V

0 V

TT

input

V

input

1.5 V

ref

/ V

3

TT

t

PHL

PLH

PHL

PLH

V

/V

V

OH TT

OL

OH

OL

1.5 V

output

1.5 V

V

ref

V

002aab003

002aab004

Fig 7. 5BI to 7BO or 6BI to 7BO2

Fig 8. EN1 to nAO or EN2 to nAO

3.0 V

input

1.5 V

0 V

t

PZL

PLZ

V

OH

OL

output

1.5 V

V

+ 0.3 V

OL

002aab005

Fig 9. EN1 to 5A (I/O) or EN2 to 6A (I/O)

9397 750 13264

Product data sheet

Rev. 01 — 2 June 2005

12 of 19

GTL2007

Philips Semiconductors

13-bit GTL to LVTTL translator with power good control

13. Test information

V

CC

V

I

O

PULSE

GENERATOR

D.U.T.

R

500 Ω

C

50 pF

L

R

T

002aab006

Fig 10. Load circuit for A outputs

V

TT

V

CC

50 Ω

V

O

I

PULSE

GENERATOR

D.U.T.

C

30 pF

L

R

T

002aab264

Fig 11. Load circuit for B outputs

V

CC

R

V

L

CC

1.5 kΩ

V

O

I

PULSE

GENERATOR

D.U.T.

C

21 pF

L

R

T

002aab265

Fig 12. Load circuit for open-drain LVTTL I/O

R_L— Load resistor

C_L— Load capacitance; includes jig and probe capacitance

R_T— Termination resistance; should be equal to Z_OUTof pulse generators.

9397 750 13264

Product data sheet

Rev. 01 — 2 June 2005

13 of 19

GTL2007

Philips Semiconductors

13-bit GTL to LVTTL translator with power good control

14. Package outline

TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm

SOT361-1

D

E

A

X

c

H

v

M

y

A

E

Z

15

28

Q

A

2

(A )

3

A

pin 1 index

1

θ

L

p

L

1

14

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

9.8

9.6

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.8

0.5

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT361-1

MO-153

Fig 13. Package outline SOT361-1 (TSSOP28)

9397 750 13264

Product data sheet

Rev. 01 — 2 June 2005

14 of 19

GTL2007

Philips Semiconductors

13-bit GTL to LVTTL translator with power good control

15. Soldering

15.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of

soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch

SMDs. In these situations reﬂow soldering is recommended.

15.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)

vary between 100 seconds and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 °C to 270 °C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

15.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

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– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most

applications.

15.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage

(24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be

limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 seconds to 5 seconds between 270 °C and 320 °C.

15.5 Package related soldering information

Table 14: Suitability of surface mount IC packages for wave and reﬂow soldering methods

Package ^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, HTSSON..T^[3], LBGA, LFBGA, SQFP,

SSOP..T^[3], TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,

HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

not suitable^[4]

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^{[5] [6]}

not recommended^[7]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[8], PMFP^[9], WQCCN..L^[8]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal or

external package cracks may occur due to vaporization of the moisture in them (the so called popcorn

effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no

account be processed through more than one soldering cycle or subjected to infrared reﬂow soldering with

peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow oven. The package

body peak temperature must be kept as low as possible.

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[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the

solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink

on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is

deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger

than 0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered

pre-mounted on ﬂex foil. However, the image sensor package can be mounted by the client on a ﬂex foil by

using a hot bar soldering process. The appropriate soldering proﬁle can be provided on request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

16. Abbreviations

Table 15: Abbreviations

Acronym

CDM

CMOS

CPU

Description

Charged Device Model

Complementary Metal Oxide Silicon

Central Processing Unit

Electrostatic Discharge

Gunning Transceiver Logic

Human Body Model

ESD

GTL

HBM

LVTTL

MM

Low Voltage Transistor-Transistor Logic

Machine Model

PRR

Pulse Rate Repetition

TTL

Transistor-Transistor Logic

Voltage Regulator Down

VRD

17. Revision history

Table 16: Revision history

Document ID

Release date Data sheet status

20050602 Product data sheet

Change notice Doc. number

9397 750 13264

Supersedes

GTL2007_1

-

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18. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

19. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

21. Trademarks

Notice — All referenced brands, product names, service names and

20. Disclaimers

trademarks are the property of their respective owners.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

22. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

9397 750 13264

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Rev. 01 — 2 June 2005

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23. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7

7.1

8

Functional description . . . . . . . . . . . . . . . . . . . 5

Function tables . . . . . . . . . . . . . . . . . . . . . . . . . 5

Application design-in information . . . . . . . . . . 7

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8

Recommended operating conditions. . . . . . . . 8

Static characteristics. . . . . . . . . . . . . . . . . . . . . 9

Dynamic characteristics . . . . . . . . . . . . . . . . . 10

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Test information. . . . . . . . . . . . . . . . . . . . . . . . 13

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14

9

10

11

12

12.1

13

14

15

15.1

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 15

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 16

Package related soldering information . . . . . . 16

15.2

15.3

15.4

15.5

16

17

18

19

20

21

22

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 18

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Contact information . . . . . . . . . . . . . . . . . . . . 18

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 2 June 2005

Document number: 9397 750 13264

Published in The Netherlands


型号：	GTL2007
厂家：	NXP
描述：	13-bit GTL to LVTTL translator with power good control 13位GTL来的LVTTL翻译与电源良好控制
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