HEF4555BPB [NXP]
IC 4000/14000/40000 SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, PDIP16, Decoder/Driver;
| 型号： | HEF4555BPB |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, PDIP16, Decoder/Driver 解码器 解复用器 |
| 文件： | 总4页 (文件大小：40K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4555B
MSI
Dual 1-of-4 decoder/demultiplexer
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4555B
MSI
Dual 1-of-4 decoder/demultiplexer
DESCRIPTION
The HEF4555B is a dual 1-of-4 decoder/demultiplexer.
Each has two address inputs (A0 and A1), an active LOW
enable input (E) and four mutually exclusive outputs which
are active HIGH (O0 to O3). When used as a decoder,
E when HIGH, forces O0 to O3 LOW. When used as a
demultiplexer, the appropriate output is selected by the
information on A0 and A1 with E as data input. All
unselected outputs are LOW.
Fig.2 Pinning diagram.
HEF4555BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4555BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4555BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
E
enable inputs (active LOW)
address inputs
A0 and A1
O0 to O3
outputs (active HIGH)
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
Fig.1 Functional diagram.
January 1995
2
Philips Semiconductors
Product specification
HEF4555B
MSI
Dual 1-of-4 decoder/demultiplexer
Fig.3 Logic diagram (one decoder/multiplexer).
TRUTH TABLE
INPUTS
OUTPUTS
E
A0
A1
O0
O1
O2
O3
L
L
L
L
H
L
H
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
H
H
X
H
X
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
January 1995
3
Philips Semiconductors
Product specification
HEF4555B
MSI
Dual 1-of-4 decoder/demultiplexer
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
V
Propagation delays
An → On
5
10
15
5
115
45
230 ns
90 ns
65 ns
280 ns
105 ns
75 ns
250 ns
95 ns
65 ns
295 ns
110 ns
75 ns
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
88 ns + (0,55 ns/pF) CL
34 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
113 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
98 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
123 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
10 ns + ((1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
HIGH to LOW
tPHL
tPLH
tPHL
tPLH
tTHL
tTLH
30
140
55
LOW to HIGH
10
15
5
40
En → On
125
50
HIGH to LOW
10
15
5
30
150
55
LOW to HIGH
10
15
5
40
Output transition times
HIGH to LOW
60
10
15
5
30
20
60
LOW to HIGH
10
15
30
20
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
4500 fi + ∑ (foCL) × VDD
where
2
18 800 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
45 700 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
APPLICATION INFORMATION
Some examples of applications for the HEF4555B are:
• Code conversion.
• Address decoding.
• Demultiplexing: when using the enable input as data input.
January 1995
4
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