MC33908NAE_技术文档

Document Number: MC33907-MC33908D2

Rev. 5.0, 10/2016

NXP Semiconductors

Data Sheet: Advance Information

Power system basis chip with high

speed CAN and LIN transceivers

33907

33908

The 33907/33908 SMARTMOS devices area multi-output, power supply,

integrated circuit, including HSCAN and/or LIN transceivers, dedicated to the

automotive market.

POWER SYSTEM BASIS CHIP

Multiple switching and linear voltage regulators, including low-power mode

(32 μA) are available with various wake-up capabilities. An advanced power

management scheme is implemented to maintain high efficiency over wide input

voltages (down to 2.7 V) and wide output current ranges (up to 1.5 A).

The 33907/33908 include enhanced safety features, with multiple fail-safe

outputs, becoming a full part of a safety oriented system partitioning, to reach a

high integrity safety level (up to ASIL D).

The built-in enhanced high-speed CAN interface fulfills the ISO11898-2 and -5

standards. The LIN interface fulfills LIN protocol specifications 1.3, 2.0, 2.1, 2.2,

and SAEJ2602-2

AE SUFFIX (PB-FREE)

98ASA00173D

48-PIN LQFP-EP

Features

• Battery voltage sensing & MUX output pin

Applications

• Highly flexible SMPS pre-regulator, allowing two topologies: non-inverting

buck-boost and standard buck

• Switching mode power supply (SMPS) dedicated to MCU core supply, from

1.2 V to 3.3 V delivering up to 1.5 A

• Multiple wake-up sources in low-power mode: CAN, LIN, and/or IOs

• Six configurable I/Os

• Linear voltage regulator dedicated to auxiliary functions, or to a sensor supply

(V_CCAtracker or independent), 5.0 V or 3.3 V

• Electrical power steering

• Engine management

• Battery management

• Active suspension

• Gear box

• Transmission

• Electrical vehicle (EV), hybrid electrical vehicle

(HEV), and inverter

• Advanced driver assistance systems

• Linear voltage regulator dedicated to MCU A/D reference voltage or I/Os

supply (V_CCA), 5.0 V or 3.3 V

+Battery

(KL30)

VDD

33907/33908

VCORE_SNS

FB_CORE

MCU

VSUP3

VSENSE

COMP_CORE

VCCA_E

VCCA_B

VCCA

VAUX_E

VAUX_B

V_CCA

AD ref.

voltage

V_COREor

V_CCA

VDDIO

V_AUX

VAUX

SELECT

CAN-5V

MOSI

MISO

SCLK

SPI

NCS

Ignition Key

IO_0

MUX_OUT

ADC Input

NMI

(KL15)

INTB

IO_1

IO_2

V_DDIO

RSTB

Reset

IO_3

IO_4

V_DDIO

IO_5

FS0B

V_PRE

CANH

CAN BUS

DEBUG

mode

DEBUG

CANL

VSUP3

TXDL

RXDL

LIN BUS

LIN

GNDA

GND_COM

DGND

TXD RXD

V_DD

FCCU

CAN

Figure 1. 33907/33908 simplified application diagram - buck boost configuration

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

+Battery

(KL30)

VDD

33907/33908

VCORE_SNS

FB_CORE

MCU

V_PRE

VSUP3

VSENSE

COMP_CORE

VCCA_E

V_PRE

VCCA_B

VCCA

VAUX_E

VAUX_B

V_CCA

AD ref.

voltage

V_COREor

V_CCA

VDDIO

VAUX

SELECT

MOSI

MISO

SPI

CAN-5V

SCLK

NCS

MUX_OUT

Ignition Key

(KL15)

ADC Input

NMI

IO_0

IO_1

IO_2

INTB

V_DDIO

RSTB

Reset

IO_3

IO_4

V_DDIO

IO_5

FS0B

V_PRE

CANH

CAN BUS

VSUP3

DEBUG

mode

DEBUG

CANL

LIN

TXDL

RXDL

LIN BUS

V_DD

LIN

GNDA

GND_COM

DGND

TXD RXD

FCCU

CAN

Figure 2. Simplified application diagram - buck configuration, V_AUXnot used, V_CCA= 100 mA

33907/33908

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NXP Semiconductors

1

Orderable parts

Table 1. Orderable part variations

Temperature (T )

V_CORE

Part number

Package

CAN

LIN

Notes

A

MC33907NAE

MC33908NAE

MC33907LAE

MC33908LAE

0

1

0.8 A

1.5 A

0.8 A

1.5 A

(1)

-40 to 125 °C

48-pin LQFP exposed pad

1

Notes

1. To order parts in Tape & Reel, add the R2 suffix to the part number.

33907/33908

NXP Semiconductors

3

2

Internal Block Diagram

V_PRE

VSUP3

TSD

V_PRESMPS

V_CORESMPS

V_PRE

TSD

VCCA_E

VCCA_B

VCCA

VAUX_E

VAUX_B

VAUX

V_AUXLinear Regulator

V_CCALinear Regulator

V_REF

(2.5 V)

Die

Temp

V_SENSE

GNDA

V_PRE

V_SUP3

V_CAN

Internal Linear

Regulator

TSD

CAN-5V

Analog

Reference #1

MUX

Interface

Charge Pump

MUX_OUT

IO_1

IO_0

SELECT

Select

DEBUG

INTB

MOSI

MISO

SCLK

NCS

IO_0

IO_1

IO_2

IO_3

IO_4

V2p5

Logic

Main

OSC

Main

Debug

6

I/Os

Interface

Power Management

State Machine

SPI

Main

IO_5

MISO FS

Select

VDDIO

V_AUXV_CCAFB__CORE

CAN-5V

VDDIO

V_SUP1&2

CAN diag V_SENSE

Debug

V2p5Logic

FS

SPI

FS

VDDIO

Voltage Regulator

SUPERVISOR

(Over & undervoltage)

V_PRE

RSTB

FS0B

Analog Reference #2

FS

5

FAIL SAFE Machine

V_PRE

V_SUP3

OSC

FS

V_SENSE

VSENSE

RXD

CAN-5V

CANH

HSCAN Interface

LIN Interface

TXD

CANL

GND_COM

RXDL

TXDL

LIN

Fail Safe Logic & supply

Figure 3. 33907L/33908L with CAN and LIN simplified internal block diagram

33907/33908

NXP Semiconductors

4

V_PRE

VSUP3

TSD

V_PRESMPS

V_CORESMPS

V_PRE

TSD

VCCA_E

VAUX_E

VAUX_B

VAUX

VCCA_B

VCCA

V_AUXLinear Regulator

V_CCALinear Regulator

V_REF

(2.5 V)

Die

Temp

V_SENSE

GNDA

V_PRE

V_SUP3

V_CAN

Internal Linear

Regulator

TSD

CAN-5V

Analog

Reference #1

MUX

Interface

Charge Pump

MUX_OUT

IO_1

IO_0

SELECT

Select

DEBUG

INTB

MOSI

MISO

SCLK

NCS

IO_0

IO_1

IO_2

IO_3

IO_4

V2p5

Logic

Main

OSC

Main

Debug

6

I/Os

Interface

Power Management

State Machine

SPI

Main

IO_5

MISO FS

V_DDIO

CAN-5V V_AUXV_CCAFB__CORE

VDDIO

V_SUP1&2

CAN diag V_SENSE

Select

V2p5Logic

FS

Debug

SPI

FS

V_DDIO

Voltage Regulator

SUPERVISOR

(Over & undervoltage)

V_PRE

RSTB

FS0B

Analog Reference #2

FS

5

FAIL SAFE Machine

V_PRE

V_SUP3

OSC

FS

V_SENSE

VSENSE

RXD

CAN-5V

CANH

HSCAN Interface

TXD

CANL

GND_COM

Fail Safe Logic & supply

Figure 4. 33907N/33908N with CAN only simplified internal block diagram

33907/33908

NXP Semiconductors

5

3

Pin connections

3.1

Pinout diagram for 33907/33908

Transparent top view

BOOT_CORE

SW_CORE

VCORE_SNS

COMP_CORE

FB_CORE

SELECT

VDDIO

VSUP1

VSUP2

VSENSE

VSUP3

LIN

GND_COM

CAN_5V

CANH

INTB

CANL

NCS

IO_4

SCLK

IO_5

MOSI

IO_0

MISO

Figure 5. 33907L/33908L pinout with CAN and LIN

Transparent top view

BOOT_CORE

SW_CORE

VCORE_SNS

COMP_CORE

FB_CORE

SELECT

VDDIO

VSUP1

VSUP2

VSENSE

VSUP3

NC

GND_COM

CAN_5V

CANH

CANL

INTB

NCS

IO_4

SCLK

IO_5

MOSI

IO_0

MISO

Figure 6. 33907N/33908N pinout with CAN only

33907/33908

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NXP Semiconductors

3.2

Pin definitions

A functional description of each pin can be found in the functional pin description section beginning on page 26.

Table 2. 33907/33908 pin definition

33907L/

33908L

33907N/

33908N

Pin name

Type

Definition

pin number pin number

Power supply of the device. An external reverse battery protection diode in series is

mandatory

1

2

3

1

2

3

VSUP1

VSUP2

A_IN

Second power supply. Protected by the external reverse battery protection diode used for

VSUP1. VSUP1 and VSUP2 must be connected together externally.

Sensing of the battery voltage. Must be connected prior to the reverse battery protection

diode.

VSENSE

Third power supply dedicated to the device supply. Protected by the external reverse battery

protection diode used for VSUP1. Must be connected between the reverse protection diode

and the input PI filter.

4

5

4

VSUP3

LIN

A_IN

LIN single-wire bus transmitter and receiver. NC: pin must be left open for 33907N/33908N

version

NC

A_IN/OUT

6

7

8

9

6

7

8

9

GND_COM

CAN_5V

CANH

GND

Dedicated ground for CAN

A_OUT

Output voltage for the embedded CAN interface

A_IN/OUT HSCAN output High

A_IN/OUT HSCAN output Low

CANL

Can be used as digital input (load dump proof) with wake-up capability or as an output gate

driver

Digital input: Pin status can be read through the SPI. Can be used to monitor error signals

from another IC for safety purposes.

Wake-up capability: Can be selectable to wake-up on a rising or falling edge, or on a

10

11

10

11

D_IN

A_OUT

IO_4:5

transition

Output gate driver: Can drive a logic level low-side NMOS transistor. Controlled by the SPI.

Can be used as analog or digital input (load dump proof) with wake-up capability (selectable)

Analog input: Pin status can be read through the MUX output pin

Digital input: Pin status can be read through the SPI. Can be used to monitor error signals

from another IC for safety purposes

Wake-up capability: Can be selectable to wake-up on a rising or falling edge, or on a

transition

Rk: For safety purposes, IO_1 can also be used to monitor the middle point of a redundant

resistor bridge connected on Vcore (in parallel to the one used to set the Vcore voltage).

12

13

12

13

A_IN

D_IN

IO_0:1

FS0B

Output of the safety block (active low). The pin is asserted low at start-up and when a fault

condition is detected. Open drain structure.

14

D_OUT

D_IN

15

16

15

16

DEBUG

AGND

Debug mode entry input

GROUND Analog ground connection

Multiplexed output to be connected to an MCU ADC input. Selection of the analog parameter

is available at MUX-OUT through the SPI.

17

MUX_OUT

A_OUT

D_IN

Digital input pin with wake-up capability (logic level compatible)

Digital INPUT: Pin status can be read through the SPI. Can be used to monitor error signals

from MCU for safety purposes.

Wake-up capability: Can be selectable to wake-up on a rising or falling edge, or on a

18

19

18

19

IO_2:3

transition.

Transceiver input from the MCU which controls the state of the HSCAN bus. Internal pull-up

to VDDIO. Internal pull-up to VDDIO.

20

21

22

20

21

TXD

RXD

TXDL

D_IN

D_OUT Receiver output which reports the state of the HSCAN bus to the MCU

Transceiver input from the MCU which controls the state of the LIN bus. Internal pull-up to

VDDIO. NC: pin must be left open for 33907N/33908N version

NC

D_IN

33907/33908

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Table 2. 33907/33908 pin definition (continued)

33907L/

33908L

33907N/

33908N

Pin name

Type

Definition

pin number pin number

Receiver output which reports the state of the LIN bus to the MCU. NC: pin must be left open

for 33907N/33908N version

23

24

NC

24

RXDL

RSTB

D_OUT

This output is asserted low when the safety block reports a failure. The main function is to

D_OUT reset the MCU. Reset input voltage is also monitored in order to detect external reset and

fault condition. Open drain structure.

25

26

27

28

25

26

27

28

MISO

MOSI

SCLK

NCS

D_OUT SPI bus. Master Input Slave Output

D_IN

SPI bus. Master Output Slave Input

SPI Bus. Serial clock

No Chip Select (Active low)

This output pin generates a low pulse when an Interrupt condition occurs. Pulse duration is

configurable. Internal pull-up to VDDIO.

29

INTB

D_OUT

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

VDDIO

SELECT

A_IN

D_IN

A_IN

Input voltage for MISO output buffer. Allows voltage compatibility with MCU I/Os.

Hardware selection pin for VAUX and VCCA output voltages

VCORE voltage feedback. Input of the error amplifier.

Compensation network. Output of the error amplifier.

VCORE output voltage sense

FB_CORE

COMP_CORE

VCORE_SNS

SW_CORE

VCORE switching point

BOOT_CORE A_IN/OUT Bootstrap capacitor for VCORE internal NMOS gate drive

VPRE

VAUX

A_OUT

VPRE output voltage

VAUX output voltage. External PNP ballast transistor. Collector connection

VAUX voltage regulator. External PNP ballast transistor. Base connection

VAUX voltage regulator. External PNP ballast transistor. Emitter connection

VCCA voltage regulator. External PNP ballast transistor. Emitter connection

VCCA voltage regulator. External PNP ballast transistor. Base connection

VCCA output voltage. External PNP ballast transistor. Collector connection

Low-side MOSFET gate drive for “Non-inverting Buck-boost” configuration

VAUX_B

VAUX_E

VCCA_E

VCCA_B

VCCA

GATE_LS

DGND

GROUND Digital ground connection

BOOT_PRE A_IN/OUT Bootstrap capacitor for the VPRE internal NMOS gate drive

SW_PRE2

SW_PRE1

A_IN

Second pre-regulator switching point

First pre-regulator switching point

33907/33908

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NXP Semiconductors

4

General product characteristics

4.1

Maximum ratings

Table 3. Maximum ratings

All voltages are with respect to ground, unless otherwise specified. Exceeding these ratings may cause a malfunction or permanent

damage to the device.

Symbol

Ratings

Value

Unit

Notes

Electrical ratings

V_SUP1/2/3

V_SENSE

(2)

DC Voltage at Power Supply Pins

DC Voltage at Battery Sense Pin

-1.0 to 40

-14 to 40

-1.0 to 40

-0.3 to 8

V

V_SW1,2

DC Voltage at SW_PRE1 and SW_PRE2 Pins

DC Voltage at VPRE Pin

V_PRE

V_{GATE_LS}

V_{BOOT_PRE}

V_{SW_CORE}

V_{CORE_SNS}

V_{BOOT_CORE}

V_{FB_CORE}

V_{COMP_CORE}

V_{AUX_E,B}

V_AUX

DC Voltage at Gate_LS pin

-0.3 to 8

DC Voltage at BOOT_PRE pin

DC Voltage at SW_CORE pin

-1.0 to 50

-1.0 to 8.0

0.0 to 8.0

0.0 to 15

-0.3 to 2.5

-0.3 to 40

-2.0 to 40

-0.3 to 8.0

-0.3 to 40

DC Voltage at VCORE_SNS pin

DC Voltage at BOOT_CORE pin

DC Voltage at FB_CORE pin

DC Voltage at COMP_CORE pin

DC Voltage at VAUX_E, VAUX_B pin

DC Voltage at VAUX pin

V_{CCA_B,E}

V_CCA

DC Voltage at VCCA_B, VCCA_E pin

DC Voltage at VCCA pin

V_DDIO

DC Voltage at VDDIO

V_FS0

DC Voltage at FS0B (with ext R mandatory)

DC Voltage at DEBUG

V_DEBUG

V_{IO_0,1,4,5}

DC Voltage at IO_0:1; 4:5 (with ext R = 5.1 kΩ in series mandatory)

DC Voltage at INTB, RSTB, MISO, MOSI, NCS, SCLK, MUX_OUT, RXD, TXD,

RXDL, TXDL, IO_2, IO_3

V

-0.3 to V_DDIO+0.3

V

DIG

V_SELECT

DC Voltage at SELECT

-0.3 to 8.0

-27 to 40

V

DC Voltage on CANL, CANH

DC Voltage on LIN

BUS_CAN

V

-18 to 40V

-0.3 to 8.0

-5.0 to 5.0

V

BUS_LIN

V

DC Voltage on CAN_5 V

V

CAN_5V

I_{_}IO_{0, 1, 4, 5}

IOs Maximum Current Capability(IO_0, IO_1, IO_4, IO_5)

mA

Notes

2. All Vsups (V_SUP1/2/3) shall be connected to the same supply (Figure 58)

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Table 3. Maximum ratings (continued)

All voltages are with respect to ground, unless otherwise specified. Exceeding these ratings may cause a malfunction or permanent

damage to the device.

Symbol

Ratings

Value

Unit

Notes

ESD Voltage

Human Body Model (JESD22/A114) - 100 pF, 1.5 kΩ

• All pins

V_ESD-HBM1

V_ESD-HBM2

V_ESD-HBM3

V_ESD-HBM4

±2.0

±4.0

±6.0

±8.0

kV

• VSUP1,VSUP2, VSUP3, VSENSE, VAUX, IO_0:1, IO_4:5,FS0B, DEBUG

• CANH, CANL

• LIN

Charge Device Model (JESD22/C101):

V_ESD-CDM1

V_ESD-CDM2

• All Pins

• Corner Pins

±500

±750

V

System level ESD (Gun Test)

• VSUP1, VSUP2, VSUP3, VSENSE, VAUX, IO_0:1, IO_4:5, FS0B

330 Ω / 150 pF Unpowered According to IEC61000-4-2:

330 Ω / 150 pF Unpowered According to OEM LIN, CAN, FLexray Conformance

2.0 kΩ / 150 pF Unpowered According to ISO10605.2008

2.0 kΩ / 330 pF Powered According to ISO10605.2008

• CANH, CANL

V_ESD-GUN1

V_ESD-GUN2

V_ESD-GUN3

V_ESD-GUN4

±8.0

kV

(3)

V_ESD-GUN5

V_ESD-GUN6

V_ESD-GUN7

V_ESD-GUN8

330 Ω / 150 pF Unpowered According to IEC61000-4-2:

330 Ω / 150 pF Unpowered According to OEM LIN, CAN, FLexray Conformance

2.0 kΩ / 150 pF Unpowered According to ISO10605.2008

2.0 kΩ / 330 pF Powered According to ISO10605.2008

• LIN

±15.0

±12.0

±15.0

kV

V_ESD-GUN9

V_ESD-GUN10

V_ESD-GUN11

V_ESD-GUN12

330 Ω / 150 pF Unpowered According to IEC61000-4-2:

330 Ω / 150 pF Unpowered According to OEM LIN, CAN, FLexray Conformance

2.0 kΩ / 150 pF Unpowered According to ISO10605.2008

2.0 kΩ / 330 pF Powered According to ISO10605.2008

±15.0

±12.0

±15.0

kV

Thermal ratings

T_A

T_J

Ambient Temperature

Junction Temperature

Storage Temperature

-40 to 125

-40 to 150

-55 to 150

°C

T_STG

Thermal resistance

R_θJA

(4)

(5)

(6)

Thermal Resistance Junction to Ambient

Thermal Resistance Junction to Case Top

Thermal Resistance Junction to Case Bottom

30

24.2

0.9

°C/W

R_θJCTOP

R_θJCBOTTOM

Notes

3. Compared to AGND.

4. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC - 883 Method 1012.1).

6. Thermal resistance between the die and the solder par on the bottom of the packaged based on simulation without any interface resistance.

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NXP Semiconductors

4.2

Static electrical characteristics

Table 4. Operating range

T_CASE= -40 °C to 125 °C, unless otherwise specified. V_SUP= V_{SUP_UV_L}to 40 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V_SUP< 40 V, thermal dissipation must be considered (Figure 25).

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

Power supply

I_SUP123

Power Supply Current in Normal Mode (V_SUP> V_{SUP_UV_7}

)

2.0

–

3.5

32

42

8.5

–

13.0

5.0

–

mA

µA

V

I_SUP3

Power Supply Current for VSUP3 in Normal Mode (V_SUP> V_{SUP_UV_7}

Power Supply Current in LPOFF (V_SUP= 14 V at T_A= 25 °C)

Power Supply Current in LPOFF (V_SUP= 18 V at T_A= 80 °C)

Power Supply Undervoltage Warning

)

I_{SUP_LPOFF1}

I_{SUP_LPOFF2}

V_{SNS_UV}

–

60

–

V_{SNS_UV_HYST}

V_{SUP_UV_7}

V_{SUP_UV_5}

V_{SUP_UV_L}

V_{SUP_UV_L_B}

V_{SUP_UV_HYST}

Power Supply Undervoltage Warning Hysteresis

0.1

7.0

–

V

Power Supply Undervoltage Lockout (power-up)

–

8.0

5.6

2.7

4.6

–

V

Power Supply Undervoltage Lockout (power-up)

–

V

Power Supply Undervoltage Lockout (falling - Boost config.)

Power Supply Undervoltage Lockout (falling - Buck config.)

Power Supply Undervoltage Lockout Hysteresis

–

V

(7)

(8)

–

V

–

0.1

V

V_PREvoltage pre-regulator

V_PREOutput Voltage

6.25

V_{PRE_UV_4}

P3

–

6.75

–

• Buck mode (V_SUP> V_{SUP_UV_7}

)

V_SUP

R_{DSON_PR}

_{E *}I_PRE

-

• Buck mode (V_{SUP_UV_7}≥ V_SUP≥ 4.6 V)

V_PRE

V

A

• Boost mode (V_SUP≥ 2.7 V)

6.0

–

7.0

V_PREMaximum Output Current Capability

• Buck or Boost with V_SUP> V_{SUP_UV_7}

2.0

0.5

2.0

1.0

0.3

–

2.0

–

• Buck with V_{SUP_UV_7}≥ V_SUP≥ 4.6 V

• Boost with V_{SUP_UV_7}≥ V_SUP≥ 6.0 V

• Boost with 6.0 V ≥ V_SUP≥ 4.0 V

• Boost with 4.0 V ≥ V_SUP≥ 2.7 V

(8)

I_PRE

V_PREMaximum Output Current Capability in LPOFF at low V_SUP

voltage

• Buck with V_{SUP_UV_7}≥ V_SUP≥ 4.6 V

• Boost with V_{SUP_UV_7}≥ V_SUP≥ 6.0 V

• Boost with 6.0 V ≥ V_SUP≥ 4.0 V

• Boost with 4.0 V ≥ V_SUP≥ 2.7 V

0.05

2.0

1.0

0.3

–

(8)

I_{PRE_LPOFF}

I_{PRE_LIM}

I_{PRE_OC}

V_{PRE_UV}

V_PREOutput Current Limitation with V_SUP≤ 28 V

3.5

5.0

5.5

–

A

V

V_PREOvercurrent Detection Threshold (in buck mode only) with V_SUP

≤ 28 V

V_PREUndervoltage Detection Threshold (Falling)

6.0

Notes

7. V_{SUP_UV_L_B}= V_{PRE_UV_4P3}+ R_{DSON_PRE}* I_PRE

8. Guaranteed by design

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Table 4. Operating range (continued)

T_CASE= -40 °C to 125 °C, unless otherwise specified. V_SUP= V_{SUP_UV_L}to 40 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V_SUP< 40 V, thermal dissipation must be considered (Figure 25).

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

V_PREvoltage pre-regulator (continued)

(9)

V_{PRE_UV_HYST}

V_{PRE_UV_4P3}

V_PREUndervoltage Hysteresis

0.05

4.2

–

0.15

4.5

V

V_PREShut-off Threshold (Falling - buck and buck/boost)

V_PREShut-off Hysteresis

V_{PRE_UV_4P3_}

(9)

0.05

–

0.15

V

HYST

R_{DSON_PRE}

L_{IR_VPRE}

V_PREPass Transistor On Resistance with V_SUP≤ 28 V

–

200

–

mΩ

(9)

V_PRELine Regulation

20

mV

V_PRELoad Regulation for C_OUT= 57 µF

• I_PREfrom 50 mA to 2.0 A - Buck mode

LOR_{VPRE_BUCK}

–

100

500

–

mV

V_PRELoad Regulation for C_OUT= 57 µF

• I_PREfrom 50 mA to 2.0 A - Boost mode

(9)

LOR_{VPRE_BOOST}

V_{PRE_LL_H}

V_{PRE_LL_L}

–

200

180

–

V_PREPulse Skipping Thresholds

T_{WARN_PRE}

T_{SD_PRE}

T_{SD_PRE_HYST}

V_{SUP_IPFF}

V_PREThermal Warning Threshold

V_PREThermal Shutdown Threshold

V_PREThermal Shutdown Hysteresis

I_PFFInput Voltage Detection

–

160

–

125

–

°C

V

(9)

10

–

18

24

–

V_{SUP_IPFF_HYST}I_PFFInput Voltage Hysteresis

0.2

1.7

V_PRE-1

–

V

I_{PRE_IPFF_PK}

V_{G_LS_OH}

V_{G_LS_OL}

I_PFFHigh-side Peak Current Detection with V_SUP≤ 28 V

–

A

LS Gate Driver High Output Voltage (I_OUT= 50 mA)

LS Gate driver Low Level (I_OUT= 50 mA)

–

V_PRE

0.5

V

–

V

V_corevoltage regulator

V_{CORE_FB}V_COREFeedback Input Voltage

0.784

0.8

0.816

V

A

V_COREOutput Current Capability in Normal Mode

• 33907N

• 33908N

• 33907L

• 33908L

–

0.8

1.5

0.8

1.5

I_CORE

V_COREOutput Current Limitation

• 33907N

1

1.8

1

–

2

3.5

2

I_{CORE_LIM}

• 33908N

• 33907L

• 33908L

A

1.8

3.5

R_{DSON_CORE}

V_COREPass Transistor On Resistance

–

200

mΩ

Notes

9. Guaranteed by design

33907/33908

12

NXP Semiconductors

Table 4. Operating range (continued)

T_CASE= -40 °C to 125 °C, unless otherwise specified. V_SUP= V_{SUP_UV_L}to 40 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V_SUP< 40 V, thermal dissipation must be considered (Figure 25).

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

V_corevoltage regulator (continued)

(10) (11)

LOR_{VCORE_1.2}

LOR_{VCORE_3.3}

V_CORETransient Load regulation - 1.2 V range

V_CORETransient Load regulation - 3.3 V range

-60

–

60

mV

,

(10) (11)

-100

100

,

V_{CORE_LL_H}

V_{CORE_LL_L}

–

180

160

–

V_COREPulse Skipping Thresholds

mV

T_{WARN_CORE}

T_{SD_CORE}

V_COREThermal Warning Threshold

V_COREThermal Shutdown Threshold

–

160

–

125

–

°C

(10)

(12)

T_{SD_CORE_HYST}V_COREThermal Shutdown Hysteresis

V_CCAvoltage regulator

10

V_CCAOutput Voltage

• 5.0 V config. with Internal ballast at 100 mA

4.95

4.9

4.85

3.2505

3.234

3.201

5.0

3.3

5.05

5.1

5.15

3.3495

3.366

3.399

• 5.0 V config with external ballast at 200 mA

• 5.0 V config with external ballast at 300 mA

• 3.3 V config with Internal ballast at 100 mA

• 3.3 V config with external ballast at 200 mA

• 3.3 V config with external ballast at 300 mA

V_CCA

V

I_{CCA_IN}

V_CCAOutput Current (int. MOSFET)

–

100

300

675

200

1.1

mA

V

I_{CCA_OUT}

V_CCAOutput Current (external PNP)

I_{CCA_LIM_INT}

I_{CCA_LIM_OUT}

I_{CCA_LIM_FB}

V_{CCA_LIM_FB}

V_CCAOutput Current Limitation (int. MOSFET)

V_CCAOutput Current Limitation (external PNP)

V_CCAOutput Current Limitation Foldback

V_CCAOutput Voltage Foldback Threshold

100

300

80

0.5

0.03

V_{CCA_LIM_HYST}V_CCAOutput Voltage Foldback Hysteresis

0.3

V

I_{CCA_BASE_SC}

–

20

–

30

–

V_CCABase Current Capability

I_{CCA_BASE_SK}

mA

T_{WARN_CCA}

TSD_CCA

V_CCAThermal Warning Threshold (int. MOSFET only)

V_CCAThermal Shutdown Threshold (int. MOSFET only)

V_CCAThermal Shutdown Hysteresis

–

160

–

125

–

°C

(13)

TSD_{CCA_HYST}

10

V_CCATransient Load Regulation

• I_CCA= 10 mA to 100 mA (internal MOSFET)

LORT_VCCA

–

1.0

%

• I_CCA= 10 mA to 300 mA (external ballast)

Notes

10. Guaranteed by design.

11. C_OUT= 40 µF, I_CORE= 10 mA to 1.5 A, dI_CORE/dt ≤ 2.0 A/µs

12. External PNP gain within 150 to 450

13. Guaranteed by design.

33907/33908

NXP Semiconductors

13

Table 4. Operating range (continued)

T_CASE= -40 °C to 125 °C, unless otherwise specified. V_SUP= V_{SUP_UV_L}to 40 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V_SUP< 40 V, thermal dissipation must be considered (Figure 25).

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

Vaux voltage regulator

V_{AUX_5}

V_{AUX_33}

V_AUXOutput Voltage (5.0 V configuration)

V_AUXOutput Voltage (3.3 V configuration)

V_AUXTracking Error (V_{AUX_5}and V_{AUX_33}

V_AUXOutput Current

4.85

3.2

-15

–

5.0

3.3

–

5.15

3.4

V

V_{AUX_TRK}

I_{AUX_OUT}

I_{AUX_LIM}

)

+15

300

700

530

1.1

mV

mA

V

–

V_AUXOutput Current Limitation

300

100

0.5

0.03

–

I_{AUX_LIM_FB}

V_{AUX_LIM_FB}

V_AUXOutput Current Limitation Foldback

V_AUXOutput Voltage Foldback Threshold

–

V_{AUX_LIM_HYST}V_AUXOutput Voltage Foldback Hysteresis

–

0.3

V

I_{AUX_BASE_SC}

–

7.0

–

-7.0

–

V_AUXBase Current Capability

I_{AUX_BASE_SK}

mA

TSD_AUX

TSD_{AUX_HYST}

LOR_VAUX

V_AUXThermal Shutdown Threshold

V_AUXThermal Shutdown Hysteresis

160

–

°C

(14)

10

15

V_AUXStatic Load Regulation (I_{AUX_OUT}= 10 mA to 300 mA)

–

mV

V_AUXTransient Load Regulation

• I_{AUX_OUT}= 10 mA to 300 mA

(14)

LORT_VAUX

–

1.0

%

CAN_5V voltage regulator

V_CANOutput Voltage

V_CAN

V_SUP> 6.0 V in Buck mode

4.8

5.0

5.2

V

V_SUP> V_{SUP_UV_L}in Boost mode

I_{CAN_OUT}

I_{CAN_LIM}

V_CANOutput Current

–

100

250

–

mA

°C

V

V_CANOutput Current Limitation

V_CANThermal Shutdown Threshold

V_CANThermal Shutdown Hysteresis

V_CANUndervoltage Detection Threshold

V_CANUndervoltage Hysteresis

100

160

–

TSD_CAN

–

(14)

TSD_{CAN_HYST}

V_{CAN_UV}

V_{CAN_UV_HYST}

V_{CAN_OV}

V_{CAN_OV_HYST}

LOR_VCAN

10

–

4.25

0.07

5.2

0.07

–

4.8

0.22

5.55

0.22

–

V

V_CANOvervoltage Detection Threshold

V_CANOvervoltage Hysteresis

–

V

–

V

(14)

V_CANLoad Regulation (from 0 to 50 mA)

100

mV

Notes

14. Guaranteed by design.

33907/33908

14

NXP Semiconductors

Table 4. Operating range (continued)

T_CASE= -40 °C to 125 °C, unless otherwise specified. V_SUP= V_{SUP_UV_L}to 40 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V_SUP< 40 V, thermal dissipation must be considered (Figure 25).

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

Fail-safe machine voltage supervisor

V_{PRE_OV}

V_PREOvervoltage Detection Threshold

V_PREOvervoltage Hysteresis

7.2

–

0.1

–

8.0

–

V

(15)

V_{PRE_OV_HYST}

V_{CORE_FB_UV}

V_COREFB Undervoltage Detection Threshold

0.67

0.45

0.773

0.58

V_{CORE_FB_UV_D}V_COREFB Undervoltage Detection Threshold - Degraded mode

–

V_{CORE_FB_UV_}

(15)

V_COREFB Undervoltage Hysteresis

10

0.84

10

–

27

0.905

30

mV

V

HYST

V_{CORE_FB_OV}

V_COREFB Overvoltage Detection Threshold

V_COREFB Overvoltage Hysteresis

V_{CORE_FB_OV_HYS}

mV

T

V_{CORE_FB_DRIFT}V_{CORE_FB}Drift versus IO_1

I_{PD_CORE}V_COREInternal Pull-down Current (active when V_{COR E}is enabled)

V_{CCA_UV_5}

50

5.0

4.5

3.0

–

100

12

–

150

25

mV

mA

V

V_CCAUndervoltage Detection Threshold (5.0 V config)

V_CCAUndervoltage Detection Threshold (Degraded 5.0 V)

V_CCAUndervoltage Detection Threshold (3.3 V config)

V_CCAUndervoltage Hysteresis

4.75

3.2

–

V_{CCA_UV_5D}

V_{CCA_UV_33}

V_{CCA_UV_HYST}

V_{CCA_OV_5}

V_{CCA_OV_33}

V_{CCA_OV_HYST}

R_{PD_CCA}

–

V

–

V

(15)

0.07

–

V

V_CCAOvervoltage Detection Threshold (5.0 V config)

V_CCAOvervoltage Detection Threshold (3.3 V config)

V_CCAOvervoltage Hysteresis

5.25

3.4

–

5.5

3.6

–

V

–

V

0.15

–

V

V_CCAInternal Pull-down Resistor (active when V_CCAis disabled)

V_AUXUndervoltage Detection Threshold (5.0 V config)

V_AUXUndervoltage Detection Threshold (Degraded 5.0 V)

V_AUXUndervoltage Detection Threshold (3.3 V config)

V_AUXUndervoltage Hysteresis

50

160

4.75

3.2

–

Ω

V

V_{AUX_UV_5}

4.5

3.0

–

V_{AUX_UV_5D}

V_{AUX_UV_33}

V_{AUX_UV_HYST}

V_{AUX_OV_5}

–

V

–

V

(15)

0.07

–

V

V_AUXOvervoltage Detection Threshold (5.0 V config)

V_AUXOvervoltage Detection Threshold (3.3 V config)

V_AUXOvervoltage Hysteresis

5.25

3.4

–

5.5

3.6

–

V

V_{AUX_OV_33}

V_{AUX_OV_HYST}

R_{PD_AUX}

–

V

0.07

–

V

V_AUXInternal Pull-down Resistor (active when V_AUXis disabled)

50

170

Ω

Notes

15. Guaranteed by design.

33907/33908

NXP Semiconductors

15

Table 4. Operating range (continued)

T_CASE= -40 °C to 125 °C, unless otherwise specified. V_SUP= V_{SUP_UV_L}to 40 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V_SUP< 40 V, thermal dissipation must be considered (Figure 25).

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

Fail-safe outputs

V_{RSTB_OL}

(16)

Reset Low Output Level (I_RSTB = 2.0 mA and 2.0 V < V_SUP< 40 V)

Reset Output Current Limitation

–

12

1.0

–

0.5

25

–

V

mA

V

I_{RSTB_LIM}

V_{RSTB_IL}

External Reset Detection Threshold (falling)

External Reset Detection Threshold (rising)

V_{RSTB_IH}

2.0

–

V

V_{RSTB_IN_HYST}External Reset Input Hysteresis

0.2

–

V

V_{FS0B_OL}

I_{FS0B_LK}

I_{FS0B_LIM}

FS0B Low Output Level (I_FS0b = 2.0 mA)

0.5

1.0

12

V

FS0B Input Current Leakage (V_FS0B= 28 V)

FS0B Output Current Limitation

–

µA

mA

6.0

Analog input - multi-purpose IOs

V_{IO_ANA_WD}

V_{IO_ANA_TG}

I_{IO_IN_ANA}

Measurable Input Voltage (wide range)

3.0

–

19

9.0

100

V

Measurable Input Voltage (tight range)

Input Current

µA

Digital input

Digital High Input voltage level (IO_0:1, IO_4:5)

• Min Limit = 2.7 V at V_SUP= 40 V

V_{IO_IH}

2.6

–

V

V_{IO23_IH}

V_{IO_IL}

V_{IO_HYST}

V_{IO23_IL}

Digital High Input voltage level (IO_2, IO_3)

Digital Low Input voltage Level (IO_0:1; IO_4:5)

Input Voltage Hysteresis (IO_0:1, IO_4:5)

Digital Low Input voltage Level (IO_2, IO_3)

Input Voltage Hysteresis (IO_2, IO_3)

Input Current for IO_0:1

2.0

–

V

2.1

500

0.9

700

100

1.0

5.0

1.0

(17)

50

120

–

mV

V

–

V_{IO23_HYST}

I_{IO_IN_0:1}

I_{IO_IN_1}

200

-5.0

-1.0

-5.0

-1.0

450

–

mV

µA

Input Current for IO_1 when used for FB_Core monitoring

Input Current for IO_2:5

–

I_{IO_IN_2:5}

I_{IO_IN_LPOFF}

–

Input Current for IO_0:5 in LPOFF

–

Output gate driver

V_{IO_OH}

High Output Level at I_{IO_OUT}= -2.5 mA

Low Output Level at I_{IO_OUT}= +2.5 mA

V_PRE- 1.5

0.0

–

V_PRE

1.0

V

V_{IO_OL}

V_{IO_OUT_SK}

V_{IO_OUT_SC}

2.5

–

-2.5

Output Current Capability

mA

Notes

16. For V_SUP< 2.0 V, all supplies are already off and external pull-up on RSTB (e.g V_COREor V_CCA) pulls the line down.

17. Guaranteed by design.

33907/33908

16

NXP Semiconductors

Table 4. Operating range (continued)

T_CASE= -40 °C to 125 °C, unless otherwise specified. V_SUP= V_{SUP_UV_L}to 40 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V_SUP< 40 V, thermal dissipation must be considered (Figure 25).

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

Analog multiplexer

V_{AMUX_ACC}

(18)

Voltage Sense Accuracy (V_SNS, IO_0, IO_1) using 5.1 kΩ resistor

-5.0

–

5.0

%

V_{AMUX_WD_5}

Divider Ratio (wide input voltage range) at V_DDIO= 5.0 V

–

5.0

7.0

2.0

3.0

2.5

9.9

2.15

–

V_{AMUX_WD_3P3}Divider Ratio (wide input voltage range) at V_DDIO= 3.3 V

V_{AMUX_TG_5}

V_{AMUX_TG_3P3}

V_{AMUX_REF1}

V_{AMUX_REF2}

V_{AMUX_TP_CO}

V_{AMUX_TP}

Divider Ratio (tight input voltage range) at V_DDIO= 5.0 V

Divider Ratio (tight input voltage range) at V_DDIO= 3.3 V

Internal Voltage Reference with 6.0 V < V_SUP< 19 V

Internal Voltage Reference with V_SUP≤ 6.0 V or V_SUP≥ 19 V

Internal Temperature sensor coefficient

–

2.475

2.468

–

2.525

2.532

–

V

(19)

mV/°C

V

Temperature Sensor MUX_OUT output voltage (at T_J=165°C)

2.08

2.22

Interrupt

V_{INTB_OL}

R_{PU_INT}

I_{INT_LK}

Low Output Level (I_INT= 2.5 mA)

Internal Pull-up Resistor (connected to VDDIO)

Input Leakage Current

–

10

–

0.5

–

V

KΩ

µA

1

CAN transceiver

CAN logic input pin (TXD)

V_{TXD_IH}TXD High Input Threshold

V_{TXD_IL}

0.7 x V_DDIO

–

0.3 x V_DDIO

50

V

TXD Low Input Threshold

–

TXD_PULL-UP

TXD_LK

TXD Main Device Pull-up

20

33

–

KΩ

µA

TXD Input Leakage Current, V_TXD= V_DDIO

-1.0

1.0

CAN logic output pin (RXD)

V_{RXD_OL1}Low Level Output Voltage (I

V_{RXD_OL2}

= 250 µA)

= 1.5 mA)

–

0.4

0.9

V

RXD

Low Level Output Voltage (I

V_DDIO

0.4V

-

VOUT_HIGH

High Level Output Voltage (I

= -250 µA, V_DDIO= 3.0 V to 5.5 V)

–

V

RXD

Notes

18. If a higher resistor value than recommended is used, the accuracy degrades.

19. Guaranteed by design

33907/33908

NXP Semiconductors

17

Table 4. Operating range (continued)

T_CASE= -40 °C to 125 °C, unless otherwise specified. V_SUP= V_{SUP_UV_L}to 40 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V_SUP< 40 V, thermal dissipation must be considered (Figure 25).

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

CAN output pins (CANH, CANL)

V_{DIFF_COM_MODE}Differential Input Comparator Common Mode Range

V_{IN_DIFF_SLEEP}Differential Input Voltage Threshold in Sleep Mode

-12

0.5

50

–

12

0.9

–

V

V_{IN_HYST}

R_{IN_CHCL}

R_{IN_DIFF}

Differential Input Hysteresis (in TX, RX mode)

CANH, CANL Input Resistance

mV

kΩ

%

5.0

10

50

CAN Differential Input Resistance

Input Resistance Matching

100

3.0

R_{IN_MATCH}

-3.0

CANH Output Voltage (45 Ω < R_BUS< 65 Ω)

• TX dominant state

V_CANH

2.75

2.0

–

2.5

4.5

3.0

V

• TX recessive state

CANL Output Voltage (45 Ω < R_BUS< 65 Ω)

• TX dominant state

V_CANL

0.5

2.0

–

2.5

2.25

3.0

V

• TX recessive state

V_{CAN_SYM}

CAN dominant voltage symmetry (V_CANL+ V_CANH

)

4.5

5

5.5

Differential Output Voltage

• TX dominant state (45 Ω < R_BUS< 65 Ω)

• TX recessive state

V

_OH-V_OL

1.5

-50

2.0

0.0

3.0

50

V

mV

CANL Sink Current Under Short-circuit Condition (V_CANL≤ 12 V, CANL

I_CANL-SK

I_CANH-SC

R_INSLEEP

V_CANLP

40

–

100

-40

mA

driver ON, TXD low)

CANH Source Current Under Short-circuit Condition (V_CANH= -2.0 V,

CANH driver ON, TXD low)

-100

CANH, CANL Input Resistance Device Supplied and in CAN Sleep

Mode

5.0

–

50

kΩ

CANL, CANH Output Voltage in Sleep Modes. No termination load.

-0.1

0.0

0.1

V

CANH, CANL Input Current, Device Unsupplied, (V_CANH,V_CANL=5.0V)

• V_SUPand V_CANconnected to GND

(20)

I_CAN

-10

–

10

µA

• V_SUPand V_CANconnected to GND via 47k resistor

T_OT

Overtemperature Detection

Overtemperature Hysteresis

160

–

°C

T_HYST

20

Digital interface

MISO_H

MISO_L

I_MISO

High Output Level on MISO (I_MISO= 1.5 mA)

Low Output Level on MISO (I_MISO= 2.0 mA)

Tri-state Leakage Current (V_DDIO= 5.0 V)

Supply Voltage for MISO Output Buffer

Current consumption on VDDIO

V_DDIO- 0.4

–

V

–

0.4

5.0

5.5

3.0

1.0

–

-5.0

3.0

–

µA

V

V_DDIO

–

IV_DDIO

1.0

–

mA

µA

V

SPI_LK

SCLK, NCS, MOSI Input Current

-1.0

2.0

200

–

V_{SPI_IH}

R_SPI

SCLK, NCS, MOSI High Input Threshold

NCS, MOSI Internal Pull-up (pull-up to VDDIO)

SCLK, NCS, MOSI Low Input Threshold

–

400

–

800

0.8

KΩ

V

V_{SPI_IL}

33907/33908

18

NXP Semiconductors

Table 4. Operating range (continued)

T_CASE= -40 °C to 125 °C, unless otherwise specified. V_SUP= V_{SUP_UV_L}to 40 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V_SUP< 40 V, thermal dissipation must be considered (Figure 25).

Symbol

Debug

Parameter

Min.

Typ.

Max.

Unit

Notes

V_{DEBUG_IL}

V_{DEBUG_IH}

I_{DEBUG_LK}

Low Input Voltage Threshold

High Input Voltage Threshold

Input Leakage Current

2.1

4.35

-10

2.35

4.6

–

2.6

4.97

10

V

µA

LIN transceiver (when 7.0 V < Vsup1,2,3 < 18 V, unless otherwise specified) (33907L/33908L)

LIN logic input pin (TXDL)

V_{TXDL_IH}

V_{TXDL_IL}

TXDL High Input Threshold

2.0

–

V

TXDL Low Input Threshold

0.8

50

1.0

TXDL_PULL-UP

TXDL_LK

TXDL Internal Pull-up (to VDDIO)

TXD Input Leakage Current, V_TXDL= VDDIO

20

33

–

kΩ

µA

-1.0

LIN logic input pin (RXDL)

V_{RXDL_OL1}Low Level Output Voltage (I

V_{RXDL_OL2}

= 250 µA)

= 1.5 mA)

–

0.4

0.9

–

V

RXDL

Low Level Output Voltage (I

V_{RXDL_OUT_HIGH}High Level Output Voltage (I

= -250 µA, V_DDIO= 3.0 V to 5.5 V) V_DDIO-0.4V

RXDL

LIN output pin

Input Leakage Current at the Receiver. Dominant State (Driver OFF,

_BAT= 12 V, V_BUS= 0 V)

(21)

I_{BUS_PAS_DOM}

I_{BUS_PAS_REC}

-1.0

–

mA

µA

V

Input Leakage Current at the Receiver. Recessive State (Driver OFF,

20

8.0 V < V_BAT< 18 V, 8.0 V < V_BUS< 18 V, V_BUS≥ V_BAT

)

V_{DRIVER_DOM}

V_{BUS_DOM}

V_{BUS_REC}

V_{BUS_WU}

Driver Dominant Voltage

–

0.251 V_SUP

0.4 V_SUP

–

V

Receiver Dominant State

–

Receiver Recessive State

0.6 V_SUP

0.4 V_SUP

–

LIN Wake-up Detection Threshold (7.0 V< V_SUP< 18 V)

V_SUPUndervoltage Threshold

0.6 V_SUP

7.0

V_{LIN_UV}

Series Diode Voltage Drop (D_{SER_MASTER}and D_{SER_INT}in pull-up

path)

V_{SER_DIODE}

0.4

0.7

1.0

V

(22)

(23)

I_{BUS_LIM}

R_SLAVE

V_{SHIFT_GND}

V_{SHIFT_BAT}

Notes

Current Limitation for Driver Dominant State (V_BUS= 18 V)

LIN Pull-up Resistor

40

20

–

200

60

mA

kΩ

V

Ground Shift (V_{SHIFT_GND}= V_{GND_ECU}- V_{GND_BATTERY)}

0.0

11.5%V_BAT

Battery Voltage Shift (V_{SHIFT_BAT}= V_BATTERY- V_{SHIFT_GND}- V_BAT

)

V

20. Guaranteed by design and characterization.

21. V_BATis the voltage at the input of the control unit.

22. Current flowing inside the pin. A transceiver must be capable to sink at least 40 mA.

23. V_BAT: voltage across the battery connectors of the vehicle. V_{GND_ECU}: voltage on the local ECU ground connector with respect to battery ground

of the vehicle (V_{GND_BATTERY}).

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Table 4. Operating range (continued)

T_CASE= -40 °C to 125 °C, unless otherwise specified. V_SUP= V_{SUP_UV_L}to 40 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V_SUP< 40 V, thermal dissipation must be considered (Figure 25).

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

LIN output pin (continued)

Difference Between Battery Shift and Ground Shift

(24)

(25)

V_{SHIFT_DIF}

0.0

–

8.0% V_BAT

V

(V_{SHIFT_DIF}= V_{SHIFT_BAT}- V_{SHIFT_GND}

V_{BUS_CNT =}(V_{TH_REC}+ V_{TH_DOM})/2

V_{HYST =}V_{TH_REC}- V_{TH_DOM}

)

V_{BUS_CNT}

V_HYST

0.475 V_SUP

–

0.525 V_SUP

0.175 V_SUP

V

Ground Disconnection. GND = V_SUP,0 V < V_BUS< 18 V, V_BAT= 12 V.

Loss of Local GND does not affect communication in the remaining

network

(26)

I_{BUS_NO_GND}

-1.0

–

1.0

mA

µA

VBAT disconnection. V_SUP= GND, 0 V < V_BUS< 18 V. Node sustains

the current that can flow under this condition. BUS remains operational.

I_{BUS_NO_BAT}

–

100

–

(27)

LIN_TSD

LIN_{TSD_HYST}

C_LIN

LIN Thermal Shutdown

180

20

–

°C

pF

LIN Thermal Shutdown Hysteresis

LIN internal capacitor

–

10

Notes

24. This constraint refers to duty cycle D1 and D2 only.

25. V_{TH_DOM}: receiver threshold of the recessive to dominant LIN bus edge. V_{TH_REC}receiver threshold of the dominant to recessive LIN bus edge.

26. V_SUPis the voltage at the input of the device (different from Vbat when a reverse current protection diode is implemented.

27. Guaranteed by design.

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4.3

Dynamic electrical characteristics

Table 5. Dynamic electrical characteristics

T_CASE= -40 °C to 125 °C, unless otherwise specified. V_SUP= V_{SUP_UV_L}to 40 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V_SUP< 40 V, thermal dissipation must be considered (Figure 25).

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

Digital interface timing

f_SPI

SPI Operation Frequency (50% DC)

MISO Transition Speed, 20 - 80%

0.5

–

8.0

MHz

ns

• V_DDIO= 5.0 V, C_LOAD= 50 pF

• V_DDIO= 5.0 V, C_LOAD= 150 pF

t_{MISO_TRANS}

5.0

–

30

50

t_CLH

t_CLL

Minimum Time SCLK = HIGH

62

–

ns

Minimum Time SCLK = LOW

t_PCLD

Propagation Delay (SCLK to data at 10% of MISO rising edge)

NCS = LOW to Data at MISO Active

SCLK Low Before NCS Low (setup time SCLK to NCS change H/L)

SCLK Change L/H after NCS = low

30

75

–

t_CSDV

–

t_SCLCH

t_HCLCL

t_SCLD

75

40

100

–

SDI Input Setup Time (SCLK change H/L after MOSI data valid)

SDI Input Hold Time (MOSI data hold after SCLK change H/L)

SCLK Low Before NCS High

–

t_HCLD

–

t_SCLCL

t_HCLCH

t_PCHD

t_ONNCS

t_{NCS_MIN}

–

SCLK High After NCS High

–

NCS L/H to MISO at High-impedance

NCS Min. High Time

75

–

500

10

NCS Filter Time

40

NCS

t_ONNCS

t_HCLCH

t_SCLCHt_HCLCL

t_CLH

t_CLL

t_SCLCL

SCLK

MISO

MOSI

t_PCHD

z

t_PCLD

Not used

t_CSDV

Tri-state

LSB

MSB

t_HCLD

MSB

t_SCLD

LSB

Figure 7. SPI timing diagram

500 ns min

NCS

3.5 µs min

Any Fail-safe

Any main

Any Fail-safe

Any Fail Safe

Any Main register

Any Fail Safe

register access

register acces

register access

register acces

register access

acces

Figure 8. Register access restriction

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Table 5. Dynamic electrical characteristics (continued)

T_CASE= -40 °C to 125 °C, unless otherwise specified. V_SUP= V_{SUP_UV_L}to 40 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V_SUP< 40 V, thermal dissipation must be considered (Figure 25).

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

CAN dynamic characteristics

t_DOUT

t_DOM

TXD Dominant State Timeout

Bus Dominant Clamping Detection

0.8

–

5.0

ms

Propagation Loop Delay TXD to RXD

• R_LOAD= 120 Ω, C between CANH and CANL = 100 pF,

C at RxD < 15 pF

t_LOOP

–

255

ns

t_1PWU

t_3PWU

t_3PTO1

t_3PTO2

Single Pulse Wake-up Time

0.5

–

5.0

1.0

–

µs

Multiple Pulse Wake-up Time

–

Multiple Pulse Wake-up Timeout (120 µs bit selection)

Multiple Pulse Wake-up Timeout (360 µs bit selection)

110

350

120

360

–

Delay to Enable CAN by SPI Command (NCS rising edge) to CAN to

Transmit (device in normal mode and CAN interface in TX/RX mode)

(28)

t_{CAN_READY}

–

100

µs

Fail-safe state machine

OSC_FSSM

CLK_{FS_MIN}

t_{IC_ERR}

Oscillator

405

150

4.0

7.0

0.8

1.0

–

495

–

kHz

µs

Fail-safe Oscillator Monitoring

IO_0:5 Filter Time

20

t_{ACK_FS}

Acknowledgement Counter (used for IC error handling IO_1 and IO_5)

9.7

1.3

2.0

ms

t_{_DFS_RECOVERY}IO_0 Filter Time to Recover from Deep Reset and Fail State

t_{IO1_DRIFT_MON}IO_1 filter time

Fail-safe output

t_{RSTB_FB}

t_{FSOB_FB}

t_{RSTB_BLK}

t_{FSOB_BLK}

t_{RSTB_POR}

t_{RSTB_LG}

t_{RSTB_ST}

t_{RSTB_IN}

RSTB Feedback Filter Time

8.0

180

12

–

15

µs

ms

µs

FS0B Feedback Filter Time

RSTB Feedback Blanking Time

FS0B Feedback Blanking Time

Reset Delay Time (after a Power On Reset or from LPOFF)

Reset Duration (long pulse)

–

320

23.6

10

–

(29)

15.9

–

8.0

1.0

8.0

550

Reset duration (short pulse)

–

1.3

15

External Reset Delay time

–

t_{DIAG_SC}

Fail-safe Output Diagnostic Counter (FS0B)

–

800

VSUP voltage supply

C_SUPMinimum capacitor on Vsup

44

–

µF

Notes

28. For proper CAN operation, TXD must be set to high level before CAN enable by SPI, and must remain high for at least T_{CAN_READY.}

29. This timing is not guaranteed in case of fault during startup phase (after Power On Reset of from LPOFF)

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Table 5. Dynamic electrical characteristics (continued)

T_CASE= -40 °C to 125 °C, unless otherwise specified. V_SUP= V_{SUP_UV_L}to 40 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V_SUP< 40 V, thermal dissipation must be considered (Figure 25).

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

V_PREvoltage pre-regulator

f_{SW_PRE}

t_{SW_PRE}

V_PRESwitching Frequency

V_{SW_PRE}On and Off Switching Time

418

–

440

–

462

30

kHz

ns

(30)

t_{PRE_SOFT}

t_{PRE_BLK_LIM}

t_{IPRE_OC}

V_PRESoft Start Duration (C_OUT≤ 100 µF)

V_PRECurrent Limitation Blanking Time

V_PREOvercurrent Filtering Time

500

200

30

20

3.0

–

700

600

120

40

µs

–

ns

(30)

–

ns

t_{PRE_UV}

V_PREUndervoltage Filtering Time

Vpre Shut-off Filtering Time

–

µs

t_{PRE_UV_4p3}

d_IPRE/DT

t_{PRE_WARN}

t_{PRE_TSD}

–

6.0

25

µs

(30)

V_PRELoad Regulation Variation

–

A/ms

µs

V_PREThermal Warning Filtering Time

V_PREThermal Detection Filtering Time

I_PFFInput Voltage Filtering Time

30

1.3

1.0

100

–

40

–

µs

t_{VSUP_IPFF}

t_{IPRE_IPFF}

t_{LS_RISE/FALL}

–

5.0

300

50

µs

I_PFFHigh-side Peak Current Filter Time

LS Gate Voltage Switching Time (I_OUT= 300 mA)

–

ns

–

ns

V_SENSEvoltage regulator

t_{VSNS_UV}

V_SNSUndervoltage Filtering Time

1.0

–

3.0

µs

V_COREvoltage regulator

t_{CORE_BLK_LIM}

f_{SW_CORE}

V_CORECurrent Limitation Blanking Time

20

2.28

6.0

–

2.4

–

40

2.52

12

ns

MHz

ns

V_CORESwitching Frequency

t_{SW_CORE}

V_{SW_CORE}On and Off Switching Time

V_CORESoft Start (C_OUT= 100 µF max)

V_COREThermal Warning Filtering Time

V_COREThermal Detection Filtering Time

V_{CORE_SOFT}

t_{CORE_WARN}

t_{CORE_TSD}

–

10

V/ms

µs

30

–

40

0.5

–

µs

V_CCAvoltage regulator

t_{CCA_LIM}

V_CCAOutput Current Limitation Filter Time

1.0

–

3.0

µs

t_{CCA_LIM_OFF1}

t_{CCA_LIM_OFF2}

10

50

–

V_CCAOutput Current Limitation Duration

ms

t_{CCA_WARN}

t_{CCA_TSD}

dI_LOAD/dt

V_{CCA_SOFT}

Notes

30. Guaranteed by characterization.

V_CCAThermal Warning Filtering Time

V_CCAThermal Detection Filter Time (int. MOSFET)

V_CCALoad Transient

30

1.5

–

40

–

µs

(30)

2.0

–

A/ms

V/ms

V_CCASoft Start (5.0 V and 3.3 V)

–

50

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Table 5. Dynamic electrical characteristics (continued)

T_CASE= -40 °C to 125 °C, unless otherwise specified. V_SUP= V_{SUP_UV_L}to 40 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V_SUP< 40 V, thermal dissipation must be considered (Figure 25).

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

V_AUXvoltage regulator

t_{AUX_LIM}

V_AUXOutput Current Limitation Filter Time

V_AUXOutput Current Limitation Duration

1.0

–

3.0

µs

t_{AUX_LIM_OFF1}

t_{AUX_LIM_OFF2}

10

50

–

ms

t_{AUX_TSD}

dI_AUX/dt

V_AUXThermal Detection Filter Time

V_AUXLoad Transient

1.5

–

2.0

–

µs

(31)

A/ms

V/ms

V_{AUX_SOFT}

V_AUXSoft Start (5.0 V and 3.3 V)

–

50

CAN_5V voltage regulator

t_{CAN_LIM}

t_{CAN_TSD}

t_{CAN_UV}

t_{CAN_OV}

dI_CAN/dt

Output Current Limitation Filter Time

2.0

1.0

4.0

100

–

4.0

–

µs

V_CANThermal Detection Filter Time

V_CANUndervoltage Filtering Time

V_CANOvervoltage Filtering Time

V_CANLoad Transient

–

7.0

200

–

µs

–

µs

(31)

100

A/ms

Fail-safe machine voltage supervisor

t_{PRE_OV}

t_{CORE_UV}

t_{CORE_OV}

t_{CCA_UV}

t_{CCA_OV}

t_{AUX_UV}

t_{AUX_OV}

V_PREOvervoltage Filtering Time

128

4.0

–

234

10

µs

V_COREFB Undervoltage Filtering Time

V_COREFB Overvoltage Filtering Time

V_CCAUndervoltage Filtering Time

V_CCAOvervoltage Filtering Time

V_AUXUndervoltage Filtering Time

V_AUXOvervoltage Filtering Time

128

4.0

234

10

128

4.0

234

10

128

234

Digital input - multi-purpose ios

F_{IO_IN}

Digital Input Frequency Range

0.0

–

100

10

kHz

µs

Analog multiplexer

SPI Selection to Data Ready to be Sampled on Mux_out

• V_DDIO= 5.0 V, C_{MUX_OUT}= 1.0 nF

t_{MUX_READY}

Interrupt

t_{INTB_LG}

t_{INTB_ST}

INTB Pulse Duration (long)

INTB Pulse Duration (short)

90

20

100

25

–

µs

Functional sate machine

t_{WU_GEN}General Wake-up Signal Deglitch Time (for any wu signal on IOs)

Notes

60

70

80

µs

31. Guaranteed by characterization.

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Table 5. Dynamic electrical characteristics (continued)

T_CASE= -40 °C to 125 °C, unless otherwise specified. V_SUP= V_{SUP_UV_L}to 40 V, unless otherwise specified. All voltages referenced to

ground. When 28 V < V_SUP< 40 V, thermal dissipation must be considered (Figure 25).

Symbol

Parameter

Min.

Typ.

Max.

Unit

Notes

LIN dynamic characteristics (when 7.0 V < Vsup1, 2, 3 < 18 V, unless otherwise specified) (33907L/33908L)

t_{RX_PD}

Receiver Propagation Delay (T_{RX_PD}= MAX (t_{REC_PDR}, t_{REC_PDF}))

Symmetry of Receiver Propagation Delay (T_{RX_SYM}= t_{REC_PDF -}

–

6.0

2.0

µs

t_{RX_SYM}

-2.0

t_{REC_PDR}

)

t_{BUS_WU}

t_{XD_DOM}

BUS Wake-up Filter Time

–

5.0

15

–

250

–

µs

ms

TXD_L Permanent Dominant State Delay

t_{LIN_SHORT_GND}LIN Short-circuit to GND Deglitcher

–

ms

BD_FAST

Fast Baud Rate

100

KB/s

Duty Cycle D1

TH_REC(max) = 0.744 x V_SUP, TH_DOM(max) = 0.581 x V_SUP

V_SUP7.0 V to 18 V, t_BIT= 50 µs

(32)

D1

0.396

–

0.581

–

%

D1 = t_BUS-rec(min)/(2t_BIT

)

Duty Cycle D2

TH_REC(min) = 0.422 x V_SUP, TH_DOM(min) = 0.284 x V_SUP

V_SUP7.6 V to 18 V, t_BIT= 50 µs

D2

D3

D4

–

D2 = t_BUS-rec(max)/(2t_BIT

)

Duty Cycle D3

TH_REC(max) = 0.778 x V_SUP, TH_DOM(max) = 0.616 x V_SUP

V_SUP7.0 V to 18 V, t_BIT= 96 µs

0.417

D3 = t_BUS-rec(min)/(2t_BIT

)

Duty Cycle D4

TH_REC(min) = 0.389 x V_SUP, TH_DOM(min) = 0.251 x V_SUP

V_SUP7.6 V to 18 V, t_BIT= 96 µs

–

0.59

D4 = t_BUS-rec(max)/(2t_BIT

)

Notes

32. LIN Driver, Bus load conditions (CBUS,RBUS): 1.0 nF;1.0 kΩ / 6.8 nF;660 Ω / 10 nF;500 Ω

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5

Functional pin description

5.1

Introduction

The 33907/33908 is the third generation of the System Basis Chip, combining:

• High efficiency switching voltage regulator for MCU, and linear voltage regulators for integrated CAN interface, external ICs such as

sensors, and accurate reference voltage for A to D converters.

• Built-in enhanced high-speed CAN interface (ISO11898-2 and -5), and LIN interface (LIN up to Rev. 2.2/ SAEJ2602-2), with local and

bus failure diagnostic, protection, and Fail-safe operation mode.

• Low-power mode, with ultra low-current consumption.

• Various wake-up capabilities.

• Enhanced safety features with multiple fail-safe outputs and scheme to support ASIL D applications.

5.2

Power supplies (VSUP1, VSUP2, VSUP3)

VSUP1 and VSUP2 are the inputs pins for internal supply dedicated to SMPS regulators. VSUP3 is the input pin for internal voltage

reference. VSUP1, 2, and 3 are robust against ISO7637 pulses.

VSUP1,2, and 3 shall be connected to the same supply (Figure 58).

5.3

Vsense input (VSENSE)

This pin must be connected to the battery line (before the reverse battery protection diode), via a serial resistor. It incorporates a threshold

detector to sense the battery voltage, and provide a battery early warning. It also includes a resistor divider to measure the VSENSE

voltage via the MUX-OUT pin. VSENSE pin is robust against ISO7637 pulses.

5.4

Pre-regulator (VPRE)

A highly flexible SMPS pre-regulator is implemented in the 33907/33908. It can be configured as a “non-inverting buck-boost converter”

(Figure 27) or “standard buck converter” (Figure 26), depending on the external configuration (connection of pin GATE_LS). The

configuration is detected automatically during start-up sequence.

The SMPS pre-regulator is working in current mode control and the compensation network is fully integrated in the device. The high-side

switching MOSFET is also integrated to make the current control easier. The pre-regulator delivers a typical output voltage of 6.5 V, which

is used internally. Current limitation, overcurrent, overvoltage, and undervoltage detectors are provided. VPRE is enabled by default.

5.5

VCORE Output (from 1.2 V to 3.3 V range)

The VCORE block is an SMPS regulator. The voltage regulator is a step down DC-DC converter operating in voltage control mode. The

output voltage is configurable from 1.2 V to 3.3 V range thanks to an external resistor divider connected between VCORE and the

feedback pin (FB_CORE) (as example in Figure 1, Figure 2, and Figure 58).

The stability of the converter is done externally, by using the COMP_CORE pin. Current limitation, overvoltage, and undervoltage

detectors are provided. VCORE can be turned ON or OFF via a SPI command, however it is not recommended to turn OFF VCORE by

SPI when VCORE is configured safety critical (both overvoltage and undervoltage have an impact on RSTB and FS0B). VCORE

overvoltage information disables VCORE. Diagnostics are reported in the dedicated register and generate an Interrupt. VCORE is enabled

by default.

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5.6

VCCA output, 5.0 V or 3.3 V selectable

The VCCA voltage regulator is used to provide an accurate voltage output (5.0 V, 3.3 V) selectable through an external resistor connected

to the SELECT pin.

The VCCA output voltage regulator can be configured using an internal transistor delivering very good accuracy ( 1.0% for 5.0 V

configuration and 1.5% for 3.3 V configuration), with a limited current capability (100 mA) for an analog to digital converter, or with an

external PNP transistor, giving higher current capability (up to 300 mA) with lower output voltage accuracy ( 3.0% for 300 mA) when using

a local ECU supply.

Current limitation, overvoltage, and undervoltage detectors are provided. VCCA can be turned ON or OFF via a SPI command, however

it is not recommended to turn OFF VCCA by SPI when VCCA is configured safety critical (both overvoltage and undervoltage have an

impact on RSTB and FS0B). VCCA overcurrent (with the use of external PNP only) and overvoltage information disables VCCA.

Diagnostics are reported in the dedicated register and generate an Interrupt. VCCA is enabled by default.

5.7

VAUX output, 5.0 V or 3.3 V selectable

The VAUX pin provides an auxiliary output voltage (5.0 V, 3.3 V) selectable through an external resistor connected to SELECT pin. It uses

an external PNP ballast transistor for flexibility and power dissipation constraints. The VAUX output voltage regulator can be used as

“auxiliary supply” (local ECU supply) or “sensor supply” (external ECU supply) with the possibility to be configured as a tracking regulator

following VCCA.

Current limitation, overvoltage, and undervoltage detectors are provided. VAUX can be turned ON or OFF via a SPI command, however

it is not recommended to turn OFF VAUX by SPI when VAUX is configured safety critical (both overvoltage and undervoltage have an

impact on RSTB and FS0B). VAUX overcurrent and overvoltage information disables V_AUX, reported in the dedicated register, and

generates an Interrupt. V_AUXis enabled by default.

5.8

SELECT Input (VCCA, VAUX voltage configuration)

VCCA and VAUX output voltage configurations are set by connecting an external resistor between SELECT pin and Ground. According

to the value of this resistor, the voltage of VCCA and VAUX are configured after each Power On Reset, and after a wake-up event when

device is in LPOFF. Information latches until the next hardware configuration read. Regulator voltage values can be read on the dedicated

register via the SPI.

Table 6. V_CCA/V_AUXVoltage Selection (Figure 59)

V_CCA(V)

V_AUX(V)

R Select

Recommended value

3.3

5.0

3.3

5.0

3.3

5.0

3.3

<7.0 KΩ

5.1 KΩ 5.0%

12 KΩ 5.0%

24 KΩ 5.0%

51 KΩ 5.0%

10.8 << 13.2 KΩ

21.6 << 26.2 KΩ

45.9 << 56.1 KΩ

When VAUX is not used, the output VCCA voltage configuration is set using an external resistor connected between the SELECT and the

VPRE pin.

Table 7. V_CCAVoltage Selection (V_AUXnot used, Figure 60, Figure 61)

V_CCA(V)

R Select

Recommended Value

<7.0 KΩ

5.1 KΩ 5.0%

24 KΩ 5.0%

12 KΩ 5.0%

51 KΩ 5.0%

3.3

21.6 << 26.2 KΩ

10.8 << 13.2 KΩ

45.9 << 56.1 KΩ

5.0

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5.9

CAN_5V voltage regulator

The CAN_5V voltage regulator is a linear regulator dedicated to the internal HSCAN interface. An external capacitor is required. Current

limitation, overvoltage, and undervoltage detectors are provided. If the internal CAN transceiver is not used, the CAN_5V regulator can

supply an external load (CAN_5V voltage regulator). CAN_5V is enabled by default.

5.10 INTERRUPT (INTB)

The INTB output pin generates a low pulse when an Interrupt condition occurs. The INTB behavior as well as the pulse duration are set

through the SPI during INIT phase. INTB has an internal pull-up resistor connected to VDDIO.

5.11 CANH, CANL, TXD, RXD

These are the pins of the high speed CAN physical interface. The CAN transceivers provides the physical interface between the CAN

protocol controller of an MCU and the physical dual wires CAN bus. The CAN interface is connected to the MCU via the RXD and TXD

pins.

5.11.1 TXD

TXD is the device input pin to control the CAN bus level. TXD is a digital input with an internal pull-up resistor connected to VDDIO. In the

application, this pin is connected to the microcontroller transmit pin.

In Normal mode, when TXD is high or floating, the CANH and CANL drivers are OFF, setting the bus in a recessive state. When TXD is

low, the CANH and CANL drivers are activated and the bus is set to a dominant state. TXD has a built-in timing protection that disables

the bus when TXD is dominant for more than T_DOUT. In LPOFF mode, VDDIO is OFF, pulling down this pin to GND.

5.11.2 RXD

RXD is the bus output level report pin. In the application, this pin is connected to the microcontroller receive pin. In Normal mode, RXD is

a push-pull structure. When the bus is in a recessive state, RXD is high. When the bus is dominant, RXD is low. In LPOFF mode, this pin

is in high-impedance state.

5.11.3 CANH and CANL

These are the CAN bus pins. CANL is a low side driver to GND, and CANH is a high side driver to CAN_5V. In Normal mode and TXD

high, the CANH and CANL drivers are OFF, and the voltage at CANH and CANL is approximately 2.5 V, provided by the internal bus

biasing circuitry. When TXD is low, CANL is pulled to GND and CANH to CAN_5V, creating a differential voltage on the CAN bus.

In LPOFF mode, the CANH and CANL drivers are OFF, and these pins are pulled down to GND via the device RIN_CHCL resistors. CANH

and CANL have integrated ESD protection and extremely high robustness versus external disturbance, such as EMC and electrical

transients. These pins have current limitation and thermal protection.

5.12 LIN, TXDL, RXDL

These pins apply to 33907L and 33908L versions.

These are the pins of the LIN physical interface. The LIN transceivers provides the physical interface between the MCU and the physical

single wire LIN bus. The LIN interface is connected to the MCU via the RXDL and TXDL pins.

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5.12.1 TXDL

The TXDL input pin is the MCU interface to control the state of the LIN output. TXDL is a digital input with an internal pull-up resistor

connected to VDDIO. In the application, this pin is connected to the microcontroller transmit pin.

In Normal mode, when TXDL is high or floating, the LIN output transistor is OFF, setting the bus in recessive state. When TXDL is low,

the LIN output transistor is ON and the bus is set to a dominant state. TXDL has a built-in timing protection that disables the bus when

TXDL is dominant for more than T_{XD_DOM}. In LPOFF mode, VDDIO is OFF, pulling down this pin to GND.

5.12.2 RXDL

RXDL is the bus output level report pin. In the application, this pin is connected to the microcontroller receive pin. In Normal mode, RXD

is a push-pull structure. When the bus is in a recessive state, RXD is high. When the bus is dominant, RXD is low. In LPOFF mode, this

pin is in high-impedance state.

5.12.3 LIN

This is the LIN bus pin. The LIN driver is a low-side MOSFET with internal overcurrent thermal shutdown. An internal pull-up resistor with

a serial diode structure is integrated so no external pull-up components are required for the application in a slave node. An additional pull-

up resistor of 1.0 kΩ must be added when the device is used in the master node. In Normal mode and TXDL high, the LIN transistor is

OFF, and the voltage at LIN is approximately VSUP3, provided by the pull up resistor with a serial diode structure. When TXD is low, LIN

is pulled to GND

The device has two selectable baud rates: 20 kBits/s for Normal Baud rate and 10 kBits/s for slow baud rate. An additional fast baud rate

(100 kBits/s) is implemented. It can be used to flash the MCU or in the garage for diagnostic. The LIN Consortium specification does not

specify electrical parameters for this baud rate. The communication only must be guaranteed. In LPOFF mode, the LIN transistor is OFF,

and this pin is pulled up to VSUP3. LIN has integrated ESD protection and extremely high robustness versus external disturbance, such

as EMC and electrical transients.

5.13 Multiplexer output MUX_OUT

The MUX_OUT pin (Figure 9) delivers analog voltage to the MCU ADC input. The voltage to be delivered to MUX_OUT is selected via

the SPI, from one of the following parameters:

• VSENSE

• VIO_0

• VIO_1

• Internal 2.5 V reference

• Die temperature sensor T(°C) = (V_AMUX- V_{AMUX_TP}) / V_{AMUX_TP_CO}+ 165

Voltage range at MUX_OUT is from GND to VDDIO (3.3 V or 5.0 V)

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VSENSE

R

1

SPI selection

Mux_out

R

2

R

3

R

5

R

4

3.3 V

Ratio#1 Ratio#2

3.3 V

5.0 V

Ratio#1

5.0 V

Ratio#2

SPI selection

Internal 2.5 V reference

Same as above

IO_0

IO_1

SPI selection

Die temperature sensor

Figure 9. Simplified analog multiplexer block diagram

5.14 I/O pins (I/O_0:I/O_5)

The 33907/33908 includes six multi-purpose I/Os (I/O_0 to I/O_5). I/O_0, I/O_1, I/O_4, and I/O_5 are load dump proof and robust against

ISO7637 pulses. An external serial resistor must be connected to those pins to limit the current during ISO pulses. I/O_2 and I/O_3 are

not load dump proof.

Table 8. I/Os configuration

I/0 number

Analog input

Digital input Wake-up capability

Output gate driver

IO_0

X

IO_1

IO_2

IO_3

IO_4

IO_5

X

• IO_0:1 are selectable as follows:

Analog input (load dump proof) sent to the MCU through the MUX_OUT pin. Wake-up input on the rising or falling edge or based on

the previous state. Digital input (logic level) sent to the MCU through the SPI. Safety purpose: Digital input (logic level) to perform

an IC error monitoring (both IO_0 AND IO_1 are used if configured as safety inputs, see Figure 11).

• IO_1 is also selectable as follow:

Safety purpose: FB_Core using a second resistor bridge (R3/R4 duplicated) connected to IO_1, to detect external resistor drift and

trigger when FB_Core - IO_1 > 150 mV max.

• IO_2:3 are selectable as follows:

Digital input (logic level) sent to the MCU through the SPI. Wake-up input (logic level) on the rising or falling edge or based on the

previous state. Safety purpose: Digital input (logic level) to monitor MCU error signals (both IO_2 AND IO_3 are used if configured

as safety inputs). Only bi-stable protocol is available.

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When IO_2:3 are used as safety inputs to monitor FCCU error outputs from the NXP MCU, the monitoring is active only when the

Fail-safe sate machine is in “normal WD running” state (Figure 14) and all the phases except the “Normal Phase” are considered as

an Error.

Config Phase

Reset Phase Normal Phase

Error Phase

FCCU_eout[0]

FCCU_eout[1]

Figure 10. IO_2:3 MCU error monitoring: bi-stable protocol

• IO_4:5 are selectable as follows:

Digital input (logic level) sent to the MCU through the SPI. Wake-up input (load dump proof) on rising or falling edge or based on

previous state. Output gate driver (from V_PRE) for low-side logic level MOSFET. Safety purpose: Digital input (logic level) to perform

an IC error monitoring (both IO_4 AND IO_5 are used if configured as safety inputs, see Figure 11).

Error signal (IO_4 input)

Acknowledgment counter

33907_8 Internal IO_4 signal

latched

Reset

counter

Restart Acknowledgment

counter

Acknowledgement signal

from MCU (IO_5 input)

Filter time

RSTB

FS0B

The error is acknowledged by the MCU

then, internal IO_4 signal is released

The error is NOT

acknowledged by the MCU

So, FS0B is activated at the

end of the counter

Figure 11. External error signal handling

5.15 SAFE output pins (FS0B, RSTB)

FS0B is asserted low when a fault event occurs (See Faults triggering FS0B activation on page 45). The objective of this pin is to drive

an electrical safe circuitry independent from MCU to deactivate the whole system and set the ECU in a protected and known state.

After each power on reset or after each wake-up event (LPOFF) the FS0B pin is asserted low. Then the MCU can decide to release the

FS0B pin, when the application is ready to start. An external pull-up circuitry is mandatory connected to VDDIO or VSUP3.

• If the pull-up is connected to VDDIO, the value recommended is 5.0kΩ, there will be no current in LPOFF since VDDIO is OFF in

LPOFF mode.

• If the pull-up is connected to VSUP3, the value must be above 10 kΩ, there will be a current in the pull-up resistor to consider at

application level in LPOFF mode.

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The RSTB pin must be connected to MCU and is active low. An external pull-up resistor must be connected to VDDIO. In default

configuration, the RST delay time has three possible values depending on the mode and product configuration:

• The longest one is used automatically following a Power On Reset or when resulting from LPOFF mode (Low Power Off).

• The two reset durations are then available in the INIT_FSSM1 register, which are 1.0 ms and 10 ms. The configured duration is

finally used in the normal operation when a fault occurs leading to a reset activation. The INIT_FSSM1 register is available (writing)

in the INIT FS phase.

5.16 DEBUG input (entering in debug mode)

The DEBUG pin allows the product to enter Debug mode. To activate the Debug mode, voltage applied to the DEBUG pin must be within

the V_{DEBUG_IL}and V_{DEBUG_IH}range at start-up. If the voltage applied to DEBUG pin is out of these limits, before V_COREramp-up, the

device settles into Normal mode. When the Debug mode is activated, the FS0B output is asserted low at start-up. As soon as the FS0B

is released to “high” via SPI (Good WD answer and FS_OUT writing) this pin is never activated whatever the fault is reported.

In Debug mode, any errors from watchdog are ignored (No reset and No fail-safe), even if the whole functionality of the watchdog is kept

ON (Seed, LFSR, Wd_refresh counter, WD error counter). This allows an easy debug of the hardware and software routines (i.e. SPI

commands). When the Debug mode is activated, the CAN transceiver is set to Normal operation mode. This allows communication with

the MCU, in case SPI communication is not available (case of MCU not programmed). To exit Debug mode, the pin must be tied to Ground

through an external pull-down resistor or to VPRE through an external pull-up resistor and a Power On Reset occurs.

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6

Functional device operation

6.1

Mode and state description of main state machine

The device has several operation modes. The transition and conditions to enter or leave each mode are illustrated in the functional state

diagram (Figure 13). Two state machines are working in parallel. The Main state machine is in charge of the power management (VPRE,

VCORE, VCCA, VAUX,...) and the fail-safe state machine is in charge of all the safety aspect (WD, RSTB, FS0B,...).

6.1.1 Buck or buck boost configuration

An external low side logic level MOSFET (N-type) is required to operate in non-inverting buck-boost converter. The connection of the

external MOSFET is detected automatically during the start-up phase (after a Power On Reset or From LPOFF).

• If the external low-side MOSFET is NOT connected (GATE_LS pin connected to PGND), the product is configured as a standard

buck converter.

• If the external low-side MOSFET is connected (GATE_LS pin connected to external MOSFET gate), the product is configured as a

non-inverting buck-boost converter.

The automatic detection is done by pushing 300 μA current on Gate_LS pin and monitoring the corresponding voltage generated. If a

voltage >120 mV is detected before the 120 μs timeout, the non-inverting buck-boost configuration is locked. Otherwise, the standard

buck configuration is locked. The boost driver has a current capability of 300 mA.

6.1.2 VPRE on

Pre-regulator is an SMPS regulator. In this phase, the pre-regulator is switched ON and a softstart with a specified duration t_{PRE_SOFT}is

started to control the VPRE output capacitor charge.

6.1.3 Select pin configuration

This phase is detecting the required voltage level on VAUX and VCCA, according to resistor value connected between the SELECT pin

and ground. If the SELECT pin is connected to VPRE via the resistor, it disables the VAUX regulator at start-up.

6.1.4 VCORE/VAUX/VCCA on

In this stage, the three regulators VCORE, VAUX, VCCA are switched ON at the same time with a specified soft start duration. The

CAN_5V is also started at that time.

6.1.5 INIT main

This mode is automatically entered after the device is “Powered ON”. When RSTB is released, initialization phase starts where the device

can be configured via the SPI. During INIT phase, some registers can only be configured in this mode (refer to Table 15 and Table 16).

Other registers can be written in this mode, and also in Normal mode.

Once the INIT registers configurations are complete, a last register called “INIT INT” must be configured to switch to Normal mode. Writing

data in this register (even same default values), automatically locks the INIT registers, and the product switches automatically to Normal

mode in the Main state machine.

6.1.6 Normal

In this mode, all device functions are available. This mode is entered by a SPI command from the INIT phase by writing in the INIT INT

register. While in Normal mode, the device can be set to Low Power mode (LPOFF) using secured SPI command.

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6.1.7 Low power mode off

The Main State Machine has 3 LPOFF modes with different conditions to enter and exit each LPOFF mode as described here after. After

wake up from LPOFF, all the regulators are enabled by default. In LPOFF, all the regulators are switched OFF. The register configuration,

the Vpre behavior and the ISO pulse requirement are valid for the 3 LPOFF modes.

6.1.7.1

LPOFF - sleep

Entering in Low Power mode LPOFF - SLEEP is only available if the product is in Normal mode by sending a secured SPI command. In

this mode, all the regulators are turned OFF and the MCU connected to the VCORE regulator is unsupplied.

Before entering in LPOFF Power mode OFF-sleep, the Reset Error Counter must go back to value “0” (“N” consecutive good watchdog

refresh decreases the reset error counter to 0). “N” = RSTb_err_2:0 x (WD_refresh_2:0 + 1). Once the 33907/33908 is in LPOFF - SLEEP,

the device monitors external events to wake-up and leave the Low Power mode. The wake-up events can occur and depending of the

device configuration from:

• CAN

• LIN

• I/O inputs

When a wake-up event is detected, the device starts the main state machine again by detecting the VPRE configuration (BUCK or BUCK-

BOOST), the wake-up source is reported to the dedicated SPI register, and the Fail-safe state machine is also restarted.

6.1.7.2

LPOFF - V

PRE_UV

LPOFF- V_{PRE_UV}is entered when the device is in the INIT or Normal mode, and if the VPRE voltage level is passing the V_{PRE_UV_L_4P3}

threshold (typ 4.3 V). After 1.0 ms the device attempts to recover by switching ON the VPRE again.

6.1.7.3

LPOFF - deep FS

LPOFF - DEEP FS is entered when the device is in Deep Fail-safe and if the Key is OFF (IO_0 is low). To exit this mode, a transition to

high level on IO_0 is required. IO_0 is usually connected to key ON key OFF signal.

6.1.7.4

Register configuration in LPOFF

In LPOFF, the register settings of the Main State Machine are kept because the internal 2.5 V main digital regulator is available for wake-

up operation. However, the register settings of the Fail-safe state machine are erased because the 2.5 V fail safe digital regulator is not

available in LPOFF. As a consequence, after a wake-up event, the configuration of the Fail-safe registers must be done again during

initialization phase (256 ms open window).

6.1.7.5

V

behavior in LPOFF

PRE

When device is in LPOFF Sleep mode, and if the VSUP < V_{SUP_UV_7}, VPRE is switched on to maintain internal biasing and wake-up

capabilities on IOs, CAN or LIN.

• If V_PREis configured as a non-inverting buck-boost converter, VPRE is switched ON in SMPS mode with boost functionality.

• If V_PREis configured as a standard buck converter, V_PREis switched ON in Linear mode following V_SUP

.

6.1.7.6

ISO pulse in LPOFF

If the application has to sustain ISO pulses on V_BATin LPOFF mode, the connection of a an external zener diode and a serial resistor to

the ground is mandatory (see Figure 12). During repetitive ISO pulses on Vbat, the capacitors connected on V_SUPline are more and more

charged and cannot be discharged thanks to the extremely low-current needed to maintain wake-up capabilities on IOs, CAN, and LIN.

As a consequence, if a leakage path is not created artificially with those discrete components the voltage on V_SUPline can exceed the

absolute maximum rating supported by this pin.

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V

BAT

33907_08

33907/33908

VSUP3

VSENSE

Figure 12. Components involved under ISO pulse in LPOFF

6.2

Mode and state description of fail-safe state machine

6.2.1 LBIST

Included in the fail-safe machine, the Logic Built-in Self Test (LBIST) verifies the correct functionality of the FSSM at start-up. The fail-safe

state machine is fully checked and if an issue is reported, the RSTB stays low and after 8 s, the device enters in DEEP Fail-safe. LBIST

is run at start-up and after each wake-up event when the device is in LPOFF mode.

6.2.2 Select pin configuration

This phase detects the required voltage level to apply on VAUX and VCCA, according to the resistor value connected between the

SELECT pin and ground, (V_AUXused) or between the SELECT pin and VPRE (V_AUXnot used). This mode is the equivalent mode seen

in the main state machine. Difference is in the fail-safe machine, this detection is used to internally set the UV/OV threshold on VCCA and

VAUX for the voltage supervision.

6.2.3 ABIST

Included in the fail-safe machine, the Analog Built-in Self Test (ABIST) verifies the correct functionality of the analog part of the device,

like the overvoltage and undervoltage detections of the voltage supervisor and the RTSTB and FS0B fail-safe outputs feedback (Table 9).

The ABIST is run at start-up and after each wake-up event when device is in LPOFF mode.

Table 9. Regulators and fail-safe pins checked during ABIST

Parameters

Overvoltage

Undervoltage

OK/NOK

VPRE

VCORE

X

VCCA

VAUX

IO_1 FB_Core Delta

RSTB

X

FS0B

6.2.4 Release RSTB

In this state, the device releases the RSTB pin.

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6.2.5 INIT FS

This mode is automatically entered after the device is “powered on” and only if Built-in Self Tests (Logic and Analog) have been passed

successfully. This INIT FS mode starts as soon as RSTB is released (means no “Activate RST” faults are present and no external reset

is requested). Faults leading to an “Activate RST” are described in Reset error counter.

In this mode, the device can be configured via the SPI within a maximum time of 256 ms, including first watchdog refresh. Some registers

can only be configured in this mode and is locked when leaving INIT FS mode (refer to Table 15 and Table 16). It is recommended, to

configure first the device before sending the first WD refresh. As soon as the first good watchdog refresh is sent by the MCU, the device

leaves this mode and goes into Normal WD mode.

6.2.6 Normal WD is running

In this mode, the device waits for a periodic watchdog refresh coming from the MCU, within a specific configured window timing.

Configuration of the watchdog window period can be set during INIT FS phase or in this mode. This mode is exited if there are consecutive

bad watchdog refreshes if there is an external reset request, or if a fault occurs leading to a RSTB activation.

6.2.7 RST delay

When the reset pin is asserted low by the device, a delay runs, to release the RSTB, if there are no faults present. The reset low duration

time is configurable via the SPI in the INIT_ FSSM1 register, which is accessible for writing only in the INIT FS phase.

6.3

Deep fail safe state

The Fail-safe state machine monitors the RSTB pin of the device and count the number of reset(s) happening in case of fault detection

(see Reset error counter). As soon as either the Reset Error Counter reach its final value or the RESET pin remains asserted low for more

than 8.0 s, the device moves to Deep Fail-safe state, identified by the “Wait Deep Fail-safe” state in the functional state diagram

(Figure 13).

When the device is in Deep Fail-safe state, all the regulators are OFF. To exit this state, a Key OFF / Key ON action is needed. IO_0 is

usually connected to key signal. Key OFF (IO_0 low) will move the device to LPOFF-Deep FS, and Key ON (IO_0 high) will wake-up the

device.

The final value of the Reset Error Counter can be configured to 2 or 6 in the register INIT FSSM 2. During power up phase, the 8.0 s timer

starts when the Fail-safe state machine enters in the “Select pin config detection” state and stop when the RSTB pin is released. During

“INIT FS” state, the 8.0 s timer can be disabled in the register INIT SUPERVISOR 2. During “Normal WD running” state, the 8.0 s timer is

activated at each RSTB pin assertion.

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6.4

Functional state diagram

V_SUP> V_{SUP_UV_5}Wait

Fail

SAFE

No POR Fail Safe

PowerDown

From

Anywhere

POR Fail Safe &

Fail Safe Reg. ON

& V_SUP> V_{SUP_UV_5}

V_SUP< V_{SUP_UV_L}

PowerDown

LBIST

From

Anywhere

POR Fail Safe

V_SUP< V_{SUP_UV_5}

Buck or

Buck Boost

configuration

detection

- RSTb is asserted low

LBIST Done &

_PRE>V_{PRE_UV}

V

120µs elapsed

V_{SUP <}V_{SUP_UV_5}

Vpre OFF

V_PRE

ON

SELECT pin

config.

V_PRE<V_{PRE_UV}

- RSTb is asserted low

Vpre ON

detection

V_PRE>V_{PRE_UV}

1ms elapsed &

V_{CORE >}V_{CORE_UV &}

V_{CCA >}V_{CCA_UV &}

V_{AUX >}V_{AUX_UV}

V_PRE<V_{PRE_UV}

SELECT pin

config.

detection

- RSTb is asserted low

ABIST

Wait

Deep Fail

Safe

1ms elapsed

RST delay=8s or

RST error counter = 6

ABIST Pass

Vcore/Vaux/

Vcca ON

No IO_0

No activate RST &

RST delay expired

- RSTb delay running

- RSTb is asserted low

RST Delay

External

RST

Activate RST

- Unlock SPI init registers

- SPI config

Release

RSTb

- RSTb is released

V_{PRE_UV_L4P3}

INIT MAIN

No external RST &

No activate RST

External

RST

INIT done

(init int reg. writing)

- Unlock SPI init registers

- Start 256ms open window

- RSTb is released

- SPI init registers locked

INIT FS

Activate RST or

WD Not OK

NORMAL

V_{PRE_UV_L4P3}

MODE

WD OK

SPI command

External

RST

NORMAL

WD is

- Start WD close/open window

RUNNING

Activate

RST

LPOFF -

V_{PRE_UV}

LPOFF -

SLEEP

- V_CAN/V_CORE/V_AUX/V_CCAOFF

- Fail Safe OFF

LPOFF -

DEEP FS

1ms

CAN/IOs event

Rise IO_0

Activate RST : any UV, any OV, WD,

IO_23 error, deep fail safe, reset by spi,

IO_1 FB_core delta, FS0b short to VDD,

SPI DED

Wake up

- V_CAN/V_COREOFF

- V_AUX/V_CCAOFF

- OSC Main ON

- FailSafe ON

POR Fail Safe &

Fail Safe Reg. ON

FAIL SAFE STATE MACHINE

MAIN STATE MACHINE

Figure 13. Simplified state diagram

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37

6.5

Fail-safe machine

To fulfill safety critical applications, the 33907/33908 integrates a dedicated fail-safe machine (FSM). The FSM is composed of three main

sub-blocks: the Voltage Supervisor (VS), the Fail-safe state machine (FSSM), and the Fail-safe output driver (FSO).The FSM is electrically

independent from the rest of the circuitry, to avoid common cause failure.

For this reason, the FSM has its own voltage regulators (analog and digital), dedicated bandgap, and its own oscillator. Three power

supply pins (VSUP 1, 2, & 3) are used to overtake a pin lift issue. The internal voltage regulators are directly connected on VSUP (one

bonding wire per pin is used). Additionally, the ground connection is redundant as well to avoid any loss of ground.

All the voltages generated in the device are monitored by the voltage supervisor (under & overvoltage) owing to a dedicated internal

voltage reference (different from the one used for the voltage regulators). The result is reported to the MCU through the SPI and delivered

to the Fail-safe state machine (FSSM) for action, in case of a fault. All the safety relevant signals feed the FSSM, which handles the error

handling and controls the fail-safe outputs.

There are two fail-safe outputs: RSTB (asserted low to reset the MCU), and FS0B (asserted low to control any fail-safe circuitry). The Fail-

safe machine is in charge of bringing and maintaining the application in a Fail-safe state. Four sub Fail-safe states are implemented to

handle the different kinds of failures, and to give a chance for the system to come back to a normal state.

6.5.1 Fail-safe machine state diagram

No POR Fail-safe

From

PowerDown

Anywhere

POR Fail-safe

- RSTb is asserted low

LBIST

LBIST Done &

V_PRE>V_{PRE_UV}

SELECT pin

config.

V_PRE<V_{PRE_UV}

- RSTb is asserted low

detection

1ms elapsed &

V_{CORE >}V_{CORE_UV &}

V_{CCA >}V_{CCA_UV &}

V_{AUX >}V_{AUX_UV}

- RSTb is asserted low

ABIST

RSTb delay = 8s

IO_0

ABIST Pass

No activate RST &

RST delay expired

- RSTb delay running

- RSTb is asserted low

RST delay=8s OR

Rst_error_count=6

Assert RSTb

External

RST

Activate RST

Release

RSTb

- RSTb is released

- V_CAN/V_COREOFF

- V_AUX/V_CCAOFF

- Fail Safe OFF

- FS0b = Low

Deep Fail

Safe

No external RST &

No activate RST

External RSTb =

- RSTb = Low

8s

External

RST

- Unlock SPI init registers

- Start 256ms open window

- RSTb is released

Activate

RST

INIT FS

2 > RST_error_count < 6

Activate RST or

WD Not OK

FS0b low & No

activate RST &

RST delay expired

WD OK

RST_err_count = 0

& FS_OUT ok

External

RST

RST delay=8s

- FS0b is asserted low

FS0B Low

Ext. IC error (IO0:1

and/or IO4:5)

NORMAL

WD is

RUNNING

Release

FSOb

-FS0b is

released

- Start WD close/open window

No FS0b

Ext. IC error (IO0:1

and/or IO4:5)

Figure 14. Detailed fail-safe state diagram

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6.5.2 Watchdog operation

A windowed watchdog is implemented in the 33907/33908 and is based on “question/answer” principle (Challenger). The watchdog must

be continuously triggered by the MCU in the open watchdog window, otherwise an error is generated. The error handling and watchdog

operations are managed by the Fail-safe state machine. For debugging purpose, this functionality can be inhibited by setting the right

voltage on the DEBUG pin at start-up.

The watchdog window duration is selectable through the SPI during the INIT FS phase or in Normal mode. The following values are

available: 1.0 ms, 2.0 ms, 3.0 ms, 4.0 ms, 6.0 ms, 8.0 ms, 12 ms, 16.0 ms, 24 ms, 32 ms, 64 ms, 128 ms, 256 ms, 512 ms, and 1024 ms.

The watchdog can also be inhibited through the SPI register to allow “reprogramming” (ie.at vehicle level through CAN).

An 8-bit pseudo-random word is generated, due to a Linear Feedback Shift Register implemented in the 33907/33908. The MCU can send

the seed of the LFSR or use the LFSR generated by the 33907/33908 during the INIT phase and performs a pre-defined calculation. The

result is sent through the SPI during the “open” watchdog window and verified by the 33907/33908. When the result is right, a new LFSR

is generated and the watchdog window is restarted. When the result is wrong, the WD error counter is incremented, the watchdog window

is restarted, an INTB is generated, and the LFSR value is not changed. Any access to the WD register during the “closed” watchdog

window is considered a wrong WD refresh.

6.5.2.1

Normal operation (first watchdog refresh)

At power up, when the RSTB is released as high (after around 16 ms), the INIT phase starts for a maximum duration of 256 ms and this

is considered as a fully open watchdog window. During this initialization phase the MCU sends the seed for the LFSR, or uses the default

LFSR value generated by the 33907/33908 (0xB2), available in the WD_LFSR register (Table 75). Using this LFSR, the MCU performs

a simple calculation based on this formula. As an example, the result of this calculation based on LFSR default value (0xB2) is 0x4D.

NOT

LFSR_OUT[7:0]

x

4

+

-

/

WD_answer[7:0]

6

4

Figure 15. Watchdog answer calculation

The MCU sends the results in the WD answer register (Table 77). When the watchdog is properly refreshed during the open window, the

256 ms open window is stopped and the initialization phase is finished. A new LFSR is generated and available in the WD LFSR register,

Table 74. If the watchdog refresh is wrong or if the watchdog is not refreshed during this 256 ms open window (INIT FS phase), the device

asserts the reset low and the RSTB error counter is incremented by “1”.

After a good watchdog refresh, the device enters the Normal WD refresh mode, where open and closed windows are defined either by

the configuration made during initialization phase in the watchdog window register (Table 73), or by the default value already present in

this register (3.0 ms).

6.5.2.2

Normal watchdog refresh

The watchdog must be refreshed during every open window of the window period configured in the register Table 73. Any WD refresh

restarts the window. This ensures the synchronization between MCU and 33907/33908.

The duration of the “window” is selectable through the SPI with no access restriction, means the window duration can be changed in the

INIT phase or Normal mode. Doing the change in normal operation allow the system integrator to configure the watchdog window duration

on the fly:

• The new WD window duration (except after disable) will be taken into account when a write in the WD_answer register occurs (good

or bad WD answer) or when the previous WD window is finished without any writing (WD timeout)

• The new WD window duration after disable will be taken into account when SPI command is validated

The duty cycle of the window is set to 50% and is not modifiable.

Window Period

CLOSED

OPEN

CLOSED

OPEN

Refresh

Slot

Refresh

Slot

Figure 16. Windowed watchdog

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6.5.2.3

Watchdog in debug mode

When the device is in debug mode (entered via the DEBUG pin), the watchdog continues to operate, but does not affect the device

operation by asserting a reset or fail-safe pins. For the user, operation appears without the watchdog. If needed and to debug the

watchdog itself, the user can operate as in Normal mode and check LFSR values, the watchdog refresh counter, the watchdog error

counter, and reset counter. This allows the user to debug their software and ensure a good watchdog strategy in the application.

6.5.2.4

Wrong watchdog refresh handling

Error counters and strategy are implemented in the device to manage wrong watchdog refreshes from the MCU. According to consecutive

numbers of wrong watchdog refreshes, the device can decide to assert the RSTB only, or to go in deep Fail-safe mode where only a Power

On Reset or a transition on IO_O helps the system to recover.

6.5.2.5

Watchdog error counter

The watchdog error counter is implemented in the device to filter the incorrect watchdog refresh. Each time a watchdog failure occurs, the

device increments this counter by 2. The WD error counter is decremented by 1 each time the watchdog is properly refreshed. This

principle ensures that a cyclic “OK/NOK” behavior converges to a failure detection. To allow flexibility in the application, the maximum

value of this counter is configurable in the INIT_WD register, but only when device is in INIT FS mode.

Watchdog Error Counter

WD_CNT_error = 6

Watchdog Error Counter

WD_CNT_error = 2

Watchdog Error Counter

WD_CNT_error = 4

WD refresh NOK

0

WD refresh OK

WD refresh NOK

1

2

1

WD refresh OK

2

3

4

5

6

WD refresh NOK

2

WD refresh NOK

WD refresh OK

3

WD refresh NOK

4

WD refresh NOK

Figure 17. Watchdog error counter configuration (INIT_WD register, Bits WD_CNT_error_1:0)

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6.5.2.6

Watchdog refresh counter

The watchdog refresh counter is used to decrement the RST error counter. Each time the watchdog is properly refreshed, the watchdog

refresh counter is incremented by “1”. Each time the watchdog refresh counter reaches “6” and if next WD refresh is also good, the RST

error counter is decremented by “1” (case with WD_CNT_refresh_1:0 configured at 6).

Whatever the position is in the watchdog refresh counter, each time there is a wrong refresh watchdog, the watchdog refresh counter is

reset to “0”. To allow flexibility in the application, the maximum value of this watchdog refresh counter is configurable in the INIT_WD

register, but only when device is in INIT FS mode.

Watchdog Refresh Counter

WD_CNT_refresh = 2

Watchdog Refresh Counter

WD_CNT_refresh = 1

Watchdog Refresh Counter

WD_CNT_refresh = 6

Watchdog Refresh Counter

WD_CNT_refresh = 4

WD Refresh NOK

0

WD Refresh OK

1

WD Refresh NOK /

WD_OFF

WD Refresh NOK /

WD_OFF

WD Refresh NOK /

WD_OFF

WD Refresh OK /

WD Refresh NOK /

WD_OFF

WD Refresh OK

2

WD Refresh NOK /

WD Refresh OK /

WD_OFF

WD Refresh NOK /

WD_OFF

WD Refresh OK

3

WD Refresh NOK /

WD_OFF

WD Refresh OK

4

WD Refresh NOK /

WD_OFF

WD Refresh OK /

WD Refresh NOK /

WD_OFF

WD Refresh OK

5

WD Refresh NOK /

WD_OFF

WD Refresh OK

6

WD Refresh OK /

WD Refresh NOK /

WD_OFF

Figure 18. Watchdog refresh counter configuration (INIT_WD register, WD_CNT_refresh_1:0)

Table 10. Watchdog error table

Window

CLOSED

WD_NOK

No_issue

OPEN

BAD Key

WD_NOK

WD_OK

WD_NOK

SPI

GOOD Key

None (time out)

Any access to the watchdog register during the “closed” watchdog window is considered as a wrong watchdog refresh. Watchdog timeout,

meaning no WD refresh during closed or open windows, is considered as a wrong WD refresh.

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6.5.3 Reset error counter

The reset error counter manages the reset events and counts the number of resets occurring in the application. This counter is

incremented not only for the reset linked to consecutive wrong refresh watchdogs, but also for other sources of reset (undervoltage,

overvoltage, external reset). The RST error counter is incremented by 1, each time a reset is generated.

The reset error counter has two output values (intermediate and final). The intermediate output value is used to handle the transition from

reset (RSTB is asserted low) to reset and fail where RSTB and FS0B are activated. The final value is used to handle the transition from

reset and fail to deep reset and fail (Deep Fail-safe mode), where regulators are off, RSTB and FS0B are activated, and a power on reset

or a transition on IO_0 is needed to recover. The intermediate value of the reset error counter is configurable to “1” or “3” using the

RSTB_err_FS bit in the INIT FSSM2 register (Table 71).

If RSTB_err_FS is set to “0”, it means the device activates FS0B when the reset error counter reaches level “3”.

If RSTB_err_FS is set to “1”, it means the device activates FS0B when the reset error counter reaches level “1”.

This configuration must be done during INIT FS phase.

The final value of the reset error counter is based on the intermediate configuration.

• RSTB_err_FS = 0 / Intermediate = 3; Final = 6 (Figure 19). When reset error counter reaches 6, the device goes into deep reset and

fails.

• RSTB_err_FS = 1 / Intermediate = 1; Final = 2 (Figure 20). When reset error counter reaches 2, the device goes into deep reset and

fails.

In any condition, if the RSTB is asserted LOW for a duration longer than eight seconds, the device goes into deep reset and fails.

Conditions that leads to an increment of the RSTB error counter, and according to the product configuration are:

• Watchdog error counter = 6

• Watchdog refresh NOK during INIT phase or Watchdog timeout

• IO_23 error detection (FCCU)

• Undervoltage

• Overvoltage

• IO_1 FB_Core Delta

• FS0B shorted to VDD

• SPI DED

• Reset request by the SPI

• External reset

Conditions leading to a transition go to FS, according to the product configuration are:

• IO_01/IO_23/IO_45 error detection

• Undervoltage

• Overvoltage

• IO_1 FB_Core Delta

• Analog BIST fail

• SPI DED

• RSTB shorted to high

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Reset Error Counter

(Cfg SPI RSTb_err_FS=0; WD_CNT_refresh=6)

7 consecutive WD Refresh OK

(7 = WD_CNT_refresh + 1)

gotoFS

POR or from

LPOFF mode

0

INCR

7 consecutive WD Refresh OK

1

2

3

4

5

6

INCR = WD error counter = WD_CNT_error[1:0] |

WD refresh NOK during INIT |

IO23_ERR |UV/OV |

IO_1 FB_Core delta |

FS0b_shorttovdd |

INCR

gotoFS

7 consecutive WD Refresh OK

SPI DED |

Reset by SPI |

External reset

Active FS0

gotoFS = IO01/23/45_ERR |

UV/OV|

INCR

7 consecutive WD Refresh OK

IO_1 FB_Core delta |

ABIST_fail |

Active FS0

SPI DED |

RSTb_short2hi

INCR

Active FS0

Turn OFF regulators

RSTb asserted for 8

seconds

Figure 19. RSTB error counter (RSTB_err_FS = 0)

Reset Error Counter

(Cfg SPI RSTb_err_FS=1; WD_CNT_refresh=6)

INCR = WD error counter = WD_CNT_error[1:0] |

7 consecutive WD Refresh OK

(7 = WD_CNT_refresh + 1)

WD refresh NOK during INIT |

IO23_ERR |UV/OV |

IO_1 FB_Core delta |

FS0b_shorttovdd |

SPI DED |

0

1

2

POR or from

LPOFF mode

INCR/gotoFS

7 consecutive WD Refresh OK

Reset by SPI |

External reset

Active FS0

INCR

gotoFS = IO01/23/45_ERR |

UV/OV |

Active FS0

Turn OFF regulators

IO_1 FB_Core delta |

ABIST_fail |

RSTb asserted for 8

seconds

SPI DED |

RSTb_short2hi

Figure 20. RSTB error counter(RSTb_err_FS = 1)

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6.5.3.1

RST error counter at start-up or resuming from LPOFF mode

At start-up or when resuming from LPOFF mode the reset error counter starts at level 1 and FS0B is asserted low. To remove activation

of FS0B, the RST error counter must go back to value “0” (seven consecutive good watchdog refresh decreases the reset error counter

down to 0) and a right command is sent to FS_OUT register (Figure 23).

1st WD refresh OK after

INIT phase. Start of the

WD window

New fully OPEN window of

256 ms

WD window

OK

NOK

OK

NOK

WD error

counter

6

4

3

0

2

5

Reset error

counter

1

RSTb

RSTB

delay time

WD Refresh

counter

0

1

0

1

0

Figure 21. Example of WD operation generating a reset (WD_error_cnt = 6)

New fully OPEN window of

256 ms

WD window

OK

NOK

4

OK

WD error

counter

0

6

Reset error

counter

1

2

1

RSTb

delay time

1

3

2

5

6

0

1

WD Refresh

counter

0

4

Figure 22. Example of WD operation leading a decrement of the reset error counter (WD_resfresh_cnt = 6)

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# WD refresh counter max value +1

consecutive WD answers OK

# WD refresh counter max value +1

consecutive WD answers OK

WD error counter

= 6

WD error counter

= 6

FS_OUT

write OK

WD error counter

= 6

FS_OUT

write OK

Reset error counter

RST_ERR_CNT

1

0

1

2

3

2

1

0

Reset delay

RSTb

FS0b

Output stage ON

OFF

ON

OFF

Figure 23. Reset error counter and FS0B deactivation sequence (RSTB_err_FS = 0 & WD_CNT_error1:0 = 6)

6.5.4 Fail-safe output (FS0B) deactivation

When the fail-safe output FS0B is asserted low by the device due to a fault, some conditions must be validated before allowing the FS0B

pin to be deactivated by the device. These conditions are:

• Fault is removed

• Reset error counter must be at “0”

• FS_OUT register must be filled with the right value.

6.5.4.1

Faults triggering FS0B activation

The activation of the FS0B is clearly dependent on the product configuration, but the following items can be settled:

• IO_01/IO_23/IO_45 error detection

• Undervoltage

• Overvoltage

• IO_1 FB_Core Delta

• Analog BIST fail (not configurable)

• SPI DED (not configurable)

• RSTB shorted to high (not configurable)

• RSTB error counter level

6.5.5 SPI DED

Some SPI registers affect some safety critical aspects of the fail-safe functions, and thus are required to be protected against SEU (Single

Event Upset). Only fail-safe registers are concerned. During INIT FS mode, access to fail-safe registers for product configuration is open.

Then once the INIT FS phase is over, the Hamming circuitry is activated to protect registers content.

At this stage, if there is 1 single bit flip, the detection is made due to hamming code, and the error is corrected automatically (fully

transparent for the user), and a flag is sent. If there are two errors (DED - Dual Error Detection), the detection is made due to hamming

code but detected errors cannot be corrected. Flag is sent, RSTB and FS0B are activated.

6.5.6 FS_OUT register

When fault is removed and reset error counter changes back to level “0”, a right word must be filled in the FS_OUT register. The value is

dependant on the current WD_LFSR. LSB and MSB must be swapped and negative operation per bit must be applied.

WD_LFSR_7:0=

FS_OUT_7:0 =

b7

b0

b6

b1

b5

b2

b4

b3

b4

b2

b5

b1

b6

b0

b7

Figure 24. FS_OUT register based on LFSR value

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6.6

Input voltage range

Due to the flexibility of the pre-regulator, the device can cover a wide battery input voltage range. However, a more standard voltage range

can still be covered using only the Buck configuration.

V_SUP

Buck only

Buck-Boost

No operation

Risk of damage

40 V

Extended voltage range

Potential Vpre thermal limitation

28 V

19 V

Extended voltage range

Amux limitation

Extended voltage range

Amux limitation

Normal voltage range

V_{SUP_UV_7}

Extended voltage range

Vpre output current limitation

6.0 V

2.7 V

Extended voltage range

V_PREoutput current limitation

4.6 V

No operation

Figure 25. Input voltage range

> 28 V: Potential VPRE thermal limitation

• V

SUP

R

, Current limitation and Overcurrent detection are specified for V

< 28 V.

SUP

DS(on)

• V

< 19 V: Mux_out limitation

SUP

IO_0 and IO_1 maximum analog input voltage range is 19 V. Internal 2.5 V reference voltage accuracy degraded.

• Buck only, V < V

:

SUP_UV_7

SUP

CAN communication is guaranteed for V

> 6.0 V. LIN communication according to SAEJ2602-2 specification is stopped

SUP

(V

< 7.0 V). For V

and V

5.0 V configuration, undervoltage triggers at low V

(refer to V

and V

).

SUP

CCA

AUX

SUP

CCA_UV_5

AUX_UV_5

6.7

Power management operation

A thermal sensor is implemented as close as possible to the pass transistor of each regulator (VPRE, VCORE, VCCA, VCAN) and an

associated individual Thermal Shutdown (TSD) protect these regulators independently. When the TSD threshold of a specific regulator is

reached, this regulator only is switched OFF and the information is reported in the main state machine. The regulator restarts automatically

when the junction temperature of the pass transistor decrease below the TSD threshold.

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6.7.1 VPRE voltage pre-regulator

A highly flexible SMPS pre-regulator is implemented in the 33907/33908. Depending on the input voltage requirement, the device can be

configured as “non-inverting buck-boost converter” (Figure 27) or “standard buck converter” (Figure 26). An external logic level MOSFET

(N-type) is required to operate in “non-inverting buck-boost converter”. The connection of the external MOSFET is detected automatically

during the start-up phase.

The converter operates in Current Control mode in any configuration. The high-side switching MOSFET is integrated to make the current

control easier. The PWM frequency is fixed at 440 kHz typical. The compensation network is fully integrated. VPRE output voltage is

regulated between 6.0 V and 7.0 V.

If the full current capability is not used for VCORE, VCCA, VAUX and CAN_5V, additional external LDO can be connected to VPRE to

fulfill application needs while the current load remains below the maximum current capability in all conditions.

L_V_PRE

ESR cap.

<100 mΩ

<10 mΩ

PGND PGND

PGND

Figure 26. Pre-regulator: buck configuration

L_Vpre

ESR cap.

<100 mΩ

ESR cap.

<10 mΩ

D_BB

PGND PGND

PGND

Optional

PGND

Figure 27. Pre-regulator: buck boost configuration

When the converter is set up to work in boost mode at low V

, the transition between buck and boost mode is automatically handled

SUP

by the device at V

threshold. Transition between buck mode and boost mode is based on hysteresis (Figure 28).

SUP_UV_7

• When VSUP > V

• When VSUP < V

, the converter works in buck mode and VPRE output is regulated at 6.5 V typic.

, the converter works in boost mode and VPRE output is regulated at 6.3 V typic.

SUP_UV_7

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D (%)

100

D buck

D boost

V_PRE(V)

6.5

66

50

33

25

0

7.5

12

18

24

V_IN(V)

Figure 28. Transition between buck and boost

6.7.1.1

Power up and power down sequence

V_{SNS_UV}

V_{SUP_UV_5}

V_{SUP_UV_L_B}

Vbattery

0V

Vsup

Boost

Buck_Boost Mask

Boost

Buck

Vpre_EN

Vpre

Vcore

V_{CORE_FB_UV * ((R3+R4)/R4)}

INTB

(Vddio=Vcore)

RSTB

RST delay time

Figure 29. Buck configuration power-up and power-down

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V_{SUP_UV_7}

V_{SUP_UV_5}

V_{SUP_UV_L}

Vbattery

Vsup

0V

Buck_Boost Mask

Boost

Buck

Vpre_EN

Vpre

Vcore

INTB

V_{CORE_FB_UV * ((R3+R4)/R4)}

(Vddio=Vcore)

RSTB

RST delay time

Figure 30. Buck boost configuration power-up and power-down

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6.7.1.2

Cranking management

When VPRE is set up to work in buck only mode, the application can work down to VSUP = V

= 4.6V with a minimum of 500 mA

SUP_UV_L_B

current guaranteed on VPRE.

.

V_SENSE

V_SUP

V_{SNS_UV}

V_{SUP_UV_L_B}

Buck_Boost

Mask

Buck

V_{PRE_EN}

V_PRE

V_CORE

INTB

V_{CORE_FB_UV * ((R3+R4)/R4)}

RSTB

Figure 31. Behavior during cranking (buck configuration)

When VPRE is set up to work in boost mode, the application can work down to VSUP = V

= 2.7V with a minimum of 300 mA

SUP_UV_L

current guaranteed on VPRE. The boost mode configuration help to pass LV124 specification requiring a minimum of 3.2 V on V

during cold cranking conditions.

supply

BAT

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V_SUP

V_{SUP_UV_7}

V_{SUP_UV_L}

Buck_Boost

Mask

Buck

Boost

V_{PRE_EN}

V_PRE

V_CORE

INTB

V_{CORE_FB_UV * ((R3+R4)/R4)}

RSTB

Figure 32. Behavior during cranking (buck boost configuration)

6.7.1.3

Light load condition

In order to improve the converter efficiency and avoid any unwanted output voltage increase, VPRE voltage regulator operates in Pulse

Skipping mode during light load condition.

The transition between Normal mode and Pulse Skipping mode is based on the comparison between the error amplifier output (EA_out)

and pre-defined thresholds V

and V

. When the Error Amplifier output reaches V

, VPRE high-side transistor is

PRE_LL_H

PRE_LL_L

switched OFF. When the Error Amplifier output reaches V

period (Figure 33).

, VPRE high-side transistor is switched ON again for the next switching

PRE_LL_H

VPR E

VSUP1/2

EA_out

Vpre_LL_H

Vpre_LL_L

EA_ out

Error Amplifier

Li gh t L oa d

VPRE HS

Driver

Comparat or

(H y st 2 0m V )

Light Load

flag

HS Gate

drive

Ref

Vp re_L L_L

GND

SW_PRE

Figure 33. Description of light load condition

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6.7.1.4

Input power feed forward condition

In order to improve the converter efficiency during high input power condition, VPRE switching frequency is reduced from 440 kHz to

220 kHz when VSUP > V and I > I to decrease the switching losses. The transition between the two frequencies

SUP_IPFF

PRE

PRE_IPFF_PK

is transparent for the application.

VSUP_IPFF

V_SUP

Ipk envelop

IPFF

V_{PRE_FSW}

440 kHz

Figure 34. Input power feed forward principle

440 kHz

220 KHz

6.7.1.5

Overcurrent detection and current limitation

Overcurrent protection:

6.7.1.5.1

In order to ensure the integrity of the high-side MOSFET, an overcurrent detection is implemented. The regulator is switched OFF by the

Main State machine when the over-current detection threshold I is reached three consecutive times. The overcurrent detection is

PRE_OC

blanked when the pass transistor is switched ON during T

to avoid parasitic switch OFF of the high-side gate driver.

PRE_OC

The VPRE output voltage decrease causes an undervoltage condition on one of the cascaded regulators (VCORE, VCCA, VAUX) and

bring the device in Fail-safe state. The overcurrent protects the regulator in case of SW_PRE pin shorted to GND. The overcurrent works

in Buck mode only.

6.7.1.5.2

Current limitation:

A current limitation is also implemented to avoid uncontrolled power dissipation inside the device (duty cycle control) and limits the current

below I . The current limitation is blanked when the pass transistor is switched ON during T to allow short-circuit

PRE_LIM

PRE_BLK_LIM

detection on SW_PRE pin.

When I threshold is reached during Buck mode, the high-side integrated MOSFET is switched OFF. When I

threshold is

PRE_LIM

reached during Boost mode, the external low-side MOSFET is switched OFF. In both cases, the MOSFET is not switched ON again before

the next rising edge of the switching clock.

The current limitation will induce a duty cycle reduction and will lead to VPRE output voltage to fall down gradually and may cause an

undervoltage condition on one of the cascaded regulators (VCORE, VCCA, VAUX) and bring the device in Fail-safe state. The current

limitation does not switch OFF the regulator. The current limitation protects the regulator when VPRE pin is shorted to GND.

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IPRE_OC

IPRE_LIM

IPRE_SW

SW_PRE

VPRE

TPRE_OC

TPRE_BLK_ILIM

Figure 35. Overcurrent and current limitation scheme

6.7.1.6

VPRE voltage monitoring

The overvoltage detection switches OFF the regulator. The undervoltage detector is disabled when the regulator is switched OFF

reporting an undervoltage. Diagnostic is reported in the dedicated register and generate an Interrupt.

The undervoltage detection does not switches OFF the regulator. However, V

decrease may induce an undervoltage on a regulator

PRE

attached to V

(VCORE, VCCA, VAUX, or CAN_5V), and bring the application in Fail-safe state depending on the supervisor

PRE

configuration (registers INIT SUPERVISOR 1,2,3).

6.7.1.7

VPRE efficiency

VPRE efficiency versus current load is given for information based on typical external component criteria described in the table close to

the graph and at three different V voltages (8.0 V, 14 V, and 18 V) covering typical automotive operating range. The efficiency is valid

SUP

in buck mode only and above 200 mA load on VPRE in order to be in continuous mode in the 22 µH inductor. The efficiency is calculated

and has to be verified by measurement at application level.

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Figure 36. V

efficiency

PRE

6.7.2 VCORE voltage regulator

This voltage regulator is a step-down DC-DC converter operating in Voltage Control mode. The high side switching MOSFET is integrated

in the device and the PWM frequency is fixed at 2.4 MHz typical. The output voltage is configurable from 1.2 V to 3.3 V range and

adjustable around these voltages with an external resistor divider (R3/R4) connected between V

(Figure 37).

and the feedback pin (FB_CORE)

CORE

VCORE = V

x ((R3 + R4) / R4)

CORE_FB

The voltage accuracy is 2.0% (without the external resistor bridge R3/R4 accuracy) and the max output current is 1.5 A. The stability of

the overall converter is done by an external compensation network (R1/C1/R2/C2) connected to the pin COMP_CORE. It is recommended

to use 1% accuracy resistors and set R4 = 8.06 kΩ and adjust R3 to obtain the final VCORE voltage needed for the MCU core supply.

L_Vcore

ESR cap.

<100mΩ

C1

PGND

R3

GND

PGND

R1

PGND

VCORE_SNS

FB_CORE

R4

GND

COMP_CORE

Figure 37. VCORE buck regulator

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6.7.2.1

Light load condition

In order to improve the converter efficiency and avoid any unwanted output voltage increase, VCORE voltage regulator operates in Pulse

Skipping mode during light load condition. The principle is the same as the VPRE implementation described in details in Light load

condition.

6.7.2.2

Current limitation

A current limitation is implemented to avoid uncontrolled power dissipation inside the device (duty cycle control) and limits the current

below I . The current limitation is banked when the pass transistor is switched ON during T to avoid parasite

CORE_LIM

CORE_BLK_LIM

detection. When I

threshold is reached, the high-side integrated MOSFET is switched OFF. The MOSFET is not switched ON

CORE_LIM

again before the next rising edge of the switching clock.

The current limitation will induce a duty cycle reduction and will lead to VCORE output voltage to fall down gradually and may cause an

undervoltage condition and bring the device in Fail-safe state. The current limitation does not switch OFF the regulator.

6.7.2.3

Voltage monitoring

The overvoltage detection switches OFF the regulator. The regulator remains ON in case of undervoltage detection. Diagnostic is reported

in the dedicated register, generate an Interrupt and may bring the application in Fail-safe state depending on the supervisor configuration

(registers INIT SUPERVISOR 1,2, 3).

6.7.2.4

VCORE efficiency

Vcore efficiency versus current load is given for information based on typical external component criteria described in the table close to

the graph and at two different VCORE voltages (3.3 V, and 1.2 V) covering most of the 32-bit MCU supply range. The efficiency is valid

above 200 mA load on V

in order to be in continuous mode in the 2.2 µH inductor. The efficiency is calculated and has to be verified

CORE

by measurement at application level. One of the major contributor degrading the efficiency at V

= 1.2 V is the external diode during

CORE

the recirculation phase. Lower the diode Forward Voltage (V ) is, the better the efficiency.

F

Figure 38. V

efficiency

CORE

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6.7.3 Charge pump and bootstrap

Both switching MOSFETs of VPRE and VCORE SMPS are driven by external bootstrap capacitors. Additionally, a charge pump is

implemented to ensure 100% duty cycle for both converters. Each converter uses a 100 nF external capacitor minimum to operate

properly.

6.7.4 VCCA voltage regulator

VCCA is a linear voltage regulator mainly dedicated to supply the MCU I/Os, especially the ADC. The output voltage is selectable at 5.0 V

or 3.3 V. Since this output voltage can be used to supply MCU I/Os, the output voltage selection is done using an external resistor

connected to the SELECT pin and ground if VAUX is used. When VAUX is not used, the resistor is connected between the SELECT pin

and VPRE.

When VCCA is used with the internal MOS transistor, VCCA_E pin must be connected to VPRE. The voltage accuracy is 1.0% for 5.0 V

configuration and 1.5% for 3.3 V configuration with an output current capability at 100 mA.

When VCCA is used with an external PNP transistor to boost the current capability up to 300 mA, the connection is detected automatically

during the start-up sequence of the 33907/33908. In such condition, the internal pass transistor is switched OFF and all the current is

driven through the external PNP to reduce the internal power dissipation. The output voltage accuracy with an external PNP is reduced

to 3.0% at 300 mA current load. The VCCA output voltage is used as a reference for the Auxiliary voltage supply (VAUX) when VAUX

is configured as a tracking regulator.

6.7.4.1

Current limitation

A current limitation is implemented to avoid uncontrolled power dissipation of the internal MOSFET or external PNP transistor. By default,

the current limitation threshold is selected based on the auto detection of the external PNP during start up phase.

• When the internal MOSFET transistor is used, the current is limited to I

and the regulator is kept ON

CCA_LIM_INT

• When the external PNP transistor is used, the current is limited to I

and the regulator is switch OFF after a dedicated

CCA_LIM_OUT

duration T

under current limitation. A SPI command is needed to restart the regulator.

CCA_LIM_OFF

In case of external PNP configuration only, the lowest current limitation threshold can be selected by SPI in the register INIT VREG 2

instead of the highest one. In order to limit the power dissipation in the external PNP transistor in case of short circuit to GND of VCCA

pin, a current limitation foldback scheme is implemented to reduce the current limitation to I

when V

is below V

.

CCA_LIM_FB

CCA

CCA_LIM_FB

6.7.4.2

Voltage monitoring

The overvoltage detection switches OFF the regulator. The regulator remains ON in case of undervoltage detection. Diagnostic is reported

in the dedicated register, generate an Interrupt and may bring the application in Fail-safe state depending on the supervisor configuration

(registers INIT SUPERVISOR 1, 2, 3).

6.7.5 VAUX voltage regulator

VAUX is a highly flexible linear voltage regulator that can be used either as an auxiliary supply dedicated to additional device in the ECU

or as a sensor supply (i.e. outside the ECU). An external PNP transistor must be used (no internal current capability). If VAUX is not used

in the application, VAUX_E and SELECT pins must be connected to VPRE in order to not populate the external PNP as described in

Figure 60.

If VAUX is used as an auxiliary supply, the output voltage is selectable between 5.0 V, 3.3 V. Since this voltage rail can be used to supply

MCU IOs, the selection is done with an external resistor connected between the SELECT pin and ground. In such case, the voltage

accuracy is 3.0% with a maximum output current capability at 300 mA. If VAUX is used as a sensor supply rail, the output voltage is

selectable between 5.0 V and 3.3 V. VCCA can be used as reference for the sensor supply used as tracker. The selection is done during

the INIT phase and secured (bit V

in the register INIT VREG2). The tracking accuracy is 15 mV.

AUX_TRK_EN

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NXP Semiconductors

L3 - 2.2 µH

Vcore

VDD_LV_1.2V

C7

40µF

D4

C10

R1

C6

100nF

R3

PGND

Boot_core

Vcore_sns

SW2

FB1

MCU

R4

Vcore

Buck – 1.5A

GND

Comp1

R2

C11

Vcca_E

Vcca_B

V_Peripherals & I/O

VCCA - LDO1

100/300mA

Vcca 5V

V_ADC_5V

ADC_IN

C8

4.7 µF

Int 3.3/

5V ref

GND

Input ref

Vaux_E

Vaux_B

PNP2

VAUX - LDO2

Vaux 5V

300mA

C9

4.7 µF

Ext

Sensor

GND

33907/33908

ECU

limit

Figure 39. Example of V

used in tracker mode

AUX

6.7.5.1

Current limitation

A current limitation is implemented to avoid uncontrolled power dissipation of the external PNP transistor. The current is limited to I

AUX_LIM

and the regulator is switch OFF after a dedicated duration T

under current limitation. A SPI command is needed to restart the

AUX_LIM_OFF

regulator. In order to limit the power dissipation in the external PNP transistor in case of short-circuit to GND of VAUX pin, a current

limitation foldback scheme is implemented to reduce the current limitation to I

when V

is below V

.

AUX_LIM_FB

AUX

AUX_LIM_FB

VAUX

Vaux

(3.3Vor

5V)

Vaux_LIM_FB

IAUX

Iaux_LIM_FB

Iaux_LIM

Figure 40. V

current limitation scheme with foldback mechanism

AUX

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6.7.5.2

Voltage monitoring

The overvoltage detection switches OFF the regulator. The regulator remains ON in case of undervoltage detection. Diagnostic is reported

in the dedicated register, generate an Interrupt and may bring the application in Fail-safe state depending on the supervisor configuration

(registers INIT SUPERVISOR 1, 2, 3).

6.7.6 CAN_5V voltage regulator

The CAN_5V voltage regulator is a linear regulator fully dedicated to the internal HSCAN interface. By default, the CAN_5V regulator and

the undervoltage detector are enabled, the overvoltage detector is disabled. The overvoltage detector can be enabled by SPI during

INIT_MAIN sate.

If the overvoltage detector is enabled, the CAN_5V regulator switches OFF when an overvoltage is detected. The undervoltage detector

is disabled when the regulator is switched OFF reporting an undervoltage. Diagnostic is reported in the dedicated register and generate

an Interrupt. The CAN_5V regulator is not safety regulator. Consequently, the CAN_5V voltage monitoring (overvoltage, undervoltage)

will never assert RSTB or FS0B Fail-safe pins.

If the 33907/33908 internal CAN transceiver is not used in the application, the CAN_5V regulator can be used to supply an external

standalone CAN or FLEX-RAY transceiver, providing that the current load remains below the maximum current capability in all conditions.

In that case, the internal CAN transceiver must be put in Sleep mode without wake-up capability.

6.7.7 Power dissipation

The 33907/33908 provides high performance SMPS and Linear regulators to supply high end MCU in automotive applications. Each

regulator can deliver:

• V

(6. 5V) up to 2.0 A

PRE

(from 1.2 V to 3.3 V range) up to 0.8 A (33907) or up to 1.5 A (33908)

CORE

(3.3 V or 5.0 V) up to 100 mA (with internal MOS) or up to 300 mA (with external PNP)

(3.3 V or 5.0 V) up to 300 mA (with external PNP)

(5.0 V) up to 100 mA

CCA

AUX

CAN

A thermal dissipation analysis has to be performed based on application use case to ensure the maximum silicon junction temperature

does not exceed 150 °C.

Two use cases covering the two main V

voltage configurations are provided in Figure 41.

CORE

• use case 1: V

• use case 2: V

= 3.3 V, I

= 1.2 V, I

= 0.7 A, V

= 1.4 A, V

with int. MOS

with ext. PNP

CORE

CCA

Both use cases have a total internal power dissipation below 0.9 W. A junction to ambient thermal resistivity of 30 °C/W allows the

application to work up to 125 °C ambient temperature. A good soldering of the package expose pad is highly recommended to achieve

such thermal performance.

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Vsup = 14V and 25% of CAN traffic

Main contributors to the IC's Power dissipation

Vcca

21%

Vcore

51%

Vcore

33%

Vpre

28%

Vpre

25%

Vcca

2%

Vaux

5%

Vaux

5%

CAN transceiver

8%

CAN transceiver

7%

Internal IC

8%

Internal IC

7%

0.765 W

0.829 W

TOTAL PDIS

use case 1: Vcore=3.3V, Icore=0.7A, Vcca with int. MOS

1) CAN transceiver dissipation includes CAN_5V regulator dissipation.

=

TOTAL PDIS

=

use case 2: Vcore=1.2V, Icore=1.4A, Vcca with ext. PNP

2) 25% CAN traffic means the CAN bus is dominant for 25% of time and recessive for the remaining 75%.

Figure 41. Power dissipation use case

The main contributors to the device power dissipation are VPRE, VCORE, and VCCA (when used with internal PMOS) regulators. In

comparison, the power dissipation from the Internal IC, VAUX and CAN transceiver are negligible. VPRE power dissipation is mainly

induced by the loading of the regulators it is supplying, mainly VCORE, VCCA and VAUX which are application dependant. The total

device power dissipation, depending on the variation of these three regulators, is detailed in Figure 42 with the environmental conditions

in the associated table.

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59

Pdis VS Icore

Pdis VS Icca

Pdis VS Ipre

6.5V

Vpre

Ipre

Icore + Icca

+ Iaux + Ican

3.3V and 1.2V

Icore + Icca

+ Iaux + Ican

3.3V

From 0.5 to 2A

3.3V

0.3A

Vcore

Icore

Vcca

from 0.25 to 1.5A

3.3V

0.7A

3.3V and 5V

20 to 100mA

3.3V

50mA

3.3V

Icca

3.3V

Vaux

Iaux

200mA

5V

200mA

5V

200mA

5V

CAN_5V

Ican

33mA

Figure 42. Power dissipation versus I

, I

, or I

CORE CCA PRE

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6.7.8 Start-up sequence

In order to provide a safe and well known start-up sequence, the 33907/33908 includes an undervoltage lock-out. This undervoltage lock-

out is only applicable when the device is under a Power-On-Reset condition, which means the initial condition is VSUP < V

(i.e.

SUP_UV_L

below 2.7 V max). In all the other conditions (i.e. LPOFF), the device is able to operate (and therefore to restart) down to V

other different voltage rails automatically start, as described in Figure 43.

. The

SUP_UV_L

Vsup_uv_5

Vsup

Vint_2.5

LBIST

120us

Vpre_EN

Vpre_uv

Vpre

Vcca/Vaux

Vcore

INTB

(Vddio=Vcore)

1ms

Select pin

RSTB

UV Lock-out

~16ms

Figure 43. Start-up scheme

The final value of VAUX and VCCA depends on the hardware configuration (resistor values on the SELECT pin). The typical start up

sequence takes around 16 ms to release RSTB. RSTB can be pulled low after those 16 ms by the MCU, if it is not ready to run after power

up.

If an internal or external fault happen during this start up phase (ABIST fault due to regulator shorted for example), the 8.0 s timer

monitoring the RSTB pin low, will finally send the device in Deep Fail-safe mode after 8.0 s.

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6.8

CAN transceiver

The high speed CAN (Controller Area Network) transceiver provides the physical interface between the CAN protocol controller of an MCU

and the physical dual wires CAN bus. It offers excellent EMC and ESD performance and meets the ISO 11898-2 and ISO11898-5

standards.

CAN_5V

V_DDIO

Bus Biasing

2.5V

CAN_5V Monitor

Pre

Driver

Dominant

time out

Input

TXD

RXD

CAN H

CAN L

Rin

V_DDIO

CAN_5V

Mode

Pre

Driver

Buffer

and

Control

V_DDIO

Main

Logic

Over

Temperature

Differential

Receiver

V_SUP3

Wake-up

Receiver

WU report

to main loic

Figure 44. CAN simplified block diagram

6.8.1 Operating modes

6.8.1.1

Normal mode

When CAN mode bits configuration is “11” (CAN in normal operation), the device is able to transmit information from TXD to the bus and

report the bus level to the RXD pin. When TXD is high, CANH and CANL drivers are off and the bus is in the recessive state (unless it is

in an application where another device drives the bus to the dominant state). When TXD is low, CANH and CANL drivers are ON and the

bus is in the dominant state. When CAN mode bits configuration is “01” (CAN in listen only), the device is only able to report the bus level

to the RXD pin. TXD driver is OFF and the device is NOT able to transmit information from TXD to the bus. TXD is maintained high by

internal pull up resistor TXD

connected to VDDIO.

PULL-UP

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high

TXD

low

CANH

CANL

dominant

0.9V

Vdiff

(CANH - CANL)

0.5V

recessive

high

0.7V_DDIO

RXD

0.3V_DDIO

low

Tloop (R-D)

Tloop (D-R)

Figure 45. CAN timing diagram

6.8.1.2

Sleep mode

When the device is in LPOFF mode, the CAN transceiver is automatically set in Sleep mode with or without wake-up capability depending

on CAN mode bits configuration. In that case, the CANH and CANL pins are pulled down to GND via the internal RIN resistor, the TXD

and RXD pins are pulled down to GND, both driver and receiver are OFF.

The CAN mode is automatically changed to Sleep with wake-up capability if not configured to Sleep without wake-up capability when the

device enters is LPOFF. After LPOFF, the initial CAN mode prior to enter LPOFF is restored (Figure 46).

CAN state before entering LPOFF

CAN state in LPOFF

CAN state

CAN state after LPOFF

CAN_mode

CAN state

[1:0]

0

[1:0]

0

Sleep, no wake-up capability

Listen Only

0

Sleep, no wake-up capability

Listen Only

1

10

11

Sleep, wake-up capability

Normal

10

Sleep, wake-up capability

10

11

Sleep, wake-up capability

Normal

Figure 46. CAN transition when device goes to LPOFF

6.8.2 Fault detection

6.8.2.1

TXD permanent dominant (timeout)

If TXD is set low for a time longer than T

parameter, the CAN drivers are disabled, and the CAN bus will return to recessive state.

DOUT

The CAN receiver continues to operate. This prevent the bus to be set in dominant state permanently in case a failure set the TXD input

to low level permanently.

The CAN_mode MSB bit is set to 0 and the flag TXD_dominant is reported in the Diag CAN1 register. The device recovers from this error

detection after setting the CAN_mode to Normal Operation and when a high level is detected on TXD. The TXD failure detection is

operating when the CAN transceiver is in Normal mode and Listen only mode.

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recovery condition: TXD high

high

TXD

BUS

low

recessive

dominant

T_DOUT

TXD dom time out expired

high

RXD

low

Figure 47. TXD Dominant Timeout Detection

6.8.2.2

RXD permanent recessive

If RXD is detected high for seven consecutive receive/dominant cycles, the CAN drivers and receiver are disabled, and the CAN bus will

return to recessive state. This prevent a CAN protocol controller to start CAN message on TXD pin, while RXD is shorted to a recessive

level, and seen from a CAN controller as a bus idle state.

The CAN_mode MSB bit is set to 0 and the flag RXD_recessive is reported in the Diag CAN1 register. The device recovers from this error

detection after setting the CAN_mode to Normal Operation. The RXD failure detection is operating when the CAN transceiver is in Normal

mode and Listen only mode.

6.8.2.3

CAN bus short-circuits

CANL short to GND and CANL short to Battery are detected and reported to the device main logic. The CAN driver and receiver are not

be disabled. CANH short to GND and CANH short to Battery are detected and reported to the device main logic. The CAN driver and

receiver are not be disabled. The CANH and CANL failure detection is operating when the CAN transceiver is in Normal mode.

If the CAN bus is dominant for a time longer than T

, due for instance to an external short-circuit from another CAN node, the flag

DOM

CAN_dominant is reported in the Diag CAN1 register. This failure does not disable the bus driver. The CAN bus dominant failure detection

is operating when the CAN transceiver is in Normal mode and Listen Only mode.

6.8.2.4

CAN current limitation

The current flowing in and out of the CANH and CANL driver is limited to 100 mA, in case of short-circuit (parameters I

and

CANL-SK

I

).

CANH-SC

6.8.2.5

CAN overtemperature

If the driver temperature exceeds the TSD (T ), the CAN drivers are disabled, and the CAN bus will return to recessive state. The CAN

OT

receiver continues to operate. The CAN_mode MSB bit is set to 0 and the flag CAN_OT is reported in the Diag CAN_LIN register.

An hysteresis is implemented in this protection feature. The device overtemperature and recovery conditions are shown in Figure 48. The

CAN drivers remain disabled until the temperature has fallen below the OT threshold minus hysteresis. The device will recover from this

error detection after setting the CAN_mode to Normal Operation and when a high level is detected on TXD.

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Overtemperature Threshold

Hysteresis

Event 3

Hysteresis

Temperature

Event 1

Event 2

Event 4

Event 3

low

high

TXD

recessive

dominant

BUS

Event 1: over temperature detection. CAN driver disable.

Event 2: temperature falls below “overtemp. threshold minus hysteresis” => CAN driver remains disable.

Event 3: temperature below “overtemp. threshold minus hysteresis” and TxD high to low transition => CAN driver enable.

Event 4: temperature above “overtemp. threshold minus hysteresis” and TxD high to low transition => CAN driver remains disable.

Figure 48. Overtemperature behavior

6.8.2.6

Distinguish CAN diagnostics and CAN errors

The CAN errors can generate an interruption while the CAN diagnostics are reported in the digital for information only. The interruption

generated by the CAN errors can be inhibited setting INT_inh_CAN bit at “1” in the “INIT INT” register.

The list of CAN Diagnostic and CAN Error bits is provided in Table 11.

Table 11. CAN diagnostic and CAN error bits

Register

Bit

Flag type

Effect

CANH_batt

CANH_gnd

CANL_batt

Diagnostic

Error

No impact on CAN transceiver

Turn OFF CAN transceiver

No impact on CAN transceiver

DIAG CAN1

CANL_gnd

CAN_dominant

RXD_recessive

TXD_dominant

CAN_OT

Error

DIAG CAN_LIN

CAN_OC

Diagnostic

6.8.3 Wake-up mechanism

The device include bus monitoring circuitry to detect and report bus wake-ups when the device is in LPOFF and CAN mode configuration

is different than Sleep/NO wake-up capability. Two wake-up detection are implemented: single dominant pulse and multiple dominants

pulses. The wake-up mechanism is selected by SPI in the main logic and wake-up events are reported. The event must occur within the

T_3PTOXtimeout. T

= T

or T

depending on the SPI selection.

3PTOX

3PTO1

3PTO2

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6.8.3.1

Single pulse detection

In order to activate wake-up report, 1 event must occur on the CAN bus:

- event 1: a dominant level for a time longer that T_1PWU

Figure 49. Single pulse wake-up pattern illustration

6.8.3.2

Multiple pulse detection

In order to activate wake-up report, three events must occur on the CAN bus:

- event 1: a dominant level for a time longer that t_1PWUfollowed by

- event 2: a recessive level (event 2) longer than t_3PWUfollowed by

- event 3: a dominant level (event 3) longer than t_3PWU

.

The three events and the timeout function avoid that a permanent dominant state on the bus generates permanent wake-up situation

which would prevent system to enter in low-power mode.

Figure 50. Multiple pulse wake-up pattern illustration

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6.9

LIN transceiver

This chapter applies to 33907L and 33908L versions.

The Local Interconnect Network (LIN) is a serial communication protocol, designed to support automotive networks in conjunction with a

Controller Area Network (CAN). The LIN transceiver is operational from a V_SUPof 7.0 V to 18 V DC and compatible with LIN Protocol

Specification 1.3, 2.0, 2.1, 2.2 and SAEJ2602-2.

6.9.1 Simplified block diagram

LIN Wake up

LIN overtemperature

LIN transmitter

and receiver Enabled

in Recessive State

VSUP3

Normal Baud Rate (20kbps)

Slow Baud Rate (10kbps)

Fast Baud Rate (100kbps)

SR_control

V_SUPUndervoltage

TXD Dominant

Sleep_mode

LIN transmitter in

Recessive State

LIN Interface

LIN transmitter in

Recessive State

30 k

725 k

Ω

LIN

LIN Driver

X 1

35µA

TXD

GND

RXD

Receiver

Figure 51. LIN simplified block diagram

6.9.2 Operating modes

6.9.2.1

Normal mode

When LIN mode bits configuration is “11” (LIN in normal operation), the device is able to transmit information from TXDL to the bus and

report the bus level to the RXDL pin. When TXDL is high, LIN driver is OFF and the bus is in the recessive state (unless it is in an

application where another device drives the bus to the dominant state). When TXDL is low, LIN driver is ON and the bus is in the dominant

state.

When LIN mode bits configuration is “01” (LIN in listen only), the device is only able to report the bus level to the RXDL pin. TXDL driver

is OFF and the device is NOT able to transmit information from TXDL to the bus. TXDL is maintained high by internal pull-up resistor

TXDL

connected to VDDIO.

PULL-UP

6.9.2.2

Sleep mode

When the device is in LPOFF mode, the LIN transceiver is automatically set in Sleep mode with or without wake-up capability depending

on LIN mode bits configuration. In that case, the LIN pin is pulled up to V

RXDL pins are pulled down to GND.

via the internal resistor and diode structure, the TXDL and

SUP

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6.9.3 Baud rate selection

The device has two selectable baud rates: 20 kB/s for Normal Baud rate and 10 kB/s for slow baud rate. An additional fast baud rate

(100 kB/s) can be used to flash the MCU or in the garage for diagnostic. The LIN Consortium specification does not specified electrical

parameters for this baud rate. The communication only is guaranteed. The baud rate selection is done by SPI setting during the INIT phase

of the main logic. Depending of the baud rate setting, the corresponding LIN slope control is automatically selected.

Figure 52. LIN timings for normal baud rate (20 kB/s)

Figure 53. LIN timings for slow baud rate (10 kB/s)

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Figure 54. LIN receiver timings

6.9.4 Fault detection

6.9.4.1

VSUP undervoltage

A V

undervoltage (V

) detection is implemented to be compliant with SAEJ2602-2 standard. At low V

voltage

SUP

LIN_UV

SUP

(VSUP<V

), the LIN bus goes in recessive state to avoid wrong communication.

LIN_UV

6.9.4.2

TXDL permanent dominant (timeout)

If TXDL is set low for a time longer than t

parameter, the LIN driver is disabled and the LIN bus will return to recessive state. This

XD_DOM

prevents the bus to be set in dominant state permanently, in case a failure sets the TXDL input permanently to a low level.

The LIN receiver continues to operate. The LIN_mode MSB bit is set to 0 and the flag TXDL_dominant is reported in the Diag CAN_LIN

register. The device recovers from this error detection after setting the LIN_mode to normal operation and when a high level is detected

on TXDL. The TXDL failure detection is operating when the LIN transceiver is in Normal mode and Listen Only mode.

6.9.4.3

RXDL permanent recessive

If RXDL is detected high for seven consecutive receive/dominant cycles, the LIN driver and receiver are disabled and the LIN bus returns

to recessive state. The LIN_mode MSB bit is set to 0 and the flag RXDL_recessive is reported in the Diag CAN_LIN register. The device

recovers from this error detection after setting the LIN_mode to normal operation, and when a high level is detected on TXDL. The RXDL

failure detection is operating when the LIN transceiver is in Normal mode and Listen Only mode.

6.9.4.4

LIN bus short-circuit

If the LIN bus is dominant for a time longer than t

, due for instance to an external short-circuit to GND, the detection is

LIN_SHORT_GND

reported to the device main logic. The BUS bus failure detection is operating when the LIN transceiver is in Normal mode and Listen Only

mode.

6.9.4.5

LIN current limitation

In case of LIN short-circuit to Battery, the current flowing out of the LIN driver is limited to 200 mA (parameter I

), and the LIN driver

BUS_LIM

is not shut down. The LIN bus goes in recessive state when the current limitation occurs and returns in the same functional mode as before

failure when the current falls below the current limitation value.

6.9.4.6

LIN overtemperature

If the driver temperature exceeds the TSD (t

), the LIN driver is disabled and the LIN bus will return to recessive state. The LIN

LIN_SD

receiver continues to operate. The LIN_mode MSB bit is set to 0 and the flag LIN_OT is reported in the Diag CAN_LIN register.

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A hysteresis is implemented in this protection feature. The LIN driver remain disabled until the temperature has fallen below the OT

threshold minus hysteresis. The device recovers from this error detection after setting the LIN_mode to normal operation, and when a

high level is detected on TXDL.

6.9.4.7

LIN errors

The interruption generated by the LIN errors can be inhibited setting INT_inh_LIN bit at “1” in the “INIT INT” register. The list of LIN error

bits is provided in Table 12.

Table 12. LIN error bits

Register

Bit

Flag type

Effect

LIN_dominant

RXDL_recessive

TXDL_dominant

LIN_OT

Error

Turn OFF LIN transceiver

DIAG CAN_LIN

6.9.5 Wake-up mechanism

The device can wake-up by a LIN dominant pulse longer than t

. Dominant pulse means: a recessive to dominant transition, wait

BUS_WU

for t > t

, then a dominant to recessive transition.

BUS_WU

V_{LIN_REC}

V_{BUS_WU}

V_{LIN_DOM}

LIN Wake up

validation

T_{BUS_WU}

Figure 55. LIN wake-up pattern illustration

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7

Serial peripheral interface

7.1

High level overview

7.1.1 SPI

The device is using a 16 bits SPI, with the following arrangement:

MOSI, Master Out Slave In bits:

• Bit 15 read/write

• Bit 14 Main or fail-safe register target

• bit 13 to 9 (A4 to A0) to select the register address. Bit 8 is a parity bit in write mode, Next bit (=0) in read mode.

• bit7 to 0 (D7 to D0): control bits

MISO, Master IN Slave Out bits:

• bits 15 to 8 (S15 to S8) are device status bits

• bits 7 to 0(Do7 to Do0) are either extended device status bits, device internal control register content or device flags.

Figure 56 is an overview of the SPI implementation.

7.1.2 Parity bit 8 calculation

The parity is used for write to register command (bit 15,14 = 01). It is calculated based on the number of logic ones contained in bits

15-9, 7-0 sequence (this is the whole 16-bits of the write command except bit 8).

Bit 8 must be set to 0 if the number of 1 is odd.

Bit 8 must be set to 1 if the number of 1 is even.

7.1.3 Device status on MISO

When a write operation is performed to store data or control bit into the device, MISO pin reports a 16-bit fixed device status composed

of two bytes: Device Fixed Status (bits 15 to 8) + extended Device Status (bits 7 to 0). In a read operation, MISO reports the fixed device

status (bits 15 to 8), and the next eight bits are content of the selected register. A standard serial peripheral interface (SPI) is integrated

to allow bi-directional communication between the 33907/33908 and the MCU. The SPI is used for configuration and diagnostic purposes.

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

D7 D6 D5 D4 D3 D2 D1 D0

MOSI R/W M/FS A4

A2

A3

A1

A0

S9

P

register address

Parity

S8

data

Do7 Do6 Do5 Do4 Do3 Do2 Do1 Do0

MISO S15 S14

S13

S11

S12

S10

Extended Device Status, Register Control bits or Device Flags

Device Status

CSb active low. Must be raised at end of 16 clocks,

for write commands, MOSI bits [15] = [1].

CSb

SCLK

SCLK signal is low outside of CSB active

MOSI and MISO data changed at SCLK rising edge

and sampled at falling edge. Msb first.

MOSI Don’t care

Don’t care

Tri state

C1

C0

D0

Do0

MISO tri state outside of CSB active

MISO

Tri state

S15

S14

SPI wave form, and signals polarity

Figure 56. SPI overview

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The device contains several registers. Their address is coded on 7 bits (bits 15 to 9). Each register controls or reports part of the device

function. Data can be written to the register, to control the device operation or set default value or behavior. Every register can also be

read back in order to ensure that its content (default setting or value previously written) is correct.

7.1.4 Register description

Although the minimum time between two NCS low sequences is defined by t_ONNCS(Figure 57), two consecutive accesses to the fail-safe

registers must be done with a 3.5 µs minimum NCS high time in between. Although the minimum time between two fail-safe registers

accesses is 3.5 µs, some SPI accesses to the main registers can be done in between (Figure 57).

7.2

Detail operation

Figure 57. MOSI / MISO SPI command organization

Table 13. MOSI bits description

Description

Set if it is a READ or WRITE Command

R / W

M / FS

A4:0

P

0

READ

1

WRITE

Description

Split the addresses between Fail-safe State machine and main Logic

0

Main

1

Fail-safe

Description

Set the address to Read or Write

0

See Register Mapping

1

Description

Parity bit (only use in Write mode). Set to 0 in Read mode

Number of “1” (bit15:9 and bit 7:0) is odd

0

1

Number of “1” (bit15:9) and bit 7:0) is even

Description

Data in Write mode. Shall be set to 00h in Read mode

D7:0

0

1

See Register Details

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Table 14. MISO bits description

Description

Report an error in the SPI communication

0

No Failure

SPI_G

1

Failure

Reset Condition

Description

Power On Reset / When initial event cleared on read

Report a wake-up event. Logical OR of all wake-up sources

0

No WU event

WU

1

WU event

Reset Condition

Description

Power On Reset / When initial event cleared on read

Report a CAN event (Diagnostic)

0

No event

CAN_G

1

CAN event

Reset Condition

Description

Power On Reset / When initial event cleared on read

Report a LIN event (diagnostic)

0

No event

LIN_G

1

LIN event

Reset Condition

Description

Power On Reset / When initial event cleared on read

Report a change in IOs state

0

No IO transition

IO_G

1

IO transition

Reset Condition

Description

Power On Reset / when initial event cleared on read

Report an event from V_{PRE-REGULATOR}and battery monitoring (status change or failure)

0

No event

VPRE_G

1

Event occurred

Reset Condition

Description

Power On Reset / when initial event cleared on read

Report an event from V_COREregulator (status change or failure)

No event

0

VCORE_G

1

Event occurred

Reset Condition

Description

Power On Reset / when initial event cleared on read

Report an event from V_CCA, V_AUX, or V_CANregulators (status change or failure)

No event

0

VOTHERS_G

1

Event occurred

Reset Condition

Power On Reset / when initial event cleared on read

SPI_G = SPI_err or SPI_clk or SPI_Req or SPI_Parity or SPI_FS_err or SPI_FS_clk or SPI_FS_Req or SPI_FS_Parity

WU_G = IO_5_WU or IO_4_WU or IO_3_WU or IO_2_WU or IO_1_WU or IO_0_WU or PHY_WU

CAN_G = CANH_BATT or CANH_GND or CANL_BATT or CANL_GND or CAN_dominant or RXD_recessive or TXD_dominant or

CAN_OT or CAN_OC

LIN_G = LIN_OT or RXDL_recessive or TXDL_dominant or LIN_dominant

IO_G = IO_5 or IO_4 or IO_3 or IO_2 or IO_1 or IO_0

Vpre_G = VSNS_UV or VSUP_UV_7 or IPFF or ILIM_PRE or TWARN_PRE or BOB or VPRE_STATE_flag or VPRE_OV or VPRE_UV

Vcore_G = ILIM_CORE or TWARN_CORE or VCORE_STATE_flag or VCORE_OV or VCORE_UV

Vothers_G = ILIM_CCA or TWARN_CCA or TSD_CCA or ILIM_CCA_OFF or VCCA_UV or VCCA_OV or ILIM_AUX or VAUX_TSD or

ILIM_AUX_OFF or VAUX_OV or VAUX_UV or ILIM_CAN or VCAN_UV or VCAN_OV or TSD_CAN

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7.2.1 Register address table

Table 15 is a list of device registers and addresses coded in bits 13 to 9 in MOSI for main logic.

Table 15. Register mapping of main logic

Address

Register

Write description

Table ref

FS/M

A4

A3

A2

A1

A0

Hex

NOT USED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

#0(00h)

#1(01h)

N/A

Write during INIT phase then read only

N/A

INIT Vreg 1

INIT Vreg2

Table 18

Table 20

Table 22

Table 24

Table 26

Table 28

N/A

#2(02h)

INIT CAN_LIN

INIT IO_WU1

INIT IO_WU2

INIT INT

#3(03h)

#4(04h)

#5(05h)

#6(06h)

NOT USED

HW Config

#7(07h)

#8(08h)

Read only

Table 30

Table 32

N/A

WU Source

NOT USED

IO_input

#9(09h)

Read only

#10(0Ah)

#11(0Bh)

#12(0Ch)

#13(0Dh)

#14(0Eh)

#15(0Fh)

#16(10h)

#17(11h)

#18(12h)

#19(13h)

#20(14h)

#21(15h)

#22(16h)

#23(17h)

#24(18h)

#25(19h)

N/A

Read only

Table 34

Table 36

Table 38

Table 40

Table 42

Table 44

Table 46

Table 48

Table 50

N/A

Status Vreg#1

Status Vreg#2

Diag Vreg#1

Diag Vreg#2

Diag Vreg#3

Diag CAN1

Diag CAN_LIN

Diag SPI

Read only

NOT USED

MODE

N/A

Write during Normal and Read

Table 52

Table 54

Table 56

Table 58

Table 60

Vreg Mode

IO_OUT/AMUX

CAN_LIN Mode

CAN Mode 2

Table 16 is a list of device registers and addresses coded in bits 13 to 9 in MOSI for fail-safe logic

Table 16. Register mapping of fail-safe logic

Address

Register

Write description

Table ref

FS/M

A4

A3

A2

A1

A0

Hex

INIT Supervisor#1

INIT Supervisor#2

INIT Supervisor#3

INIT FSSM#1

1

0

1

0

1

0

1

0

1

0

1

0

#33(21h)

#34(22h)

#35(23h)

#36(24h)

#37(25h)

#38(26h)

Write during INIT phase then Read only

Write (No restriction) and Read

Table 62

Table 64

Table 66

Table 68

Table 70

Table 72

INIT FSSM#2

WD_Window

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Table 16. Register mapping of fail-safe logic (continued)

Address

Register

Write description

Table ref

FS/M

A4

A3

A2

A1

A0

Hex

WD_LFSR

WD_answer

FS_OUT

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

#39(27h)

#40(28h)

#41(29h)

#42(2Ah)

#43(2Bh)

#44(2Ch)

#45(2Dh)

#46(2Eh)

Write (No restriction) and Read

Write (No restriction)

Write during INIT phase then Read only

Read only

Table 74

Table 76

Table 78

Table 80

Table 82

Table 84

Table 86

Table 88

RSTb request

INIT WD

Diag FS1

WD_Counter

Diag_FS2

Read only

7.2.2 Secured SPI command

Some SPI commands must be secured to avoid unwanted change of the critical bits. In the fail-safe machine and in the main state

machine, the secured bits are calculated from the data bits sent as follows:

Table 17. Secured SPI

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Data 3

Data 2

Data 1

Data 0

Secure 3

Secure2

Secure 1 Secure 0

• Secure 3 = NOT(Bit5)

• Secure 2 = NOT(Bit4)

• Secure 1 = Bit7

• Secure 0 = Bit6

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7.3

Detail of register mapping

7.3.1 Init VREG 1

Table 18. INIT VREG1 register configuration

Write

bit15

bit14

bit13

bit12

bit11

bit10

bit9

bit8

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Vcore_

FB

MOSI

MISO

1

0

1

P

0

Ipff_DIS

0

Vcore_ Vothers

G

Reserve

d

Reserve

d

Reserve Vcore_F

SPI_G

WU

CAN_G LIN_G

IO_G

Vpre_G

0

Ipff_DIS

0

_G

d

B

Read

bit15

bit14

bit13

bit12

bit11

bit10

bit9

bit8

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

MOSI

0

1

0

Vcore_ Vothers

_G

Reserve

d

Reserve

d

Reserve Vcore_F

MISO

SPI_G

WU

CAN_G LIN_G

IO_G

Vpre_G

0

Ipff_DIS

0

G

d

B

Table 19. Description and configuration of the bits (Default value in bold)

Description

DISABLE the input Power Feed Forward (IPFF) function of V_PRE

0

ENABLED

IPFF_DIS

Vcore_FB

1

DISABLED

Reset condition Power On Reset

Description

Configure the monitoring of the second V_COREresistor string

No Monitoring (IO_1 is used as analog & digital input)

Monitoring enabled (IO_1 can NOT be used for analog/digital input neither for WU from LPOFF)

0

1

Reset condition Power On Reset

7.3.2 Init Vreg 2

Table 20. INIT VREG2 register configuration

Write

bit15

bit14

bit13

bit12

bit11

bit10

bit9

bit8

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Tcca_li

m_off

Taux_li Vaux_tr

m_off k_EN

MOSI

MISO

1

0

1

0

P

0

Icca_lim

0

Vcore_ Vothers

_G

Tcca_li

m_off

Taux_li Vaux_tr

SPI_G

WU

CAN_G

LIN_G

IO_G

Vpre_G

0

Icca_lim

0

reserved

G

m_off

k_EN

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Table 20. INIT VREG2 register configuration (continued)

Read

bit15

bit14

bit13

bit12

bit11

bit10

bit9

bit8

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

MOSI

MISO

0

1

0

Vcore_ Vothers

_G

Tcca_li

m_off

Taux_li Vaux_tr

m_off

SPI_G

WU

CAN_G

LIN_G

IO_G

Vpre_G

0

Icca_lim

0

reserved

G

k_EN

Table 21. INIT VREG2. description and configuration of the bits (default value in bold)

Description

Configure the current limitation duration before regulator is switched off. Only used for external PNP

0

10 ms

T_{CCA_LIM_OFF}

1

50 ms

Reset condition Power On Reset

Description

Configure the current limitation threshold. Only available for external PNP

0

I_{CCA_LIM_OUT}

I_{CCA_LIM}

1

I_{CCA_LIM_INT}

Reset condition Power On Reset

Description

Configure the current limitation duration before regulator is switched off. Only used for external PNP

0

10 ms

T_{AUX_LIM_OFF}

1

50 ms

Reset condition Power On Reset

Description

Configure V_AUXregulator as a tracker

0

No tracking. HW configuration is used

V_{AUX_TRK_EN}

1

Tracking enabled

Reset condition Power On Reset

7.3.3 Init CAN_LIN

Table 22. INIT CAN_LIN register description

Write

bit15

bit14

bit13

bit12

bit11

bit10

bit9

bit8

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

LIN_SR LIN_SR

_1 _0

CAN_w

u_conf

CAN_w

u_TO

MOSI

MISO

1

0

1

P

0

LIN_SR LIN_SR

Vcore_ Vothers

_G

CAN_w Reserve Reserve CAN_w Reserve

u_conf u_TO

SPI_G

WU

CAN_G LIN_G

IO_G

Vpre_G

0

G

d

_1

_0

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Table 22. INIT CAN_LIN register description (continued)

Read

bit15

bit14

bit13

bit12

bit11

bit10

bit9

bit8

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

MOSI

MISO

0

1

0

LIN_SR LIN_SR

_1

Vcore_ Vothers

_G

CAN_w Reserve Reserve CAN_w Reserve

u_conf

SPI_G

WU

CAN_G LIN_G

IO_G

Vpre_G

0

G

d

u_TO

d

_0

Table 23. INIT CAN_LIN. description and configuration of the bits (default value in bold)

Description

Define the CAN wake-up mechanism

3 dominant pulses

0

CAN_wu_conf

CAN_wu_to

1

Single dominant pulse

Reset condition Power On Reset

Description

Define the CAN wake-up timeout (in case of CAN_wu_conf = 0)

0

120 µs

1

360 µs

Reset condition Power On Reset

Description

Configure the LIN slew rate

00

01

1X

20 kbits/s

LIN_SR_1:0

10 kbits/s

Fast baud rate (Max: 100 kbits/s)

Reset condition Power On Reset

7.3.4 INIT IO_WU1

Table 24. INIT IO_WU1 register description

Write

bit15

bit14

bit13

bit12

bit11

bit10

bit9

bit8

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

INT_inh INT_inh

MOSI

MISO

1

0

1

0

P

WU_0_1 WU_0_0 WU_1_1 WU_1_0 WU_2_1 WU_2_0

_IO_1

_IO_0

Vothers

_G

INT_inh INT_inh

SPI_G

WU

CAN_G LIN_G

IO_G

Vpre_G Vcore_G

WU_0_1 WU_0_0 WU_1_1 WU_1_0 WU-2-1 WU_2_0

_IO_1

_IO_0

Read

bit15

bit14

bit13

bit12

bit11

bit10

bit9

bit8

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

MOSI

0

1

0

Vothers

_G

INT_inh INT_inh

MISO

SPI_G

WU

CAN_G LIN_G

IO_G

Vpre_G Vcore_G

WU_0_1 WU_0_0 WU_1_1 WU_1_0 WU-2-1 WU_2_0

_IO_1

_IO_0

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Table 25. INIT IO_WU1. description and configuration of the bits (default value in bold)

Description

Wake-up configuration for IO_0

NO wake-up capability

00

01

10

11

Wake-up on rising edge only

Wake-up on falling edge only

Wake-up on any edge

WU_0_1:0

Reset condition Power On Reset

Description

Wake-up configuration for IO_1

00

01

10

11

NO wake-up capability

Wake-up on rising edge only

Wake-up on falling edge only

Wake-up on any edge

WU_1_1:0

Reset condition Power On Reset

Description

Wake-up configuration for IO_2

00

01

10

11

NO wake-up capability

Wake-up on rising edge only

Wake-up on falling edge only

Wake-up on any edge

WU_2_1:0

Reset condition Power On Reset

Description

Inhibit the INT pulse for IO_1. IO_1 masked in IO_G. Avoid INT when used in FS

0

INT NOT masked

INT_inh_IO_1

INT_inh_IO_0

1

INT masked

Reset condition Power On Reset

Description

Inhibit the INT pulse for IO_0. IO_0 masked in IO_G. Avoid INT when used in FS

0

INT NOT masked

1

INT masked

Reset condition Power On Reset

7.3.5 INIT IO_WU2

Table 26. INIT IO_WU2 register description

Write

bit15

bit14

bit13

bit12

bit11

bit10

bit9

bit8

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

INT_inh INT_inh

_IO_23 _IO_45

MOSI

MISO

1

0

1

0

1

P

WU_3_1 WU_3_0 WU_4_1 WU_4_0 WU_5_1 WU_5_0

Vcore_ Vothers

_G

INT_inh INT_inh

_IO_23 _IO_45

SPI_G

WU

CAN_G

LIN_G

IO_G

Vpre_G

WU_3_1 WU_3_0 WU_4_1 WU_4_0 WU_5_1 WU_5_0

G

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Table 26. INIT IO_WU2 register description (continued)

Read

bit15

bit14

bit13

bit12

bit11

bit10

bit9

bit8

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

MOSI

MISO

0

1

0

1

0

Vcore_ Vothers

G

INT_inh INT_inh

_IO_23 _IO_45

SPI_G

WU

CAN_G

LIN_G

IO_G

Vpre_G

WU_3_1 WU_3_0 WU_4_1 WU_4_0 WU_5_1 WU_5_0

_G

Table 27. INIT IO_WU2. description and configuration of the bits (default value in bold)

Description

Wake-up configuration for IO_3

NO wake-up capability

00

01

10

11

Wake-up on rising edge only

Wake-up on falling edge only

Wake-up on any edge

WU_3_1:0

WU_4_1:0

WU_5_1:0

Reset condition Power On Reset

Description

Wake-up configuration for IO_4

00

01

10

11

NO wake-up capability

Wake-up on rising edge only

Wake-up on falling edge only

Wake-up on any edge

Reset condition Power On Reset

Description

Wake-up configuration for IO_5

00

01

10

11

NO wake-up capability

Wake-up on rising edge only

Wake-up on falling edge only

Wake-up on any edge

Reset condition Power On Reset

Description

Inhibit the INT pulse for IO_4 & IO_5. IO_4 & IO_5 masked in IO_G. Avoid INT when used in FS

0

INT NOT masked

INT_inh_IO_45

INT_inh_IO_23

1

INT masked

Reset condition Power On Reset

Description

Inhibit the INT pulse for IO_2 & IO_3. IO_2 & IO_3 masked in IO_G. Avoid INT when used in FS

0

INT NOT masked

1

INT masked

Reset condition Power On Reset

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7.3.6 INIT INT

Table 28. INIT INT register description

Write

bit15

bit14

bit13

bit12

bit11

bit10

bit9

bit8

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

INT_inh

_Vother

s

INT_dur INT_inh INT_inh INT_inh INT_inh INT_inh

ation _LIN _all _Vsns _Vpre _Vcore

INT_inh

_CAN

MOSI

MISO

1

0

1

0

P

INT_inh

_Vother

s

Vcore_ Vothers INT_dur INT_inh INT_inh INT_inh INT_inh INT_inh

INT_inh

_CAN

SPI_G

WU

CAN_G

LIN_G

IO_G

Vpre_G

G

_G

ation

_LIN

_all

_Vsns

_Vpre

_Vcore

Read

bit15

bit14

bit13

bit12

bit11

bit10

bit9

bit8

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

MOSI

0

1

0

INT_inh

_Vother

s

Vcore_ Vothers INT_dur INT_inh INT_inh INT_inh INT_inh INT_inh

_G ation _LIN _all _Vsns _Vpre _Vcore

INT_inh

_CAN

MISO

SPI_G

WU

CAN_G

LIN_G

IO_G

Vpre_G

G

Table 29. INIT INT. description and configuration of the bits (default value in bold)

Description

Define the duration of the INTerrupt pulse

0

100 µs

INT_duration

INT_inh_LIN

INT_inh_all

1

25 µs

Reset condition Power On Reset

Description

Inhibit the INT for LIN error bits

0

All INT sources

1

LIN error bits changed INHIBITED

Reset condition Power On Reset

Description

Inhibit ALL the INT

All INT sources

All INT INHIBITED

0

1

Reset condition Power On Reset

Description

Inhibit the INT for V_{SNS_UV}

0

All INT sources

INT_inh_Vsns

INT_inh_Vpre

1

V_{SNS_UV}INT INHIBITED

Reset condition Power On Reset

Description

Inhibit the INT for V_PREstatus event (cf. register status Vreg1)

All INT sources

0

1

V_PREstatus changed INHIBITED

Reset condition Power On Reset

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Table 29. INIT INT. description and configuration of the bits (default value in bold) (continued)

Description

Inhibit the INT for V_COREstatus event (cf. register status Vreg2)

All INT sources

0

INT_inh_Vcore

INT_inh_Vothers

INT_inh_CAN

1

V_COREstatus changed INHIBITED

Reset condition Power On Reset

Description

Inhibit the INT for V_CCA/ V_AUXand V_CANstatus event (cf. register status Vreg2)

0

All INT sources

1

V_CCA/ V_AUX/ V_CANstatus changed INHIBITED

Reset condition Power On Reset

Description

Inhibit the INT for CAN error bits

0

All INT sources

1

CAN error bits changed INHIBITED

Reset condition Power On Reset

7.3.7 HW config

Table 30. HW config register description

Read

bit15

0

bit14

0

bit13

0

bit12

1

bit11

0

bit10

0

bit9

0

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

MOSI

Vaux Vcca_

CAN_

G

Vpre_ Vcore_ Vother LS_det

s_G ect

Vcca_ Vaux_

MISO SPI_G

WU

LIN_G

IO_G

not

PNP_d

etect

1

0

DBG

G

HW

used

Table 31. HW config. description and configuration of the bits (default value in bold)

Description

Report the hardware configuration of V_PRE(Buck only or Buck-Boost)

0

Buck-Boost

LS_detect

1

Buck only

Reset condition Power On Reset / Refresh after LPOFF

Description

Report if V_AUXis used

0

1

V

_AUXis used (external PNP is assumed to be connected, V_AUXcan be switched OFF/ON through SPI)

_AUXis not used

V

_AUXnot used

Reset condition Power On Reset / Refresh after LPOFF

Description

Report the connection of an external PNP on V_CCA

External PNP connected

0

1

V_{CCA_PNP_DETECT}

Internal MOSFET

Reset condition Power On Reset / Refresh after LPOFF

Description

Report the hardware configuration for V_CCA

0

3.3 V

V_{CCA_HW}

1

5.0 V

Reset condition Power On Reset / Refresh after LPOFF

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Table 31. HW config. description and configuration of the bits (default value in bold) (continued)

Description

Report the hardware configuration for V_AUX

0

5.0 V

V_{AUX_HW}

1

3.3 V

Reset condition Power On Reset / Refresh after LPOFF

Description

Report the configuration of the DEBUG mode

Normal operation

0

1

DBG

DEBUG mode selected

Reset condition Power On Reset / Refresh after LPOFF

7.3.8 WU source

Table 32. WU source register description

Read

bit15

0

bit14

0

bit13

0

bit12

1

bit11

0

bit10

0

bit9

1

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

MOSI

MISO

CAN_

G

Vpre_ Vcore_ Vother IO_5_ IO_4_ IO_3_ IO_2_ IO_1_ IO_0_

s_G WU WU WU WU WU WU

Phy_W

U

SPI_G

WU

LIN_G

IO_G

0

G

Table 33. WU source. description and configuration of the bits (default value in bold)

Description

Report a wake-up event from IO_5

No Wake-up

0

IO_5_WU

IO_4_WU

IO_3_WU

IO_2_WU

IO_1_WU

1

WU event detected

Reset condition Power On Reset / Read

Description

Report a wake-up event from IO_4

0

No Wake-up

1

WU event detected

Reset condition Power On Reset / Read

Description

Report a wake-up event from IO_3

0

No Wake-up

1

WU event detected

Reset condition Power On Reset / Read

Description

Report a wake-up event from IO_2

0

No Wake-up

1

WU event detected

Reset condition Power On Reset / Read

Description

Report a wake-up event from IO_1

0

No Wake-up

1

WU event detected

Reset condition Power On Reset / Read

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Table 33. WU source. description and configuration of the bits (default value in bold)(continued)

Description

Report a wake-up event from IO_0

No Wake-up

0

IO_0_WU

Phy_WU

1

WU event detected

Reset condition Power On Reset / Read

Description

Report a wake-up event from CAN or LIN

0

No Wake-up

1

WU event detected

Reset condition Power On Reset / Read CAN_wu or/and LIN_wu

7.3.9 IO input

Table 34. IO input register description

Read

bit15

0

bit14

0

bit13

0

bit12

1

bit11

0

bit10

1

bit9

1

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

MOSI

MISO

CAN_

G

Vpre_ Vcore_ Vother

s_G

SPI_G

WU

LIN_G

IO_G

IO_5

IO_4

0

IO_3

IO_2

0

IO_1

IO_0

G

Table 35. IO input. description and configuration of the bits

Description

Report IO_5 digital state in Normal mode. No update in LPOFF mode since wake-up features available

0

1

Low

IO_5

IO_4

IO_3

IO_2

IO_1

High

Reset condition Power On Reset

Description

Report IO_4 digital state in Normal mode. No update in LPOFF mode since wake-up features available

0

1

Low

High

Reset condition Power On Reset

Description

Report IO_3 digital state in Normal mode. No update in LPOFF mode since wake-up features available

0

1

Low

High

Reset condition Power On Reset

Description

Report IO_2 digital state in Normal mode. No update in LPOFF mode since wake-up features available

0

1

Low

High

Reset condition Power On Reset

Description

Report IO_1 digital state in Normal mode. No update in LPOFF mode since wake-up features available

0

1

Low

High

Reset condition Power On Reset

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Table 35. IO input. description and configuration of the bits(continued)

Description

Report IO_0 digital state in Normal mode. No update in LPOFF mode since wake-up features available

0

1

Low

IO_0

High

Reset condition Power On Reset

7.3.10 Status Vreg1

Table 36. STATUS VREG1 register description

Read

bit15 bit14 bit13 bit12 bit11 bit10

bit9

0

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

MOSI

MISO

0

1

0

SPI_

G

CAN_ LIN_

Vpre_ Vcore_ Vothers_

Twarn_pr

e

Vpre_stat

e

WU

IO_G

IpFF

Ilim_pre

BoB

0

G

Table 37. Status Vreg1. description and configuration of the bits (default value in bold)

Description

Input Power Feed Forward

Normal Operation

0

I_PFF

1

Ipff mode activated

Reset condition Power On Reset / Read

Description

Report a current limitation condition on V_PRE

0

No current limitation (I_{PRE_PK}< I_{PRE_LIM}

)

I_{LIM_PRE}

T_{WARN_PRE}

BoB

1

Current limitation (I_{PRE_PK}> I_{PRE_LIM}

)

Reset condition Power On Reset / Read

Description

Report a thermal warning from V_PRE

0

No thermal warning (T_J< T_{WARN_PRE})

1

Thermal warning (T_J> T_{WARN_PRE})

Reset condition Power On Reset / Read

Description

Report a running mode of V_PRE

0

Buck

1

Boost

Reset condition Power On Reset

Description

Report the activation state of V_PRESMPS

0

SMPS OFF

V_{PRE_STATE}

1

SMPS ON

Reset condition Power On Reset

7.3.11 Status VREG2

Table 38. STATUS VREG2 register description

Read

bit15

0

bit14

0

bit13

0

bit12

1

bit11

1

bit10

0

bit9

1

bit8

0

bit7

0

bit6

0

bit5

bit4

0

bit3

bit2

0

bit1

bit0

MOSI

0

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Table 38. STATUS VREG2 register description

CAN_

G

Vpre_ Vcore_ Vother Ilim_co Twarn_ Vcore_ Twarn_ Ilim_cc Ilim_au Ilim_ca

MISO

SPI_G

WU

LIN_G

IO_G

0

G

s_G

re

core

state

cca

a

x

n

Table 39. Status Vreg2. description and configuration of the bits (default value in bold)

Description

Report a current limitation condition on V_CORE

No current limitation (I_{CORE_PK}< I_{CORE_LIM}

Current limitation (I_{CORE_PK}> I_{CORE_LIM}

0

)

I_{LIM_CORE}

T_{WARN_CORE}

V_{CORE_STATE}

T_{WARN_CCA}

I_{LIM_CCA}

1

)

Reset condition Power On Reset / Read

Description

Report a thermal warning from V_CORE

No thermal warning (T_J< T_{WARN_CORE}

Thermal warning (T_J> T_{WARN_CORE}

0

)

1

)

Reset condition Power On Reset / Read

Description

Report the activation state of V_CORESMPS

0

SMPS OFF

1

SMPS ON

Reset condition Power On Reset

Description

Report a thermal warning from V_CCA. Available only for internal pass MOSFET

No thermal warning (T_J< T_{WARN_CCA}

Thermal warning (T_J> T_{WARN_CCA}

0

)

1

)

Reset condition Power On Reset

Description

Report a current limitation condition on V_CCA

No current limitation (I_CCA< I_{CCA_LIM}

Current limitation (I_CCA> I_{CCA_LIM}

0

)

1

)

Reset condition Power On Reset / Read

Description

Report a current limitation condition on V_AUX

No current limitation (I_AUX< I_{AUX_LIM}

Current limitation (I_AUX> I_{AUX_LIM}

0

)

I_{LIM_AUX}

1

)

Reset condition Power On Reset / Read

Description

Report a current limitation condition on V_CAN

No current limitation (I_CAN< I_{CAN_LIM}

Current limitation (I_CAN> I_{CAN _LIM}

0

)

I_{LIM_CAN}

1

)

Reset condition Power On Reset / Read

7.3.12 Diag Vreg1

Table 40. DIAG VREG1 register description

Read

bit15

0

bit14

0

bit13

0

bit12

1

bit11

1

bit10

1

bit9

0

bit8

bit7

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

MOSI

MISO

0

CAN_

G

Vpre_ Vcore_ Vother Vsns_u Vsup_u Tsd_pr Vpre_ Vpre_u Tsd_co Vcore_ Vcore_

s_G v_7 OV re FB_OV FB_uv

SPI_G

WU

LIN_G

IO_G

G

v

e

v

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Table 41. Diag Vreg1. description and configuration of the bits (default value in bold)

Description

Detection of V_BATTERYbelow V_{SNS_UV}

V_BAT> V_{SNS_UV}

0

V_{SNS_UV}

V_{SUP_UV_7}

T_{SD_PRE}

1

V_BAT< V_{SNS_UV}

Reset condition Power On Reset / Read

Description

Detection of V_SUPbelow V_{SUP_UV_7}

0

V_SUP> V_{SUP_UV_7}

1

V_SUP< V_{SUP_UV_7}

Reset condition Power On Reset / Read

Description

Thermal shutdown of V_PRE

No TSD (T_J< T_{SD_PRE}

TSD occurred (T_J> T_{SD_PRE}

0

)

1

)

Reset condition Power On Reset / Read

Description

V_PREovervoltage detection

No overvoltage (V_PRE< V_{PRE_OV}

Overvoltage detected (V_PRE> V_{PRE_OV}

0

)

V_{PRE_OV}

1

)

Reset condition Power On Reset

Description

V_PREundervoltage detection

No undervoltage (VPRE > VPRE_UV)

Undervoltage detected (V_PRE< V_{PRE_UV}

0

V_{PRE_UV}

1

)

Reset condition Power On Reset / Read

Description

Thermal shutdown of V_CORE

No TSD (T_J< T_{SD_CORE}

TSD occurred (T_J> T_{SD_CORE}

0

)

T_{SD_CORE}

V_{CORE_FB_OV}

V_{CORE_FB_UV}

1

)

Reset condition Power On Reset / Read

Description

V_COREovervoltage detection

No overvoltage (V_{CORE_FB}< V_{CORE_FB_OV}

Overvoltage detected (V_{CORE_FB}> V_{CORE_FB_OV}

0

)

1

)

Reset condition Power On Reset / Read

Description

V_COREundervoltage detection

0

No undervoltage (V_{CORE_FB}> V_{CORE_FB_UV})

1

Undervoltage (V_{CORE_FB}< V_{CORE_FB_UV}

)

Reset condition Power On Reset / Read

7.3.13 Diag Vreg2

Table 42. DIAG VREG2 register description

Read

bit15

0

bit14

0

bit13

0

bit12

1

bit11

1

bit10

1

bit9

1

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

MOSI

CAN_

G

Vpre_ Vcore_ Vother Tsd_C Vcan_ Vcan_u

s_G an OV

Tsd_au Ilim_au Vaux_ Vaux_u

x_off OV

MISO SPI_G

WU

LIN_G

IO_G

0

G

v

x

v

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Table 43. Diag Vreg2. description and configuration of the bits (default value in bold)

Description

Thermal shutdown of V_CAN

NO TSD (T_J< T_{SD_CAN}

TSD occurred (T_J> T_{SD_CAN}

0

)

T_{SD_CAN}

V_{CAN_OV}

V_{CAN_UV}

T_{SD_AUX}

1

)

Reset condition Power On Reset / Read

Description

V_CANOvervoltage detection

No Overvoltage (V_CAN< V_{CAN_OV}

Overvoltage detected (V_CAN> V_{CAN_OV}

0

)

1

)

Reset condition Power On Reset / Read

Description

V_CANundervoltage detection

0

No undervoltage (V_CAN> V_{CAN_UV})

1

Undervoltage detected (V_CAN< V_{CAN_UV})

Reset condition Power On Reset / Read

Description

Thermal shutdown of V_AUX

No TSD (T_J< T_{SD_AUX}

TSD occurred (T_J> T_{SD_AUX}

0

)

1

)

Reset condition Power On Reset

Description

Maximum current limitation duration

T_{_LIMITATION}< T_{AUX_LIM_OFF}

T_{_LIMITATION}>T_{AUX_LIM_OFF}

0

I_{LIM_AUX_OFF}

V_{AUX_OV}

V_{AUX_UV}

1

Reset condition Power On Reset / Read

Description

V_AUXovervoltage detection

0

No overvoltage (V_AUX< V_{AUX_OV})

1

Overvoltage detected (V_AUX> V_{AUX_OV})

Reset condition Power On Reset / Read

Description

V_AUXundervoltage detection

0

No undervoltage (V_AUX> V_{AUX_UV})

1

Undervoltage detected (V_AUX< V_{AUX_UV})

Reset condition Power On Reset / Read

7.3.14 Diag Vreg3

Table 44. DIAG VREG3 register description

Read

bit15

0

bit14

0

bit13

1

bit12

0

bit11

0

bit10

0

bit9

0

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

MOSI

CAN_

G

Vpre_ Vcore_ Vother Tsd_cc

s_G

Ilim-

cca_off

Vcca_

OV

Vcca_

UV

MISO SPI_G

WU

LIN_G

IO_G

0

G

a

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Table 45. Diag Vreg3. description and configuration of the bits (default value in bold)

Description

Thermal shutdown of V_CCA

NO TSD (T_J< T_{SD_CCA}

TSD occurred (T_J> T_{SD_CCA}

0

)

T_{SD_CCA}

I_{LIM_CCA_OFF}

V_{CCA_OV}

1

)

Reset condition Power On Reset / Read

Description

Maximum current limitation duration. Available only when an external PNP is connected

T_{_LIMITATION}< T_{CCA_LIM_OFF}

0

1

T_{_LIMITATION}>T_{CCA_LIM_OFF}

Reset condition Power On Reset / Read

Description

V_CCAovervoltage detection

0

No overvoltage (V_CCA< V_{CCA_OV})

1

Overvoltage detected (V_CCA> V_{CCA_OV})

Reset condition Power On Reset / Read

Description

V_CCAundervoltage detection

0

No undervoltage (V_CCA> V_{CCA_UV})

V_{CCA_UV}

1

Undervoltage detected (V_CCA< V_{CCA_UV})

Reset condition Power On Reset

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7.3.15 Diag CAN1

Table 46. DIAG CAN1 register description

Read

bit15

0

bit14

0

bit13

1

bit12

0

bit11

0

bit10

0

bit9

1

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

MOSI

MISO

CAN_d

ominan

t

RXD_r TXD_d

ecessiv ominan

CAN_

G

Vpre_ Vcore_ Vother CANH_ CANH_ CANL_ CANL_

s_G batt gnd batt gnd

SPI_G

WU

LIN_G

IO_G

0

G

e

t

Table 47. Diag CAN1. description and configuration of the bits (default value in bold)

Description

CANH short-circuit to battery detection

No failure

0

CANH_batt

CANH_gnd

1

Failure detected

Reset condition Power On Reset / Read

Description

CANH short-circuit to GND detection

0

No failure

1

Failure detected

Reset condition Power On Reset / Read

Description

CANL short-circuit to battery detection

0

No failure

CANL_batt

1

Failure detected

Reset condition Power On Reset / Read

Description

CANL short-circuit to GND detection

0

No failure

CANL_gnd

1

Failure detected

Reset condition Power On Reset / Read

Description

CAN Bus dominant clamping detection

0

No failure

CAN_dominant

RXD_recessive

TXD_dominant

1

Failure detected

Reset condition Power On Reset / Read

Description

RXD recessive clamping detection (short-circuit to 5.0 V)

0

No failure

1

Failure detected

Reset condition Power On Reset / Read

Description

TXD dominant clamping detection (short-circuit to GND)

0

No failure

1

Failure detected

Reset condition Power On Reset / Read

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7.3.16 Diag CAN_LIN

Table 48. DIAG CAN_LIN register description

Read

bit15

0

bit14

0

bit13

1

bit12

0

bit11

0

bit10

1

bit9

0

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

MOSI

MISO

TXDL_

domina

nt

RXDL_

recessi

ve

Vcore_ Vothers LIN_do

G

LIN_O

T

CAN_O CAN_O

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

0

_G

minant

T

C

Table 49. Diag CAN_LIN. description and configuration of the bits (default value in bold)

Description

LIN bus dominant clamping detection

No failure

0

LIN_dominant

TXDL_dominant

RXDL_recessive

LIN_OT

1

Failure detected

Reset condition Power On Reset / Read

Description

LIN TXD dominant clamping detection (short-circuit to GND)

0

No failure

1

Failure detected

Reset condition Power On Reset / Read

Description

LIN RXD recessive clamping detection (short-circuit to 5.0 V)

0

No failure

1

Failure detected

Reset condition Power On Reset / Read

Description

LIN overtemperature detection

No failure

0

1

Failure detected

Reset condition Power On Reset / Read

Description

CAN overtemperature detection

No failure

0

CAN_OT

1

Failure detected

Reset condition Power On Reset / Read

Description

CAN overcurrent detection

No failure

0

CAN_OC

1

Failure detected

Reset condition Power On Reset / Read

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7.3.17 Diag SPI

Table 50. DIAG SPI register description

Read

bit15

0

bit14

0

bit13

1

bit12

0

bit11

0

bit10

1

bit9

1

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

MOSI

MISO

Vcore_ Vothers

G

SPI_re

q

SPI_pa

rity

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

SPI_err

0

SPI_clk

0

_G

Table 51. Diag SPI. description and configuration of the bits (default value in bold)

Description

Secured SPI communication check

No error

0

SPI_err

SPI_CLK

SPI_req

1

Error detected in the secured bits

Reset condition Power On Reset / Read

Description

SCLK error detection

0

16 clock cycles during NCS low

Wrong number of clock cycles (<16 or > 16)

1

Reset condition Power On Reset / Read

Description

Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address)

0

No error

1

SPI violation

Reset condition Power On Reset / Read

Description

SPI parity bit error detection

Parity bit OK

0

SPI_parity

1

Parity bit error

Reset condition Power On Reset / Read

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7.3.18 Mode

Table 52. Mode register description

Write

bit15

1

bit14

0

bit13

1

bit12

0

bit11

1

bit10

0

bit9

1

bit8

P

bit7

0

bit6

0

bit5

bit4

bit3

bit2

bit1

bit0

Goto_L INT_re Secure Secure Secure Secure

POFF quest _3 _2 _1 _0

MOSI

MISO

Vcore_ Vothers Reserv Reserv Reserv Reserv

G

Reserv Reserv

ed

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

INIT Normal

_G

ed

Read

MOSI

bit15

0

bit14

0

bit13

1

bit12

0

bit11

1

bit10

0

bit9

1

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

INIT

Vcore_ Vothers Reserv Reserv Reserv Reserv

Reserv Reserv

MISO

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

Normal

G

_G

ed

Table 53. Mode. description and configuration of the bits (default value in bold)

Description

Configure the device in Low Power mode V_REGOFF (LPOFF)

0

No action

Goto_LPOFF

1

LPOFF mode

Reset condition Power On Reset

Description

Report if INIT mode of the main logic state machine is entered

0

Not in INIT mode

INIT

1

INIT MODE

Reset condition Power On Reset

Description

Report if Normal mode of the main logic state machine is entered

0

Not in Normal mode

Normal

1

Normal mode

Reset condition Power On Reset

Description

Request for an INT pulse

0

1

No Request

INT_request

Secure 3:0

Request for an INT pulse

Reset condition Power On Reset

Description Secured bits based on write bits

secured_3 = NOT(bit5)

Secured_2 = NOT(bit4)

Secured_1 = bit7

Secured_0 = bit6

7.3.19 Vreg mode

Table 54. VREG mode register description

Write

bit15

bit14

bit13

bit12

bit11

bit10

bit9

bit8

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

33907/33908

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Table 54. VREG mode register description

Vcore_ Vcca_ Vaux_ Vcan_ Secure Secure Secure Secure

EN EN EN EN _3 _2 _1 _0

MOSI

1

0

1

0

1

0

P

CAN_

G

Vpre_ Vcore_ Vother Reserv Reserv Reserv Reserv Vcore_ Vcca_ Vaux_ Vcan_

MISO

SPI_G

WU

LIN_G

IO_G

G

s_G

ed

EN

Read

MOSI

bit15

0

bit14

0

bit13

1

bit12

0

bit11

1

bit10

1

bit9

0

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

CAN_

G

Vpre_ Vcore_ Vother Reserv Reserv Reserv Reserv Vcore_ Vcca_ Vaux_ Vcan_

MISO

SPI_G

WU

LIN_G

IO_G

G

s_G

ed

EN

Table 55. VREG mode. description and configuration of the bits (default value in bold)

Description

V_COREcontrol (Switch OFF NOT recommended if V_COREis SAFETY critical)

0

DISABLED

V_{CORE_EN}

V_{CCA_EN}

V_{AUX_EN}

V_{CAN_EN}

Secure 3:0

1

ENABLED

Reset condition Power On Reset

Description

V_CCAcontrol (Switch OFF NOT recommended if V_CCAis SAFETY critical)

0

DISABLED

1

ENABLED

Reset condition Power On Reset

Description

V_AUXcontrol (Switch OFF NOT recommended if V_AUXis SAFETY critical)

0

DISABLED

1

ENABLED

Reset condition Power On Reset

Description

V_CANcontrol

DISABLED

ENABLED

0

1

Reset condition Power On Reset

Description Secured bits based on write bits

secured_3 = NOT(bit5)

Secured_2 = NOT(bit4)

Secured_1 = bit7

Secured_0 = bit6

7.3.20 IO_OUT-AMUX

Table 56. IO_OUT-AMUX register description

Write

bit15

1

bit14

0

bit13

1

bit12

0

bit11

1

bit10

1

bit9

1

bit8

P

bit7

bit6

bit5

bit4

bit3

0

bit2

bit1

bit0

IO_out IO_out IO_out IO_out

_4_EN _4 _5_EN _5

Amux_ Amux_ Amux_

MOSI

MISO

2

1

0

Vcore_ Vothers IO_out IO_oou IO_out IO_out Reserv Amux_ Amux_ Amux_

G

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

_G

_4_EN

t_4

_5_EN

_5

ed

2

1

0

33907/33908

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NXP Semiconductors

Table 56. IO_OUT-AMUX register description

Read

bit15

0

bit14

0

bit13

1

bit12

0

bit11

1

bit10

1

bit9

1

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

MOSI

MISO

Vcore_ Vothers IO_out IO_out IO_out IO_out Reserv Amux_ Amux_ Amux_

G

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

_G

_4_EN

_4

_5_EN

_5

ed

2

1

0

Table 57. IO_OUT-AMUX. description and configuration of the bits (default value in bold)

Description

Enable the output gate driver capability for IO_4

High-impedance (IO_4 configured as input)

ENABLED (IO_4 configured as output gate driver)

0

IO_out_4_EN

IO_out_4

1

Reset condition Power On Reset

Description

Configure IO_4 output gate driver state

0

LOW

1

HIGH

Reset condition Power On Reset

Description

Enable the output gate driver capability for IO_5

0

High-impedance (IO_5 configured as input)

IO_out_5_EN

IO_out_5

1

ENABLED (IO_5 configured as output gate driver)

Reset condition Power On Reset

Description

Configure IO_5 output gate driver state

0

LOW

1

HIGH

Reset condition Power On Reset

Description

000

Select AMUX output

Vref

001

Vsns wide range

IO_0 wide range

IO_1 wide range

Vsns tight range

IO_0 tight range

IO_1 tight range

Die Temperature Sensor

010

011

AMUX_2:0

100

101

110

111

Reset condition Power On Reset

7.3.21 CAN_LIN mode

Table 58. CAN_LIN mode register description

Write

bit15

1

bit14

0

bit13

1

bit12

1

bit11

0

bit10

0

bit9

0

bit8

P

bit7

bit6

bit5

bit4

bit3

bit2

bit1

0

bit0

0

CAN_ CAN_

mode_ mode_

CAN_a LIN_m LIN_m LIN_au

uto_dis ode_1 ode_0 to_dis

MOSI

1

0

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Table 58. CAN_LIN mode register description

CAN_ CAN_

mode_ mode_

LIN_wu

CAN_a LIN_m LIN_m LIN_au CAN_w

CAN_

G

Vpre_ Vcore_ Vother

MISO SPI_G

WU

LIN_G

IO_G

G

s_G

uto_dis ode_1 ode_0 to_dis

u

1

0

Read

bit15

bit14

0

bit13

1

bit12

1

bit11

0

bit10

0

bit9

0

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

MOSI

0

CAN_ CAN_

mode_ mode_

LIN_wu

CAN_

G

Vpre_ Vcore_ Vother

s_G

CAN_a LIN_m LIN_m LIN_au CAN_w

uto_dis ode_1 ode_0 to_dis

MISO SPI_G

WU

LIN_G

IO_G

G

u

1

0

Table 59. CAN_LIN mode. description and configuration of the bits (default value in bold)

Description

Configure the CAN mode

Sleep / NO wake-up capability

LISTEN ONLY

00

01

10

11

CAN_mode_1:0

CAN_auto_dis

LIN_mode_1:0

Sleep / Wake-up capability

Normal operation mode

Reset condition Power On Reset

Description

Automatic CAN Tx disable

NO auto disable

Reset CAN_mode from “11” to “01” on CAN over temp or TXD dominant or RXD recessive event

0

1

Reset condition Power On Reset

Description

Configure the LIN mode

00

01

10

11

Sleep / NO wake-up capability

LISTEN ONLY

Sleep / Wake-up capability

Normal operation mode

Reset condition Power On Reset

Description

Automatic LIN Tx Disable

0

No Auto disable

LIN_auto_dis

CAN_wu

1

Reset LIN_mode from “11” to “01” on LIN over temp or TXDL dominant or RXDL recessive event

Reset condition

Description

Report a wake-up event from the CAN

No wake-up

0

1

Wake-up detected

Reset condition Power On Reset / Read

Description

Report a wake-up event from the LIN

0

No wake-up

LIN_WU

1

Wake-up detected

Reset condition Power On Reset / Read

Notes

33. CAN mode is automatically configured to “sleep + wake-up capability[10]” if CAN mode was different than “sleep + no wake-up capability [00]”

before the device enters in LPOFF. After LPOFF, the initial CAN mode prior to enter LPOFF is restored.

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7.3.22 Can_Mode_2

Table 60. CAN_MODE_2 register description

Write

bit15

1

bit14

0

bit13

1

bit12

1

bit11

0

bit10

0

bit9

1

bit8

P

bit7

0

bit6

0

bit5

0

bit4

bit3

bit2

bit1

bit0

Vcan_

OV_Mo

n

secure secure secure secure

_3

MOSI

MISO

_2

_1

_0

Vcan_

OV_Mo

n

Vcore_ Vothers

G

Reserv Reserv Reserv

ed

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

0

_G

ed

Read

MOSI

bit15

0

bit14

0

bit13

1

bit12

1

bit11

0

bit10

0

bit9

1

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

Vcan_

OV_Mo

n

Vcore_ Vothers

Reserv Reserv Reserv

MISO

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

0

G

_G

ed

Table 61. CAN_MODE_2. description and configuration of the bits (default value in bold)

Description

VCAN OV Monitoring

0

OFF. V_CANOV is not monitored. Flag is ignored

Vcan_OV_Mon

Secure 3:0

1

ON. V_CANOV flag is under monitoring. In case of OV the V_CANregulator is switched OFF.

Reset condition Power On Reset

Description Secured bits based on write bits

Secured_3 = NOT(bit5)

Secured_2 = NOT(bit4)

Secured_1 = bit7

Secured_0 = bit6

7.3.23 INIT SUPERVISOR1

Table 62. INIT SUPERVISOR1 register description

Write

bit15

1

bit14

1

bit13

0

bit12

0

bit11

0

bit10

0

bit9

1

bit8

P

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Vcore_ Vcore_ Vcca_F Vcca_F secure Secure Secure Secure

FS1 FS_0 S_1 S_0 _3 _2 _1 _0

MOSI

MISO

Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS Vcore_ Vcore_ Vcca_F Vcca_F

G

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

_G

_err

_CLK

_Req _Parity FS1

FS_0

S_1

S_0

Read

MOSI

bit15

0

bit14

1

bit13

0

bit12

0

bit11

0

bit10

0

bit9

1

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

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Table 62. INIT SUPERVISOR1 register description

Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS Vcore_ Vcore_ Vcca_F Vcca_F

MISO

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

G

_G

_err

_CLK

_Req _Parity FS1

FS_0

S_1

S_0

Table 63. INIT SUPERVISOR1. description and configuration of the bits (default value in bold)

Description

00

V

_COREsafety input.

No effect of V_{CORE_FB_OV}and V_{CORE_FB_UV}on RSTb and FSxx

_{CORE_FB_OV}DOES HAVE an impact on RSTb and FSxx. V_{CORE_FB_UV}DOES HAVE an impact on RSTb

V

only

01

Vcore_FS1:0

10

V

_{CORE_FB_OV}DOES HAVE an impact on RSTb and FSxx. No effect of V_{CORE_FB_UV}on RSTb and FSxx

11

Both V_{CORE_FB_OV}and _{VCORE_FB_UV}DO HAVE an impact on RSTb and FSxx

Reset condition Power On Reset

Description

V_CCAsafety input.

00

01

10

11

No effect of V_{CCA_OV}and V_{CCA_UV}on RSTb and FSxx

V

_{CCA_OV}DOES HAVE an impact on RSTb and FSxx. V_{CCA_UV}DOES HAVE an impact on RSTb only

_{CCA_OV}DOES HAVE an impact on RSTb and FSxx. No effect of V_{CCA_UV}on RSTb and FSxx

Vcca_FS1:0

Both V_{CCA_OV}and V_{CCA_UV}DO HAVE an impact on RSTb and FSxx

Reset condition Power On Reset

Description

Secured bits based on write bits

Secured_3 = NOT(bit5)

Secured_2 = NOT(bit4)

Secured_1 = bit7

Secure3:0

Secured_0 = bit6

Description

Secured SPI communication check, concerns Fail-safe logic only

No error

0

SPI_FS_err

1

Error detected in the secured bits

Reset condition Power On Reset

SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both

main and fail-safe logics. Other errors flagged by the SPI_CLK_ bit

Description

0

16 clock cycles during NCS low

SPI_FS_CLK

1

Wrong number of clock cycles (<16 or >16)

Reset condition Power On Reset

Invalid SPI access (Wrong Write or Read, Write to INIT registers in Normal mode, wrong address), concerns

fail-safe logic only.

Description

0

No error

SPI_FS_Req

1

SPI violation

Reset condition Power On Reset

Description

SPI parity bit error detection, concerns fail-safe logic only

0

Parity bit OK

SPI_FS_Parity

1

Parity bit ERROR

Reset condition Power On Reset

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7.3.24 INIT SUPERVISOR2

Table 64. INIT SUPERVISOR2 register description

Write

bit15

1

bit14

1

bit13

0

bit12

0

bit11

0

bit10

1

bit9

0

bit8

P

bit7

bit6

bit5

0

bit4

bit3

bit2

bit1

bit0

Vaux_F Vaux_F

S1 S_0

Secure Secure Secure Secure

MOSI

MISO

DIS_8s

_3

0

_2

_1

_0

Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS

G

Vaux_F Vaux_F

S1

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

DIS_8s

_G

_err

_CLK

_req _Parity

S_0

Read

MOSI

bit15

0

bit14

1

bit13

0

bit12

0

bit11

0

bit10

1

bit9

0

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS

Vaux_F Vaux_F

MISO

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

0

DIS_8s

G

_G

_err

_CLK

_req _Parity

S1

S_0

Table 65. INIT SUPERVISOR2. description and configuration of the bits (default value in bold)

Description

V_AUXsafety input.

00

01

10

11

No effect of V_{AUX_OV}and V_{AUX_UV}on RSTb and FSxx

V

_{AUX_OV}DOES HAVE an impact on RSTb and FSxx. V_{AUX_UV}DOES HAVE an impact on RSTb only

_{AUX_OV}DOES HAVE an impact on RSTb and FSxx. No effect of V_{AUX_UV}on RSTb and FSxx

Vaux_FS1:0

Both V_{AUX_OV}and V_{AUX_UV}DO HAVE an impact on RSTb and FSxx

Reset condition Power On Reset

Description

Disable the 8.0 s timer used to enter Deep Fail-safe mode

0

ENABLED

DIS_8s

1

DISABLED

Reset condition Power On Reset

Description

Secured bits based on write bits

Secured_3 = NOT(bit5)

Secured_2 = NOT(bit4)

Secured_1 = bit7

Secure3:0

SPI_FS_err

Secured_0 = bit6

Description

Secured SPI communication check, concerns fail-safe logic only.

No error

0

1

Error detected in the secured bits

Reset condition Power On Reset

SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both

main and fail-safe logics. Other errors flagged by SPI_CLK_ bit

Description

0

16 clock cycles during NCS low

SPI_FS_CLK

1

Wrong number of clock cycles (<16 or >16)

Reset condition Power On Reset

33907/33908

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Table 65. INIT SUPERVISOR2. description and configuration of the bits (default value in bold) (continued)

Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns

fail-safe Logic only

Description

0

No error

SPI_FS_Req

1

SPI violation

Reset condition Power On Reset

Description

SPI parity bit error detection, concerns fail-safe logic only

0

Parity bit OK

SPI_FS_Parity

1

Parity bit ERROR

Reset condition Power On Reset

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7.3.25 INIT SUPERVISOR3

Table 66. INIT SUPERVISOR3 register description

Write

bit15

1

bit14

1

bit13

0

bit12

0

bit11

0

bit10

1

bit9

1

bit8

P

bit7

0

bit6

bit5

bit4

0

bit3

bit2

bit1

bit0

Vcca_5 Vaux_5

Secure Secure Secure Secure

MOSI

MISO

D

_3

0

_2

_1

_0

Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS

G

Reserv Vcca_5 Vaux_5

ed

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

_G

_err

_CLK

_req _Parity

D

Read

MOSI

bit15

0

bit14

1

bit13

0

bit12

0

bit11

0

bit10

1

bit9

1

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS

Reserv Vcca_5 Vaux_5

ed

MISO

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

0

G

_G

_err

_CLK

_req _Parity

D

Table 67. INIT SUPERVISOR3. description and configuration of the bits (default value in bold)

Description

Configure the V_CCAundervoltage in degraded mode. Only valid for 5.0 V

Normal 5.0 V undervoltage detection threshold (V_{CCA_UV_5}

Degraded mode, i.e lower undervoltage detection threshold applied (V_{CCA_UV_D}

0

)

V_{CCA_5D}

1

)

Reset condition Power On Reset

Description

Configure the V_AUXundervoltage in degraded mode. Only valid for 5.0 V

Normal 5.0 V undervoltage detection threshold (V_{AUX_UV_5}

Degraded mode, i.e lower undervoltage detection threshold applied (V_{AUX_UV_5D}

0

)

V_{AUX_5D}

1

)

Reset condition Power On Reset

Description

Secured bits based on write bits

Secured_3 = NOT(bit5)

Secured_2= NOT(bit4)

Secured_1=bit7

Secure3:0

SPI_FS_err

Secured_0=bit6

Description

Secured SPI communication check, concerns fail-safe logic only

No error

0

1

Error detected in the secured bits

Reset condition Power On Reset

SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both

main and fail-safe logics. Other errors flagged by the SPI_CLK_ bit

Description

0

16 clock cycles during NCS low

SPI_FS_CLK

SPI_FS_Req

1

Wrong number of clock cycles (<16 or >16)

Reset condition Power On Reset

Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns

fail-safe logic only

Description

0

No error

1

SPI violation

Reset condition Power On Reset

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Table 67. INIT SUPERVISOR3. description and configuration of the bits (default value in bold) (continued)

Description

SPI parity bit error detection, concerns fail-safe logic only

0

Parity bit OK

SPI_FS_Parity

1

Parity bit ERROR

Reset condition Power On Reset

7.3.26 Init FSSM1

Table 68. INIT FSSM1 register description

Write

bit15

1

bit14

1

bit13

0

bit12

0

bit11

1

bit10

0

bit9

0

bit8

P

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

IO_01_ IO_1_F IO_45_ RSTb_l Secure Secure Secure Secure

FS

MOSI

S

FS

ow

_3

_2

_1

_0

SPI_F

S_Parit

y

CAN_

G

Vpre_ Vcore_ Vother SPI_F SPI_F SPI_F

IO_01_ IO_1_F IO_45_ RSTb_l

MISO SPI_G

WU

LIN_G

IO_G

G

s_G

S_err S_CLK S_req

FS

S

FS

ow

Read

bit15

bit14

1

bit13

0

bit12

0

bit11

1

bit10

0

bit9

0

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

MOSI

0

SPI_F

S_Parit

y

CAN_

G

Vpre_ Vcore_ Vother SPI_F SPI_F SPI_F

s_G S_err S_CLK S_req

IO_01_ IO_1_F IO_45_ RSTb_l

FS FS ow

MISO SPI_G

WU

LIN_G

IO_G

G

S

Table 69. INIT FSSM1. description and configuration of the bits (default value in bold)

Description

Configure the couple of IO_1:0 as safety inputs

NOT SAFETY

0

IO_01_FS

IO_1_FS

1

SAFETY CRITICAL

Reset condition Power On Reset

Description

Configure IO_1 as safety inputs

0

NOT SAFETY

1

SAFETY CRITICAL (External resistor bridge monitoring active)

Reset condition Power On Reset

Description

Configure the couple of IO_5:4 as safety inputs

0

NOT SAFETY

IO_45_FS

RSTb_low

1

SAFETY CRITICAL

Reset condition Power On Reset

Description

Configure the Rstb LOW duration time

0

10 ms

1

1.0 ms

Reset condition Power On Reset

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NXP Semiconductors

Table 69. INIT FSSM1. description and configuration of the bits (default value in bold) (continued)

Description

Secured bits based on write bits

Secured_3 = NOT(bit5)

Secured_2 = NOT(bit4)

Secured_1 = bit7

Secure3:0

Secured_0 = bit6

Description

Secured SPI communication check, concerns fail-safe logic only

No error

0

SPI_FS_err

1

Error detected in the secured bits

Reset condition Power On Reset

SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both

main and fail-safe logics. Other errors flagged by the SPI_CLK_ bit

Description

0

16 clock cycles during NCS low

SPI_FS_CLK

1

Wrong number of clock cycles (<16 or >16)

Reset condition Power On Reset

Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns

fail-safe logic only

Description

0

No error

SPI_FS_Req

1

SPI violation

Reset condition Power On Reset

Description

SPI parity bit error detection, concerns fail-safe logic only

0

Parity bit OK

SPI_FS_Parity

1

Parity bit ERROR

Reset condition Power On Reset

7.3.27 Init FSSM2

Table 70. INIT FSSM2 register description

Write

bit15

1

bit14

1

bit13

0

bit12

0

bit11

1

bit10

0

bit9

1

bit8

P

bit7

bit6

bit5

PS

bit4

0

bit3

bit2

bit1

bit0

RSTb_ IO_23_

err_FS FS

Secure Secure Secure Secure

_3

MOSI

MISO

_2

_1

_0

0

Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS RSTb_ IO_23_

G

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

PS

_G

_err

_CLK

_req _Parity err_FS

FS

33907/33908

NXP Semiconductors

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Table 70. INIT FSSM2 register description (continued)

Read

bit15

0

bit14

1

bit13

0

bit12

0

bit11

1

bit10

0

bit9

1

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

MOSI

MISO

Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS RSTb_ IO_23_

G

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

PS

0

_G

_err

_CLK

_req _Parity err_FS

FS

Table 71. INIT FSSM2. description and configuration of the bits (default value in bold)

Description

Configure the couple of IO_3:2 as safety inputs for FCCU monitoring

0

NOT SAFETY

IO_23_FS

RSTb_err_FS

PS

1

SAFETY CRITICAL

Reset condition Power On Reset

Description

Configure the values of the RSTb error counter

0

intermediate = 3; final = 6

1

intermediate = 1; final = 2

Reset condition Power On Reset

Description

Configure the F_CCUpolarity

0

Fccu_eaout_1:0 active HIGH

1

Fccu_eaout_1:0 active LOW

Reset condition Power On Reset

Description

Secured bits based on write bits

Secured_3 = NOT(bit5)

Secured_2 = NOT(bit4)

Secured_1 = bit7

Secure3:0

SPI_FS_err

Secured_0 = bit6

Description

Secured SPI communication check, concerns fail-safe logic only

No error

0

1

Error detected in the secured bits

Reset condition Power On Reset

SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both

main and fail-safe logics. Other errors flagged by SPI_CLK_ bit

Description

0

16 clock cycles during NCS low

SPI_FS_CLK

1

Wrong number of clock cycles (<16 or >16)

Reset condition Power On Reset

Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns

fail-safe Logic only

Description

0

No error

SPI_FS_Req

1

SPI violation

Reset condition Power On Reset

Description

SPI parity bit error detection, concerns fail-safe logic only

0

Parity bit OK

SPI_FS_Parity

1

Parity bit ERROR

Reset condition Power On Reset

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7.3.28 WD window

Table 72. WD window register description

Write

bit15

1

bit14

1

bit13

0

bit12

0

bit11

1

bit10

1

bit9

0

bit8

P

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

WD_wi WD_wi WD_wi WD_wi Secure Secure Secure Secure

ndow3 ndow2 ndow1 ndow0 _3 _2 _1 _0

MOSI

MISO

Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS WD_wi WD_wi WD_wi WD_wi

G

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

_G

_err

_CLK

_req _Parity ndow3 ndow2 ndow1 ndow0

Read

MOSI

bit15

0

bit14

1

bit13

0

bit12

0

bit11

1

bit10

1

bit9

0

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS WD_wi WD_wi WD_wi WD_wi

MISO

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

G

_G

_err

_CLK

_req _Parity ndow3 ndow2 ndow1 ndow0

Any WRITE command to the WD_window in the Normal mode must be followed by a READ command to verify the correct change of the WD window

duration

Table 73. WD window. description and configuration of the bits (default value in bold)

Description

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Configure the watchdog window duration. Duty cycle if set to 50%

DISABLE

1.0 ms

2.0 ms

3.0 ms

4.0 ms

6.0 ms

8.0 ms

12 ms

WD_Window_3:0

16 ms

24 ms

32 ms

64 ms

128 ms

256 ms

512 ms

1024 ms

Reset condition Power On Reset

Description Secured bits based on write bits

Secured_3 = NOT(bit5)

Secured_2 = NOT(bit4)

Secured_1 = bit7

Secure3:0

Secured_0 = bit6

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Table 73. WD window. description and configuration of the bits (default value in bold) (continued)

Description

Secured SPI communication check, concerns fail-safe logic only

No error

0

SPI_FS_err

1

Error detected in the secured bits

Reset condition Power On Reset

SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both

main and fail-safe logics. Other errors flagged by the SPI_CLK bit.

Description

0

16 clock cycles during NCS low

SPI_FS_CLK

1

Wrong number of clock cycles (<16 or >16)

Reset condition Power On Reset

Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns

fail-safe logic only

Description

0

No error

SPI_FS_Req

1

SPI violation

Reset condition Power On Reset

Description

SPI parity bit error detection, concerns fail-safe logic only

0

Parity bit OK

SPI_FS_Parity

1

Parity bit ERROR

Reset condition Power On Reset

7.3.29 WD_LFSR

Table 74. WD LFSR register description

Write

bit15

1

bit14

1

bit13

0

bit12

0

bit11

1

bit10

1

bit9

1

bit8

P

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF

SR_7 SR_6 SR_5 SR_4 SR_3 SR_2 SR_1 SR_0

MOSI

MISO

CAN_

G

Vpre_ Vcore_ Vother WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF

G

SPI_G

WU

LIN_G

IO_G

G

s_G

SR_7 SR_6 SR_5 SR_4 SR_3 SR_2 SR_1 SR_0

Read

MOSI

bit15

0

bit14

1

bit13

0

bit12

0

bit11

1

bit10

1

bit9

1

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

CAN_

G

Vpre_ Vcore_ Vother WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF

s_G SR_7 SR_6 SR_5 SR_4 SR_3 SR_2 SR_1 SR_0

MISO

SPI_G

WU

LIN_G

IO_G

G

Table 75. WD LFSR. description and configuration of the bits

Description

WD 8 bits LFSR value. Used to write the seed at any time

0...

1...

WD_LFSR_7:0

bit7:bit0: 10110010 default value at start-up or after a Power on reset: 0xB2 ^{(34), (35)}

Reset condition Power On Reset

Notes

34. Value Bit7:Bit0: 1111 1111 is prohibited.

35. During a write command, MISO reports the previous register content.

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7.3.30 WD answer

Table 76. WD answer register description

Write

bit15

1

bit14

1

bit13

0

bit12

1

bit11

0

bit10

0

bit9

0

bit8

P

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

WD_an WD_an WD_an WD_an WD_an WD_an WD_an WD_an

swer_7 swer_6 swer_5 swer_4 swer_3 swer_2 swer_1 swer_0

MOSI

MISO

Vcore_ Vothers

G

IO_FS_

G

FS_EC FS_reg

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

RSTb

FS0

WD

FS0_G

0

_G

C

_Ecc

Read

MOSI

bit15

0

bit14

1

bit13

0

bit12

1

bit11

0

bit10

0

bit9

0

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

Vcore_ Vothers

IO_FS_

G

FS_EC FS_reg

MISO

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

RSTb

FS0

WD

FS0_G

0

G

_G

C

_Ecc

Table 77. WD answer. description and configuration of the bits (default value in bold)

Description

WD answer from the MCU

0...

1...

WD_answer_7:0

Answer = (NOT(((LFSR x 4)+6)-4))/4

Reset condition Power On Reset / RSTb LOW

Description

Report a reset event

No Reset

0

RSTb

1

Reset occurred

Reset condition Power On Reset / Read

Description

Report a fail-safe event

No fail-safe

0

FS0b

1

Fail safe event occurred / Also default state at power-up after LPOFF as FS0b is asserted low

Reset condition Power On Reset / Read

Description

Report a watchdog refresh ERROR

0

WD refresh OK

WD

1

WRONG WD refresh

Reset condition Power On Reset / Read

Description

Report a fail-safe output failure

0

No failure

FS0_G

1

Failure

Reset condition Power On Reset / Read

Description

Report an IO monitoring error

No error

0

IO_FS_G

1

Error detected

Reset condition Power On Reset

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107

Table 77. WD answer. description and configuration of the bits (default value in bold) (continued)

Description

Report an error code correction on fail-safe state machine

0

No ECC

FS_ECC

1

ECC done

Reset condition Power On Reset / Read

Description

Report an error code correction on fail-safe registers

0

No ECC

FS_req_ECC

1

ECC done

Reset condition Power On Reset / Read

FS0_G = RSTB_short_high or FS0B_short_high or FS0B_short_low

IO_FS_G = IO_01_fail or IO_1_fail or IO_23_fail or IO_45_fail

Values of the three registers WD_answer, WD_counter, and DIAG_FS2 are updated at the end of any SPI access to one of these

registers. To always get up to date values, it is recommended to make two consecutive SPI accesses to these registers. Example: read

WD_answer, read again WD_answer, read WD_counter, read DIAG_FS2. The first read updates the three registers and the second read

report the latest information.

7.3.31 Fail-safe out (FS_out)

Table 78. Fail-safe out register description

Write

bit15

1

bit14

1

bit13

0

bit12

1

bit11

0

bit10

0

bit9

1

bit8

P

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

FS_out FS_out FS_out FS_out FS_out FS_out FS_out FS_out

MOSI

MISO

_7

0

_6

0

_5

0

_4

0

_3

0

_2

0

_1

0

_0

0

Vcore_ Vothers

G

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

_G

Table 79. Fail-safe out. description and configuration of the bits

Description

Secured 8 bits word to release the FS0b

0...

FS_out_7:0

1...

Depend on LFSR_out value and calculation

Power On Reset -> Default = 00h

Reset condition

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7.3.32 RSTB request

Table 80. RSTB request register description

Write

bit15

1

bit14

1

bit13

0

bit12

1

bit11

0

bit10

1

bit9

0

bit8

P

bit7

0

bit6

0

bit5

bit4

0

bit3

bit2

bit1

bit0

RSTb_r

equest

Secure Secure Secure Secure

MOSI

MISO

_3

0

_2

0

_1

0

_0

0

Vcore_ Vothers

G

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

0

_G

Table 81. RSTB request. description and configuration of the bits (default value in bold)

Description

Request a RSTb low pulse

No request

0

RSTb_request

Secure3:0

1

Request a RSTb low pulse

Reset condition Power On Reset / When RSTb done

Description

Secured bits based on write bits

Secured_3 = NOT(bit5)

Secured_2 = NOT(bit4)

Secured_1 = bit7

Secured_0 = bit6

7.3.33 INIT_WD

Table 82. INIT WD register description

Write

bit15

1

bit14

1

bit13

0

bit12

1

bit11

0

bit10

1

bit9

1

bit8

P

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

WD_C WD_C WD_C WD_C

NT_err NT_err NT_refr NT_refr

or_1

secure secure secure secure

3

MOSI

MISO

2

1

0

or_0

esh_1 esh_0

SPI_F WD_C WD_C WD_C WD_C

S_Parit NT_err NT_err NT_refr NT_refr

CAN_

G

Vpre_ Vcore_ Vother SPI_F SPI_F SPI_F

G

SPI_G

WU

LIN_G IO_G

G

s_G

S_err S_CLK S_Req

y

or_1

or_0

esh_1 esh_0

Read

MOSI

bit15

0

bit14

1

bit13

0

bit12

1

bit11

0

bit10

1

bit9

1

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

SPI_F WD_C WD_C WD_C WD_C

S_Parit NT_err NT_err NT_refr NT_refr

CAN_

G

Vpre_ Vcore_ Vother SPI_F SPI_F SPI_F

s_G S_err S_CLK S_Req

MISO

SPI_G

WU

LIN_G IO_G

G

y

or_1

or_0

esh_1 esh_0

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109

Table 83. INIT WD. description and configuration of the bits (default value in bold)

Description

Configure the maximum value of the WD error counter

00

01

10

11

6

4

2

WD_CNT_error_1:0

Reset Condition Power On Reset

Description

Configure the maximum value of the WD refresh counter

00

01

10

11

6

4

2

1

WD_CNT_refresh_

1:0

Reset Condition Power On Reset

Description

Secured bits based on write bits

Secured_3 = NOT(bit5)

Secured_2 = NOT(bit4)

Secured_1 = bit7

Secure3:0

Secured_0 = bit6

Description

Secured SPI communication check, concerns fail-safe logic only

No error

0

SPI_FS_err

1

Error detected in the secured bits

Reset condition Power On Reset

SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both

main and fail-safe logics. Other errors flagged by the SPI_CLK bit.

Description

0

16 clock cycles during NCS low

SPI_FS_CLK

1

Wrong number of clock cycles (<16 or >16)

Reset condition Power On Reset

Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns

fail-safe logic only

Description

0

No error

SPI_FS_Req

1

SPI violation

Reset condition Power On Reset

Description

SPI parity bit error detection, concerns fail-safe logic only

0

Parity bit OK

SPI_FS_Parity

1

Parity bit ERROR

Reset condition Power On Reset

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7.3.34 Diag FS1

Table 84. DIAG FS1 register description

Read

bit15

0

bit14

1

bit13

0

bit12

1

bit11

1

bit10

0

bit9

0

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

MOSI

MISO

Vcore_ Vothers RSTb_ RSTb_

G

FS0b_ FS0b_

diag_1 diag_0

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

0

_G

ext

diag

Table 85. Diag FS1. description and configuration of the bits (default value in bold)

Description

Report a RSTb short-circuit to HIGH

No Failure

0

RSTb_diag

RSTb_ext

1

Short-circuit HIGH

Reset condition Power On Reset / Read

Description

Report an external RSTb

No external RSTb

External RSTb

0

1

Reset condition Power On Reset / Read

Description

Report a failure on FS0b

No Failure

00

01

1X

FS0b_diag_1:0

Short-circuit LOW / open load

Short-circuit HIGH

Reset condition Power On Reset / Read

7.3.35 WD counter

Table 86. WD counter register description

Read

bit15 bit14 bit13 bit12 bit11 bit10

bit9

1

bit8

0

bit7

0

bit6

0

bit5

0

bit4

bit3

0

bit2

bit1

bit0

0

MOSI

MISO

0

1

0

1

0

SPI_

G

CAN_ LIN_

Vpre_ Vcore_ Vothers_ WD_err WD_err WD_err

WD_ref WD_refr WD_refr

resh_2 esh_1 esh_0

WU

IO_G

0

G

_2

_1

_0

33907/33908

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111

Table 87. WD counter. description and configuration of the bits (default value in bold)

Description

000

Report the value of the watchdog error counter

WD_err_2:0

From 0 to 5 (6 generates a Reset and this counter is reset to 0)

to 110

Reset condition

Description

000

Power On Reset

Report the value of the watchdog refresh counter

WD_refresh_2:0

From 0 to 6 (7 generate a decrease of the RST_err_cnt and this counter is reset to 0)

Power On Reset

to 111

Reset condition

7.3.36 Diag FS2

Table 88. DIAG FS2 register description

Read

bit15

0

bit14

1

bit13

0

bit12

1

bit11

1

bit10

1

bit9

0

bit8

0

bit7

0

bit6

0

bit5

0

bit4

0

bit3

0

bit2

0

bit1

0

bit0

0

MOSI

MISO

Vcore_ Vothers RSTb_ RSTb_ RSTb_

G

IO_45_ IO_23_ IO_1_F IO_01_

fail fail ail fail

SPI_G

WU CAN_G LIN_G IO_G Vpre_G

0

_G

err_2

err_1

err_0

Table 89. Diag FS2. description and configuration of the bits (default value in bold)

Description

Report the value of the RSTb error counter

000

001

…

RSTb_err_2:0

Error counter is set to 1 by default

110

Reset condition Power On Reset

Description

Report an error in the IO_45 protocol

0

No error

IO_45_fail

IO_23_fail

IO_1_fail

1

Error detected

Reset condition Power On Reset / Read

Description

Report an error in the FCCU protocol

0

No error

1

Error detected

Reset condition Power On Reset / Read

Description

Report an error in the IO_1 monitoring (external resistor string monitoring)

0

No error

1

Error detected

Reset condition Power On Reset

Description

Report an error in the IO_01 protocol

0

No error

IO_01_fail

1

Error detected

Reset condition Power On Reset / Read

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8

List of interruptions and description

The INTB output pin generates a low pulse when an Interrupt condition occurs. The INTB behavior as well as the pulse duration are set

through the SPI during INIT phase. It is possible to mask some Interruption source (see Detail of register mapping).

Table 90. Interruptions list

Event

Description

V_{SNS_UV}

V_{SUP_UV_7}

I_PFF

Detection of V_BATTERYbelow 8.5 V

Detection of V_SUPbelow 7.0 V (after reverse current protection diode)

Input power feed forward. Based on V_SUPand I_{PRE_PEAK}

Pre-regulator Current Limitation

I_{LIM_PRE}

T_{WARN_PRE}

BoB

Temperature warning on the pass transistor

Return the running state of V_PREconverter (Buck or Boost mode)

Return the activation state of V_PREDC/DC converter

Report a V_PREovervoltage detection

V

_{PRE_STATE}(V_{PRE_SMPS_EN})

_PREOV

_PREUV

Report a V_PREundervoltage detection

I_{LIM_CORE}

V_CORECurrent limitation

T_{WARN_CORE}

Temperature warning on the pass transistor

Return the activation state of V_COREDC/DC converter

Report a V_COREovervoltage detection

V

_{CORE_STATE}(V_{CORE_SMPS_EN}

_COREOV

)

_COREUV

Report a V_COREundervoltage detection

V_CCACurrent limitation

I_{LIM_CCA}

T_{WARN_CCA}

TSD_VCCA

Temperature warning on the pass transistor (Internal Pass transistor only)

Temperature shutdown of the VCCA

I_{LIM_CCA_OFF}

Current limitation maximum duration expiration. Only used when external PNP connected.

Report a V_CCAovervoltage detection

V

_CCAOV

_CCAUV

Report a V_CCAundervoltage detection

I_{LIM_AUX}

V_AUXCurrent limitation

I_{LIM_AUX_OFF}

Current limitation maximum duration expiration. Only used when external PNP connected.

Report a V_AUXovervoltage detection

V

_AUXOV

_AUXUV

Report a V_AUXundervoltage detection

TSD_VAUX

I_{LIM_CAN}

Temperature shutdown of the VAUX

V_CANCurrent limitation

V

_CANOV

_CANUV

Report a V_CANovervoltage detection

Report a V_CANundervoltage detection

TSD_CAN

IO_0

Temperature shutdown on the pass transistor. Auto restart when T_J< (TSD_CAN- TSD_{CAN_HYST}).

Report IO_0 digital state change

IO_1

Report IO_1 digital state change

IO_2

Report IO_2 digital state change

IO_3

Report IO_3 digital state change

IO_4

Report IO_4 digital state change

IO_5

Report IO_5 digital state change

IO_0_WU

IO_1_WU

IO_2_WU

Report IO_0 WU event

Report IO_1 WU event

Report IO_2 WU event

33907/33908

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113

Table 90. Interruptions list (continued)

IO_3_WU

Report IO_3 WU event

IO_4_WU

Report IO_4 WU event

IO_5_WU

Report IO_5 WU event

CAN_WU

Report a CAN wake-up event

CAN_OT

CAN overtemperature detection

RXD_recessive

TXD_dominant

CAN_dominant

LIN_WU

CAN RXD recessive clamping detection (short-circuit to 5.0 V)

CAN TXD dominant clamping detection (short circuit to GND)

CAN bus dominant clamping detection

Report a LIN wake-up event

LIN_OT

LN over-temperature detection

RXDL_recessive

TXDL dominant

LIN dominant

INT_Request

SPI_err

LIN RXDL recessive clamping detection (short to high)

LIN TXDL dominant clamping detection (short to GND)

LIN bus dominant clamping detection

MCU request for an Interrupt pulse

Secured SPI communication check

SPI_CLK

Report a wrong number of CLK pulse different than 16 during the NCS low pulse in Main state machine

Invalid SPI access (Wrong write or read, write to INIT registers in normal mode, wrong address)

Report a Parity error in Main state machine

SPI_Req

SPI_Parity

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9

Typical applications

Snubber values must be fine tuned as

linked also to board layout performance

Snubber values must be fine tuned as

linked also to board layout performance

2.2 µH

22 µH

ESR cap.

<10mΩ

Vcore Voltage

ESR cap.

<100mΩ

ESR cap.

<10mΩ

C1

R1

PGND

R3

R4

330pF

PGND

1 µH

PGND

PGND PGND PGND PGND

Vbat

PGND

Capacitors must be close to Vpre pin

PGND

Optional

GND

PGND

To IO_1

GND

VCORE_SNS

FB_CORE

1KΩ

GND

PGND

R4

GND

Optional

VSUP3

COMP_CORE

5.1 kΩ

C2

R2

VSENSE

Optional

VCCA_E

VCCA_B

VCCA

1µF

Vcca_PNP

SELECT pin Configuration for VCCA & VAUX

(R select connected to GND)

ESR cap.

<100mΩ

EMI sup. Capacitor must be connected

closed to load (220nF) and connected to

GND

Vcca Vaux Rselect (KΩ)

Recommended Value

Capacitor closed to

Vcca pin

VAUX_E

VAUX_B

3.3V

5V

3.3V

5V

3.3V

< 7

5.1KΩ +/-5%

12KΩ +/-5%

24KΩ +/-5%

51KΩ +/-5%

Vaux_PNP

GND

5V 10.8 <<13.2

5V 21.6 <<26.4

3.3V 45.9 <<56.1

Connected to Vcca or Vcore

(If connected to Vcore, must be

connected closed to coutx 10µF

ESR cap.

<100mΩ

EMI sup. Capacitor must be connected

closed to load (100nF 100pF) and

connected to GND

VDDIO

+

x 2)

VAUX

Capacitor must be

close to Vaux pin

MOSI

MISO

SCLK

NCS

GND

4

Components selection for Vcore voltage (current range 10mA -> 800mA, DI/DT = 2A/µs)

MCU SPI

GND

1µF

Vcore voltage R3(+/-1%)

R4(+/-1%)

8.06KΩ

R1(+/-5%)

200Ω

510Ω

C1

220pF

680pF

R2(+/-5%)

39KΩ

18KΩ

C2

1nF

150pF

Cout

CAN-5V

SELECT

1.23V

3.3V

4.32KΩ

24.9KΩ

2*10µF

0R

Optional

GND

MUX_OUT

INTB

MCU inputs

MCU Int.

Vbat

RSelect

Resistor must be

close to Select pin

Key on

GND

Vcca (5V or 3.3V), available configurations

5.1 kΩ

Whithout Ext. PNP : 100mA capability +/-1% accuracy for 5V

configuration, +/-1.5% accuracy for 3.3V configuration,

With Ext. PNP : < 200mA +/-2% accuracy

IO_0

IO_1

IO_2

VDDIO

Optional

From 2nd Vcore

resistor bridge

5.1KΩ

GND

With Ext. PNP : 300mA capability +/-3% accuracy

MCU RESET

Optional

RSTB

FCCU monitoring

from Freescale

MCU

VDDIO

or VSUP3

Example of IO

connection and usage

Vaux (5V or 3.3V)

300mA capability +/-3% accuracy

IO_3

IO_4

IO_5

GND

5.1KΩ if connected to VDDIO

>10KΩ if connected to Vsup3

Recommended

connection for IOs not

used in the application

To Fail Safe

circuitry

FS0B

5.1 kΩ

5.1KΩ

Vpre

10KΩ

MUX_OUT (output selected by SPI)

5.1 kΩ

GND

Vsense or

GND

VIO_0 or

VIO_1 or

DEBUG

mode

CANH

DEBUG

Internal 2.5V reference voltage (2.5V +/-1%)

11KΩ

120Ω

GND

RXD

TXD

Ground Connections

PGND ground plane connected to DGND pin

GND ground plane connected to AGND and GND_COM pins

MCU CAN

CANL

LIN

VSUP3

PGND (DGND) and GND (AGND & GND_COM) connected together far from

PGND ground plane.

TXDL

RXDL

MCU LIN

LIN BUS

GNDA

GND

GND_COM

GND

DGND

PGND

Figure 58. 33907/33908 simplified application schematic with non-inverting buck-boost configuration

33907/33908

33907L_08L

Optional

VAUX_E

VAUX_B

VCCA_E

VCCA_B

VCCA

Vcca_PNP

Vaux_PNP

ESR cap.

<100 mΩ

ESR cap.

<100 mΩ

VAUX

GND

RSelect

SELECT

GND

Figure 59. V

/V

connection

AUX CCA

33907/33908

NXP Semiconductors

115

VPRE

33907/33908

33907L_08L

Optional

VAUX_E

VAUX_B

VCCA_E

VCCA_B

VCCA

Vcca_PNP

NC

ESR cap.

<100 mΩ

NC

VAUX

GND

RSelect

SELECT

Figure 60. VCCA connection, V

not used

AUX

VPRE

33907/33908

33907L_8L

VAUX_E

VAUX_B

VCCA_E

NC

VCCA_B

VCCA

NC

ESR cap.

<100 mΩ

VAUX

GND

RSelect

SELECT

Figure 61. V

not used, V

configuration up to 100 mA

AUX

CCA

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NXP Semiconductors

10

Packaging

10.1

Package mechanical dimensions

Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and

perform a keyword search for the drawing’s document number.

Table 91. Package mechanical dimensions

Package

Suffix

Package outline drawing number

7.0 x 7.0, 48-Pin LQFP Exposed Pad, with 0.5 mm

pitch, and a 4.5 x 4.5 exposed pad

AE

98ASA00173D

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References

The following are URLs where you can obtain information on related NXP products and application solutions

NXP.com support

Description

URL

pages

MC33907_08 System Basis Chip:

AN4766

AN4661

Recommendations for PCB layout and external https://www.nxp.com/webapp/Download?colCode=AN4766

components

Designing the VCORE Compensation Network

http://www.nxp.com/files/analog/doc/app_note/AN4661.pdf

For The MC33907/MC33908 System Basis Chips

Integrating the MPC5643L and MC33907/08 for

http://www.nxp.com/files/analog/doc/app_note/AN4442.pdf

Safety Applications

AN4442

AN4388

Quad Flat Package (QFP)

http://www.nxp.com/files/analog/doc/app_note/AN4388.pdf

http://www.nxp.com/webapp/sps/site/

prod_summary.jsp?code=MC33908&fpsp=1&tab=Design_Tools_Tab

Power Dissipation Tool (Excel file)

MC33907_8SMUG

FMEDA

MC33907_8 Safety Manual - User Guide

https://www.nxp.com/webapp/Download?colCode=MC33907_8SMUG

Upon demand

MC33907_8 FMEDA

Evaluation Board

http://www.nxp.com/webapp/sps/site/

prod_summary.jsp?code=KIT33907LAEEVB

KIT33907LAEEVB

KIT33908LAEEVB

http://www.nxp.com/webapp/sps/site/

prod_summary.jsp?code=KIT33908LAEEVB

Evaluation Board

http://www.nxp.com/webapp/sps/site/

prod_summary.jsp?code=KITMPC5643DBEVM

KITMPC5643DBEVM Evaluation Daughter Board (Qorivva MPC5643L)

MC33907 Product Summary Page

MC33908 Product Summary Page

Analog Home Page

http://www.nxp.com/webapp/sps/site/prod_summary.jsp?code=MC33907

http://www.nxp.com/webapp/sps/site/prod_summary.jsp?code=MC33908

http://www.nxp.com/analog

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Revision history

Revision

Date

Description of changes

11/2014

12/2014

•

Product Preview release

1.0

Initial release. No change to content.

•

Corrected WD_LFSR register access in read mode

Added

Added clarifications after Table 77

Correct minor typographic errors

Changed document status to Advance Information

Changed the document order number to MC33907-MC33908D2

(35)

2.0

3.0

1/2015

2/2015

•

Corrected Revision History

Corrected typo for ICORE_LIM

•

Updated V

max. value from 8.2 to 8.0 V in Table 4

SUP_UV_7

Updated Thermal Resistance values in Table 3

Changed Thermal Resistance Junction to Case Top value from 14.4 to 24.2 in Table 3 on page 10

Corrected a typo on page 46 (changed “For V

and V

5.0 V” to “For V

and V

5.0 V”)

SUP

AUX

CCA

AUX

4.0

5.0

Corrected typo for V

in Table 4 on page 20

BUS_CNT

Corrected typo for D2 and D3 in Table 5 on page 25

8/2016

•

Updated to NXP document form and style

10/2016

Corrected format (default values in bold) of the default SPI register values to match Data sheet Rev. 4.0, 2/2015

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Information in this document is provided solely to enable system and software implementers to use NXP products.

There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits

based on the information in this document. NXP reserves the right to make changes without further notice to any

products herein.

How to Reach Us:

Home Page:

NXP.com

Web Support:

http://www.nxp.com/support

NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular

purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical"

parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications,

and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each

customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor

the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the

following address:

http://www.nxp.com/terms-of-use.html.

NXP, the NXP logo, Freescale, the Freescale logo, SafeAssure, the SafeAssure logo, the Energy Efficient logo, and

SMARTMOS are trademarks of NXP B.V. All other product or service names are the property of their respective

Document Number: MC33907-MC33908D2

Rev. 5.0

10/2016


型号：	MC33908NAE
厂家：	NXP
描述：	System Basis Chip, CAN ONLY, 5V , 1.5A VCORE, QFP 48, Tray
文件：	总123页 (文件大小：1390K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC33908NAE [NXP]

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