MPC93H51FA_技术文档

MPC93H51

Rev 4, 10/2004

Freescale Semiconductor

Technical Data

Low Voltage PLL Clock Driver

MPC93H51

The MPC93H51 is a 3.3 V compatible, PLL based clock generator targeted for

high performance clock distribution systems. With output frequencies of up to

240 MHz and a maximum output skew of 150 ps the MPC93H51 is an ideal

solution for the most demanding clock tree designs. The device offers 9 low skew

clock outputs. Each is configurable to support the clocking needs of the various

high-performance microprocessors including the PowerQuicc II integrated

communication microprocessor. The devices employs a fully differential PLL

design to minimize cycle-to-cycle and long-term jitter.

LOW VOLTAGE 3.3 V

PLL CLOCK GENERATOR

Features

•

9 outputs LVCMOS PLL clock generator

25 – 240 MHz output frequency range

Fully integrated PLL

Compatible to various microprocessors such as PowerQuicc II

Supports networking, telecommunications and computer applications

Configurable outputs: divide-by-2, 4 and 8 of VCO frequency

LVPECL and LVCMOS compatible inputs

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-03

External feedback enables zero-delay configurations

Output enable/disable and static test mode (PLL enable/disable)

Low skew characteristics: maximum 150 ps output-to-output

32-lead LQFP package

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-03

32-lead Pb-free Package Available

Ambient Temperature Range 0°C to +70°C

Pin & Function Compatible with the MPC951

Functional Description

The MPC93H51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal oper-

ation of the MPC93H51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback path.

The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected

to match the VCO frequency range. With available output dividers of divide-by-4 and divide-by-8, the internal VCO of the

MPC93H51 is running at either 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is

either one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using the

FSELA, FSELB, FSELC and FSELD pins, respectively. The available output-to-input frequency ratios are 4:1, 2:1, 1:1, 1:2 and

1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input (TCLK).

The MPC93H51 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode,

the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended for system

diagnostics, test and debug purpose. This test mode is fully static, and the minimum clock frequency specification does not apply.

The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes the PLL to loose

lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase locked loop, also

enabling the PLL to recover to normal operation. The MPC93H51 is 3.3 V compatible and requires no external loop filter compo-

nents. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the

capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the MPC93H51 outputs

can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a 7x7 mm²32-lead LQFP

package.

Application Information

The fully integrated PLL of the MPC93H51 allows the low skew outputs to lock onto a clock input and distribute it with essen-

tially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset

between the outputs and the reference signal.

This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

(pullup)

PCLK

0

1

0

1

0

1

÷ 2

÷ 4

÷ 8

PLL

Ref

FB

(pulldown)

D

Q

QA

QB

TCLK

(pulldown)

REF_SEL

EXT_FB

0

1

200–480 MHz

(pullup)

PLL_EN

QC0

QC1

0

1

(pulldown)

FSELA

FSELB

(pulldown)

QD0

FSELC

FSELD

QD1

QD2

QD3

QD4

0

1

(pulldown)

OE

The MPC93H51 requires an external RC filter for the analog power supply pin V . Please see APPLICATIONS INFORMATION for details.

CCA

Figure 1. MPC93H51 Logic Diagram

24 23 22 21 20 19 18 17

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

QD2

GND

QB

V

CCO

QD3

GND

QD4

V

CCO

QA

MPC93H51

GND

TCLK

V

CCO

PLL_EN

REF_SEL

OE

PCLK

1

2

3

4

5

6

7

8

Figure 2. Pinout: 32-Lead LQFP Package Pinout (Top View)

MPC93H51

Advanced Clock Drivers Device Data

Freescale Semiconductor

2

Table 1. Pin Description

I/O

Type

LVPECL

Function

PCLK, PCLK

Input

Differential clock reference

Low voltage positive ECL input

TCLK

Input

LVCMOS

Single ended reference clock signal or test clock

Feedback signal input, connect to a QA, QB, QC, QD output

Selects input reference clock

Output A divider selection

EXT_FB

REF_SEL

FSELA

FSELB

FSELC

FSELD

OE

Input

Output B divider selection

Input

Outputs C divider selection

Outputs D divider selection

Output enable/disable

Input

QA

Output

Supply

Bank A clock output

QB

Bank B clock output

QC0, QC1

QD0 – QD4

Bank C clock outputs

Bank D clock outputs1.5

V

Positive power supply for the PLL

Positive power supply for I/O and core

Negative power supply

CCA

CC

GND

Ground

Table 2. Function Table

Control

REF_SEL

PLL_EN

Default

0

1

0

1

Selects PCLK as reference clock

Selects TCLK as reference clock

Test mode with PLL disabled. The input clock is PLL enabled. The VCO output is routed to the

directly routed to the output dividers

Outputs enabled

output dividers

OE

0

Outputs disabled, PLL loop is open

VCO is forced to its minimum frequency

FSELA

FSELB

FSELC

FSELD

0

QA = VCO ÷ 2

QB = VCO ÷ 4

QC = VCO ÷ 4

QD = VCO ÷ 4

QA = VCO ÷ 4

QB = VCO ÷ 8

QC = VCO ÷ 8

QD = VCO ÷ 8

Table 3. Absolute Maximum Ratings⁽¹⁾

Symbol

Characteristics

Min

–0.3

Max

Unit

V

Condition

V

Supply Voltage

3.9

CC

V

DC Input Voltage

DC Output Voltage

DC Input Current

DC Output Current

Storage Temperature

V

+0.3

V

IN

CC

V

+0.3

V

OUT

I

±20

mA

°C

IN

I

±50

OUT

T

–65

150

S

1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these

conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated

conditions is not implied.

MPC93H51

Advanced Clock Drivers Device Data

Freescale Semiconductor

3

Table 4. General Specifications

Symbol

Characteristics

Min

Typ

÷ 2

Max

Unit

V

Condition

V

Output Termination Voltage

ESD (Machine Model)

ESD (Human Body Model)

Latch-Up

V

TT

CC

MM

HBM

LU

200

2000

200

V

mA

pF

C

Power Dissipation Capacitance

Input Capacitance

10

Per output

Inputs

PD

C

4.0

IN

Table 5. DC Characteristics (V_CC= 3.3 V ± 5%, T_A= 0° to 70°C)

Symbol

Characteristics

Min

Typ

Max

+ 0.3

CC

Unit

V

Condition

V

Input High Voltage

Input Low Voltage

2.0

V

LVCMOS

LVPECL

IH

V

0.8

V

IL

V

Peak-to-Peak Input Voltage

Common Mode Range

Output High Voltage

PCLK, PCLK

250

1.0

2.4

mV

V

PP

(1)

V

-0.6

CC

CMR

(2)

V

I

= –24 mA

OH

V

Output Low Voltage

0.55

0.30

V

I

= 24 mA

= 12 mA

OL

Z

Output Impedance

7 – 10

Ω

OUT

I

Input Leakage Current

±150

12.0

14.0

µA

mA

V

= V or GND

CC

IN

I

Maximum PLL Supply Current

Maximum Quiescent Supply Current

6.0

CCA

CCQ

I

10.0

All V Pins

CC

1. V

(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V

range

CMR

and the input swing lies within the V (DC) specification.

PP

2. The MPC93H51 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated

transmission line to a termination voltage of V . Alternatively, the device drives up to two 50 Ω series terminated transmission lines.

TT

MPC93H51

Advanced Clock Drivers Device Data

4

Freescale Semiconductor

Table 6. AC Characteristics (V_CC= 3.3 V ± 5%, T_A= 0° to 70°C)⁽¹⁾

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

(2)

f

Input Frequency

÷ 4 feedback

÷ 8 feedback

Static test mode

50

25

0

120

60

300

MHz PLL_EN = 1

MHz PLL_EN = 0

ref

f

VCO Frequency

200

480

MHz

VCO

MAX

(2)

Maximum Output Frequency

÷ 2 output

÷ 4 output

÷ 8 output

100

50

25

240

120

60

MHz

f

Reference Input Duty Cycle

Peak-to-Peak Input Voltage

Common Mode Range

25

500

1.2

75

%

refDC

V

PCLK, PCLK

1000

mV LVPECL

PP

(3)

V

-0.9

CC

V

LVPECL

CMR

(4)

t , t

TCLK Input Rise/Fall Time

1.0

ns

0.8 to 2.0 V

r

f

t

Propagation Delay (static phase offset)

TCLK to EXT_FB

(∅)

–150

0

+150

+250

ps

PLL locked

PCLK to EXT_FB

t

Output-to-Output Skew

Output Duty Cycle

300

ps

sk(o)

DC

100 – 240 MHz

50 – 120 MHz

25 – 60 MHz

45

47.5

48.75

50

55

52.5

51.75

%

t , t

Output Rise/Fall Time

Output Disable Time

Output Enable Time

0.1

1.0

ns

0.55 to 2.4 V

r

f

t

7.0

PLZ, HZ

6.0

PZL, ZH

BW

PLL closed loop bandwidth

÷ 2 feedback

÷ 4 feedback

÷ 8 feedback

9.0 – 20.0

3.0 – 9.5

1.2 – 2.1

MHz -3 db point of

MHz PLL transfer

characteristic

t

Cycle-to-cycle jitter

Single Output Frequency Configuration

÷ 4 feedback

40

25

ps

RMS value

JIT(CC)

t

Period Jitter

Single Output Frequency Configuration

÷ 4 feedback

ps

JIT(PER)

t

I/O Phase Jitter

30

5

ps

JIT(∅)

t

Maximum PLL Lock Time

ms

LOCK

1. AC characteristics apply for parallel output termination of 50 Ω to V

TT.

2. The PLL will be unstable with a divide by 2 feedback ratio.

3. V

(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V

range

CMR

and the input swing lies within the V (AC) specification. Violation of V

or V impacts static phase offset t

.

PP

CMR

PP

(∅)

4. The MPC93H51 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t , can only be guaranteed if

(∅)

t /t are within the specified range.

r

f

MPC93H51

Advanced Clock Drivers Device Data

Freescale Semiconductor

5

APPLICATIONS INFORMATION

The output division settings establish the output

Programming the MPC93H51

relationship. In addition, it must be ensured that the VCO will

be stable given the frequency of the outputs desired. The

feedback frequency should be used to situate the VCO into a

frequency range in which the PLL will be stable. The design

of the PLL supports output frequencies from 25 MHz to

240 MHz while the VCO frequency range is specified from

200 MHz to 480 MHz and should not be exceeded for stable

operation.

The MPC93H51 clock driver outputs can be configured

into several divider modes. In addition, the external feedback

of the device allows for flexibility in establishing various input-

to-output frequency relationships. The output divider of the

four output groups allows the user to configure the outputs

into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even

dividers ensure that the output duty cycle is always 50%.

Table 7 illustrates the various output configurations. The

table describes the outputs using the input clock frequency

CLK as a reference.

Table 7. Output Frequency Relationship⁽¹⁾for an Example Configuration

Inputs

Outputs

FSELA

FSELB

FSELC

FSELD

QA

QB

CLK

QC

QD

CLK

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2 * CLK

4 * CLK

2 * CLK

4 * CLK

CLK

CLK ÷ 2

2* CLK

CLK

2 * CLK

CLK ÷ 2

CLK

CLK ÷ 2

2 * CLK

CLK

CLK ÷ 2

2 * CLK

CLK

2 * CLK

CLK

2 * CLK

CLK ÷ 2

CLK

CLK ÷ 2

2 * CLK

CLK

2 * CLK

CLK

1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB.

Using the MPC93H51 in Zero-Delay Applications

the output-to-output skew (t_SK(O)relative to the feedback

output.

Nested clock trees are typical applications for the

MPC93H51. For these applications the MPC93H51 offers a

differential LVPECL clock input pair as a PLL reference. This

allows for the use of differential LVPECL primary clock

distribution devices such as the Freescale Semiconductor

MC100EP111 or MC10EP222, taking advantage of its

superior low-skew performance. Clock trees using LVPECL

for clock distribution and the MPC93H51 as LVCMOS PLL

fanout buffer with zero insertion delay will show significantly

lower clock skew than clock distributions developed from

CMOS fanout buffers.

fref = 100 MHz

QA

TCLK

2 x 100 MHz

QB

REF_SEL

QC0

QC1

1

PLL_EN

FSELA

FSELB

FSELC

FSELD

1

0

QD0

QD1

QD2

QD3

4 x 100 MHz

The external feedback option of the MPC93H51 PLL

allows for its use as a zero delay buffer. The PLL aligns the

feedback clock output edge with the clock input reference

edge and virtually eliminates the propagation delay through

the device.

QD4

Ext_FB

MPC93H51

100 MHz (Feedback)

The remaining insertion delay (skew error) of the

MPC93H51 in zero-delay applications is measured between

the reference clock input and any output. This effective delay

consists of the static phase offset (SPO or t_(∅)), I/O jitter

(t_JIT(∅), phase or long-term jitter), feedback path delay and

Figure 3. MPC93H51 Zero-Delay Configuration

(Feedback of QD4)

MPC93H51

Advanced Clock Drivers Device Data

Freescale Semiconductor

6

Calculation of Part-to-Part Skew

the lowest VCO frequency (200 MHz for the MPC93H51).

Applications using a higher VCO frequency exhibit less I/O

jitter than the AC characteristic limit. The I/O jitter

characteristics in Figure 5 can be used to derive a smaller

I/O jitter number at the specific VCO frequency, resulting in

tighter timing limits in zero-delay mode and for part-to-part

The MPC93H51 zero delay buffer supports applications

where critical clock signal timing can be maintained across

several devices. If the reference clock inputs (TCLK or PCLK)

of two or more MPC93H51 are connected together, the

maximum overall timing uncertainty from the common TCLK

input to any output is:

skew t_SK(PP)

.

t

_SK(PP)= t_(∅)+ t_SK(O)+ t_{PD, LINE(FB)}+ t_JIT(∅)• CF

Max. I/O Jitter versus Frequency

This maximum timing uncertainty consists of 4

components: static phase offset, output skew, feedback

board trace delay and I/O (phase) jitter:

30

25

20

TCLK

15

Common

t

PD,LINE(FB)

—t

(∅)

10

5

QFB

Device 1

t

JIT(∅)

0

200

225

250 275

300

325

350

375

400

Any Q

Device 1

+t

SK(O)

VCO frequency [MHz]

Figure 5. Maximum I/O Jitter (RSM)

versus Frequency for V_CC= 3.3 V

+t

(∅)

QFB

Device2

Power Supply Filtering

t

JIT(∅)

The MPC93H51 is a mixed analog/digital product. Its

analog circuitry is naturally susceptible to random noise,

especially if this noise is seen on the power supply pins.

Noise on the V_CCA(PLL) power supply impacts the device

characteristics, for instance I/O jitter. The MPC93H51

provides separate power supplies for the output buffers (V_CC

and the phase-locked loop (V_CCA) of the device.The purpose

of this design technique is to isolate the high switching noise

digital outputs from the relatively sensitive internal analog

phase-locked loop. In a digital system environment where it

is more difficult to minimize noise on the power supplies, a

second level of isolation may be required. The simple but

effective form of isolation is a power supply filter on the V_CCA

pin for the MPC93H51.

Any Q

Device 2

+t

SK(O)

Max. skew

t

SK(PP)

)

Figure 4. MPC93H51 Maximum Device-to-Device Skew

Due to the statistical nature of I/O jitter, a RMS value (1 σ)

is specified. I/O jitter numbers for other confidence factors

(CF) can be derived from Table 8.

Table 8. Confidence Factor CF

CF

Probability of Clock Edge within the Distribution

± 1σ

± 2σ

± 3σ

± 4σ

± 5σ

± 6σ

0.68268948

0.95449988

0.99730007

0.99993663

0.99999943

0.99999999

Figure 6 illustrates a typical power supply filter scheme.

The MPC93H51 frequency and phase stability is most

susceptible to noise with spectral content in the 100 kHz to 20

MHz range; therefore, the filter should be designed to target

this range. The key parameter that needs to be met in the

final filter design is the DC voltage drop across the series filter

resistor R_F. From the data sheet the I_CCAcurrent (the current

sourced through the V_CCApin) is typically 6 mA (12 mA

maximum), assuming that a minimum of 3.0 V must be

maintained on the V_CCApin. The resistor R_Fshown

in Figure 6 must have a resistance of 5–15 Ω to meet the

voltage drop criteria.

The feedback trace delay is determined by the board

layout and can be used to fine-tune the effective delay

through each device. In the following example calculation, an

I/O jitter confidence factor of 99.7% (± 3σ) is assumed,

resulting in a worst case timing uncertainty from input to any

output of –251 ps to 351 ps relative to TCLK (V_CC= 3.3 V and

f_VCO= 400 MHz):

t_SK(PP)= [–50ps...150ps] + [–150ps...150ps] +

[(17ps @ –3)...(17ps @ 3)] + t_{PD, LINE(FB)}

t_SK(PP)= [–251ps...351ps] + t_{PD, LINE(FB)}

Above equation uses the maximum I/O jitter number

shown in the AC characteristic table for V_CC= 3.3 V (17 ps

RMS). I/O jitter is frequency dependant with a maximum at

MPC93H51

Advanced Clock Drivers Device Data

Freescale Semiconductor

7

MPC93H51

Output

Buffer

R

F

V

CCA

CC

Z

= 50Ω

22 µF

0.01 µF

O

R = 36Ω

S

MPC93H51

10Ω

OutA

IN

CC

MPC93H51

Output

Buffer

Z

= 50Ω

O

R = 36Ω

S

OutB0

OutB1

Figure 6. V_CCAPower Supply Filter

10Ω

As the noise frequency crosses the series resonant point

of an individual capacitor, its overall impedance begins to

look inductive and thus increases with increasing frequency.

The parallel capacitor combination shown ensures that a low

impedance path to ground exists for frequencies well above

the bandwidth of the PLL. Although the MPC93H51 has

several design features to minimize the susceptibility to

power supply noise (isolated power and grounds and fully

differential PLL), there still may be applications in which

overall performance is being degraded due to system power

supply noise. The power supply filter schemes discussed in

this section should be adequate to eliminate power supply

noise related problems in most designs.

R = 36Ω

S

Figure 7. Single versus Dual Transmission Lines

The waveform plots in Figure 8 show the simulation results

of an output driving a single line versus two lines. In both

cases, the drive capability of the MPC93H51 output buffer is

more than sufficient to drive 50 Ω transmission lines on the

incident edge. Note from the delay measurements in the

simulations, a delta of only 43 ps exists between the two

differently loaded outputs. This suggests that the dual line

driving need not be used exclusively to maintain the tight

output-to-output skew of the MPC93H51. The output

waveform in Figure 8 shows a step in the waveform. This

step is caused by the impedance mismatch seen looking into

the driver. The parallel combination of the 36 Ω series resistor

plus the output impedance does not match the parallel

combination of the line impedances. The voltage wave

launched down the two lines will equal:

Driving Transmission Lines

The MPC93H51 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user, the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of less than 20 Ω, the

drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines the reader is referred to Freescale application note

AN1091. In most high performance clock networks,

point-to-point distribution of signals is the method of choice.

In a point-to-point scheme, either series terminated or parallel

terminated transmission lines can be used. The parallel

technique terminates the signal at the end of the line with a

50 Ω resistance to V_CC÷ 2.

V_L= V_S(Z₀÷ (R_S+ R₀+ Z₀))

Z₀= 50 Ω || 50 Ω

R_S= 36 Ω || 36 Ω

R₀= 14 Ω

V_L= 3.0 (25 ÷ (18 + 17 + 25)

= 1.31 V

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each

output of the MPC93H51 clock driver. For the series

terminated case, however, there is no DC current draw; thus,

the outputs can drive multiple series terminated lines.

Figure 7 illustrates an output driving a single series

terminated line versus two series terminated lines in parallel.

When taken to its extreme the fanout of the MPC93H51 clock

driver is effectively doubled due to its capability to drive

multiple lines.

At the load end, the voltage will double to 2.6 V due to the

near unity reflection coefficient. It will then increment towards

the quiescent 3.0 V in steps separated by one round trip delay

(in this case 4.0 ns).

Since this step is well above the threshold region it will not

cause any false clock triggering; however, designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines, the

situation in Figure 9 should be used. In this case the series

terminating resistors are reduced such that when the parallel

combination is added to the output buffer impedance the line

impedance is perfectly matched.

MPC93H51

Advanced Clock Drivers Device Data

Freescale Semiconductor

8

3.0

2.5

2.0

1.5

1.0

0.5

0

MPC93H51

Output

Buffer

Z

= 50Ω

OutA

t = 3.8956

R = 22Ω

O

S

OutB

t = 3.9386

D

10Ω

R = 22Ω

O

S

In

14Ω + 22Ω || 22Ω = 50Ω || 50Ω

25Ω = 25Ω

Figure 9. Optimized Dual Line Termination

2

4

6

8

10

12

14

TIME (nS)

Figure 8. Single versus Dual Waveforms

MPC93H51 DUT

Pulse

Generator

Z

= 50 Ω

Z

= 50Ω

O

Z = 50Ω

R = 50Ω

T

V

TT

Figure 10. TCLK MPC93H51 AC Test Reference for V_CC= 3.3 V

MPC93H51 DUT

Z

= 50Ω

O

Differential Pulse

Generator

Z

= 50 Ω

O

Z = 50Ω

R = 50 Ω

T

V

TT

V

TT

Figure 11. PCLK MPC93H51 AC Test Reference

MPC93H51

Advanced Clock Drivers Device Data

Freescale Semiconductor

9

PCLK

V

CC

TCLK

÷2

V

CMR

V

CMR

GND

V

CC

÷2

V

÷2

Ext_FB

CC

Ext_FB

GND

t

(∅)

Figure 12. Propagation Delay (t_PD, status phase offset)

Test Reference

Figure 13. Propagation Delay (t_PD) Test Reference

V

CC

V

÷2

V

÷2

CC

GND

t

V

P

CC

V

÷2

CC

T

0

GND

DC = t /T x 100%

P

0

t

SK(O)

The time from the PLL controlled edge to the non controlled edge, divided

by the time between PLL controlled edges, expressed as a percentage

The pin-to-pin skew is defined as the worst case difference in propagation delay

between any similar delay path within a single device

Figure 14. Output Duty Cycle (DC)

Figure 15. Output-to-Output Skew t_SK(O)

T

= |T -T

|

T

= |T -1/f |

N 0

JIT(CC)

N

N+1

JIT(P)

T

N+1

N

T

0

The variation in cycle time of a signal between adjacent cycles, over a random

sample of adjacent cycle pairs

The deviation in cycle time of a signal with respect to the ideal period

over a random sample of cycles

Figure 16. Cycle-to-Cycle Jitter

Figure 17. Period Jitter

TCLK

(PCLK)

V

= 3.3 V

2.4

CC

Ext_FB

0.55

T

= |T -T mean|

0 1

JIT(∅)

t

R

F

The deviation in t for a controlled edge with respect to a t mean

0

in a random sample of cycles

Figure 18. I/O Jitter

Figure 19. Transition Time Test Reference

MPC93H51

10

Advanced Clock Drivers Device Data

Freescale Semiconductor

PACKAGE DIMENSIONS

4X

0.20

H

A-B D

6

D1

3

A, B, D

e/2

D1/2

32

PIN 1 INDEX

1

25

F

A

B

E1/2

6

E1

E

4

DETAIL G

E/2

DETAIL G

8

17

NOTES:

9

7

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES PER

ASME Y14.5M, 1994.

3. DATUMS A, B, AND D TO BE DETERMINED AT

DATUM PLANE H.

D

4

D/2

4X

D

4. DIMENSIONS D AND E TO BE DETERMINED AT

SEATING PLANE C.

0.20

C

A-B D

5. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED

THE MAXIMUM b DIMENSION BY MORE THAN

0.08-mm. DAMBAR CANNOT BE LOCATED ON THE

LOWER RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSION AND ADJACENT LEAD OR

PROTRUSION: 0.07-mm.

H

^28Xe

32X

0.1 C

6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM

PLASTIC BODY SIZE DIMENSIONS INCLUDING

MOLD MISMATCH.

7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.

8. THESE DIMENSIONS APPLY TO THE FLAT

SECTION OF THE LEAD BETWEEN 0.1-mm AND

0.25-mm FROM THE LEAD TIP.

SEATING

PLANE

C

DETAIL AD

BASE

METAL

PLATING

b1

c

c1

MILLIMETERS

DIM

A

A1

A2

b

b1

c

c1

D

MIN

1.40

0.05

1.35

0.30

0.09

MAX

1.60

0.15

1.45

0.45

0.40

0.20

0.16

b

5

8

^8X(θ1˚)

M

0.20

C

A-B

D

R R2

SECTION F-F

R R1

9.00 BSC

D1

e

E

E1

L

L1

q

q1

R1

R2

S

7.00 BSC

0.80 BSC

9.00 BSC

7.00 BSC

A2

A

0.25

GAUGE PLANE

0.50

1.00 REF

0˚ 7˚

12 REF

0.70

(S)

A1

L

θ˚

0.08

0.20

---

(L1)

0.20 REF

DETAIL AD

CASE 873A-03

ISSUE B

32-LEAD LQFP PACKAGE

MPC93H51

Advanced Clock Drivers Device Data

Freescale Semiconductor

11

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

support@freescale.com

USA/Europe or Locations Not Listed:

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Information in this document is provided solely to enable system and software

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LDCForFreescaleSemiconductor@hibbertgroup.com

MPC93H51

Rev. 4

10/2004


型号：	MPC93H51FA
厂家：	NXP
描述：	IC,CPU SYSTEM CLOCK GENERATOR,CMOS,QFP,32PIN,PLASTIC 驱动逻辑集成电路
文件：	总12页 (文件大小：329K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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