MPC93R51FA [NXP]
93R SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32;
| 型号： | MPC93R51FA |
| 厂家： | 
NXP |
| 描述： | 93R SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32 驱动 输出元件 逻辑集成电路 |
| 文件： | 总12页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC93R51
Rev. 4, 1/2005
Freescale Semiconductor
Technical Data
Low Voltage PLL Clock Driver
MPC93R51
The MPC93R51 is a 3.3 V compatible, PLL based clock generator targeted for
high performance clock distribution systems. With output frequencies of up to
240 MHz and a maximum output skew of 150 ps, the MPC93R51 is an ideal
solution for the most demanding clock tree designs. The device offers 9 low skew
clock outputs, each is configurable to support the clocking needs of the various
high-performance microprocessors including the PowerQuicc II integrated
communication microprocessor. The devices employ a fully differential PLL
design to minimize cycle-to-cycle and long-term jitter.
LOW VOLTAGE 3.3 V
PLL CLOCK GENERATOR
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
9 outputs LVCMOS PLL clock generator
25–240 MHz output frequency range
Fully integrated PLL
Compatible to various microprocessors such as PowerQuicc II
Supports networking, telecommunications and computer applications
Configurable outputs: divide-by-2, 4 and 8 of VCO frequency
LVPECL and LVCMOS compatible inputs
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
External feedback enables zero-delay configurations
Output enable/disable and static test mode (PLL enable/disable)
Low skew characteristics: maximum 150 ps output-to-output
Cycle-to-cycle jitter max. 22 ps RMS
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
32-lead LQFP package
32-lead Pb-free Package Available
Ambient Temperature Range 0°C to +70°C
Pin & Function Compatible with the MPC951
Functional Description
The MPC93R51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal
operation of the MPC93R51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback
path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be
selected to match the VCO frequency range. With available output dividers of divide-by-4 and divide-by-8, the internal VCO of
the MPC93R51 is running at either 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs
is either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using
the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2
and 1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input
(TCLK). The MPC93R51 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test
mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended
for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification
does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes
the PLL to loose lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase
locked loop, also enabling the PLL to recover to normal operation. The MPC93R51 is 3.3 V compatible and requires no external
loop filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible
levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the
MPC93R51 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a
7x7 mm2 32-lead LQFP package.
Application Information
The fully integrated PLL of the MPC93R51 allows the low skew outputs to lock onto a clock input and distribute it with
essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase
offset between the outputs and the reference signal.
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Freescale Confidential Proprietary, NDA Required / Preliminary
(Pullup)
PCLK
PCLK
0
1
0
1
÷2
÷4
÷8
0
1
Ref
FB
(Pulldown)
D
D
D
Q
Q
Q
QA
QB
TCLK
PLL
(Pulldown)
(Pulldown)
REF_SEL
EXT_FB
0
1
200 – 480 MHz
(Pullup)
PLL_EN
QC0
QC1
0
1
(Pulldown)
(Pulldown)
(Pulldown)
FSELA
FSELB
QD0
FSELC
FSELD
(Pulldown)
QD1
QD2
QD3
QD4
0
1
D
Q
(Pulldown)
OE
The MPC93R51 requires an external RC filter for the analog power supply pin V
. Please see application section for details.
CCA
Figure 1. MPC93R51 Logic Diagram
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
QD2
GND
QB
15
14
13
12
11
10
9
V
CCO
QD3
GND
QD4
V
CCO
QA
MPC93R51
GND
TCLK
V
CCO
PLL_EN
REF_SEL
OE
PCLK
1
2
3
4
5
6
7
8
Figure 2. Pinout: 32-Lead Package Pinout (Top View)
MPC93R51
Advanced Clock Drivers Devices
Freescale Semiconductor
2
Table 1. Pin Description
Number
Name
Type
LVPECL
Description
PCLK, PCLK
Input
Differential clock reference
Low voltage positive ECL input
Single ended reference clock signal or test clock
Feedback signal input, connect to a QA, QB, QC, QD output
Selects input reference clock
Output A divider selection
TCLK
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
EXT_FB
REF_SEL
FSELA
FSELB
FSELC
FSELD
OE
Input
Input
Input
Input
Output B divider selection
Input
Outputs C divider selection
Outputs D divider selection
Output enable/disable
Input
Input
QA
Output
Output
Output
Output
Supply
Supply
Supply
Bank A clock output
QB
Bank B clock output
QC0, QC1
QD0 – QD4
Bank C clock outputs
Bank D clock outputs
V
V
V
V
Positive power supply for the PLL
Positive power supply for I/O and core
Negative power supply
CCA
CC
CC
CC
GND
Ground
Table 2. Function Table
Control
REF_SEL
PLL_EN
Default
0
1
0
1
Selects PCLK as reference clock
Selects TCLK as reference clock
Test mode with PLL disabled. The input clock is
directly routed to the output dividers
PLL enabled. The VCO output is routed to the
output dividers
OE
0
Outputs enabled
Outputs disabled, PLL loop is open
VCO is forced to its minimum frequency
FSELA
FSELB
FSELC
FSELD
0
0
0
0
QA = VCO ÷ 2
QB = VCO ÷ 4
QC = VCO ÷ 4
QD = VCO ÷ 4
QA = VCO ÷ 4
QB = VCO ÷ 8
QC = VCO ÷ 8
QD = VCO ÷ 8
Table 3. Absolute Maximum Ratings(1)
Symbol
Characteristics
Min
-0.3
-0.3
-0.3
Max
Unit
V
Condition
V
Supply Voltage
4.6
CC
V
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
V
V
+0.3
V
IN
CC
CC
V
+0.3
V
OUT
I
±20
mA
mA
°C
IN
I
±50
OUT
T
Storage Temperature
-55
150
S
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated
conditions is not implied.
MPC93R51
Advanced Clock Drivers Devices
Freescale Semiconductor
3
Table 4. General Specifications
Symbol
Characteristics
Output Termination Voltage
ESD (Machine Model)
ESD (Human Body Model)
Latch-Up
Min
Typ
÷ 2
Max
Unit
V
Condition
V
V
TT
CC
MM
HBM
LU
200
2000
200
V
V
mA
pF
pF
C
Power Dissipation Capacitance
10
Per output
PD
C
4.0
Inputs
IN
Table 5. DC Characteristics (VCC = 3.3 V ± 5%, TA = 0° to 70°C)
Symbol
Characteristics
Input High Voltage
Min
Typ
Max
+ 0.3
CC
Unit
V
Condition
V
2.0
V
LVCMOS
LVCMOS
IH
V
Input Low Voltage
0.8
V
IL
V
Peak-to-Peak Input Voltage
Common Mode Range
Output High Voltage
Output Low Voltage
PCLK, PCLK
PCLK, PCLK
250
1.0
2.4
mV LVPECL
PP
(1)
V
V
–0.6
V
V
LVPECL
CMR
CC
(2)
V
I
= –24 mA
OH
OH
V
0.55
0.30
V
V
I
I
= 24 mA
= 12 mA
OL
OL
OL
Z
Output Impedance
14 –17
Ω
OUT
I
Input Leakage Current
Maximum PLL Supply Current
±150
5.0
µA
mA
V
V
= V or GND
CC
IN
IN
I
3.0
7.0
Pin
CCA
CCA
CCQ
I
Maximum Quiescent Supply Current
10
mA All V Pins
CC
1. V
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
range
CMR
CMR
and the input swing lies within the V (DC) specification.
PP
2. The MPC93R51 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
transmission line to a termination voltage of V . Alternatively, the device drives up to two 50 Ω series terminated transmission lines.
TT
MPC93R51
Advanced Clock Drivers Devices
Freescale Semiconductor
4
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0° to 70°C)(1)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
(2)
f
Input Frequency
÷ 4 feedback
÷ 8 feedback
Static test mode
50
25
0
120
60
300
MHz PLL_EN = 1
MHz PLL_EN = 1
MHz PLL_EN = 0
ref
f
f
VCO Frequency
200
480
MHz
VCO
MAX
2
Maximum Output Frequency
÷ 2 output
÷ 4 output
÷ 8 output
100
50
25
240
120
60
MHz
MHz
MHz
f
Reference Input Duty Cycle
Peak-to-Peak Input Voltage
Common Mode Range
25
500
1.2
75
%
refDC
V
PCLK, PCLK
PCLK, PCLK
1000
mV LVPECL
PP
(3)
V
V
–0.9
CC
V
LVPECL
CMR
(4)
t , t
TCLK Input Rise/Fall Time
1.0
ns
0.8 to 2.0 V
r
f
t
Propagation Delay (static phase offset)
TCLK to EXT_FB
(∅)
-50
+25
+150
+325
ps
ps
PLL locked
PLL locked
PCLK to EXT_FB
t
Output-to-Output Skew
Output Duty Cycle
150
ps
sk(o)
DC
100 – 240 MHz
50 – 120 MHz
25 – 60 MHz
45
47.5
48.75
50
50
50
55
52.5
51.75
%
%
%
t , t
Output Rise/Fall Time
Output Disable Time
Output Enable Time
0.1
1.0
7.0
6.0
ns
ns
ns
0.55 to 2.4 V
r
f
t
t
PLZ, HZ
PZL, ZH
BW
PLL closed loop bandwidth
÷ 4 feedback
÷ 8 feedback
3.0 – 9.5
1.2 – 2.1
MHz –3 db point of
MHz PLL transfer characteristic
t
Cycle-to-cycle jitter
Single Output Frequency Configuration
÷ 4 feedback
10
22
15
ps
ps
RMS value
RMS value
RMS value
JIT(CC)
t
Period Jitter
Single Output Frequency Configuration
÷ 4 feedback
8.0
JIT(PER)
t
I/O Phase Jitter
4.0 – 17
ps
JIT(∅)
t
Maximum PLL Lock Time
1.0
ms
LOCK
1. AC characteristics apply for parallel output termination of 50 Ω to V
TT.
2. The PLL will be unstable with a divide by 2 feedback rati,o
3. V
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
range
CMR
CMR
and the input swing lies within the V (AC) specification. Violation of V
or V impacts static phase offset t
.
PP
CMR
PP
(∅)
4. The MPC93R51 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t , can only be guaranteed if t /t
(∅)
r f
are within the specified range.
MPC93R51
Advanced Clock Drivers Devices
Freescale Semiconductor
5
APPLICATIONS INFORMATION
The output division settings establish the output
Programming the MPC93R51
relationship. In addition, it must be ensured that the VCO will
be stable given the frequency of the outputs desired. The
feedback frequency should be used to situate the VCO into a
frequency range in which the PLL will be stable. The design
of the PLL supports output frequencies from 25 MHz to
240 MHz while the VCO frequency range is specified from
200 MHz to 480 MHz and should not be exceeded for stable
operation.
The MPC93R51 clock driver outputs can be configured
into several divider modes. In addition, the external feedback
of the device allows for flexibility in establishing various input
to output frequency relationships. The output divider of the
four output groups allows the user to configure the outputs
into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even
dividers ensure that the output duty cycle is always 50%.
Table 7 illustrates the various output configurations. The
table describes the outputs using the input clock frequency
CLK as a reference.
Table 7. Output Frequency Relationship(1) for an Example Configuration
Inputs
Outputs
FSELA
FSELB
FSELC
FSELD
QA
QB
CLK
QC
QD
CLK
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2 * CLK
2 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
4 * CLK
4 * CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK ÷ 2
2* CLK
CLK
2 * CLK
2 * CLK
CLK ÷ 2
CLK ÷ 2
CLK
CLK
CLK ÷ 2
2 * CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK ÷ 2
2 * CLK
CLK
2 * CLK
2 * CLK
CLK
2 * CLK
2 * CLK
CLK ÷ 2
CLK ÷ 2
CLK
CLK
CLK
CLK ÷ 2
2 * CLK
CLK
2 * CLK
2 * CLK
CLK
1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB.
Using the MPC93R51 in Zero-Delay Applications
(tJIT(∅), phase or long-term jitter), feedback path delay and
the output-to-output skew (tSK(O) relative to the feedback
output.
Nested clock trees are typical applications for the
MPC93R51. For these applications the MPC93R51 offers a
differential LVPECL clock input pair as a PLL reference. This
allows for the use of differential LVPECL primary clock
distribution devices such as the Freescale MC100EP111 or
MC10EP222, taking advantage of its superior low-skew
performance. Clock trees using LVPECL for clock distribution
and the MPC93R51 as LVCMOS PLL fanout buffer with zero
insertion delay will show significantly lower clock skew than
clock distributions developed from CMOS fanout buffers.
The external feedback option of the MPC93R51 PLL
allows for its use as a zero delay buffer. The PLL aligns the
feedback clock output edge with the clock input reference
edge and virtually eliminates the propagation delay through
the device.
fref = 100 MHz
QA
TCLK
2 x 100 MHz
2 x 100 MHz
QB
REF_SEL
QC0
QC1
1
PLL_EN
FSELA
FSELB
FSELC
FSELD
1
1
0
0
0
QD0
QD1
QD2
QD3
4 x 100 MHz
QD4
Ext_FB
MPC93R51
100 MHz (Feedback)
The remaining insertion delay (skew error) of the
MPC93R51 in zero-delay applications is measured between
the reference clock input and any output. This effective delay
consists of the static phase offset (SPO or t(∅)), I/O jitter
Figure 3. MPC93R51 Zero-Delay Configuration
(Feedback of QD4)
MPC93R51
Advanced Clock Drivers Devices
Freescale Semiconductor
6
Calculation of Part-to-Part Skew
the lowest VCO frequency (200 MHz for the MPC93R51).
Applications using a higher VCO frequency exhibit less I/O
jitter than the AC characteristic limit. The I/O jitter
characteristics in Figure 5 can be used to derive a smaller
I/O jitter number at the specific VCO frequency, resulting in
tighter timing limits in zero-delay mode and for part-to-part
The MPC93R51 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs (TCLK or PCLK)
of two or more MPC93R51 are connected together, the
maximum overall timing uncertainty from the common TCLK
input to any output is:
skew tSK(PP)
.
t
SK(PP) = t(∅) + tSK(O) + tPD, LINE(FB) + tJIT(∅) · CF
Max. I/O Jitter versus frequency
This maximum timing uncertainty consists of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter.
30
25
20
15
10
5
TCLK
Common
t
PD,LINE(FB)
—t
(∅)
QFB
Device 1
Device 1
t
JIT(∅)
0
75
225
250
275 300
325
350
375
400
VCO frequency [MHz]
Any Q
+t
SK(O)
Figure 5. Max. I/O Jitter (RMS) Versus Frequency
for VCC = 3.3 V
+t
(∅)
Power Supply Filtering
QFB
Device2
t
JIT(∅)
The MPC93R51 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Noise on the VCCA (PLL) power supply impacts the device
characteristics, for instance, I/O jitter. The MPC93R51
provides separate power supplies for the output buffers (VCC
Any Q
Device 2
+t
SK(O)
Max. skew
t
)
SK(PP)
and the phase-locked loop (VCCA) of the device. The purpose
of this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies, a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the VCCA
pin for the MPC93R51.
Figure 4. MPC93R51 Max. Device-to-Device Skew
Due to the statistical nature of I/O jitter, a RMS value (1 σ)
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 8.
Table 8. Confidence Factor CF
CF
Probability of clock edge within the distribution
Figure 6 illustrates a typical power supply filter scheme.
The MPC93R51 frequency and phase stability is most
susceptible to noise with spectral content in the 100 kHz to 20
MHz range; therefore, the filter should be designed to target
this range. The key parameter that needs to be met in the
final filter design is the DC voltage drop across the series filter
resistor RF. From the data sheet, the ICCA current (the current
sourced through the VCCA pin) is typically 3 mA (5 mA
maximum), assuming that a minimum of 3.0 V must be
maintained on the VCCA pin. The resistor RF shown in
Figure 6 must have a resistance of 5-15 Ω to meet the
voltage drop criteria.
± 1σ
± 2σ
± 3σ
± 4σ
± 5σ
± 6σ
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation,
an I/O jitter confidence factor of 99.7% (± 3σ) is assumed,
resulting in a worst case timing uncertainty from input to any
output of –251 ps to 351 ps relative to TCLK (VCC = 3.3 V and
f
VCO = 400 MHz):
tSK(PP) = [-50ps...150ps] + [-150ps...150ps] +
[(17ps · –3)...(17ps ·3)] + tPD, LINE(FB)
tSK(PP) = [-251ps...351ps] + tPD, LINE(FB)
Above equation uses the maximum I/O jitter number
shown in the AC characteristic table for VCC = 3.3 V (17 ps
RMS). I/O jitter is frequency dependent with a maximum at
MPC93R51
Advanced Clock Drivers Devices
Freescale Semiconductor
7
R
F
MPC93R51
OUTPUT
BUFFER
V
V
CCA
CC
22 pF
0.1 µF
0.1 µF
MPC93R51
Z
= 50Ω
O
R
R
= 36Ω
S
14Ω
OutA
IN
V
CC
MPC93R51
OUTPUT
BUFFER
Z
Z
= 50Ω
= 50Ω
= 36Ω
= 36Ω
O
S
Figure 6. VCCA Power Supply Filter
OutB0
OutB1
14Ω
As the noise frequency crosses the series resonant point
of an individual capacitor, its overall impedance begins to
look inductive, and thus, increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC93R51 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
IN
O
R
S
Figure 7. Single versus Dual Transmission Lines
The waveform plots in Figure 8 show the simulation results
of an output driving a single line versus two lines. In both
cases, the drive capability of the MPC93R51 output buffer is
more than sufficient to drive 50 Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC93R51. The output
waveform in Figure 8 shows a step in the waveform. This
step is caused by the impedance mismatch seen looking into
the driver. The parallel combination of the 36 Ω series
resistor, plus the output impedance, does not match the
parallel combination of the line impedances. The voltage
wave launched down the two lines will equal:
Driving Transmission Lines
The MPC93R51 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 Ω, the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale application note
AN1091. In most high performance clock networks,
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50 Ω resistance to VCC÷2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC93R51 clock driver. For the series
terminated case, however, there is no DC current draw, thus
the outputs can drive multiple series terminated lines.
Figure 7 illustrates an output driving a single series
terminated line versus two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC93R51 clock
driver is effectively doubled due to its capability to drive
multiple lines.
VL = VS (Z0 ÷ (RS+R0 +Z0))
Z0 = 50 Ω || 50 Ω
RS = 36 Ω || 36 Ω
R0 = 14 Ω
VL = 3.0 (25 ÷ (18+17+25)
= 1.31 V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
MPC93R51
Advanced Clock Drivers Devices
Freescale Semiconductor
8
Since this step is well above the threshold region it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the
situation in Figure 9 should be used. In this case, the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance, the line
impedance is perfectly matched.
3.0
2.5
2.0
1.5
1.0
0.5
0
OutA
= 3.8956
OutB
= 3.9386
t
D
t
D
In
MPC93R51
OUTPUT
Z
= 50Ω
= 50Ω
O
R
= 22Ω
= 22Ω
S
S
BUFFER
14Ω
Z
R
O
2
4
6
8
10
12
14
14Ω + 22Ω || 22Ω = 50Ω || 50Ω
25Ω = 25Ω
TIME (ns)
Figure 8. Single versus Dual Waveforms
Figure 9. Optimized Dual Line Termination
MPC93R51 DUT
Pulse
Generator
Z = 50Ω
Z
= 50Ω
Z = 50Ω
O
O
R
= 50Ω
R = 50Ω
T
T
V
V
TT
TT
Figure 10. TCLK MPC93R51 AC Test Reference for VCC = 3.3 V
MPC93R51 DUT
Z
= 50Ω
O
Differential Pulse
Generator
Z
= 50Ω
O
Z = 50Ω
R = 50Ω
T
R
= 50Ω
T
V
TT
V
TT
Figure 11. PCLK MPC9R351 AC Test Reference
MPC93R51
Advanced Clock Drivers Devices
Freescale Semiconductor
9
PCLK
PCLK
V
V
CC
TCLK
÷ 2
V
CC
CMR
V
CMR
GND
V
V
V
CC
CC
÷ 2
V
÷ 2
Ext_FB
CC
CC
Ext_FB
GND
GND
t
t
(∅)
(∅)
Figure 12. Propagation Delay (tPD, Static Phase
Offset) Test Reference
Figure 13. Propagation Delay (tPD) Test Reference
V
V
V
V
CC
CC
CC
CC
÷ 2
÷ 2
GND
GND
t
P
V
V
CC
CC
÷ 2
T
0
GND
DC = t /T x 100%
P
0
t
SK(O)
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device.
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage.
Figure 14. Output Duty Cycle (DC)
Figure 15. Output-to-Output Skew tSK(O)
T
= |T –T
|
N+1
T
= |T –1/f |
N 0
JIT(CC)
N
JIT(PER)
T
T
N+1
T
N
0
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs.
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles.
Figure 16. Cycle-to-Cycle Jitter
Figure 17. Period Jitter
TCLK
(PCLK)
V
=3.3 V
2.4
CC
Ext_FB
T
= |T –T mean|
0.55
JIT(∅)
0
1
t
t
R
F
The deviation in t for a controlled edge with respect to a t mean
0
0
in a random sample of cycles.
Figure 18. I/O Jitter
Figure 19. Transition Time Test Reference
MPC93R51
10
Advanced Clock Drivers Devices
Freescale Semiconductor
PACKAGE DIMENSIONS
4X
0.20
H
A-B D
6
D1
3
A, B, D
e/2
D1/2
32
PIN 1 INDEX
1
25
F
F
A
B
E1/2
6
E1
E
4
DETAIL G
E/2
DETAIL G
8
17
NOTES:
9
7
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
D
4
D/2
4X
D
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
0.20
C
A-B D
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-mm.
H
28X e
32X
0.1 C
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-mm AND
0.25-mm FROM THE LEAD TIP.
SEATING
PLANE
C
DETAIL AD
BASE
METAL
PLATING
b1
c
c1
MILLIMETERS
DIM
A
A1
A2
b
b1
c
c1
D
MIN
1.40
0.05
1.35
0.30
0.30
0.09
0.09
MAX
1.60
0.15
1.45
0.45
0.40
0.20
0.16
b
5
8
8X (θ1˚)
M
0.20
C
A-B
D
R R2
SECTION F-F
R R1
0.25
9.00 BSC
D1
e
E
E1
L
L1
q
q1
R1
R2
S
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
A2
A
GAUGE PLANE
0.50
1.00 REF
0˚ 7˚
12 REF
0.70
(S)
A1
L
θ˚
0.08
0.08
0.20
---
(L1)
0.20 REF
DETAIL AD
CASE 873A-03
ISSUE B
32-LEAD LQFP PACKAGE
MPC93R51
Advanced Clock Drivers Devices
Freescale Semiconductor
11
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MPC93R51
Rev. 4
1/2005
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