MPC93R51D [MOTOROLA]
LOW VOLTAGE PLL CLOCK DRIVER; 低电压PLL时钟驱动器
| 型号： | MPC93R51D |
| 厂家： | 
MOTOROLA |
| 描述： | LOW VOLTAGE PLL CLOCK DRIVER |
| 文件： | 总12页 (文件大小：296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC93R51/D
Rev 0, 12/2002
The MPC93R51 is a 3.3V compatible, PLL based clock generator
targeted for high performance clock distribution systems. With output
frequencies of up to 240 MHz and a maximum output skew of 150 ps the
MPC93R51 is an ideal solution for the most demanding clock tree
designs. The device offers 9 low skew clock outputs, each is configurable
to support the clocking needs of the various high-performance
microprocessors including the PowerQuicc II integrated communication
microprocessor. The devices employs a fully differential PLL design to
minimize cycle-to-cycle and long-term jitter.
LOW VOLTAGE 3.3V
PLL CLOCK GENERATOR
Features
• 9 outputs LVCMOS PLL clock generator
• 25 - 240 MHz output frequency range
• Fully integrated PLL
• Compatible to various microprocessors such as PowerQuicc II
• Supports networking, telecommunications and computer applications
• Configurable outputs: divide-by-2, 4 and 8 of VCO frequency
• LVPECL and LVCMOS compatible inputs
• External feedback enables zero-delay configurations
• Output enable/disable and static test mode (PLL enable/disable)
• Low skew characteristics: maximum 150 ps output-to-output
• Cycle-to-cycle jitter max. 22 ps RMS
FA SUFFIX
LQFP PACKAGE
CASE 873A–02
• 32 lead LQFP package
• Ambient Temperature Range 0°C to +70°C
• Pin & Function Compatible with the MPC951
Functional Description
The MPC93R51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal
operation of the MPC93R51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback
path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be
selected to match the VCO frequency range. With available output dividers of divide-by-4 and divide-by-8 the internal VCO of the
MPC93R51 is running at either 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is
either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using the
FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and
1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input (TCLK).
The MPC93R51 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the
selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended for system
diagnostics, test and debug purpose. This test mode is fully static and the minimum clock frequency specification does not apply.
The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes the PLL to loose
lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase locked loop, also
enabling the PLL to recover to normal operation. The MPC93R51 is 3.3V compatible and requires no external loop filter
components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible levels
with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC93R51
2
outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a 7x7 mm 32-lead
LQFP package.
Application Information
The fully integrated PLL of the MPC93R51 allows the low skew outputs to lock onto a clock input and distribute it with
essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase
offset between the outputs and the reference signal.
For More Information On This Product,
Motorola, Inc. 2002
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC93R51
(pullup)
PCLK
PCLK
0
0
1
÷2
÷4
÷8
0
1
PLL
Ref
(pulldown)
1
D
D
D
Q
Q
Q
QA
QB
TCLK
(pulldown)
(pulldown)
REF_SEL
EXT_FB
FB
0
1
200 - 480 MHz
(pullup)
PLL_EN
QC0
QC1
0
1
(pulldown)
(pulldown)
(pulldown)
FSELA
FSELB
QD0
FSELC
FSELD
(pulldown)
QD1
QD2
QD3
QD4
0
1
D
Q
(pulldown)
OE
The MPC93R51 requires an external RC filter for the analog power supply pin VCCA. Please see application section for details.
Figure 1. MPC93R51 Logic Diagram
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
QD2
GND
QB
VCCO
QD3
VCCO
QA
GND
QD4
MPC93R51
GND
VCCO
OE
TCLK
PLL_EN
REF_SEL
PCLK
1
2
3
4
5
6
7
8
Figure 2. Pinout: 32–Lead LQFP Package Pinout (Top View)
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MPC93R51
PIN CONFIGURATION
Pin
I/O
Type
LVPECL
Function
PCLK, PCLK
Input
Differential clock reference
Low voltage positive ECL input
TCLK
Input
Input
Input
Input
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Single ended reference clock signal or test clock
Feedback signal input, connect to a QA, QB, QC, QD output
Selects input reference clock
EXT_FB
REF_SEL
FSELA
FSELB
FSELC
FSELD
Output A divider selection
Output B divider selection
Outputs C divider selection
Outputs D divider selection
OE
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
VCC
Output enable/disable
QA
Output
Output
Output
Output
Supply
Supply
Supply
Bank A clock output
QB
Bank B clock output
QC0, QC1
QD0 - QD4
VCCA
VCC
Bank C clock outputs
Bank D clock outputs
Positive power supply for the PLL
Positive power supply for I/O and core
Negative power supply
VCC
GND
Ground
FUNCTION TABLE
Control
Default
0
1
REF_SEL
0
1
Selects PCLK as reference clock
Selects TCLK as reference clock
PLL_EN
Test mode with PLL disabled. The input clock is
directly routed to the output dividers
PLL enabled. The VCO output is routed to the
output dividers
OE
0
Outputs enabled
Outputs disabled, PLL loop is open
VCO is forced to its minimum frequency
FSELA
FSELB
FSELC
FSELD
0
0
0
0
QA = VCO ÷ 2
QB = VCO ÷ 4
QC = VCO ÷ 4
QD = VCO ÷ 4
QA = VCO ÷ 4
QB = VCO ÷ 8
QC = VCO ÷ 8
QD = VCO ÷ 8
a
ABSOLUTE MAXIMUM RATINGS
Symbol
Characteristics
Min
-0.3
-0.3
-0.3
Max
Unit
V
Condition
V
CC
Supply Voltage
4.6
V
IN
DC Input Voltage
V
V
+0.3
V
CC
V
OUT
DC Output Voltage
DC Input Current
+0.3
V
CC
I
IN
±20
mA
mA
°C
I
DC Output Current
Storage Temperature
±50
OUT
T
S
-55
150
a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
GENERAL SPECIFICATIONS
Symbol
Characteristics
Output Termination Voltage
ESD (Machine Model)
ESD (Human Body Model)
Latch–Up
Min
Typ
Max
Unit
V
Condition
V
TT
V
2
CC
MM
HBM
LU
200
2000
200
V
V
mA
pF
pF
C
Power Dissipation Capacitance
10
Per output
Inputs
PD
C
4.0
IN
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MPC93R51
DC CHARACTERISTICS (V
= 3.3V ± 5%, T = –40° to 85°C)
A
CC
Symbol
Characteristics
Input High Voltage
Min
Typ
Max
+ 0.3
Unit
V
Condition
LVCMOS
V
IH
2.0
V
CC
0.8
V
IL
Input Low Voltage
V
LVCMOS
LVPECL
LVPECL
V
PP
Peak-to-Peak Input Voltage
PCLK, PCLK
PCLK, PCLK
250
mV
a
V
CMR
Common Mode Range
Output High Voltage
Output Low Voltage
1.0
2.4
V
-0.6
V
V
CC
b
V
OH
I
=-24 mA
OH
V
OL
0.55
0.30
V
V
I = 24 mA
OL
I = 12 mA
OL
Z
OUT
Output Impedance
14 - 17
I
Input Leakage Current
Maximum PLL Supply Current
±150
5.0
µA
mA
mA
V
V
= V
or GND
IN
IN
CC
Pin
Pins
I
3.0
7.0
CCA
CCQ
CCA
I
Maximum Quiescent Supply Current
10
All V
CC
a.
V
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V range
CMR
CMR
and the input swing lies within the V
(DC) specification.
PP
b. The MPC93R51 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of V . Alternatively, the device drives up to two 50Ω series terminated transmission lines.
TT
a
= 3.3V ± 5%, T = –40° to 85°C)
A
AC CHARACTERISTICS (V
CC
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
b
f
Input Frequency
÷ 4 feedback
÷ 8 feedback
Static test mode
50
25
0
120
60
300
MHz
MHz
MHz
PLL_EN = 1
PLL_EN = 1
PLL_EN = 0
ref
f
f
VCO Frequency
200
480
MHz
VCO
b
Maximum Output Frequency
Reference Input Duty Cycle
÷ 2 output
÷ 4 output
÷ 8 output
100
50
25
240
120
60
MHz
MHz
MHz
MAX
f
25
500
1.2
75
%
refDC
V
Peak-to-Peak Input Voltage PCLK, PCLK
1000
mV
LVPECL
PP
c
V
CMR
Common Mode Range
PCLK, PCLK
V
-0.9
CC
1.0
V
LVPECL
d
tr, tf
TCLK Input Rise/Fall Time
ns
0.8 to 2.0V
t
(
Propagation Delay (static phase offset)
TCLK to EXT_FB
)
–50
+25
+150
+325
ps
ps
PLL locked
PLL locked
PCLK to EXT_FB
t
Output-to-Output Skew
150
ps
sk(o)
DC
Output Duty Cycle
100 – 240 MHz
50 – 120 MHz
25 – 60 MHz
45
47.5
48.75
50
50
50
55
52.5
51.75
%
%
%
t , t
r f
Output Rise/Fall Time
Output Disable Time
Output Enable Time
0.1
1.0
7.0
6.0
ns
ns
ns
0.55 to 2.4V
t
t
PLZ, HZ
PZL, ZH
BW
PLL closed loop bandwidth ÷ 2 feedback
÷ 4 feedback
9.0 – 20.0
3.0 – 9.5
1.2 – 2.1
MHz
MHz
MHz
–3 db point of
PLL transfer
characteristic
÷ 8 feedback
t
Cycle-to-cycle jitter
Single Output Frequency Configuration
÷ 4 feedback
10
22
15
ps
RMS value
RMS value
RMS value
JIT(CC)
t
Period Jitter
Single Output Frequency Configuration
÷ 4 feedback
8.0
ps
JIT(PER)
t
I/O Phase Jitter
4.0 – 17
ps
JIT(
)
t
Maximum PLL Lock Time
1.0
ms
LOCK
a. AC characteristics apply for parallel output termination of 50Ω to V
b. The PLL will be unstable with a divide by 2 feedback ratio.
TT
c.
V
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V range
CMR
CMR
and the input swing lies within the V
(AC) specification. Violation of V
or V
impacts static phase offset t .
( )
PP
CMR
PP
d. The MPC93R51 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t , can only be guaranteed if tr/tf
(
)
are within the specified range.
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MPC93R51
APPLICATIONS INFORMATION
Programming the MPC93R51
frequency CLK as a reference.
The MPC93R51 clock driver outputs can be configured
into several divider modes, in addition the external feedback
of the device allows for flexibility in establishing various input
to output frequency relationships. The output divider of the
four output groups allows the user to configure the outputs
into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even
dividers ensure that the output duty cycle is always 50%.
“Output Frequency Relationship for an Example
Configuration” illustrates the various output configurations,
the table describes the outputs using the input clock
The output division settings establish the output
relationship, in addition, it must be ensured that the VCO will
be stable given the frequency of the outputs desired. The
feedback frequency should be used to situate the VCO into a
frequency range in which the PLL will be stable. The design
of the PLL supports output frequencies from 25 MHz to 240
MHz while the VCO frequency range is specified from 200
MHz to 480 MHz and should not be exceeded for stable
operation.
a
Output Frequency Relationship for an Example Configuration
Inputs
Outputs
FSELA
FSELB
FSELC
FSELD
QA
QB
CLK
QC
QD
CLK
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2 * CLK
2 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
4 * CLK
4 * CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK ÷ 2
2* CLK
CLK
2 * CLK
2 * CLK
CLK ÷ 2
CLK ÷ 2
CLK
CLK
CLK ÷ 2
2 * CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK ÷ 2
2 * CLK
CLK
2 * CLK
2 * CLK
CLK
2 * CLK
2 * CLK
CLK ÷ 2
CLK ÷ 2
CLK
CLK
CLK
CLK ÷ 2
2 * CLK
CLK
2 * CLK
2 * CLK
CLK
a. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB.
Using the MPC93R51 in zero–delay applications
consists of the static phase offset (SPO or t ), I/O jitter
( )
(t
, phase or long-term jitter), feedback path delay and
JIT( )
Nested clock trees are typical applications for the
MPC93R51. For these applications the MPC93R51 offers a
differential LVPECL clock input pair as a PLL reference. This
allows for the use of differential LVPECL primary clock
distribution devices such as the Motorola MC100EP111 or
MC10EP222, taking advantage of its superior low-skew
performance. Clock trees using LVPECL for clock distribution
and the MPC93R51 as LVCMOS PLL fanout buffer with zero
insertion delay will show significantly lower clock skew than
clock distributions developed from CMOS fanout buffers.
the output-to-output skew (t
output.
relative to the feedback
SK(O)
fref = 100 MHz
TCLK
QA
QB
2 x 100 MHz
REF_SEL
QC0
1
2 x 100 MHz
QC1
PLL_EN
FSELA
FSELB
FSELC
FSELD
1
1
0
0
0
QD0
QD1
4 x 100 MHz
QD2
The external feedback option of the MPC93R51 PLL
allows for its use as a zero delay buffer. The PLL aligns the
feedback clock output edge with the clock input reference
edge and virtually eliminates the propagation delay through
the device.
QD3
QD4
Ext_FB
MPC93R51
100 MHz (Feedback)
The remaining insertion delay (skew error) of the
MPC93R51 in zero-delay applications is measured between
the reference clock input and any output. This effective delay
MPC93R51 zero–delay configuration (feedback of QD4)
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MPC93R51
Calculation of part-to-part skew
Above equation uses the maximum I/O jitter number
shown in the AC characteristic table for V =3.3V (17 ps
CC
The MPC93R51 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs (TCLK or PCLK)
of two or more MPC93R51 are connected together, the
maximum overall timing uncertainty from the common TCLK
input to any output is:
RMS). I/O jitter is frequency dependant with a maximum at
the lowest VCO frequency (200 MHz for the MPC93R51).
Applications using a higher VCO frequency exhibit less I/O
jitter than the AC characteristic limit. The I/O jitter
characteristics in Figure 4. can be used to derive a smaller
I/O jitter number at the specific VCO frequency, resulting in
tighter timing limits in zero-delay mode and for part-to-part
t
= t
+ t
+ t
+ t
CF
This maximum timing uncertainty consist of 4
SK(PP)
( )
SK(O)
PD, LINE(FB)
JIT( )
skew t
.
SK(PP)
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
TCLK
Common
t
PD,LINE(FB)
–t
(
)
QFB
Device 1
t
JIT(
)
Any Q
Device 1
+t
SK(O)
+t
(
)
QFB
Device2
t
JIT(
)
Figure 4. Max. I/O Jitter (RMS) versus frequency for
=3.3V
V
CC
Any Q
Device 2
+t
SK(O)
Max. skew
t
SK(PP)
Power Supply Filtering
Figure 3. MPC93R51 max. device-to-device skew
The MPC93R51 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Due to the statistical nature of I/O jitter a RMS value (1 ) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.
Noise on the V
(PLL) power supply impacts the device
CCA
characteristics, for instance I/O jitter. The MPC93R51
provides separate power supplies for the output buffers (V
Table 8: Confidence Facter CF
)
CC
) of the device.The purpose
CF
± 1
± 2
± 3
± 4
± 5
± 6
Probability of clock edge within the distribution
and the phase-locked loop (V
CCA
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
of this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it is
more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the V
pin for the MPC93R51.
CCA
Figure 5. illustrates a typical power supply filter scheme.
The MPC93R51 frequency and phase stability is most
susceptible to noise with spectral content in the 100kHz to
20MHz range. Therefore the filter should be designed to
target this range. The key parameter that needs to be met in
the final filter design is the DC voltage drop across the series
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a
I/O jitter confidence factor of 99.7% (± 3 ) is assumed,
resulting in a worst case timing uncertainty from input to any
output of -251 ps to 351 ps relative to TCLK (V =3.3V and
CC
filter resistor R . From the data sheet the I
current (the
pin) is typically 3 mA (5 mA
f
= 400 MHz):
F
CCA
VCO
current sourced through the V
CCA
maximum), assuming that a minimum of 3.0V must be
maintained on the V pin. The resistor R shown in
t
=
=
[–50ps...150ps] + [–150ps...150ps] +
[(17ps –3)...(17ps 3)] + t
SK(PP)
CCA
F
PD, LINE(FB)
Figure 5. “V
Power Supply Filter” must have a resistance
CCA
t
[–251ps...351ps] + t
PD, LINE(FB)
of 5–15 to meet the voltage drop criteria.
SK(PP)
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MPC93R51
R
F
MPC93R51
OUTPUT
VCCA
VCC
BUFFER
22 pF
0.01 µF
MPC93R51
Z
O
= 50Ω
R = 36Ω
S
14Ω
IN
IN
OutA
VCC
0.01 µF
MPC93R51
OUTPUT
BUFFER
Z
= 50Ω
= 50Ω
O
R = 36Ω
S
OutB0
OutB1
Figure 5. V
Power Supply Filter
CCA
14Ω
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC93R51 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Z
O
R = 36Ω
S
Figure 6. Single versus Dual Transmission Lines
The waveform plots in Figure 7. “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC93R51 output buffer is more than
sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC93R51. The output waveform in Figure 7. “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
Driving Transmission Lines
The MPC93R51 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Motorola application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to V ÷2.
CC
V
Z
R
R
V
= V ( Z ÷ (R +R +Z ))
S 0 S 0 0
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC93R51 clock driver. For the series
terminated case however there is no DC current draw, thus
the outputs can drive multiple series terminated lines.
Figure 6. “Single versus Dual Transmission Lines” illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme
the fanout of the MPC93R51 clock driver is effectively
doubled due to its capability to drive multiple lines.
L
0
S
0
L
= 50Ω || 50Ω
= 36Ω || 36Ω
= 14Ω
= 3.0 ( 25 ÷ (18+17+25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
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MPC93R51
3.0
match the impedances when driving multiple lines the
situation in Figure 8. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is perfectly
matched.
OutA
= 3.8956
OutB
= 3.9386
t
D
2.5
2.0
1.5
1.0
0.5
0
t
D
In
MPC93R51
OUTPUT
Z
O
= 50Ω
= 50Ω
R = 22Ω
S
BUFFER
14Ω
Z
O
R = 22Ω
S
14Ω + 22Ω 22Ω = 50Ω 50Ω
25Ω = 25Ω
2
4
6
8
10
12
14
TIME (nS)
Figure 8. Optimized Dual Line Termination
Figure 7. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
MPC93R51 DUT
Pulse
Generator
Z = 50
Z
O
= 50Ω
Z = 50Ω
O
R = 50Ω
T
R = 50Ω
T
V
TT
V
TT
Figure 9. TCLK MPC93R51 AC test reference for V = 3.3V
cc
MPC93R51 DUT
Z
O
= 50Ω
Differential
Pulse Generator
Z = 50
Z
O
= 50Ω
R = 50Ω
T
R = 50Ω
T
V
TT
V
TT
Figure 10. PCLK MPC93R51 AC test reference
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MPC93R51
V
PCLK
PCLK
CC
TCLK
V
CC
GND
2
2
V
CMR
V
CMR
V
V
CC
V
CC
CC
V
2
Ext_FB
CC
GND
Ext_FB
GND
t
(
)
t
(
)
Figure 11. Propagation delay (t , static phase
PD
Figure 12. Propagation delay (t ) test reference
PD
offset) test reference
V
V
CC
CC
V
CC
GND
2
V
CC
GND
2
2
t
P
V
CC
V
CC
GND
T
0
DC = t /T x 100%
P 0
t
SK(O)
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
The pin–to–pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
Figure 13. Output Duty Cycle (DC)
Figure 14. Output–to–output Skew t
SK(O)
T
= |T –T
N+1
|
T
= |T –1/f |
JIT(CC)
N
JIT(P) N 0
T
N
T
N+1
T
0
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles
Figure 15. Cycle–to–cycle Jitter
Figure 16. Period Jitter
TCLK
(PCLK)
V =3.3V
CC
2.4
0.55
Ext_FB
T
JIT(
= |T –T mean|
0 1
)
t
F
t
R
The deviation in t for a controlled edge with respect to a t mean in a
0
0
random sample of cycles
Figure 17. I/O Jitter
Figure 18. Transition Time Test Reference
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MPC93R51
OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 873A-02
ISSUE A
4X
A
A1
0.20 (0.008) AB T–U Z
32
25
1
–U–
–T–
B
V
AE
AE
P
B1
DETAIL Y
–Z–
V1
17
8
DETAIL Y
9
4X
0.20 (0.008) AC T–U Z
9
NOTES:
S1
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
DETAIL AD
G
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
–AB–
–AC–
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
SEATING
PLANE
0.10 (0.004) AC
BASE
METAL
N
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
F
D
8X M
MILLIMETERS
DIM MIN MAX
7.000 BSC
INCHES
MIN MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
R
J
A
A1
B
3.500 BSC
7.000 BSC
3.500 BSC
1.400 1.600 0.055 0.063
0.300 0.450 0.012 0.018
1.350 1.450 0.053 0.057
0.300 0.400 0.012 0.016
SECTION AE–AE
E
C
B1
C
D
E
F
W
G
H
J
K
M
N
P
0.800 BSC
0.031 BSC
Q
H
K
X
0.050 0.150 0.002 0.006
0.090 0.200 0.004 0.008
0.500 0.700 0.020 0.028
12 REF
0.090 0.160 0.004 0.006
0.400 BSC 0.016 BSC
12 REF
DETAIL AD
Q
R
1
5
1
5
0.150 0.250 0.006 0.010
S
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
S1
V
V1
W
X
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MPC93R51
NOTES
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MPC93R51
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◊
MPC93R51/D
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