MPC961CFA_技术文档

Freescale Semiconductor, Inc.

TECHNICAL DATA

Order number: MPC961C

Rev 2, 08/2004

Low Voltage Zero Delay Buffer

The MPC961 is a 2.5 V or 3.3 V compatible, 1:18 PLL based zero delay

buffer. With output frequencies of up to 200 MHz, output skews of 150 ps the

device meets the needs of the most demanding clock tree applications.

MPC961C

LOW VOLTAGE

ZERO DELAY BUFFER

Features

•

Fully Integrated PLL

Up to 200 MHz I/O Frequency

LVCMOS Outputs

Outputs Disable in High Impedance

LVCMOS Reference Clock Options

LQFP Packaging

32-lead Pb-free Package Available

±50 ps Cycle-Cycle Jitter

150 ps Output Skews

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-03

Functional Description

The MPC961 is offered with two different input configurations. The

MPC961C offers an LVCMOS reference clock while the MPC961P offers

an LVPECL reference clock.

When pulled high the OE pin will force all of the outputs (except QFB) into a high impedance state. Because the OE pin does not

affect the QFB output, down stream clocks can be disabled without the internal PLL losing lock.

The MPC961 is fully 2.5 V or 3.3 V compatible and requires no external loop filter components. All control inputs accept LVCMOS

compatible levels and the outputs provide low impedance LVCMOS outputs capable of driving terminated 50 Ω transmission lines.

For series terminated lines the MPC961 can drive two lines per output giving the device an effective fanout of 1:36. The device is

packaged in a 32 lead LQFP.

Q0

Q1

PLL

CCLK

FB_IN

Ref

FB

100 – 200 MHz

Q2

Q3

50 k

O

1

50– 100 MHz

Q14

Q15

Q16

F_RANGE

OE

50 k

QFB

The MPC961C requires an external RC filter for the analog power supply pin V_CCA. Refer to APPLICATIONS INFORMATION for details.

Figure 1. MPC961C Logic Diagram

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

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MPC961C

24 23 22 21 20 19 18 17

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

V_CC

Q12

Q13

Q14

GND

Q15

Q5

Q4

Q3

GND

Q2

MPC961C

Q1

Q0

Q16

QFB

V_CC

1

2

3

4

5

6

7

8

Figure 2. 32-Lead Pinout (Top View)

Table 1. Pin Configurations

Number

CCLK

Name

Type

LVCMOS

Description

Input

PLL reference clock signal

FB_IN

F_RANGE

OE

Input

LVCMOS

Ground

PLL feedback signal input, connect to a QFB output

PLL frequency range select

Input

Output enable/disable

Q0 – Q16

QFB

Output

Clock outputs

PLL feedback signal output, connect to a FB_IN

Negative power supply

GND

Supply

V_CCA

V_CC

PLL positive power supply (analog power supply). The MPC961C requires an

external RC filter for the analog power supply pin V_CCA. Refer to APPLICATIONS

INFORMATION for details.

V_CC

NC

Supply

V_CC

Positive power supply for I/O and core

Not connected

Table 2. Function Table

Control

Default

0

1

F_RANGE

0

PLL high frequency range. MPC961C input reference and PLL low frequency range. MPC961C input reference and

output clock frequency range is 100 – 200 MHz

output clock frequency range is 50 – 100 MHz

OE

0

Outputs enabled

Outputs disabled (high-impedance state)

484

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

MPC961C

Table 3. Absolute Maximum Ratings¹

Symbol

Characteristics

Min

Max

Unit

Condition

V_CC

Supply Voltage

–0.3

3.6

V

V_IN

DC Input Voltage

–0.3

V_CC+ 0.3

±20

V

V_OUTDC Output Voltage

I_IN

I_OUT

T_S

DC Input Current

mA

°C

DC Output Current

Storage Temperature

±50

–40

125

1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions

or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not

implied.

Table 4. DC Characteristics (V_CC= 3.3 V ± 5%, T_A= –40° to 85°C)

Symbol

Characteristics

Input HIGH Voltage

Min

Typ

Max

Unit

Condition

V_IH

2.0

V_CC+ 0.3

V

LVCMOS

V_IL

Input LOW Voltage

–0.3

2.4

0.8

V

LVCMOS

I_OH= –20 mA¹

I_OL= 20 mA¹

V_OH

Output HIGH Voltage

V_OL

Output LOW Voltage

0.55

V

Z_OUT

I_IN

Output Impedance

14

20

Ω

µA

pF

mA

V

Input Current

±120

C_IN

Input Capacitance

4.0

8.0

2.0

C_PD

I_CCA

I_CC

Power Dissipation Capacitance

Maximum PLL Supply Current

Maximum Quiescent Supply Current

Output Termination Voltage

10

Per Output

V_CCAPin

5.0

All V_CCPins

V_TT

V_CC÷ 2

1. The MPC961C is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission

line to a termination voltage of V_TT. Alternatively, the device drives up two 50 Ω series terminated transmission lines.

Table 5. AC Characteristics (V_CC= 3.3 V ± 5%, T_A= –40° to 85°C)¹

Symbol

Characteristics

Input Frequency

Min

Typ

Max

Unit

Condition

f_REF

F_RANGE = 0

F_RANGE = 1

100

50

200

100

MHz

f_MAX

Maximum Output Frequency F_RANGE = 0

F_RANGE = 1

100

50

200

100

MHz

%

f_REFDCReference Input Duty Cycle

25

75

3.0

120

t_r, t_f

t_(∅)

TCLK Input Rise/Fall Time

ns 0.7 to 1.7 V

Propagation Delay

(static phase offset)

CCLK to FB_IN

–80

ps PLL locked

Output-to-Output Skew²

Output Duty Cycle

t_sk(O)

DC_O

90

150

ps

%

F_RANGE = 0

F_RANGE = 1

40

45

50

60

55

t_r, t_f

Output Rise/Fall Time

Output Disable Time

Output Enable Time

0.1

1.0

10

15

10

15

10

ns 0.6 to 1.8 V

t_{PLZ HZ}

t_{PZL LZ}

t_JIT(CC)

,

ns

ps

ns

ms

,

Cycle-to-Cycle Jitter

RMS (1σ)³

RMS (1σ)

t_JIT(PER)Period Jitter

7.0

t_JIT(∅)

t_lock

I/O Phase Jitter

RMS (1σ)

Maximum PLL Lock Time

1. AC characteristics apply for parallel output termination of 50Ω to V_TT

2. Refer to APPLICATIONS INFORMATION for part-to-part skew calculation.

3. Refer to APPLICATIONS INFORMATION for calculation for other confidence factors than 1 σ.

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

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MPC961C

Table 6. DC Characteristics (V_CC= 2.5 V ± 5%, T_A= –40° to 85°C)

Symbol

Characteristics

Input HIGH Voltage

Min

Typ

Max

Unit

Condition

LVCMOS

V_IH

1.7

V_CC+ 0.3

V

V_IL

Input LOW Voltage

–0.3

1.8

0.7

0.6

V

LVCMOS

I_OH= –15 mA¹

I_OL= 15 mA¹

V_OH

Output HIGH Voltage

V_OL

Output LOW Voltage

V

Z_OUT

I_IN

Output Impedance

18

26

W

µA

pF

Input Current

±120

C_IN

Input Capacitance

4.0

8.0

2.0

C_PD

I_CCA

I_CC

Power Dissipation Capacitance

Maximum PLL Supply Current

Maximum Quiescent Supply Current

Output Termination Voltage

10

pF Per Output

5.0

mA V_CCAPin

mA All V_CCPins

V

V_TT

V_CC÷ 2

1. The MPC961C is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission

line to a termination voltage of V_TT. Alternatively, the device drives up two 50 Ω series terminated transmission lines.

Table 7. AC Characteristics (V_CC= 2.5 V ± 5%, T_A= –40° to 85°C)¹

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

f_REF

Input Frequency

F_RANGE = 0

F_RANGE = 1

100

50

200

100

MHz

f_MAX

Maximum Output Frequency

F_RANGE = 0

F_RANGE = 1

100

50

200

100

MHz

f_REFDC

t_r, t_f

Reference Input Duty Cycle

TCLK Input Rise/Fall Time

25

75

3.0

120

%

ns

ps

0.7 to 1.7 V

t_(∅)

Propagation Delay

(static phase offset)

CCLK to FB_IN

–80

PLL locked

Output-to-Output Skew²

Output Duty Cycle

t_sk(O)

DC_O

90

150

ps

%

F_RANGE = 0

F_RANGE = 1

40

45

50

60

55

t_r, t_f

Output Rise/Fall Time

Output Disable Time

Output Enable Time

0.1

1.0

10

15

10

15

10

ns

0.6 to 1.8 V

t_{PLZ HZ}

t_{PZL LZ}

t_JIT(CC)

,

ns

Cycle-to-Cycle Jitter

RMS (1σ)³

RMS (1σ)

ps

t_JIT(PER)Period Jitter

7.0

ps

t_JIT(∅)

t_lock

I/O Phase Jitter

RMS (1σ)

ns

Maximum PLL Lock Time

Input Frequency

ms

MHz

f_REF

F_RANGE = 0

F_RANGE = 1

100

50

200

100

f_MAX

Maximum Output Frequency

F_RANGE = 0

F_RANGE = 1

100

50

200

100

MHz

1. AC characteristics apply for parallel output termination of 50 Ω to V_TT

2. See APPLICATIONS INFORMATION for part-to-part skew calculation.

3. See APPLICATIONS INFORMATION for calculation for other confidence factors than 1 σ.

.

486

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

MPC961C

APPLICATIONS INFORMATION

schemes discussed in this section should be adequate to

Power Supply Filtering

eliminate power supply noise related problems in most designs.

The MPC961C is a mixed analog/digital product and as such

it exhibits some sensitivities that would not necessarily be seen

on a fully digital product. Analog circuitry is naturally susceptible

to random noise, especially if this noise is seen on the power

supply pins. The MPC961C provides separate power supplies

Driving Transmission Lines

The MPC961C clock driver was designed to drive high speed

signals in a terminated transmission line environment. To

provide the optimum flexibility to the user the output drivers

were designed to exhibit the lowest impedance possible. With

an output impedance of less than 15 Ω the drivers can drive

either parallel or series terminated transmission lines. For more

information on transmission lines the reader is referred to the

Application Note AN1091.

In most high performance clock networks point-to-point

distribution of signals is the method of choice. In a point-to-point

scheme either series terminated or parallel terminated

transmission lines can be used. The parallel technique

terminates the signal at the end of the line with a 50 Ω

resistance to V_CC/2. This technique draws a fairly high level of

DC current and thus only a single terminated line can be driven

by each output of the MPC961C clock driver. For the series

terminated case however there is no DC current draw, thus the

outputs can drive multiple series terminated lines. Figure 4

illustrates an output driving a single series terminated line vs

two series terminated lines in parallel. When taken to its

extreme the fanout of the MPC961C clock driver is effectively

doubled due to its capability to drive multiple lines.

for the output buffers (V_CC) and the phase-locked loop (V_CCA

)

of the device. The purpose of this design technique is to isolate

the high switching noise digital outputs from the relatively

sensitive internal analog phase-locked loop. In a controlled

environment such as an evaluation board this level of isolation

is sufficient. However, in a digital system environment where it

is more difficult to minimize noise on the power supplies, a

second level of isolation may be required. The simplest form of

isolation is a power supply filter on the V_CCApin for the

MPC961C.

Figure 3 illustrates a typical power supply filter scheme. The

MPC961C is most susceptible to noise with spectral content in

the 10 kHz to 10 MHz range. Therefore the filter should be

designed to target this range. The key parameter that needs to

be met in the final filter design is the DC voltage drop that will

be seen between the V_CCsupply and the V_CCApin of the

MPC961C. From the data sheet the I_CCAcurrent (the current

sourced through the V_CCApin) is typically 2 mA

(5 mA maximum), assuming that a minimum of 2.375 V

(V_CC= 3.3 V or V_CC= 2.5 V) must be maintained on the V_CCA

pin. The resistor R_Fshown in Figure 3 must have a resistance

of 270 Ω (V_CC= 3.3 V) or 5 to 15 Ω (V_CC= 2.5 V) to meet the

voltage drop criteria. The RC filter pictured will provide a

broadband filter with approximately 100:1 attenuation for noise

whose spectral content is above 20 kHz. As the noise

frequency crosses the series resonant point of an individual

capacitor it's overall impedance begins to look inductive and

thus increases with increasing frequency. The parallel capacitor

combination shown ensures that a low impedance path to

ground exists for frequencies well above the bandwidth of the

PLL.

MPC961

OUTPUT

BUFFER

Z

_O= 50 Ω

R_S= 36 Ω

14 Ω

OutA

IN

MPC961

OUTPUT

BUFFER

Z

_O= 50 Ω

R_S= 36 Ω

OutB0

OutB1

R_F= 270 Ω for V_CC= 3.3 V

R_F= 5–15 Ω for V_CC= 2.5 V

14 Ω

Z

R_F

V_CCA

MPC961C

V_CC

C_F

10 nF

Figure 4. Single versus Dual Transmission Lines

V_CC

The waveform plots of Figure 5 show the simulation results

of an output driving a single line verses two lines. In both cases

the drive capability of the MPC961C output buffer is more than

sufficient to drive 50 Ω transmission lines on the incident edge.

Note from the delay measurements in the simulations a delta of

only 43 ps exists between the two differently loaded outputs.

This suggests that the dual line driving need not be used

exclusively to maintain the tight output-to-output skew of the

MPC961C. The output waveform in Figure 5 shows a step in

the waveform, this step is caused by the impedance mismatch

33...100 nF

Figure 3. Power Supply Filter

Although the MPC961C has several design features to

minimize the susceptibility to power supply noise (isolated

power and grounds and fully differential PLL) there still may be

applications in which overall performance is being degraded

due to system power supply noise. The power supply filter

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

487

MPC961C

seen looking into the driver. The parallel combination of the 36

Ω series resistor plus the output impedance does not match the

parallel combination of the line impedances. The voltage wave

launched down the two lines will equal:

SPICE level and IBIS output buffer models are available for

engineers who want to simulate their specific interconnect

schemes.

Using the MPC961C in Zero-Delay Applications

VL = VS (Z_O/ (R_S+ R_O+Z_O))

Z

_O= 50 Ω || 50 Ω

R_S= 36 Ω || 36 Ω

_O= 14 Ω

Nested clock trees are typical applications for the MPC961C.

Designs using the MPC961C as LVCMOS PLL fanout buffer

with zero insertion delay will show significantly lower clock skew

than clock distributions developed from CMOS fanout buffers.

The external feedback option of the MPC961C clock driver

allows for its use as a zero delay buffer. By using the QFB

output as a feedback to the PLL the propagation delay through

the device is virtually eliminated. The PLL aligns the feedback

clock output edge with the clock input reference edge resulting

a near zero delay through the device. The maximum insertion

delay of the device in zero-delay applications is measured

between the reference clock input and any output. This effective

delay consists of the static phase offset, I/O jitter (phase or

long-term jitter), feedback path delay and the output-to-output

skew error relative to the feedback output.

R

VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)

= 1.31 V

At the load end the voltage will double, due to the near unity

reflection coefficient, to 2.62 V. It will then increment towards

the quiescent 3.0 V in steps separated by one round trip delay

(in this case 4.0 ns).

3.0

OutA

OutB

_D= 3.9386

2.5

2.0

1.5

1.0

0.5

0

t

_D= 3.8956

t

Calculation of Part-to-Part Skew

In

The MPC961C zero delay buffer supports applications

where critical clock signal timing can be maintained across

several devices. If the reference clock inputs of two or more

MPC961C are connected together, the maximum overall timing

uncertainty from the common CCLK input to any output is:

t_SK(PP)= t_(∅)+ t_SK(O)+ t_{PD, LINE(FB)}+ t_JIT(∅)· CF

This maximum timing uncertainty consist of 4 components:

static phase offset, output skew, feedback board trace delay

and I/O (phase) jitter:

2

4

6

8

10

12

14

TIME (ns)

TCLK_Common

Figure 5. Single versus Dual Waveforms

t_PD,LINE(FB)

—t_(∅)

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines the situation

in Figure 6 should be used. In this case the series terminating

resistors are reduced such that when the parallel combination

is added to the output buffer impedance the line impedance is

perfectly matched.

QFB_{Device 1}

t_JIT(∅)

Any Q_{Device 1}

+t_SK(O)

+t_(∅)

QFB_Device2

t_JIT(∅)

MPC961

OUTPUT

BUFFER

Z

_O= 50 Ω

R_S= 22 Ω

Any Q_{Device 2}

+t_SK(O)

14Ω

Max. skew

Z

_O= 50 Ω

t_SK(PP)

Figure 7. MPC961C Max. Device-to-Device Skew

14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω

25 Ω = 25 Ω

Figure 6. Optimized Dual Line Termination

Due to the statistical nature of I/O jitter a rms value (1 σ) is

specified. I/O jitter numbers for other confidence factors (CF)

can be derived from Table 8.Confidence Factor CF.

488

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

MPC961C

describes the impact of these parameters on the junction

Table 8. Confidence Factor CF

temperature and gives a guideline to estimate the MPC961C

die junction temperature and the associated device reliability.

For a complete analysis of power consumption as a function of

operating conditions and associated long term device reliability

refer to the Application Note AN1545. According the AN1545,

the long-term device reliability is a function of the die junction

temperature:

CF

Probability of clock edge within the distribution

± 1σ

± 2σ

± 3σ

± 4σ

± 5σ

± 6σ

0.68268948

0.95449988

0.99730007

0.99993663

0.99999943

0.99999999

Table 9. Die Junction Temperature and MTBF

Junction Temperature (°C)

MTBF (Years)

The feedback trace delay is determined by the board layout

and can be used to fine-tune the effective delay through each

device. In the following example calculation a I/O jitter

confidence factor of 99.7% (± 3σ) is assumed, resulting in a

worst case timing uncertainty from input to any output of -275

ps to 315 ps relative to CCLK:

100

110

120

130

20.4

9.1

4.2

2.0

t_SK(PP)= [-80ps...120ps] + [-150ps...150ps] +

Increased power consumption will increase the die junction

temperature and impact the device reliability (MTBF).

According to the system-defined tolerable MTBF, the die

junction temperature of the MPC961C needs to be controlled

and the thermal impedance of the board/package should be

optimized. The power dissipated in the MPC961C is

represented in equation 1.

Where I_CCQis the static current consumption of the

MPC961C, C_PDis the power dissipation capacitance per

output, (Μ)ΣC_Lrepresents the external capacitive output load,

N is the number of active outputs (N is always 27 in case of the

MPC961C). The MPC961C supports driving transmission lines

to maintain high signal integrity and tight timing parameters.

Any transmission line will hide the lumped capacitive load at the

end of the board trace, therefore, ΣC_Lis zero for controlled

transmission line systems and can be eliminated from

equation 1. Using parallel termination output termination results

in equation 2 for power dissipation.

[(15ps @ -3)...(15ps @ 3)] + t_{PD, LINE(FB)}

t_SK(PP)= [-275ps...315ps] + t_{PD, LINE(FB)}

Due to the frequency dependence of the I/O jitter, Figure 8

can be used for a more precise timing performance analysis.

F_RANGE = 1

F_RANGE = 0

18

16

14

12

10

8

6

4

2

0

50

70

90

110 130 150 170 190

Clock frequency [MHz]

Figure 8. Max. I/O Jitter versus Frequency

In equation 2, P stands for the number of outputs with a

parallel or thevenin termination, V_OL, I_OL, V_OH, and I_OHare a

function of the output termination technique and DC_Qis the

clock signal duty cycle. If transmission lines are used ΣC_Lis

zero in equation 2 and can be eliminated. In general, the use of

controlled transmission line techniques eliminates the impact of

the lumped capacitive loads at the end lines and greatly

reduces the power dissipation of the device. Equation 3

describes the die junction temperature T_Jas a function of the

power consumption.

Power Consumption of the MPC961C and Thermal

Management

The MPC961C AC specification is guaranteed for the entire

operating frequency range up to 200 MHz. The MPC961C

power consumption and the associated long-term reliability

may decrease the maximum frequency limit, depending on

operating conditions such as clock frequency, supply voltage,

output loading, ambient temperature, vertical convection and

thermal conductivity of package and board. This section

Equation 1

P_TOT= [ I_CCQ+ V_CC· f_CLOCK· ( N · C_PD+ Σ C_L) ] · V_CC

M

P_TOT= V_CC· [ I_CCQ+ V_CC· f_CLOCK· ( N · C_PD+ Σ C_L) ] + Σ [ DC_Q· I_OH· (V_CC– V_OH) + (1 – DC_Q) · I_OL· V_OL]

Equation 2

Equation 3

M

P

T_J= T_A+ P_TOT· R_thja

T_j,MAX– T_A

1

– (I_CCQ· V_CC

)

]

Equation 4

f_CLOCK,MAX

=

·

[

C

_PD· N · V²

R_thja

CC

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

489

MPC961C

Where R_thjais the thermal impedance of the package

(junction to ambient) and T_Ais the ambient temperature.

According to Table 9.Die Junction Temperature and MTBF, the

junction temperature can be used to estimate the long-term

device reliability. Further, combining equation 1 and equation 2

results in a maximum operating frequency for the MPC961C in

a series terminated transmission line system.

T_J,MAXshould be selected according to the MTBF system

requirements and Table 9.Die Junction Temperature and MTBF.

R_thjacan be derived from Table 10.Thermal Package

Impedance of the 32ld LQFP. The R_thjarepresent data based

on 1S2P boards, using 2S2P boards will result in a lower

thermal impedance than indicated below.

If the calculated maximum frequency is below 200 MHz, it

becomes the upper clock speed limit for the given application

conditions. The following two derating charts describe the safe

frequency operation range for the MPC961C. The charts were

calculated for a maximum tolerable die junction temperature of

110°C, corresponding to an estimated MTBF of 9.1 years, a

supply voltage of 3.3 V and series terminated transmission line

or capacitive loading. Depending on a given set of these

operating conditions and the available device convection a

decision on the maximum operating frequency can be made.

There are no operating frequency limitations if a 2.5 V power

supply or the system specifications allow for a MTBF of 4 years

(corresponding to a max. junction temperature of 120°C.

Table 10. Thermal Package Impedance of the 32ld LQFP

R_thja(1P2S board), K/W

Convection, LFPM

Still air

80

70

61

57

56

55

100 lfpm

200 lfpm

300 lfpm

400 lfpm

500 lfpm

200

f

_MAX(AC)

f_MAX(AC)

180

160

140

120

100

80

180

160

140

120

100

80

T_A= 85°C

T_A= 75°C

T

_A= 85°C

60

Safe operation

40

20

0

500

0

500

0

400

300

200

100

0

400

300

200

100

I_FPM, CONVECTION

Figure 9. Maximum MPC961C Frequency, V_CC= 3.3 V,

Figure 10. Maximum MPC961C Frequency,

V_CC= 3.3 V, MTBF 9.1 Years, 4 pF Load per Line

MTBF 9.1 Years, Driving Series Terminated

Transmission Lines

MPC961C DUT

Pulse

Generator

Z = 50 Ω

Z_O= 50 Ω

R_T= 50 Ω

V_TT

Figure 11. TCLK MPC961C AC Test Reference for V_CC= 3.3 V and V_CC= 2.5 V

490

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

MPC961C

V_CC

V

_CC÷ 2

GND

V_CC

CCLK

FB_IN

V_CC÷ 2

V

_CC÷ 2

GND

V_CC

GND

t_SK(O)

V

_CC÷ 2

GND

The pin-to-pin skew is defined as the worst case difference

in propagation delay between any similar delay path within a

single device

t_(∅)

Figure 13. Propagation Delay (t_PD, static phase

offset) Test Reference

Figure 12. Output-to-Output Skew t_SK(O)

V_CC

CCLK

V

_CC÷ 2

GND

t_P

FB_IN

T₀

DC = t_P/T₀x 100%

T_JIT(∅)= |T₀–T₁mean|

The time from the PLL controlled edge to the non controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

The deviation in t₀for a controlled edge with respect to a t₀mean

in a random sample of cycles

Figure 15. I/O Jitter

Figure 14. Output Duty Cycle (DC)

T_JIT(CC)= |T_N–T_N+1

|

T_JIT(PER)= |T_N–1/f₀|

T_N

T_N+1

T₀

The variation in cycle time of a signal between adjacent cycles,

over a random sample of adjacent cycle pairs

The deviation in cycle time of a signal with respect to the ideal

period over a random sample of cycles

Figure 17. Period Jitter

Figure 16. Cycle-to-Cycle Jitter

V_CC=3.3V

2.4

V_CC=2.5V

1.8V

0.55

0.6V

t_F

t_R

Figure 18. Output Transition Time Test

Reference

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

491


型号：	MPC961CFA
厂家：	NXP
描述：	IC,1:17 OUTPUT,BICMOS,QFP,32PIN,PLASTIC 驱动信息通信管理输出元件逻辑集成电路
文件：	总9页 (文件大小：159K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MPC961CFA [NXP]

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