MPC9819EN [NXP]

133MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20, LEAD FREE, SSOP-20;


型号：	MPC9819EN
厂家：	NXP
描述：	133MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20, LEAD FREE, SSOP-20 时钟 PC 光电二极管外围集成电路晶体
文件：	总10页 (文件大小：251K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MPC9819

Rev 3, 09/2005

Freescale Semiconductor

Technical Data

Clock Generator for PowerQUICC

and PowerPC Microprocessors and

Microcontrollers

MPC9819

The MPC9819 is a PLL-based clock generator specifically designed for

Freescale Microprocessor and Microcontroller applications including the

PowerPC and PowerQUICC. This device generates the microprocessor input

clock and other microprocessor system and bus clocks at any one of four output

frequencies. These frequencies include the popular 66- and 133-MHz PCI/X bus

frequencies. The device offers five low-skew clock outputs plus three reference

outputs. The clock input reference is 25 MHz and may be derived from an

external source or by the addition of a 25-MHz crystal to the on-chip crystal

oscillator. The extended temperature range of the MPC9819 supports

telecommunication and networking requirements.

MICROPROCESSOR

CLOCK GENERATOR

SD SUFFIX

20 SSOP PACKAGE

CASE 1461-02

Features

•

5 LVCMOS outputs for processor and other system circuitry

3 Buffered 25-MHz reference clock outputs

Crystal oscillator or external reference input

25-MHz input reference frequency

Selectable output frequencies include: 66, 100, 125, or 133 MHz

Low cycle-to-cycle and period jitter

EN SUFFIX

Package: 20-lead SSOP

20 SSOP PACKAGE

Pb-FREE PACKAGE

CASE 1461-02

3.3-V supply

Supports computing, networking, and telecommunications applications

Ambient temperature range: –40°C to +85°C

Functional Description

The MPC9819 uses a PLL with a 25-MHz input reference frequency to generate a single bank of five configurable LVCMOS

output clocks. The output frequency of this bank is configurable to either 66, 100, 125, or 133 MHz by two FSEL pins. The 25-

MHz reference may be either an external frequency source or a 25-MHz crystal. The 25-MHz crystal is directly connected to the

XTAL_IN and XTAL_OUT pins with no additional components required. An external reference may be applied to the XTAL_IN

pin with the XTAL_OUT pin left floating. The input reference, whether provided by a crystal or an external input, is also directly

buffered to a second bank of three LVCMOS outputs. These outputs may be used as the clock source for processor I/O

applications such as an Ethernet PHY.

The MPC9819 is packaged in a 20-lead SSOP package.

QA0

QA1

XTAL_IN

Ref

OSC

XTAL_OUT

PLL

400 or 500 MHz

66,100,125,133

MHz

QA2

QA3

FSEL0

FSEL1

QA4

Data

Generator

25 MHz

QREF0

QREF1

QREF2

MR/OE

Figure 1. MPC9819 Logic Diagram

Table 1. Pin Configurations

QA0, QA1, QA2, QA3, QA4

QREF0, QREF1, QREF2

XTAL_IN

I/O

Output

Input

Output

Input

—

Type

Function

LVCMOS

—

Clock Outputs

Reference Output (25 MHz)

Crystal Oscillator Input Pin

Crystal Oscillator Output Pin

XTAL_OUT

FSEL0, FSEL1

MR/OE

Configures Bank A Clock Output Frequency (pull-up)

Enables All Outputs (pull-down)

3.3-V Supply

V_DD

GND

—

Ground

Table 2. Function Table

Control

Default

133 MHz

FSEL0, FSEL1

66 MHz

125 MHz

100 MHz

MPC9819

Advanced Clock Drivers Devices

Freescale Semiconductor

XTAL_IN

XTAL_OUT

FSEL0

V_DD

QA4

QA3

GND

QA2

QA1

V_DD

FSEL1

QREF2

GND

QREF1

QREF0

V_DD

QA0

MR/OE

GND

Figure 2. MPC9819 20-Lead SSOP Package Pinout (Top View)

MPC9819 OPERATION

Crystal Oscillator

the reference frequency may be higher than the specified

25 MHz. Externally supplied capacitors on both the XTAL_IN

and XTAL_OUT pins may be used to trim the frequency as

desired.

The crystal should be located as close to the MPC9819

XTAL_IN and XTAL_OUT pins as possible to avoid any board

level parasitic.

The MPC9819 features a fully integrated Pierce oscillator

to minimize system implementation costs. Other than the

addition of a 25-MHz crystal, no external components are

required.The crystal selection should be: 25 MHz, parallel

resonant type with a load specification of C_L= 10 pF. Crystals

with a load specification of C_L= 20 pF may be used, however,

Table 3. Crystal Specifications

Parameter

Crystal Cut

Value

Fundamental AT Cut

Parallel Resonance

5–7 pF

Resonance

Shunt Capacitance (C_O)

Load Capacitance (C_L)

10 pF

Equivalent Series Resistance (ESR) 20–60 Ω

Power Supply Bypassing

External Clock Source

The MPC9819 should have all V_DDpins bypassed with

0.01 capacitors and a minimum of one 1.0 capacitor for the

overall package. All capacitors should be located as close to

the SSOP pins as possible.

An external reference source of 25 MHz may be applied to

the XTAL_IN pin. In this mode of operation, the XTAL_OUT

pin should be left floating.

MPC9819

Advanced Clock Drivers Devices

Freescale Semiconductor

Table 4. Absolute Maximum Ratings⁽¹⁾

Symbol

V_DD

I_IN

Characteristics

Min

–0.3

—

Max

3.8

Unit

Condition

Supply Voltage

DC Input Current

DC Output Current

Storage Temperature

±20

±75

125

°C

I_OUT

T_S

—

–65

1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these

conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated

conditions is not implied.

Table 5. General Specifications

Symbol

V_TT

HBM

Characteristics

Output Termination Voltage

Min

—

Typ

V_DD÷ 2

—

Max

—

Unit

Condition

ESD Protection (machine model)

ESD Protection (human body model)

Latch-Up Immunity

200

2000

200

—

°C/W

°C

C_IN

Input Capacitance

—

Inputs

C_pd

Power Dissipation Capacitance

Thermal Resistance (junction-to-ambient)

Ambient Temperature

—

8.5

—

θ_JA

—

80.8

—

T_C

–40

Table 6. DC Characteristics (V_DD= 3.3 V ± 5%, T_A= –40° to +85°C)

Symbol

V_IH

Characteristics

Input High Voltage (XTAL_IN)

Min

2.4

2.0

—

Typ

—

Max

V_DD+ 0.3

0.8

Unit

Condition

Input threshold = V_DD/2

V_IH

Input High Voltage

Input Low Voltage

Input Current⁽¹⁾

—

V_IL

—

LVCMOS

I_IN

—

150

µA

V_IN= V_DDLor GND

V_OH

V_OL

Z_OUT

I_DD

Output High Voltage

Output Low Voltage

Output Impedance

Maximum Supply Current

2.4

—

I_OH= –12 mA

I_OL= 12 mA

—

0.4

—

Ω

f_A= 66 MHz

f_A= 133 MHz

—

25 MHz reference

frequency

I_DDBASEBase Supply Current⁽²⁾

(for dynamic power dissipation calculation)

—

1. Inputs have pull-down resistors affecting the input current.

2. P_D= (V_DD* I_DDBASE) + 5 (V_DD²) * C_pd* f_A.

MPC9819

Advanced Clock Drivers Devices

Freescale Semiconductor

Table 7. AC Characteristics^{(1) (2)}(V_DD= 3.3 V ± 5%, T_A= –40° to +85°C)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Input and Output Timing Specification

f_ref

Input Reference Frequency

VCO Frequency Range

Output Frequency (QAx)

25 MHz Input

XTAL Input

MHz

f_VCO

f_MCX

FSEL0, FSEL1 = 00,01,11

FSEL0, FSEL1 = 10

400

500

MHz

FSEL0, FSEL1 = 00

FSEL0, FSEL1 = 10

FSEL0, FSEL1 = 01

FSEL0, FSEL1 = 11

66.66

100

125

133.33

—

MHz

PLL locked

Output Frequency (QREFx)

Reference Input Pulse Width

Output Duty Cycle

f_refPW

—

@ 25 MHz

f_out

Output Frequency Accuracy

Crystal⁽³⁾

External Reference

—

100

ppm

With recommended crystal

see Table 3

PLL Specifications

PLL Closed Loop Bandwidth⁽⁴⁾

500

kHz

t_LOCK

Maximum PLL Lock Time

Skew and Jitter Specifications

t_sk(O)

Output-to-Output Skew (within a bank)

t_JIT(CC)Cycle-to-Cycle Jitter

150

@ 25 MHz Input Reference

_Aoutput

@ 25 MHz Input Reference

_Aoutput

t_JIT(PER)Period Jitter

100

t_r, t_f

Output Rise/Fall Time

20% to 80%

1. AC characteristics are design targets and pending characterization.

2. AC characteristics apply for parallel output termination of 50 Ω to V_TT

3. Based upon recommended crystal specifications as outlined in operation section.

4. –3 dB point of PLL transfer characteristics.

Z = 50 Ω

Pulse

Generator

Z = 50 Ω

R_T= 50 Ω

DUT MPC9819

V_TT

Figure 3. MPC9819 AC Test Reference (LVCMOS Outputs)

MPC9819

Advanced Clock Drivers Devices

Freescale Semiconductor

Table 8. MPC9819 Pin List

Description

XTAL_IN

Description

GND

XTAL_OUT

FSEL0

V_DD

MR/OE

QA0

V_DD

FSEL1

QREF2

GND

QA1

QA2

GND

QA3

QA4

V_DD

QREF1

QREF0

V_DD

MPC9819

Advanced Clock Drivers Devices

Freescale Semiconductor

PACKAGE DIMENSIONS

PAGE 1 OF 3

CASE 1461-02

ISSUE A

20 SSOP PACKAGE

MPC9819

Advanced Clock Drivers Devices

Freescale Semiconductor

PACKAGE DIMENSIONS

PAGE 2 OF 3

CASE 1461-02

ISSUE A

20 SSOP PACKAGE

MPC9819

Advanced Clock Drivers Devices

Freescale Semiconductor

PACKAGE DIMENSIONS

PAGE 3 OF 3

CASE 1461-02

ISSUE A

20 SSOP PACKAGE

MPC9819

Advanced Clock Drivers Devices

Freescale Semiconductor

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MPC9819

Rev. 3

09/2005

MPC9819EN [NXP]

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