PC33932EKR2 [NXP]
BUF OR INV BASED PRPHL DRVR;
| 型号： | PC33932EKR2 |
| 厂家： | 
NXP |
| 描述： | BUF OR INV BASED PRPHL DRVR 驱动 接口集成电路 |
| 文件： | 总27页 (文件大小：961K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33932
Rev 4.0, 6/2012
Freescale Semiconductor
Advance Information
5.0 A Throttle Control H-Bridge
33932
The 33932 is a monolithic H-Bridge Power IC in a robust thermally
enhanced package. The 33932 has two independent monolithic
H-Bridge Power ICs in the same package. They are designed primarily
for automotive electronic throttle control, but are applicable to any low
voltage DC servo motor control application within the current and
voltage limits stated in this specification.
THROTTLE CONTROL H-BRIDGE
Each H-Bridge in the 33932 is able to control inductive loads with
currents up to 5.0 A peak. RMS current capability is subject to the
degree of heatsinking provided to the device package. Internal peak-
current limiting (regulation) is activated at load currents above 6.5 A
±1.5 A. Output loads can be pulse-width modulated (PWM-ed) at
frequencies up to 11 kHz. A load current feedback feature provides a
proportional (0.24% of the load current) current output suitable for
monitoring by a microcontroller’s A/D input. A Status Flag output
reports under-voltage, over-current, and over-temperature fault
conditions.
VW SUFFIX (PB-FREE)
98ARH98330A
44-PIN HSOP
WITH PROTRUDING
HEAT SINK
EK SUFFIX (PB-FREE)
98ASA99334D
54-PIN SOIC
Two independent inputs provide polarity control of two half-bridge
totem pole outputs. Two independent disable inputs are provided to
force the H-Bridge outputs to tri-state (high-impedance off state).
ORDERING INFORMATION
Features
Device
Temperature
• 8.0 to 28 V continuous operation (transient operation from 5.0 to
40 V)
(Add R2 Suffix for
Tape and Reel)
Package
Range (T )
A
• 235 mΩ maximum RDS(ON) at 150 °C (each H-Bridge MOSFET)
• 3.0 and 5.0 V TTL / CMOS logic compatible inputs
• Output short-circuit protection (short to VPWR or GND)
• Over-current limiting (regulation) via internal constant-off-time
PWM
MC33932VW
PC33932EK
44 HSOP
54 SOIC
-40 to 125 °C
• Temperature dependant current limit threshold reduction
• All inputs have an internal source/sink to define the default
(floating input) states
• Sleep mode with current draw < 50 µA (each half with inputs
floating or set to match default logic states)
V
V
PWR
DD
33932
SFA
FBA
VPWRA
CCPA
OUT1
MOTOR
IN1
IN2
D1
EN/D2
OUT2
PGNDA
AGNDA
V
PWR
MCU
IN3
IN4
D3
VPWRB
CCPB
OUT3
EN/D4
FBB
MOTOR
SFB
PGNDB
AGNDB
OUT4
V
DD
Figure 1. MC33932 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2009-2012. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWRA
VDD
LOGIC SUPPLY
VCP
CHARGE
PUMP
HS1
HS2
LS2
CCPA
OUT1
OUT2
TO GATES
HS1
LS1
LS1
HS2
LS2
IN1
IN2
PGND
EN/D2
D1
GATE DRIVE
AND
PROTECTION
LOGIC
VSENSE
CURRENT MIRROR
AND
CONSTANT OFF-TIME
SFA
FBA
ILIM PWM
PWM CURRENT REGULATOR
H-Bridge A
AGNDA
PGNDA
VPWRB
H-Bridge B
VDD
LOGIC SUPPLY
VCP
CHARGE
PUMP
HS1
LS1
HS2
CCPB
OUT3
OUT4
TO GATES
HS1
LS2
IN3
IN4
LS1
HS2
LS2
EN/D4
D3
PGND
GATE DRIVE
AND
PROTECTION
LOGIC
VSENSE
CURRENT MIRROR
AND
CONSTANT OFF-TIME
SFB
FBB
ILIM PWM
PWM CURRENT REGULATOR
AGNDB
PGNDB
Figure 2. 33932 Simplified Internal Block Diagram
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
PIN CONNECTIONS
PIN CONNECTIONS
AGNDA
Tab
AGNDA
54
VPWRA
1
NC
D1
FBA
EN/D2
NC
VPWRA
SFA
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
2
3
IN1
IN2
NC
NC
4
1
2
5
D1
FBA
SFA
IN1
IN2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
6
3
4
5
6
EN/D2
VPWRA
VPWRA
VPWRA
OUT1
NC
NC
7
CCPA
VPWRA
VPWRA
OUT2
OUT2
OUT2
PGNDA
PGNDA
PGNDB
PGNDB
OUT3
OUT3
OUT3
VPWRB
VPWRB
VPWRB
EN/D4
FBB
CCPA
VPWRA
OUT2
OUT2
PGNDA
PGNDA
NC
H-BRIDGE A
8
VPWRA
OUT1
OUT1
PGNDA
PGNDA
NC
PGNDB
PGNDB
OUT4
OUT4
VPWRB
CCPB
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
7
8
OUT1
9
OUT1
10
11
12
13
14
15
16
17
18
19
20
21
22
PGNDA
PGNDA
PGNDB
PGNDB
OUT4
OUT4
OUT4
VPWRB
VPWRB
CCPB
IN4
PGNDB
PGNDB
OUT3
OUT3
VPWRB
NC
H-BRIDGE B
NC
NC
NC
IN4
IN3
SFB
IN3
SFB
EN/D4
FBB
D3
D3
NC
VPWRB
VPWRB
AGNDB
Tab
AGNDB
44 HSOP
Transparent Top View
54 SOIC
Transparent Top View
Figure 3. 33932 Pin Connections
Table 1. 33932 Pin Definitions
A functional description of each pin can be found in the Functional Description section beginning on page 12.
Pin
Function
Pin
Pin
Pin Name
Formal Name
Definition
HSOP (VW) SOIC (EK)
When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated.
Schmitt trigger input with ~80 μA source so default
condition = disabled.
1
2
3
3
4
5
D1
Logic Input
Disable Input 1
(Active High)
H-Bridge A load current feedback output provides ground
referenced 0.24% of the high side output current. (Tie to GND
through a resistor if not used.)
FBA
Analog
Output
Feedback
When EN/D2 is logic HIGH, H-Bridge A is operational. When EN/
D2 is logic LOW, the H-Bridge A outputs are tri-stated and H-
Bridge A is placed in Sleep Mode. (logic input with ~80 μA sink so
default condition = Sleep Mode.)
EN/D2
Logic Input
Enable Input
These pins must be connected together physically as close as
possible and directly soldered down to a wide, thick, low
resistance supply plane on the PCB.
4-6, 39, 40 1, 9, 46, 53
VPWRA Power Input
Positive Power
Supply
H-Bridge A source of HS1 and drain LS1.
7-9
10, 11
OUT1
Power
Output
H-Bridge Output 1
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 33932 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Description section beginning on page 12.
Pin
Function
Pin
Pin
Pin Name
Formal Name
Definition
HSOP (VW) SOIC (EK)
High-current power ground pins must be connected together
physically as close as possible and directly soldered down to a
wide, thick, low resistance ground plane on the PCB. PGNDA
should be connected to PGNDB with a low-impedance path.
10, 11, 34, 12, 13, 42,
PGNDA
Power
Ground
Power Ground
35
43
High-current power ground pins must be connected together
physically as close as possible and directly soldered down to a
wide, thick, low resistance ground plane on the PCB. PGNDB
should be connected to PGNDA with a low-impedance path.
12, 13, 32, 15, 16, 39,
PGNDB
OUT4
Power
Ground
Power Ground
33
40
H-Bridge B Source of HS2 and drain of LS2.
14-16
17, 18
Power
Output
H-Bridge Output 4
These pins must be connected together physically as close as
possible and directly soldered down to a wide, thick, low
resistance supply plane on the PCB.
17, 18, 26- 19, 26, 28,
VPWRB Power Input
Positive Power
Supply
28
36
External reservoir capacitor connection for H-Bridge B internal
charge pump; connected to VPWRB. Allowable values are 30 to
100 nF. Note: This capacitor is required for the proper
performance of the device.
19
20
CCPB
Analog
Output
Charge Pump
Capacitor
Logic input control of OUT4.
20
21
22
23
24
25
IN4
IN3
Logic Input
Logic Input
Input 4
Input 3
Logic input control of OUT3.
H-Bridge B open drain active LOW Status Flag output (requires
an external pull-up resistor to V . Maximum permissible load
SFB
Logic
Output -
Status Flag B
(Active Low)
DD
current < 0.5 mA. Maximum V
< 0.4 V at 0.3 mA. Maximum
Open Drain
SFLOW
permissible pull-up voltage < 7.0 V.)
When D3 is logic HIGH, both OUT3 and OUT4 are tri-stated.
Schmitt trigger input with ~80 μA source so default condition =
disabled.
23
24
25
30
31
32
D3
Logic Input
Disable Input 3
(Active High)
H-Bridge B load current feedback output provides ground
referenced 0.24% of the high side output current. (Tie to GND
through a resistor if not used.)
FBB
Analog
Output
Feedback B
Enable Input
EN/D4
Logic Input
When EN/D4 is logic HIGH, H-Bridge B is operational. When EN/
D4 is logic LOW, the H-Bridge B outputs are tri-stated and H-
Bridge B is placed in Sleep Mode. (logic input with ~80μA sink so
default condition = Sleep Mode.)
H-Bridge B Source of HS1 and drain of LS1.
29-31
36-38
41
37, 38
44, 45
47
OUT3
OUT2
CCPA
Power
Output
H-Bridge Output 3
H-Bridge Output 2
H-Bridge A source of HS2 and drain of LS2.
Power
Output
External reservoir capacitor connection for H-Bridge A internal
charge pump; connected to VPWRA. Allowable values are 30 to
100 nF. Note: This capacitor is required for the proper
performance of the device.
Analog
Output
Charge Pump
Capacitor
Logic input control of OUT2.
42
43
50
51
IN2
IN1
Logic Input
Logic Input
Input 2
Input 1
Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1
is set to VPWRA, and when IN1 is logic LOW, OUT1 is set to
PGNDA. (Schmitt trigger Input with ~80 μA source so default
condition = OUT1 HIGH.)
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
PIN CONNECTIONS
Table 1. 33932 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Description section beginning on page 12.
Pin
Function
Pin
Pin
Pin Name
Formal Name
Definition
HSOP (VW) SOIC (EK)
H-Bridge A open drain active LOW Status Flag output (requires
44
52
SFA
Logic
Output -
Status Flag
(Active Low)
an external pull-up resistor to V . Maximum permissible load
DD
current < 0.5 mA. Maximum V
< 0.4 V at 0.3 mA. Maximum
Open Drain
SFLOW
permissible pull-up voltage < 7.0 V.)
The low-current analog signal ground must be connected to
PGND via low-impedance path (<10 mΩ, 0 Hz to 20 kHz).
TAB
-
54
27
AGNDA
AGNDB
Analog
Ground
Analog Signal
Ground
These pins have no electrical connection or function.
2, 6 - 8, 14,
21, 22, 29,
33 - 35, 41,
48, 49
NC
None
No Connect
Exposed TAB is also the main heatsinking path for the device and
must be connected to ground.
EP
EP
Thermal
Pad
Exposed Pad
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device. These parameters are not production tested.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Power Supply Voltage
V
Normal Operation (Steady-state)
Transient Over-voltage(1)
VPWR(SS)
VPWR(T)
-0.3 to 28
-0.3 to 40
Logic Input Voltage(2)
SFA, SFB Output(3)
V
-0.3 to 7.0
-0.3 to 7.0
5.0
V
V
A
V
IN
V
SF
Continuous Output Current(4)
I
OUT(CONT)
ESD Voltage(5)
Human Body Model
Machine Model
Charge Device Model
Corner Pins
V
V
±2000
±200
ESD1
ESD2
±750
±500
All Other Pins
THERMAL RATINGS
Storage Temperature
T
- 65 to 150
°C
°C
STG
Operating Temperature(6)
Ambient
T
-40 to 125
-40 to 150
A
Junction
T
J
Peak Package Reflow Temperature During Reflow(7), (8)
Approximate Junction-to Case Thermal Resistance(9)
Notes
°C
TPPRT
Note 8
<1.0
R
°C/W
THJC
1. Device will survive repetitive transient over-voltage conditions for durations not to exceed 500 ms at duty cycle not to exceed 10%.
External protection is required to prevent device damage in case of a reverse battery condition.
2. Exceeding the maximum input voltage on IN1, IN2, IN3, IN4, EN/D2, EN/D4, D1, or D3 may cause a malfunction or permanent damage
to the device.
3. Exceeding the pull-up resistor voltage on the open drain SFA or SFB pin may cause permanent damage to the device.
4. Continuous output current capability is dependent on sufficient package heatsinking to keep junction temperature ≤150 °C.
5. ESD testing is performed in accordance with the Human Body Model (C
= 100 pF, R
= 1500 Ω), Machine Model (C
= 200 pF,
ZAP
ZAP
ZAP
R
= 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).
ZAP
6. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief
non-repetitive excursions of junction temperature above 150 °C can be tolerated, provided the duration does not exceed 30 seconds
maximum. (Non-repetitive events are defined as not occurring more than once in 24 hours.)
7. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
8. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
9. Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual RθJB (junction-to-PC board)
values will vary depending on solder thickness and composition and copper trace thickness and area. Maximum current at maximum
die temperature represents ~16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the RθJA must be
<5.0 °C/W for maximum current at 70 °C ambient. Module thermal design must be planned accordingly.
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 5.0 V ≤ VPWR ≤ 28 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Specifications given for H-Bridge A apply symmetrically to H-Bridge B.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUTS (VPWR)
Operating Voltage Range(10)
V
Steady-state
Transient (t < 500 ms)(11)
V
5.0
–
–
–
28
40
PWR(SS)
V
PWR(t)
Sleep State Supply Current(12)
I
μA
PWR(SLEEP)
EN/D2 = Logic [0], IN1, IN2, D1 = Logic [1], and I
= 0 A
–
–
–
–
50
20
OUT
Standby Supply Current (Part Enabled)
I
mA
PWR(STANDBY)
I
= 0 A, V = 5.0 V
EN
OUT
Under-voltage Lockout Thresholds
V
V
4.15
–
–
–
–
V
V
PWR(FALLING)
UVLO(ACTIVE)
V
V
5.0
350
PWR(RISING)
UVLO(INACTIVE)
Hysteresis
V
150
200
mV
UVLO(HYS)
CHARGE PUMP
Charge Pump Voltage (CP Capacitor = 33 nF), No PWM
V
V
- V
V
V
CP
CP
PWR
PWR
V
V
= 5.0 V
= 28 V
3.5
–
–
–
–
PWR
PWR
12
Charge Pump Voltage (CP Capacitor = 33 nF), PWM = 11 kHz
- V
V
V
= 5.0 V
= 28 V
3.5
–
–
–
–
PWR
PWR
12
CONTROL INPUTS
Operating Input Voltage (IN1, IN2, D1, EN/D2, IN3, IN4, D3, EN/D4)
VI
–
–
5.5
V
Input Voltage (IN1, IN2, D1, EN/D2, IN3, IN4, D3, EN/D4)
Logic Threshold HIGH
V
2.0
–
–
–
–
1.0
–
V
V
IH
Logic Threshold LOW
V
IL
Hysteresis
V
250
400
mV
HYS
Logic Input Currents, VPWR = 8.0 V
I
μA
IN
Input EN/D2, EN/D4 (internal pull-downs), VIH = 5.0 V
Inputs IN1, IN2, D1, IN3, IN4, D3 (internal pull-ups), VIL = 0 V
20
80
200
-20
-200
-80
Notes
10. Device specifications are characterized over the range of 8.0 V ≤ V
≤ 28 V. Continuous operation above 28 V may degrade device
PWR
reliability. Device is operational down to 5.0V, but below 8.0 V the output resistance may increase by 50 percent.
11. Device will survive the transient over-voltage indicated for a maximum duration of 500 ms. Transient not to be repeated more than once
every 10 seconds.
12.
I
is with Sleep Mode activated and EN/ D2, = logic [0], and IN1, IN2, D1 = logic [1] or with these inputs left floating.
PWR(SLEEP)
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.0 V ≤ VPWR ≤ 28 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Specifications given for H-Bridge A apply symmetrically to H-Bridge B.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUTS OUT1, OUT2
Output-ON Resistance(14), ILOAD = 3.0 A
R
mΩ
DS(ON)
VPWR = 8.0 V, T = 25 °C
–
–
–
120
–
–
J
VPWR = 8.0 V, T = 150 °C
235
325
J
VPWR = 5.0 V, T = 150 °C
–
J
Output Current Regulation Threshold
TJ < TFB
I
A
LIM
5.2
–
6.5
4.2
8.0
–
TJ ≥ TFB (Fold back Region - see Figure 9 and Figure 11)(13)
High Side Short-circuit Detection Threshold (Short-circuit to Ground)(13)
I
11
13
11
16
14
A
A
SCH
(13)
Low Side Short-circuit Detection Threshold (Short-circuit to VPWR
Output Leakage Current(15), Outputs off, VPWR = 28 V
)
I
9.0
SCL
I
μA
OUTLEAK
V
V
= VPWR
–
–
–
100
–
OUT
OUT
= Ground
-60
Output MOSFET Body Diode Forward Voltage Drop, I
Over-temperature Shutdown(13)
= 3.0 A
V
F
–
–
2.0
V
OUT
°C
Thermal Limit at T
J
T
175
–
–
200
–
LIM
Hysteresis at T
J
T
12
HYS
(13)
Current Foldback at T
J
TFB
165
10
–
–
185
15
°C
°C
Current Foldback to Thermal Shutdown Separation(13)
HIGH SIDE CURRENT SENSE FEEDBACK
Feedback Current (pin FB sourcing current)(16)
TSEP
I
FB
I
I
I
I
I
I
= 0.0 mA
= 300 mA
= 500 mA
= 1.5 A
0.0
0.0
–
50
750
μA
μA
OUT
OUT
OUT
OUT
OUT
OUT
270
0.35
2.86
5.71
11.43
0.775
3.57
7.14
14.29
1.56
4.28
8.57
17.15
mA
mA
mA
mA
= 3.0 A
= 6.0 A
STATUS FLAG(17)
Status Flag Leakage Current(18)
I
μA
SFLEAK
V
= 5.0 V
–
–
–
–
5.0
0.4
SF
Status Flag SET Voltage(19)
= 300 µA
V
V
SFLOW
I
SF
Notes
13. This parameter is Guaranteed By Design.
14. Output-ON resistance as measured from output to VPWR and from output to GND.
15. Outputs switched OFF via D1 or EN/D2.
16. Accuracy is better than 20% from 0.5 A to 6.0 A. Recommended terminating resistor value: RFB = 270 Ω.
17. Status Flag output is an open drain output requiring a pull-up resistor to logic V
.
DD
18. Status Flag Leakage Current is measured with Status Flag HIGH and not SET.
19. Status Flag Set Voltage measured with Status Flag LOW and SET with I = 300 μA. Maximum allowable sink current from this pin is
SF
< 500 μA. Maximum allowable pull-up voltage < 7.0 V.
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.0 V ≤ VPWR ≤ 28 V, -40°C ≤ TA ≤ 125°C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
PWM Frequency(20)
f
–
–
–
–
11
20
kHz
kHz
μs
PWM
Maximum Switching Frequency During Current Limit Regulation(21)
Output ON Delay(22)
f
MAX
DON
t
V
= 14 V
–
–
18
PWR
Output OFF Delay(22)
= 14 V
t
μs
DOFF
V
–
15
12
–
–
20.5
16.5
–
12
32
PWR
LIM Output Constant-OFF Time(23) (25)
μs
μs
I
t
t
A
B
ILIM Blanking Time(24) (25)
27
Disable Delay Time(26)
t
8.0
8.0
8.0
5.0
150
–
μs
μs
μs
DDISABLE
Output Rise and Fall Time(27)
t , t
1.5
–
3.0
–
F
R
Short-circuit/Over-temperature Turn-OFF (Latch-OFF) Time(28), (29)
Power-ON Delay Time(29)
t
FAULT
t
–
1.0
100
7.0
ms
ns
POD
Output MOSFET Body Diode Reverse Recovery Time(29)
Charge Pump Operating Frequency(29)
Notes
t
75
–
RR
fCP
MHz
20. The maximum PWM frequency should be limited to frequencies < 11 kHz in order to allow the internal high side driver circuitry time to
fully enhance the high side MOSFETs.
21. The internal current limit circuitry produces a constant-OFF-time Pulse Width Modulation of the output current. The output load’s
inductance, capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time), and thus the PWM
frequency during current limit.
22. * Output Delay is the time duration from 1.5 V on the IN1 or IN2 input signal to the 20% or 80% point (dependent on the transition direction)
of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from 1.5 V on the input signal to the 80% point of
the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from 1.5 V on the input signal to the 20% point of the
output response signal. See Figure 4, page 10.
23. The time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge.
24. The time during which the current regulation threshold is ignored so that the short-circuit detection threshold comparators may have time
to act.
25. Parameter guaranteed by characterization.
26. * Disable Delay Time measurement is defined in Figure 5, page 10.
27. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal with V
= 14 V,
PWR
R
= 3.0 ohm. See Figure 6, page 10.
LOAD
28. Load currents ramping up to the current regulation threshold become limited at the ILIM value (see Figure 7). The short-circuit currents
possess a di/dt that ramps up to the I or I threshold during the ILIM blanking time, registering as a short-circuit event detection and
SCH
SCL
causing the shutdown circuitry to force the output into an immediate tri-state latch-OFF (see Figure 8). Operation in Current Limit mode
may cause junction temperatures to rise. Junction temperatures above ~160 °C will cause the output current limit threshold to “fold back”,
or decrease, until ~175 °C is reached, after which the tLIM thermal latch-OFF will occur. Permissible operation within this fold back region
is limited to non-repetitive transient events of duration not to exceed 30 seconds (see Figure 9).
29. Parameter is Guaranteed By Design.
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
5.0
1.5 V
1.5 V
0
t
DON
80%
t
DOFF
VPWR
20%
0
TIME
Figure 4. Output Delay Time
5.0 V
0 V
1.5 V
tDDISABLE
90%
0 V
TIME
Figure 5. Disable Delay Time
.
t
t
R
F
VPWR
90%
90%
10%
10%
0
TIME
Figure 6. Output Switching Time
Overload Condition
ISC Short-circuit Detection Threshold
9.0
6.5
t
= I
Blanking Time
LIM
B
t
= Constant-OFF Time (OUT1 and OUT2 Tri-stated)
A
t
t
A
B
I
LIM
0.0
5.0
t
ON
TIME
Figure 7. Current Limit Blanking Time and Constant-OFF Time
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Short-circuit Condition
t
FAULT
ISC Short-circuit Detection Threshold
9.0
6.5
Hard Short Occurs
OUT1, OUT2 Tri-stated,
SF set Low
t
B
I
LIM
0.0
5.0
(~16 μs)
t
TIME
B
Figure 8. Short-circuit Detection Turn-OFF Time tFAULT
.
Current Limit Threshold Foldback.
Operation within this region must be
limited to non-repetitive events not to
exceed 30 s per 24 hr.
6.5
4.2
t
t
SEP
LIM
Thermal Shutdown
t
HYS
t
t
LIM
FB
Figure 9. Output Current Limiting Foldback Region
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33932 has two identical H-Bridge drivers in the same
package. The only connection that is shared internally is the
Analog Ground (AGND). This description is given for the H-
Bridge A half of the total device. However, the H-Bridge B half
will exhibit identical behavior.
H-bridge outputs to a high-impedance state (all H-bridge
switches OFF). The EN/D2 pin also controls an enable
function that allows the IC to be placed in a power-conserving
Sleep mode.
The 33932 has output current limiting (via constant OFF-
time PWM current regulation), output short-circuit detection
with latch-OFF, and over-temperature detection with latch-
OFF. Once the device is latched-OFF due to a fault condition,
either of the disable inputs (D1 or EN/D2), or VPWR must be
“toggled” to clear the status flag.
Numerous protection and operational features (speed,
torque, direction, dynamic breaking, PWM control, and
closed-loop control) make the 33932 a very attractive, cost-
effective solution for controlling a broad range of small DC
motors. The 33932 outputs are capable of supporting peak
DC load currents of up to 5.0 A from a 28 V VPWR source. An
internal charge pump and gate drive circuitry are provided
that can support external PWM frequencies up to 11 kHz.
Current limiting (Load Current Regulation) is
accomplished by a constant-OFF time PWM method using
current limit threshold triggering. The current limiting scheme
is unique in that it incorporates a junction temperature-
dependent current limit threshold. This means that the
current limit threshold is “reduced to around 4.2 A” as the
junction temperature increases above 160 °C. When the
temperature is above 175 °C, over-temperature shutdown
(latch-OFF) will occur. This combination of features allows
the device to continue operating for short periods of time (<30
seconds) with unexpected loads, while still retaining
adequate protection for both the device and the load.
The 33932 has an analog feedback (current mirror) output
pin (the FB pin) that provides a constant-current source
ratioed to the active high side MOSFETs’ current. This can be
used to provide “real time” monitoring of output current to
facilitate closed-loop operation for motor speed/torque
control, or for the detection of open load conditions.
Two independent inputs, IN1 and IN2, provide control of
the two totem-pole half-bridge outputs. Two independent
disable inputs, D1 and EN/D2, provide the means to force the
FUNCTIONAL PIN DESCRIPTION
When D1 is SET (D1 = logic HIGH) in the disable state,
outputs OUT1 and OUT2 are both tri-state disabled; however,
the rest of the device circuitry is fully operational and the
supply IPWR(STANDBY) current is reduced to a few mA. Refer
to Table 3, Static Electrical Characteristics.
POWER GROUND AND ANALOG GROUND
(PGND AND AGND)
The power and analog ground pins should be connected
together with a very low-impedance connection.
POSITIVE POWER SUPPLY (VPWR)
H-BRIDGE OUTPUT (OUT1, OUT2)
VPWR pins are the power supply inputs to the device. All
VPWR pins must be connected together on the printed circuit
board with as short as possible traces, offering as low an
impedance as possible between pins.
These pins are the outputs of the H-bridge with integrated
free-wheeling diodes. The bridge output is controlled using
the IN1, IN2, D1, and EN/D2 inputs. The outputs have PWM
current limiting above the ILIM threshold. The outputs also
have thermal shutdown (tri-state latch-OFF) with hysteresis
as well as short circuit latch-OFF protection.
STATUS FLAG (SF)
This pin is the device fault status output. This output is an
active LOW open drain structure requiring a pull-up resistor
to VDD. The maximum VDD is <7.0 V. Refer to Table 5, Truth
Table, for the SF Output status definition.
A disable timer (time tB) is incorporated to distinguish
between load currents that are higher than the ILIM threshold
and short circuit currents. This timer is activated at each
output transition.
INPUT 1,2 AND DISABLE INPUT 1
(IN1, IN2, AND D1)
CHARGE PUMP CAPACITOR (CCP)
This pin is the charge pump output pin and connection for
the external charge pump reservoir capacitor. The allowable
value is from 30 to 100 nF. This capacitor must be connected
from the CCP pin to the VPWR pin. The device cannot
operate properly without the external reservoir capacitor.
These pins are input control pins used to control the
outputs. These pins are 3.0 V/5.0 V CMOS-compatible
inputs with hysteresis. IN1 and IN2 independently control
OUT1 and OUT2, respectively. D1 input is used to tri-state
disable the H-Bridge outputs.
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
The FB pin provides current sensing feedback of the
H-Bridge high side drivers. When running in the forward or
reverse direction, a ground-referenced 0.24% of load current
is output to this pin. Through the use of an external resistor to
ground, the proportional feedback current can be converted
to a proportional voltage equivalent and the controlling
microcontroller can “read” the current proportional voltage
with its analog-to-digital converter (ADC). This is intended to
provide the user with only first-order motor current feedback
for motor torque control. The resistance range for the linear
operation of the FB pin is 100 Ω <RFB <300 Ω.
ENABLE INPUT/DISABLE INPUT 2 (EN/D2)
The EN/D2 pin performs the same function as D1 pin,
when it goes to a logic LOW the outputs are immediately tri-
stated. It is also used to place the device in a Sleep mode so
as to consume very low currents. When the EN/D2 pin
voltage is a logic LOW state, the device is in the Sleep mode.
The device is enabled and fully operational when the EN pin
voltage is logic HIGH. An internal pull-down resistor
maintains the device in Sleep mode in the event EN is driven
through a high-impedance I/O or an unpowered
microcontroller, or the EN/D2 input becomes disconnected.
If PWM-ing is implemented using the disable pin input
(only D1), a small filter capacitor (~1.0 µF) may be required
in parallel with the RFB resistor to ground for spike
suppression.
FEEDBACK (FB)
The 33932 has a feedback output (FB) for “real time”
monitoring of H-Bridge high side output currents to facilitate
closed-loop operation for motor speed and torque control.
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC33932 - Functional Block Diagram
Analog Control & Protection
H-Bridge
Output Drivers
Current Sense
Voltage Regulation
Temperature Sense
Charge Pump
Gate Control Logic
Input Logic Control
OUT1 - OUT2
Fault Logic
Protection Logic Control
MCU Interface
Analog Control & Protection
Logic and Control
H-Bridge Output Drivers
Figure 10. Functional Internal Block Diagram
two half-bridge totem-pole outputs. Two independent disable
inputs are provided to force the H-Bridge outputs to tri-state
(high-impedance off-state).
ANALOG CONTROL AND PROTECTION
CIRCUITRY:
An on-chip voltage regulator supplies the internal logic.
The charge pump provides gate drive for the H-Bridge
MOSFETs. The Current and Temperature sense circuitry
provides detection and protection for the output drivers.
Output under-voltage protection shuts down the MOSFETS.
H-BRIDGE OUTPUT DRIVERS: OUT1 AND OUT2
The H-Bridge is the power output stage. The current flow
from OUT1 to OUT2 is reversible and under full control of the
user by way of the Input Control Logic. The output stage is
designed to produce full load control under all system
conditions. All protective and control features are integrated
into the control and protection blocks. The sensors for current
and temperature are integrated directly into the output
MOSFET for maximum accuracy and dependability.
GATE CONTROL LOGIC:
The 33932 is a monolithic H-Bridge Power IC designed
primarily for any low-voltage DC servo motor control
application within the current and voltage limits stated for the
device. Two independent inputs provide polarity control of
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
9.0
6.5
Typical Short-circuit Detection Threshold
Typical Current Limit Threshold
High Current Load Being Regulated via Constant-OFF-Time PWM
Moderate Current Load
PWM
Current
Limiting
0
IN1 or IN2
IN2 or IN1
IN1 or IN2
IN2 or IN1
[1]
IN1 IN2
[0]
[1]
[0]
[1]
[0]
[1]
Outputs
Tri-stated
Outputs
Tri-stated
Outputs Operation
(per Input Control Condition)
[0]
Time
Figure 11. Operating States
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS
LOGIC COMMANDS
Table 5. Truth Table
The tri-state conditions and the status flag are reset using D1 or D2. The truth table uses the following notations: L = LOW, H =
HIGH, X = HIGH or LOW, and Z = High-impedance. All output power transistors are switched off.
Input Conditions
D1 IN1
Status
Outputs
OUT1 OUT2
Device State
EN/D2
IN2
SF
Forward
Reverse
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
L
H
H
L
L
L
H
L
H
H
H
L
H
L
Freewheeling Low
Freewheeling High
Disable 1 (D1)
L
L
L
L
H
X
Z
X
X
X
X
X
X
X
H
X
X
Z
X
X
X
X
X
X
H
Z
H
X
Z
Z
Z
Z
Z
Z
H
Z
X
H
Z
Z
Z
Z
Z
Z
H
L
IN1 Disconnected
IN2 Disconnected
D1 Disconnected
Under-voltage Lockout(30)
Over-temperature(31)
Short-circuit(31)
H
H
L
L
Z
X
X
X
X
X
L
L
L
Sleep mode EN/D2
EN/D2 disconnected
Notes
H
H
Z
30. In the event of an under-voltage condition, the outputs tri-state and status flag is SET logic LOW. Upon under-voltage
recovery, status flag is reset automatically or automatically cleared and the outputs are restored to their original operating
condition.
31. When a short-circuit or over-temperature condition is detected, the power outputs are tri-state latched-OFF independent of
the input signals and the status flag is latched to logic LOW. To reset from this condition requires the toggling of either D1,
EN/D2, or V
.
PWR
Reverse
Forward
Low-Side Recirculation
High-Side Recirculation
(Forward)
V
V
(Forward)
V
V
V
PWR
V
PWR
PWR
PWR
V
PWR
V
PWR
PWR
PWR
Load
Current
Load
Current
Load
Current
ON
OUT1
OFF
OUT2
OFF
OUT1
ON
OUT2
OFF
OUT1
OFF
OUT2
ON
OUT1
ON
OUT2
LOAD
LOAD
LOAD
LOAD
OFF
ON
ON
OFF
Load
Current
ON
ON
OFF
OFF
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
Figure 12. 33932 Power Stage Operation
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
PROTECTION AND DIAGNOSTIC FEATURES
SHORT-CIRCUIT PROTECTION
OVER-TEMPERATURE SHUTDOWN AND
HYSTERESIS
If an output short-circuit condition is detected, the power
outputs tri-state (latch-OFF) independent of the input (IN1
and IN2) states, and the fault status output flag (SF) is SET
to logic LOW. If the D1 input changes from logic HIGH to logic
LOW, or if the EN/D2 input changes from logic LOW to logic
HIGH, the output bridge will become operational again and
the fault status flag will be reset (cleared) to a logic HIGH
state.
If an over-temperature condition occurs, the power outputs
are tri-stated (latched-OFF) and the fault status flag (SF) is
SET to logic LOW.
To reset from this condition, D1 must change from logic
HIGH to logic LOW, or EN/D2 must change from logic LOW
to logic HIGH. When reset, the output stage switches ON
again, provided that the junction temperature is now below
the over-temperature threshold limit minus the hysteresis.
The output stage will always switch into the mode defined
by the input pins (IN1, IN2, D1, and EN/D2), provided the
device junction temperature is within the specified operating
temperature range.
Important Resetting from the fault condition will clear the
fault status flag. Powering down and powering up the device
will also reset the 33932 from the fault condition.
INTERNAL PWM CURRENT LIMITING
OUTPUT AVALANCHE PROTECTION
The maximum current flow under normal operating
conditions should be less than 5.0 A. The instantaneous load
currents will be limited to ILIM via the internal PWM current
limiting circuitry. When the ILIM threshold current value is
reached, the output stages are tri-stated for a fixed time (TA)
of 20 µs typical. Depending on the time constant associated
with the load characteristics, the output current decreases
during the tri-state duration until the next output ON cycle
occurs.
If VPWR were to become an open circuit, the outputs
would likely tri-state simultaneously due to the disable logic.
This could result in an unclamped inductive discharge. The
VPWR input to the 33932 should not exceed 40 V during this
transient condition, to prevent electrical overstress of the
output drivers.This can be accomplished with a zener clamp
or MOV, and/or an appropriately valued input capacitor with
sufficiently low ESR (see Figure 13).
The PWM current limit threshold value is dependent on the
device junction temperature. When -40 °C <TJ <160 °C, ILIM
is between the specified minimum/maximum values. When
TJ exceeds 160 °C, the ILIM threshold decreases to 4.2 A.
Shortly above 175 °C the device over-temperature circuit will
detect tLIM and an over-temperature shutdown will occur. This
feature implements a graceful degradation of operation
before thermal shutdown occurs, thus allowing for
V
PWR
VPWR
Bulk
Low ESR
Cap.
100nF
OUT1
OUT2
M
intermittent unexpected mechanical loads on the motor’s
gear-reduction train to be handled.
9
I/Os
Important Die temperature excursions above 150 °C are
permitted only for non-repetitive durations <30 seconds.
Provision must be made at the system level to prevent
prolonged operation in the current-foldback region.
AGND PGND
Figure 13. Avalanche Protection
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
TYPICAL APPLICATIONS
INTRODUCTION
TYPICAL APPLICATIONS
INTRODUCTION
A typical application schematic is shown in Figure 14. For
precision high-current applications in harsh, noisy
environments, the VPWR by-pass capacitor may need to be
substantially larger.
V
PWR
100 μF
100 nF
VPWRA
33 nF
VDD
LOGIC SUPPLY
VCP
CHARGE
PUMP
HS1
LS1
HS2
LS2
CCPA
IN1
OUT1
OUT2
M
TO GATES
HS1
LS1
IN2
EN/D2
D1
HS2
LS2
PGND
GATE DRIVE
AND
PROTECTION
LOGIC
+5.0 V
VSENSE
CURRENT MIRRORS
AND
CONSTANT OFF-TIME
STATUS
FLAG
ILIM PWM
SFA
FBA
PWM CURRENT REGULATOR
TO
ADC
R
FB
270 Ω
1.0 μF
AGNDA
PGNDA
Figure 14. 33932 Typical Application Schematic 1/2 Device
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the 98Axxxxxxxxx listed
below. Dimensions shown are provided for reference ONLY.
VW SUFFIX
44-PIN
98ARH98330A
REVISION B
33932
Analog Integrated Circuit Device Data
18
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
VW SUFFIX
44-PIN
98ARH98330A
REVISION B
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
PACKAGING
PACKAGE DIMENSIONS
EK SUFFIX
54-PIN
98ASA99334D
REVISION C
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
PACKAGING
PACKAGE DIMENSIONS
EK SUFFIX
54-PIN
98ASA99334D
REVISION C
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
PACKAGING
PACKAGE DIMENSIONS
EK SUFFIX
54-PIN
98ASA99334D
REVISION C
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
ADDITIONAL DOCUMENTATION
PACKAGE DIMENSIONS
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM
Introduction
This thermal addendum is provided as a supplement to the MC33932 technical datasheet. The addendum provides thermal
performance information that may be critical in the design and development of system applications. All electrical, application, and
packaging information is provided in the datasheet.
Package and Thermal Considerations
The MC33932 is offered in a 54-pin SOIC-EP and a 44-pin HSOP single die package. There is a single heat source (P), a
single junction temperature (TJ), and thermal resistance (RθJA). This thermal addendum is specific to the 54-pin SOIC-EP
package.
TJ
.
=
RθJA
P
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to, and will not predict the performance of a package in an application-specific environment.
Stated values were obtained by measurement and simulation according to the standards listed below.
Table 6. Table of Thermal Resistance Data
Rating
Value
Unit
Notes
(32) (33)
Junction to Ambient
Natural Convection
Single Layer board (1s)
Four layer board (2s2p)
RθJA
58.8
°C/W
,
(32) (34)
Junction to Ambient
Natural Convection
RθJA
24.4
°C/W
,
(35)
(38)
(36)
(37)
Junction to Board
Junction to Case (bottom / flag)
Junction to Case (top)
RθJB
7.0
0.36
18
°C/W
°C/W
°C/W
°C/W
RθJC
(bottom)
RθJC
(top)
Junction to Package Top
Natural Convection
ΨJT
2.0
Notes
32. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature,
ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
33. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
34. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
35. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
36. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
37. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per
JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
38. Thermal resistance between the die and the case bottom / flag surface (simulated) (flag bottom side fixed to ambient temperature).
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
THERMAL ADDENDUM
PACKAGE DIMENSIONS
Figure 15. Transient Thermal Resistance RθJA MC33932EK on 2s2p Test Board
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
REFERENCE SECTION
PACKAGE DIMENSIONS
REFERENCE SECTION
Table 7. Thermal Analysis Reference Documents
Reference
Description
AN4146
BASICTHERMALWP
Thermal Modeling and Simulation of 12V Gen3 eXtreme Switch Devices with SPICE
Basic Principles of Thermal Analysis for Semiconductor Systems
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
REVISION HISTORY
REVISION HISTORY
REVISION DATE
DESCRIPTION
• Initial Release
1.0
2.0
3.0
8/2007
8/2008
11/2008
• Added parameters (TBD) for Change Pump Voltages in Table 3.
• Changed maximum RDS(ON) from 225 to 235 mΩ.
• Changed Peak Package Reflow Temperature During Reflow(7) (8)
,
• Changed Approximate Junction-to Case Thermal Resistance(9)
• Added PC33932EK to the Ordering Information Table
• Added EK ordering information
4.0
6/2012
• Form and style corrections
• Added note 25
• Added Thermal Addendum and Reference Document sections
• Added 98ASA99334D package drawing
• Minor corrections throughout the spec
33932
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
Information in this document is provided solely to enable system and software
implementers to use Freescale products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits on the
information in this document.
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herein. Freescale makes no warranty, representation, or guarantee regarding the
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disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in Freescale data sheets and/or
specifications can and do vary in different applications, and actual performance may
vary over time. All operating parameters, including “typicals,” must be validated for
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© 2012 Freescale Semiconductor, Inc.
Document Number: MC33932
Rev. 4.0
6/2012
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MOTOROLA
PC33981PNAR2
100A PWM BASED PRPHL DRVR, PQCC16, 12 X 12 MM, 2.10 MM HEIGHT, 0.90 MM PITCH, ROHS COMPLIANT, PLASTIC, QFN-16
NXP
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