PCA85176H-Q900 [NXP]
Universal LCD driver for low multiplex rates; 低复用率的通用LCD驱动器
| 型号： | PCA85176H-Q900 |
| 厂家： | 
NXP |
| 描述： | Universal LCD driver for low multiplex rates |
| 文件： | 总44页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA85176
Universal LCD driver for low multiplex rates
Rev. 01 — 14 April 2010
Product data sheet
1. General description
The PCA85176 is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily
cascaded for larger LCD applications. The PCA85176 is compatible with most
microprocessors or microcontrollers and communicates via a two-line bidirectional
I2C-bus. Communication overheads are minimized by a display RAM with
auto-incremented addressing, by hardware subaddressing, and by display memory
switching (static and duplex drive modes).
AEC-Q100 compliant for automotive applications.
2. Features and benefits
Single chip LCD controller and driver
Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing
Selectable display bias configuration: static, 1⁄2, or 1⁄3
Internal LCD bias generation with voltage-follower buffers
40 segment drives:
Up to twenty 7-segment alphanumeric characters
Up to ten 14-segment alphanumeric characters
Any graphics of up to 160 elements
40 × 4-bit RAM for display data storage
Auto-incremented display data loading across device subaddress boundaries
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
Independent supplies possible for LCD and logic voltages
Wide power supply range: from 1.8 V to 5.5 V
Wide logic LCD supply range:
From 2.5 V for low-threshold LCDs
Up to 8.0 V for guest-host LCDs and high-threshold twisted nematic LCDs
Low power consumption
Extended temperature range up to 95 °C
400 kHz I2C-bus interface
May be cascaded for large LCD applications (up to 2560 elements possible)
No external components required
Manufactured in silicon gate CMOS process
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 16.
PCA85176
NXP Semiconductors
Universal LCD driver for low multiplex rates
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
PCA85176H/Q900
PCA85176T/Q900
TQFP64
plastic thin quad flat package, 64 leads;
body 10 × 10 × 1.0 mm
SOT357-1
TSSOP56 plastic thin shrink small outline package, 56 leads; SOT364-1
body width 6.1 mm
4. Marking
Table 2.
Marking codes
Type number
PCA85176H/Q900
PCA85176T/Q900
Marking code
PCA85176H
PCA85176T
5. Block diagram
BP0 BP2 BP1 BP3
S0 to S39
40
V
LCD
BACKPLANE
OUTPUTS
DISPLAY SEGMENT
OUTPUTS
LCD
VOLTAGE
SELECTOR
DISPLAY
REGISTER
DISPLAY
CONTROLLER
OUTPUT BANK SELECT
AND BLINK CONTROL
LCD BIAS
GENERATOR
V
SS
CLK
CLOCK SELECT
AND TIMING
BLINKER
TIMEBASE
PCA85176
DISPLAY RAM
SYNC
POWER-ON
RESET
COMMAND
DECODER
WRITE DATA
CONTROL
DATA POINTER AND
AUTO INCREMENT
OSC
OSCILLATOR
V
DD
SCL
SDA
2
INPUT
FILTERS
I C-BUS
SUBADDRESS
COUNTER
CONTROLLER
SA0
A0
A1
A2
013aaa048
Fig 1. Block diagram of PCA85176
PCA85176_1
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 14 April 2010
2 of 44
PCA85176
NXP Semiconductors
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
n.c.
S34
S35
S36
S37
S38
S39
n.c.
n.c.
S17
S16
S15
S14
S13
S12
S11
S10
S9
3
4
5
6
7
8
PCA85176H
9
n.c.
10
11
12
13
14
15
16
SDA
SCL
SYNC
CLK
S8
S7
S6
V
S5
DD
OSC
A0
S4
n.c.
013aaa049
Top view. For mechanical details, see Figure 25.
Fig 2. Pinning diagram for TQFP64 (PCA85176H/Q900)
PCA85176_1
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 14 April 2010
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PCA85176
NXP Semiconductors
Universal LCD driver for low multiplex rates
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
BP2
BP1
BP3
S0
BP0
2
V
LCD
V
SS
3
4
SA0
A2
5
S1
6
S2
A1
7
S3
A0
8
S4
OSC
9
S5
V
DD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
S6
CLK
SYNC
SCL
SDA
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
PCA85176T
013aaa050
Top view. For mechanical details, see Figure 26.
Fig 3. Pinning diagram for TSSOP56 (PCA85176T/Q900)
PCA85176_1
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 14 April 2010
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PCA85176
NXP Semiconductors
Universal LCD driver for low multiplex rates
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
Type
TQFP64
TSSOP56
(PCA85176H/Q900) (PCA85176T/Q900)
SDA
SCL
10
44
input/output I2C-bus serial data line
input
I2C-bus serial clock
input/output clock line
11
45
CLK
13
47
VDD
14
48
supply
supply voltage
SYNC
OSC
A0 to A2
SA0
12
46
input/output cascade synchronization
15
49
input
internal oscillator enable
16 to 18
19
50 to 52
53
input
subaddress inputs
input
I2C-bus address input
ground supply voltage
LCD supply voltage
VSS
20
54
supply
supply
output
VLCD
21
55
BP0, BP2, 25 to 28
BP1, BP3
56, 1, 2, 3
LCD backplane outputs
S0 to S39 29 to 32, 34 to 47,
49 to 64, 2 to 7
4 to 43
-
output
-
LCD segment outputs
n.c.
1, 8, 9, 22 to 24,
33, 48
not connected; do not
connect and do not use as
feed through
PCA85176_1
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 14 April 2010
5 of 44
PCA85176
NXP Semiconductors
Universal LCD driver for low multiplex rates
7. Functional description
The PCA85176 is a versatile peripheral device designed to interface any
microprocessor or microcontroller with a wide variety of LCDs. It can directly drive any
static or multiplexed LCD containing up to four backplanes and up to 40 segments.
The possible display configurations of the PCA85176 depend on the number of active
backplane outputs required. A selection of display configurations is shown in Table 4. All
of these configurations can be implemented in the typical system shown in Figure 4.
Table 4.
Display configurations
Number of:
7-segment alphanumeric
Digits Indicator symbols
14-segment alphanumeric
Dot matrix
Backplanes
Elements
160
Characters
Indicator symbols
4
3
2
1
20
15
10
5
20
15
10
5
10
8
20
8
160 dots (4 × 40)
120 dots (3 × 40)
80 dots (2 × 40)
40 dots (1 × 40)
120
80
5
10
12
40
2
V
DD
t
r
R ≤
2C
B
V
V
DD
LCD
40 segment drives
4 backplanes
SDA
SCL
OSC
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
LCD PANEL
PCA85176
(up to 160
elements)
A0 A1 A2 SA0
V
SS
013aaa051
V
SS
The resistance of the power lines must be kept to a minimum.
Fig 4. Typical system configuration
The host microprocessor or microcontroller maintains the 2-line I2C-bus communication
channel with the PCA85176. The internal oscillator is enabled by connecting
pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms
are generated internally. The only other connections required to complete the system are
the power supplies (VDD, VSS, and VLCD) and the LCD panel chosen for the application.
7.1 Power-On Reset (POR)
At power-on the PCA85176 resets to the following starting conditions:
• All backplane and segment outputs are set to VLCD
• The selected drive mode is: 1:4 multiplex with 1⁄3 bias
• Blinking is switched off
• Input and output bank selectors are reset
• The I2C-bus interface is initialized
• The data pointer and the subaddress counter are cleared (set to logic 0)
PCA85176_1
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 14 April 2010
6 of 44
PCA85176
NXP Semiconductors
Universal LCD driver for low multiplex rates
• Display is disabled
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of the three
series resistors connected between VLCD and VSS. The center resistor is bypassed by
switch if the 1⁄2 bias voltage level for the 1:2 multiplex configuration is selected.
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
V
LCD and the resulting discrimination ratios (D) are given in Table 5.
Table 5.
Biasing characteristics
Number of:
LCD drive
mode
LCD bias
configuration
Voff(RMS) Von(RMS)
------------------------ ----------------------- D = ------------------------
VLCD VLCD Voff(RMS)
Von(RMS)
Backplanes Levels
static
1
2
2
3
4
2
3
4
4
4
static
0
1
∞
1
1:2 multiplex
1:2 multiplex
1:3 multiplex
1:4 multiplex
⁄
2
0.354
0.333
0.333
0.333
0.791
0.745
0.638
0.577
2.236
2.236
1.915
1.732
1
⁄
3
1
⁄
3
1
⁄
3
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode a suitable choice is VLCD > 3Vth.
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
1
Bias is calculated by ------------ , where the values for a are
1 + a
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:
a2 + 2a + n
n × (1 + a)2
Von(RMS)
=
-----------------------------
(1)
V
LCD
where the values for n are
n = 1 for static drive mode
n = 2 for 1:2 multiplex drive mode
n = 3 for 1:3 multiplex drive mode
n = 4 for 1:4 multiplex drive mode
PCA85176_1
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Product data sheet
Rev. 01 — 14 April 2010
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PCA85176
NXP Semiconductors
Universal LCD driver for low multiplex rates
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
a2 – 2a + n
n × (1 + a)2
Voff(RMS)
=
-----------------------------
(2)
(3)
V
LCD
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:
(a + 1)2 + (n – 1)
Von(RMS)
----------------------
D =
=
-------------------------------------------
(a – 1)2 + (n – 1)
Voff(RMS)
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with
1⁄2 bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
21
1⁄2 bias is ---------- = 1.528 .
3
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
• 1:3 multiplex (1⁄2 bias): VLCD
• 1:4 multiplex (1⁄2 bias): VLCD
=
=
6 × Voff(RMS) = 2.449Voff(RMS)
(4 × 3)
---------------------
= 2.309Voff(RMS)
3
These compare with VLCD = 3Voff(RMS) when 1⁄3 bias is used.
It should be noted that VLCD is sometimes referred as the LCD operating voltage.
PCA85176_1
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Product data sheet
Rev. 01 — 14 April 2010
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PCA85176
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. The
backplane (BPn) and segment (Sn) drive waveforms for this mode are shown in Figure 5.
T
fr
LCD segments
V
LCD
BP0
Sn
V
SS
state 1
(on)
state 2
(off)
V
LCD
V
SS
V
LCD
Sn+1
V
SS
(a) Waveforms at driver.
V
LCD
0 V
state 1
−V
LCD
V
LCD
state 2
0 V
−V
LCD
(b) Resultant waveforms
at LCD segment.
013aaa207
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = VLCD
.
Vstate2(t) = V(Sn + 1)(t) − VBP0(t).
Voff(RMS) = 0 V.
Fig 5. Static drive mode waveforms
PCA85176_1
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 14 April 2010
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PCA85176
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCA85176 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 6 and
Figure 7.
T
fr
V
LCD
LCD segments
V
V
/2
/2
BP0
BP1
Sn
LCD
SS
state 1
V
LCD
state 2
V
V
LCD
SS
V
LCD
V
V
SS
LCD
Sn+1
V
SS
(a) Waveforms at driver.
V
V
LCD
/2
LCD
0 V
−V
state 1
/2
LCD
−V
LCD
V
V
LCD
/2
LCD
0 V
state 2
−V
/2
LCD
LCD
−V
(b) Resultant waveforms
at LCD segment.
013aaa208
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.791VLCD
Vstate2(t) = VSn(t) − VBP1(t).
Voff(RMS) = 0.354VLCD
.
.
Fig 6. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
PCA85176_1
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 14 April 2010
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PCA85176
NXP Semiconductors
Universal LCD driver for low multiplex rates
T
fr
V
LCD
LCD segments
2V
/3
LCD
BP0
BP1
Sn
V
V
/3
LCD
SS
state 1
V
LCD
state 2
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
Sn+1
V
V
/3
LCD
SS
(a) Waveforms at driver.
V
LCD
2V
LCD
/3
V
/3
LCD
0 V
−V
state 1
/3
/3
LCD
−2V
LCD
−V
LCD
V
LCD
2V
LCD
/3
V
LCD
/3
0 V
−V
state 2
/3
/3
LCD
−2V
LCD
−V
LCD
(b) Resultant waveforms
at LCD segment.
013aaa209
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.745VLCD
Vstate2(t) = VSn(t) − VBP1(t).
Voff(RMS) = 0.333VLCD
.
.
Fig 7. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias
PCA85176_1
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Product data sheet
Rev. 01 — 14 April 2010
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PCA85176
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as
shown in Figure 8.
T
fr
V
LCD
LCD segments
2V
/3
LCD
BP0
BP1
BP2
Sn
V
V
/3
LCD
SS
state 1
state 2
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
Sn+1
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
Sn+2
V
V
/3
LCD
SS
(a) Waveforms at driver.
V
LCD
2V
LCD
/3
V
/3
LCD
state 1
0 V
−V
/3
/3
LCD
−2V
LCD
−V
LCD
V
LCD
2V
LCD
/3
V
/3
LCD
state 2
0 V
−V
/3
/3
LCD
−2V
LCD
−V
LCD
(b) Resultant waveforms
at LCD segment.
013aaa210
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.638VLCD
Vstate2(t) = VSn(t) − VBP1(t).
Voff(RMS) = 0.333VLCD
.
.
Fig 8. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
PCA85176_1
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Product data sheet
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PCA85176
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as
shown in Figure 9.
T
fr
V
LCD
LCD segments
2V
/3
/3
LCD
BP0
BP1
BP2
V
V
LCD
SS
state 1
state 2
V
LCD
2V
LCD
/3
/3
V
V
LCD
SS
V
LCD
2V
LCD
/3
/3
V
V
LCD
SS
V
LCD
2V
/3
/3
LCD
BP3
Sn
V
V
LCD
SS
V
LCD
2V
LCD
/3
/3
V
V
LCD
SS
V
LCD
2V
/3
/3
LCD
Sn+1
V
V
LCD
SS
V
LCD
2V
/3
/3
LCD
Sn+2
Sn+3
V
V
LCD
SS
V
LCD
2V
LCD
/3
/3
V
V
LCD
SS
(a) Waveforms at driver.
V
LCD
2V
LCD
/3
V
/3
LCD
state 1
0 V
−V
/3
LCD
−2V
LCD
/3
LCD
−V
V
LCD
2V
LCD
/3
V
/3
LCD
0 V
−V
state 2
/3
LCD
−2V
LCD
/3
LCD
−V
(b) Resultant waveforms
at LCD segment.
013aaa211
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.577VLCD
Vstate2(t) = VSn(t) − VBP1(t).
Voff(RMS) = 0.333VLCD
.
.
Fig 9. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias
PCA85176_1
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Product data sheet
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PCA85176
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.5 Oscillator
7.5.1 Internal clock
The internal logic of the PCA85176 and its LCD drive signals are timed either by its
internal oscillator or by an external clock. The internal oscillator is enabled by connecting
pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used
as the clock signal for several PCA85176 in the system that are connected in cascade.
7.5.2 External clock
A clock signal must always be supplied to the device; removing the clock may freeze the
LCD in a DC state, which is not suitable for the liquid crystal.
7.6 Timing
The PCA85176 timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. In cascaded
applications, the correct timing relationship between each PCA85176 in the system is
maintained by the synchronization signal at pin SYNC. The timing also generates the LCD
frame signal whose frequency is derived from the clock frequency. The frame signal
frequency is a fixed division of the clock frequency from either the internal or an external
fclk
-------
=
clock: ffr
24
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
7.8 Segment outputs
The LCD drive section includes 40 segment outputs S0 to S39 which should be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display register. When
less than 40 segment outputs are required, the unused segment outputs should be left
open-circuit.
7.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outputs can be left open-circuit.
• In 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
• In 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals
and may also be paired to increase the drive capabilities.
• In static drive mode the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
PCA85176_1
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 14 April 2010
14 of 44
PCA85176
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.10 Display RAM
The display RAM is a static 40 × 4-bit RAM which stores LCD data.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
The display RAM bit map, Figure 10, shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the
segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,
second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2,
and BP3 respectively.
display RAM addresses (columns)/segment outputs (S)
0
1
2
3
4
35 36 37 38 39
0
1
2
3
display RAM bits
(rows)/
backplane outputs
(BP)
mbe525
The display RAM bitmap shows the direct relationship between the display RAM column and the
segment outputs; and between the bits in a RAM row and the backplane outputs.
Fig 10. Display RAM bit map
When display data is transmitted to the PCA85176 the display bytes received are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and does not wait for an acknowledge cycle as with the commands. Depending
on the current multiplex drive mode, data is stored singularly, in pairs, triples or
quadruples. To illustrate the filling order, an example of a 7-segment numeric display
showing all drive modes is given in Figure 11; the RAM filling organization depicted
applies equally to other LCD types.
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drive mode
LCD segments
LCD backplanes
display RAM filling order
transmitted display byte
columns
display RAM address/segment outputs (s)
byte1
S
n+2
S
n+3
S
n+4
S
n+5
S
n+6
a
b
BP0
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
S
f
n+1
rows
static
display RAM
rows/backplane
outputs (BP)
MSB
LSB
g
0
1
2
3
c
x
x
x
b
x
x
x
a
x
x
x
f
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
S
S
n
x
x
x
e
n+7
c
b
a
f
g
e
d
DP
c
x
d
DP
x
columns
display RAM address/segment outputs (s)
byte1 byte2
BP0
a
S
S
n
1:2
b
n
n + 1 n + 2 n + 3
f
n+1
rows
MSB
LSB
DP
display RAM
rows/backplane
outputs (BP)
g
0
1
2
3
a
b
x
x
f
e
c
x
x
d
DP
x
multiplex
g
x
x
BP1
a
b
f
g
e c d
e
S
S
n+2
c
d
DP
x
n+3
columns
display RAM address/segment outputs (s)
BP0
BP1
byte1
byte2
byte3
S
S
n+1
a
1:3
b
n
n + 1 n + 2
S
n
f
n+2
rows
MSB
LSB
e
display RAM
rows/backplane
outputs (BP)
0
1
2
3
b
DP
c
a
d
g
x
f
g
multiplex
b
DP
c
a
d
g
f
e
x
x
BP2
e
c
d
DP
x
columns
display RAM address/segment outputs (s)
byte2 byte3 byte4
byte1
byte5
a
S
S
n
1:4
b
BP2
BP3
n
n + 1
BP0
BP1
f
rows
display RAM
rows/backplane
outputs (BP)
g
0
1
2
3
a
c
f
MSB
LSB
d
multiplex
e
g
d
e
c
b
a
c
b
DP
f
e
g
d
DP
DP
n+1
001aaj646
x = data bit unchanged.
Fig 11. Relationship between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus
PCA85176
NXP Semiconductors
Universal LCD driver for low multiplex rates
The following applies to Figure 11:
• In static drive mode the eight transmitted data bits are placed in row 0 of eight
successive 4-bit RAM words.
• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 of four successive 4-bit RAM words.
• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 to
three successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted.
• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 of two successive 4-bit RAM words.
7.11 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 11). Following this command,
an arriving data byte is stored at the display RAM address indicated by the data pointer.
The filling order is shown in Figure 11.
After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode:
• In static drive mode by eight
• In 1:2 multiplex drive mode by four
• In 1:3 multiplex drive mode by three
• In 1:4 multiplex drive mode by two
If an I2C-bus data access is terminated early then the state of the data pointer is unknown.
The data pointer should be re-written prior to further RAM accesses.
7.12 Subaddress counter
The storage of display data is determined by the contents of the subaddress counter.
Storage is allowed only when the content of the subaddress counter match with the
hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined
by the device-select command (see Table 12). If the content of the subaddress counter
and the hardware subaddress do not match then data storage is inhibited but the data
pointer is incremented as if data storage had taken place. The subaddress counter is also
incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCA85176 occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character.
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The hardware subaddress must not be changed while the device is being accessed on the
I2C-bus interface.
7.13 Output bank selector
The output bank selector (see Table 13) selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the
selected LCD drive mode in operation and on the instant in the multiplex sequence.
• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the contents of row 1, row 2, and then row 3
• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
• In 1:2 multiplex mode, rows 0 and 1 are selected
• In static mode, row 0 is selected
The PCA85176 includes a RAM bank switching feature in the static and 1:2 multiplex
drive modes. In the static drive mode, the bank-select command may request the contents
of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex
mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives
the provision for preparing display information in an alternative bank and to be able to
switch to it once it is assembled.
7.14 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode
or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see
Table 13). The input bank selector functions independently to the output bank selector.
7.15 Blinker
The display blinking capabilities of the PCA85176 are very versatile. The whole display
can blink at frequencies selected by the blink-select command (see Table 14). The blink
frequencies are fractions of the clock frequency. The ratio between the clock and blink
frequencies depends on the blink mode selected (see Table 6).
An additional feature is for an arbitrary selection of LCD elements to blink. This applies to
the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the blink frequency. This mode can
also be specified by the blink-select command.
In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups of
LCD elements can blink by selectively changing the display RAM data at fixed time
intervals.
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Table 6.
Blink mode
Blink frequencies[1]
Blink frequency equation
off
1
-
fclk
---------
768
fblink
=
=
=
2
3
fclk
------------
1536
fblink
fclk
------------
3072
fblink
[1] The blink frequency is proportional to the clock frequency (fclk). For the range of the clock frequency see
Table 17.
The entire display can blink at a frequency other than the nominal blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 10).
7.16 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta Line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
7.16.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 12).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 12. Bit transfer
7.16.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see Figure 13).
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SDA
SCL
SDA
SCL
S
P
START condition
STOP condition
mbc622
Fig 13. Definition of START and STOP conditions
7.16.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves (see Figure 14).
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
mga807
Fig 14. System configuration
7.16.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
• A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is illustrated in Figure 15.
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Universal LCD driver for low multiplex rates
data output
by transmitter
not acknowledge
acknowledge
data output
by receiver
SCL from
master
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
Fig 15. Acknowledgement of the I2C-bus
7.16.5 I2C-bus controller
The PCA85176 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCA85176 are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress inputs A0, A1, and A2 are
normally tied to VSS which defines the hardware subaddress 0. In multiple device
applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme, so that
no two devices with a common I2C-bus slave address have the same hardware
subaddress.
7.16.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
7.16.7 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are used to address the
PCA85176. The entire I2C-bus slave address byte is shown in Table 7.
Table 7.
I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
0
MSB
LSB
R/W
0
1
1
1
0
0
SA0
The PCA85176 is a write-only device and will not respond to a read access, therefore bit 0
should always be logic 0. Bit 1 of the slave address byte that a PCA85176 will respond to,
is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).
Having two reserved slave addresses allows the following on the same I2C-bus:
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• Up to 16 PCA85176 for very large LCD applications
• The use of two types of LCD multiplex drive
The I2C-bus protocol is shown in Figure 16. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of two possible PCA85176
slave addresses available. All PCA85176 whose SA0 inputs correspond to bit 0 of the
slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is
ignored by all PCA85176 whose SA0 inputs are set to the alternative level.
acknowledge
acknowledge by
by A0, A1 and A2
all addressed
selected
PCA85176 only
PCA85176s
R/W
0
slave address
S
A
0
0
1
1
1
0
0
A
C
COMMAND
A
DISPLAY DATA
A
P
S
1 byte
n ≥ 1 byte(s)
n ≥ 0 byte(s)
update data pointers
and if necessary,
subaddress counter
013aaa053
Fig 16. I2C-bus protocol
After an acknowledgement, one or more command bytes follow that define the status of
each addressed PCA85176.
The last command byte sent is identified by resetting its most significant bit, continuation
bit C (see Figure 17). The command bytes are also acknowledged by all addressed
PCA85176 on the bus.
MSB
LSB
C
REST OF OPCODE
msa833
Fig 17. Format of command byte
After the last command byte, one or more display data bytes may follow. Display data
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically updated
and the data directed to the intended PCA85176 device.
An acknowledgement after each byte is asserted only by the PCA85176 that are
addressed via address lines A0, A1, and A2. After the last display byte, the I2C-bus
master asserts a STOP condition (P). Alternately a START may be asserted to restart an
I2C-bus access.
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7.17 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus.
The commands available to the PCA85176 are defined in Table 8.
Table 8.
Definition of PCA85176 commands
Bit position labelled as - is not used.
Command
Bit
Operation Code
Reference
7
6
1
0
1
1
1
5
4
3
2
1
0
mode-set
C
C
C
C
C
0
-
E
B
M[1:0]
Table 10
Table 11
Table 12
Table 13
Table 14
load-data-pointer
device-select
bank-select
blink-select
P[5:0]
1
1
1
0
1
1
0
1
0
A[2:0]
0
I
O
A
BF[1:0]
All available commands carry a continuation bit C in their most significant bit position as
shown in Figure 17. When this bit is set logic 0, it indicates that the next byte of the
transfer to arrive will also represent a command. If this bit is set logic 1, it indicates that
the command byte is the last in the transfer. Further bytes will be regarded as display data
(see Table 9).
Table 9.
C bit description
Bit
Symbol Value
Description
continue bit
7
C
0
last control byte in the transfer; next byte will be regarded
as display data
1
control bytes continue; next byte will be a command too
Table 10. Mode-set command bit description
Bit
Symbol Value
Description
7
C
-
0, 1
10
-
see Table 9
6 to 5
fixed value
4
3
-
unused
E
display status
disabled[1]
0
1
enabled
2
B
LCD bias configuration
1⁄3 bias
1⁄2 bias
0
1
1 to 0
M[1:0]
LCD drive mode selection
static; BP0
01
10
11
00
1:2 multiplex; BP0, BP1
1:3 multiplex; BP0, BP1, BP2
1:4 multiplex; BP0, BP1, BP2, BP3
[1] The possibility to disable the display allows implementation of blinking under external control.
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Universal LCD driver for low multiplex rates
Table 11. Load-data-pointer command bit description
Bit
7
Symbol Value
Description
C
0, 1
0
see Table 9
fixed value
6
-
5 to 0
P[5:0]
000000 to
100111
6 bit binary value, 0 to 39; transferred to the data pointer to
define one of forty display RAM addresses
Table 12. Device-select command bit description
Bit
Symbol Value
Description
see Table 9
fixed value
7
C
0, 1
6 to 3
2 to 0
-
1100
A[2:0]
000 to 111
3 bit binary value, 0 to 7; transferred to the subaddress
counter to define one of eight hardware subaddresses
Table 13. Bank-select command bit description
Bit
Symbol Value
Description
Static
1:2 multiplex[1]
7
C
-
0, 1
see Table 9
fixed value
6 to 2
1
11110
I
input bank selection; storage of arriving display data
0
1
RAM bit 0
RAM bit 2
RAM bits 0 and 1
RAM bits 2 and 3
0
O
output bank selection; retrieval of LCD display data
0
1
RAM bit 0
RAM bit 2
RAM bits 0 and 1
RAM bits 2 and 3
[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
Table 14. Blink-select command bit description
Bit
7
Symbol Value
Description
C
-
0, 1
see Table 9
6 to 3
2
1110
fixed value
A
blink mode selection
0
1
normal blinking[1]
alternate RAM bank blinking[2]
1 to 0
BF[1:0]
blink frequency selection
00
01
10
11
off
1
2
3
[1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
[2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
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7.18 Display controller
The display controller executes the commands identified by the command decoder. It
contains the device’s status registers and coordinates their effects. The display controller
is also responsible for loading display data into the display RAM in the correct filling order.
8. Internal circuitry
V
DD
V
DD
SA0
CLK
V
V
V
SS
SS
DD
SCL
V
V
SS
DD
V
SS
OSC
V
V
SS
DD
SDA
SYNC
V
V
V
SS
SS
DD
A0, A1 A2
V
V
SS
LCD
BP0, BP1,
BP2, BP3
V
V
SS
V
LCD
LCD
S0 to S39
V
V
SS
SS
mdb076
Fig 18. Device protection circuits
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9. Limiting values
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
Table 15. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
−0.5
−0.5
−0.5
Max
+6.5
+9.0
+6.5
Unit
V
VDD
VLCD
VI
supply voltage
LCD supply voltage
input voltage
V
on each of the pins CLK,
SDA, SCL, SYNC, SA0,
OSC, A0 to A2
V
VO
output voltage
on each of the pins S0 to
S39, BP0 to BP3
−0.5
+9.0
V
II
input current
output current
supply current
−10
−10
−50
−50
−50
-
+10
mA
mA
mA
mA
mA
mW
mW
V
IO
IDD
+10
+50
IDD(LCD) LCD supply current
+50
ISS
ground supply current
total power dissipation
output power
+50
Ptot
Po
400
-
100
[1]
[2]
[3]
[4]
[5]
VESD
electrostatic discharge
voltage
HBM
MM
-
±2000
±200
±1000
200
-
V
CDM
-
V
Ilu
latch-up current
-
mA
°C
Tstg
Toper
storage temperature
operating temperature
−55
−40
+150
+95
°C
[1] Pass level; Human Body Model (HBM), according to Ref. 5 “JESD22-A114”
[2] Pass level; Machine Model (MM), according to Ref. 6 “JESD22-A115”
[3] Pass level; Charged-Device Model (CDM), according to Ref. 7 “JESD22-C101”
[4] Pass level; latch-up testing according to Ref. 8 “JESD78” at maximum ambient temperature (Tamb(max)).
[5] According to the NXP store and transport requirements (see Ref. 10 “NX3-00092”) the devices have to be
stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products
deviant conditions are described in that document.
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10. Static characteristics
Table 16. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = −40 °C to +95 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
1.8
2.5
-
-
-
-
-
5.5
8.0
20
V
[1]
VLCD
LCD supply voltage
supply current
V
[2][3]
[2][4]
IDD
fclk(ext) = 1536 Hz
fclk(ext) = 1536 Hz
μA
μA
IDD(LCD)
Logic
VP(POR)
VIL
LCD supply current
-
60
power-on reset supply voltage
LOW-level input voltage
1.0
1.3
-
1.6
V
V
on pins CLK, SYNC,
OSC, A0 to A2, SA0,
SCL, SDA
VSS
0.3VDD
[5][6]
VIH
HIGH-level input voltage
LOW-level output current
on pins CLK, SYNC,
OSC, A0 to A2, SA0,
SCL, SDA
0.7VDD
-
VDD
V
IOL
output sink current;
VOL = 0.4 V; VDD = 5 V
on pins CLK and SYNC
on pin SDA
1
3
1
-
-
-
-
-
-
mA
mA
mA
IOH(CLK)
IL
HIGH-level output current on pin CLK output source current;
VOH = 4.6 V; VDD = 5 V
leakage current
VI = VDD or VSS
;
−1
-
+1
μA
on pins CLK, SCL, SDA,
A0 to A2 and SA0
IL(OSC)
leakage current on pin OSC
input capacitance
VI = VDD
−1
-
-
+1
7
μA
[7]
[8]
CI
-
pF
LCD outputs
ΔVO
output voltage variation
on pins BP0 to BP3 and
S0 to S39
−100
-
+100
mV
RO
output resistance
VLCD = 5 V
on pins BP0 to BP3
on pins S0 to S39
-
-
1.5
6.0
-
-
kΩ
kΩ
[1] VLCD > 3 V for 1⁄3 bias.
[2] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[3] For typical values, see Figure 19.
[4] For typical values, see Figure 20.
[5] When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 15 (see Figure 18
as well).
[6] Propagation delay of driver between clock (CLK) and LCD driving signals.
[7] Periodically sampled, not 100 % tested.
[8] Outputs measured one at a time.
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Universal LCD driver for low multiplex rates
001aal523
5
4
3
2
1
0
I
DD
(μA)
2
3
4
5
6
V
(V)
DD
Tamb = 30 °C; 1:4 multiplex; VLCD = 6.5 V; fclk(ext) = 1.536 kHz; all RAM written with logic 1; no
display connected; I2C-bus inactive.
Fig 19. Typical IDD with respect to VDD
001aal524
20
I
DD(LCD)
(μA)
16
12
8
4
0
3
5
7
9
V
LCD
(V)
Tamb = 30 °C; 1:4 multiplex; fclk(ext) = 1.536 kHz; all RAM written with logic 1; no display connected.
Fig 20. Typical IDD(LCD) with respect to VLCD
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Universal LCD driver for low multiplex rates
11. Dynamic characteristics
Table 17. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = −40 °C to +95 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock
[1]
[1]
fclk(int)
internal clock frequency
PCA85176H
PCA85176T
1440
1920
960
1970
2640
-
2640
3600
4800
Hz
Hz
Hz
fclk(ext)
ffr
external clock frequency
frame frequency
internal clock
PCA85176H
PCA85176T
external clock
60
80
40
60
60
82
110
150
200
-
Hz
Hz
Hz
μs
μs
110
-
-
-
tclk(H)
tclk(L)
HIGH-level clock time
LOW-level clock time
-
Synchronization
tPD(SYNC_N) SYNC propagation delay
-
30
-
-
ns
μs
μs
tSYNC_NL
tPD(drv)
I2C-bus[3]
Pin SCL
fSCL
SYNC LOW time
1
-
-
[2]
driver propagation delay
VLCD = 5 V
-
30
SCL clock frequency
-
-
-
-
400
kHz
μs
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
1.3
0.6
-
-
tHIGH
μs
Pin SDA
tSU;DAT
tHD;DAT
data set-up time
data hold time
100
0
-
-
-
-
ns
ns
Pins SCL and SDA
tBUF
bus free time between a STOP and
1.3
-
-
μs
START condition
tSU;STO
tHD;STA
tSU;STA
set-up time for STOP condition
hold time (repeated) START condition
0.6
0.6
0.6
-
-
-
-
-
-
μs
μs
μs
set-up time for a repeated START
condition
tr
rise time of both SDA and SCL signals fSCL = 400 kHz
fSCL < 125 kHz
-
-
-
-
-
-
-
-
-
-
0.3
1.0
0.3
400
50
μs
μs
μs
pF
ns
tf
fall time of both SDA and SCL signals
capacitive load for each bus line
Cb
tw(spike)
spike pulse width
on the I2C-bus
[1] Typical output duty factor: 50 % measured at the CLK output pin.
[2] Not tested in production.
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD
.
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Universal LCD driver for low multiplex rates
1 / f
clk
t
t
clk(L)
clk(H)
0.7 V
0.3 V
DD
CLK
DD
0.7 V
0.3 V
DD
SYNC
DD
t
PD(SYNC_N)
t
SYNC_NL
10 %
80 %
10 %
BPn, Sn
t
013aaa298
PD(drv)
Fig 21. Driver timing waveforms
SDA
t
t
t
f
BUF
LOW
SCL
SDA
t
HD;STA
t
r
t
t
SU;DAT
HD;DAT
t
HIGH
t
SU;STA
t
SU;STO
mga728
Fig 22. I2C-bus timing waveforms
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Universal LCD driver for low multiplex rates
12. Application information
12.1 Cascaded operation
Large display configurations of up to 16 PCA85176 can be recognized on the same
I2C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable
I2C-bus slave address (SA0).
Table 18. Addressing cascaded PCA85176
Cluster
Bit SA0
Pin A2
Pin A1
Pin A0
Device
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
2
1
8
9
10
11
12
13
14
15
When cascaded PCA85176 are synchronized, they can share the backplane signals from
one of the devices in the cascade. Such an arrangement is cost-effective in large LCD
applications since the backplane outputs of only one device need to be through-plated to
the backplane electrodes of the display. The other PCA85176 of the cascade contribute
additional segment outputs, but their backplane outputs are left open-circuit
(see Figure 23).
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Universal LCD driver for low multiplex rates
V
V
LCD
DD
SDA
SCL
40 segment drives
PCA85176
SYNC
CLK
(2)
BP0 to BP3
OSC
(open-circuit)
A0 A1 A2 SA0
V
SS
LCD PANEL
V
LCD
V
t
r
DD
≤
R
2C
V
V
LCD
b
DD
40 segment drives
SDA
SCL
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
SYNC
CLK
4 backplanes
BP0 to BP3
PCA85176
(1)
OSC
A0 A1 A2 SA0
V
SS
V
SS
013aaa052
(1) Is master (OSC connected to VSS).
(2) Is slave (OSC connected to VDD).
Fig 23. Cascaded PCA85176 configuration
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCA85176. Synchronization is guaranteed after a power-on reset. The only time that
SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments or by defining a multiplex drive mode when PCA85176
with different SA0 levels are cascaded).
SYNC is organized as an input/output pin. The output selection is realized as an
open-drain driver with an internal pull-up resistor. A PCA85176 asserts the SYNC line at
the onset of its last active backplane signal and monitors the SYNC line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCA85176 to assert
SYNC. The timing relationship between the backplane waveforms and the SYNC signal
for the various drive modes of the PCA85176 are shown in Figure 24.
The contact resistance between the SYNC on each cascaded device must be controlled.
If the resistance is too high, the device is not able to synchronize properly; this is
particularly applicable to chip-on-glass applications. The maximum SYNC contact
resistance allowed for the number of devices in cascade is given in Table 19.
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Universal LCD driver for low multiplex rates
Table 19. SYNC contact resistance
Number of devices
Maximum contact resistance
2
6 kΩ
3 to 5
6 to 10
10 to 16
2.2 kΩ
1.2 kΩ
700 Ω
The PCA85176 can always be cascaded with other devices of the same type or
conditionally with other devices of the same family. This allows optimal drive selection for
a given number of pixels to display. Figure 21 and Figure 24 show the timing of the
synchronization signals.
In a cascaded configuration only one PCA85176 master must be used as clock source. All
other PCA85176 in the cascade must be configured as slave such that they receive the
clock from the master.
If an external clock source is used, all PCA85176 in the cascade must be configured such
as to receive the clock from that external source (pin OSC connected to VDD). Thereby it
must be ensured that the clock tree is designed such that on all PCA85176 the clock
propagation delay from the clock source to all PCA85176 in the cascade is as equal as
possible since otherwise synchronization artefacts may occur.
In mixed cascading configurations, care has to be taken that the specifications of the
individual cascaded devices are met at all times.
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NXP Semiconductors
Universal LCD driver for low multiplex rates
1
T
=
fr
f
fr
BP0
SYNC
(a) static drive mode.
BP0
(1/2 bias)
BP0
(1/3 bias)
SYNC
(b) 1:2 multiplex drive mode.
BP0
(1/3 bias)
SYNC
(c) 1:3 multiplex drive mode.
BP0
(1/3 bias)
SYNC
(d) 1:4 multiplex drive mode.
mgl755
Fig 24. Synchronization of the cascade for the various PCA85176 drive modes
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NXP Semiconductors
Universal LCD driver for low multiplex rates
13. Package outline
TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm
SOT357-1
y
X
A
48
33
Z
49
32
E
e
H
E
E
(A )
3
A
2
A
A
1
w M
p
θ
pin 1 index
b
L
p
L
64
17
detail X
1
16
Z
v
M
A
D
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.15 1.05
0.05 0.95
0.27 0.18 10.1 10.1
0.17 0.12 9.9 9.9
12.15 12.15
11.85 11.85
0.75
0.45
1.45 1.45
1.05 1.05
1.2
mm
0.25
0.5
1
0.2 0.08 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-01-19
02-03-14
SOT357-1
137E10
MS-026
Fig 25. Package outline SOT357-1 (TQFP64) of PCA85176H/Q900
PCA85176_1
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NXP Semiconductors
Universal LCD driver for low multiplex rates
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
H
v
M
A
y
E
Z
56
29
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
detail X
1
28
w
M
b
e
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions).
A
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
8o
0o
0.15
0.05
1.05
0.85
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
8.3
7.9
0.8
0.4
0.50
0.35
0.5
0.1
mm
1.2
0.5
1
0.25
0.25
0.08
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT364-1
MO-153
Fig 26. Package outline SOT364-1 (TSSOP56) of PCA85176T/Q900
PCA85176_1
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NXP Semiconductors
Universal LCD driver for low multiplex rates
14. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
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Universal LCD driver for low multiplex rates
15.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
15.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 27) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 20 and 21
Table 20. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 21. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 27.
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Universal LCD driver for low multiplex rates
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 27. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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Universal LCD driver for low multiplex rates
16. Abbreviations
Table 22. Abbreviations
Acronym
AEC
CMOS
CDM
DC
Description
Automotive Electronics Council
Complementary Metal-Oxide Semiconductor
Charged Device Model
Direct Current
HBM
I2C
Human Body Model
Inter-Integrated Circuit
Integrated Circuit
IC
LCD
LSB
Liquid Crystal Display
Least Significant Bit
MM
Machine Model
MSB
MSL
PCB
POR
RAM
RC
Most Significant Bit
Moisture Sensitivity Level
Printed-Circuit Board
Power-On Reset
Random Access Memory
Resistance and Capacitance
Root Mean Square
RMS
SCL
SDA
SMD
Serial Clock Line
Serial DAta Line
Surface-Mount Device
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17. References
[1] AN10365 — Surface mount reflow soldering description
[2] IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[4] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices
[5] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[6] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[7] JESD22-C101 — Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[8] JESD78 — IC Latch-Up Test
[9] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[10] NX3-00092 — NXP store and transport requirements
[11] SNV-FA-01-02 — Marking Formats Integrated Circuits
[12] UM10204 — I2C-bus specification and user manual
18. Revision history
Table 23. Revision history
Document ID
Release date
20100414
Data sheet status
Change notice
Supersedes
PCA85176_1
Product data sheet
-
-
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19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Applications — Applications that are described herein for any of these
19.2 Definitions
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
suitable for use in medical, military, aircraft, space or life support equipment,
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
PCA85176_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 14 April 2010
42 of 44
PCA85176
NXP Semiconductors
19.4 Trademarks
Universal LCD driver for low multiplex rates
I2C-bus — logo is a trademark of NXP B.V.
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA85176_1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 14 April 2010
43 of 44
PCA85176
NXP Semiconductors
Universal LCD driver for low multiplex rates
21. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
13
14
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 35
Handling information . . . . . . . . . . . . . . . . . . . 37
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
15
Soldering of SMD packages. . . . . . . . . . . . . . 37
Introduction to soldering. . . . . . . . . . . . . . . . . 37
Wave and reflow soldering. . . . . . . . . . . . . . . 37
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 38
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 38
15.1
15.2
15.3
15.4
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
16
17
18
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 40
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Revision history . . . . . . . . . . . . . . . . . . . . . . . 41
7
7.1
7.2
7.3
Functional description . . . . . . . . . . . . . . . . . . . 6
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 6
LCD bias generator . . . . . . . . . . . . . . . . . . . . . 7
LCD voltage selector . . . . . . . . . . . . . . . . . . . . 7
LCD drive mode waveforms . . . . . . . . . . . . . . . 9
Static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9
1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 10
1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 12
1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 13
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 14
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 14
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Display register. . . . . . . . . . . . . . . . . . . . . . . . 14
Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14
Backplane outputs . . . . . . . . . . . . . . . . . . . . . 14
Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Subaddress counter . . . . . . . . . . . . . . . . . . . . 17
Output bank selector . . . . . . . . . . . . . . . . . . . 18
Input bank selector . . . . . . . . . . . . . . . . . . . . . 18
Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Characteristics of the I2C-bus. . . . . . . . . . . . . 19
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
START and STOP conditions . . . . . . . . . . . . . 19
System configuration . . . . . . . . . . . . . . . . . . . 20
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20
I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 21
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21
Command decoder. . . . . . . . . . . . . . . . . . . . . 23
Display controller . . . . . . . . . . . . . . . . . . . . . . 25
19
Legal information . . . . . . . . . . . . . . . . . . . . . . 42
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 42
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 43
19.1
19.2
19.3
19.4
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.5
7.5.1
7.5.2
7.6
20
21
Contact information . . . . . . . . . . . . . . . . . . . . 43
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.16.1
7.16.2
7.16.3
7.16.4
7.16.5
7.16.6
7.16.7
7.17
7.18
8
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 25
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26
Static characteristics. . . . . . . . . . . . . . . . . . . . 27
Dynamic characteristics . . . . . . . . . . . . . . . . . 29
Application information. . . . . . . . . . . . . . . . . . 31
Cascaded operation . . . . . . . . . . . . . . . . . . . . 31
9
10
11
12
12.1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 April 2010
Document identifier: PCA85176_1
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