PCA85232DA_技术文档

PCA85232

LCD driver for low multiplex rates

Rev. 1 — 8 December 2010

Product data sheet

1. General description

The PCA85232 is a peripheral device which interfaces to almost any Liquid Crystal

Display (LCD)¹with low multiplex rates. It generates the drive signals for any static or

multiplexed LCD containing up to four backplanes and up to 160 segments. It can be

easily cascaded for larger LCD applications. The PCA85232 is compatible with most

microprocessors or microcontrollers and communicates via a two-line bidirectional

I²C-bus. Communication overheads are minimized by a display RAM with

auto-incremented addressing, by hardware subaddressing, and by display memory

switching (static and duplex drive modes).

AEC-Q100 compliant for automotive applications.

2. Features and benefits

Single-chip LCD controller and driver for up to 640 elements

Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing

160 segment drives:

Up to eighty 7-segment numeric characters

Up to forty 14-segment alphanumeric characters

Any graphics of up to 640 elements

May be cascaded for large LCD applications (up to 5120 elements possible)

160 × 4-bit RAM for display data storage

Software programmable frame frequency in the range of 117 Hz to 176 Hz; factory

calibrated

Wide LCD supply range: from 1.8 V for low threshold LCDs and up to 8.0 V for

guest-host LCDs and high threshold (automobile) twisted nematic LCDs

Internal LCD bias generation with voltage-follower buffers

Selectable display bias configuration: static, ¹⁄₂, or ¹⁄₃

Wide power supply range: from 1.8 V to 5.5 V

LCD and logic supplies may be separated

Low power consumption, typical: I_DD= 4 μA, I_DD(LCD)= 65 μA

400 kHz I²C-bus interface

Auto-incremental display data loading across device subaddress boundaries

Versatile blinking modes

Compatible with Chip-On-Glass (COG) technology

No external components

Two sets of backplane outputs for optimal COG configurations of the application

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 15.

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Delivery form

Version

PCA85232U/2DA/Q1 bare die

4. Marking

Table 2.

197 bumps; 6.5 × 1.16 × 0.40 mm

chips with bumps in tray PCA85232U

Marking codes

Type number

PCA85232U/2DA/Q1

Marking code

PC85132/232-1

PCA85232

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Product data sheet

Rev. 1 — 8 December 2010

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

5. Block diagram

BP0 BP1 BP2 BP3

S0 to S159

160

V

LCD

BACKPLANE

OUTPUTS

DISPLAY SEGMENT OUTPUTS

DISPLAY REGISTER

LCD

VOLTAGE

SELECTOR

OUTPUT BANK SELECT

AND BLINK CONTROL

DISPLAY

CONTROL

LCD BIAS

GENERATOR

V

SS

DISPLAY

RAM

PCA85232

CLK

BLINKER

CLOCK SELECT

TIMEBASE

AND TIMING

SYNC

COMMAND

DECODE

DATA POINTER AND

AUTO INCREMENT

WRITE DATA

CONTROL

POWER-ON

RESET

OSC

OSCILLATOR

SCL

SDA

2

SUBADDRESS

COUNTER

INPUT

FILTERS

I C-BUS

CONTROLLER

T1 T2 T3

A0 A1

SA0

SDAACK

V

DD

013aaa282

Fig 1. Block diagram of PCA85232

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

6.2 Pin description

Table 3.

Symbol

SDAACK^[1]

SDA^[1]

SCL

Pin description

Description

1 to 3

I²C-bus acknowledge output

I²C-bus serial data input

I²C-bus serial clock input

4 to 6

7 to 9

CLK

10

clock input and output

V_DD

11 to 13

supply voltage

SYNC

OSC

14

cascade synchronization input and output

selection of internal or external clock

15

T1, T2 and T3

16, 17 and 18 to 20

dedicated testing pins; to be tied to V_SSin

application mode

A0 and A1

SA0

21, 22

subaddress inputs

23

I²C-bus slave address input

ground supply voltage

LCD supply voltage

[2]

V_SS

24 to 26

27 to 29

30, 31

V_LCD

BP2 and BP0

S0 to S79

LCD backplane outputs

LCD segment outputs

LCD backplane outputs

LCD segment outputs

LCD backplane outputs

32 to 111

112 to 115

116 to 195

196, 197

BP0, BP2, BP1, and BP3

S80 to S159

BP3 and BP1

[1] For most applications SDA and SDAACK are shorted together (see Section 12.2).

[2] The substrate (rear side of the die) is connected to V_SSand should be electrically isolated.

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Product data sheet

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PCA85232

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LCD driver for low multiplex rates

7. Functional description

The PCA85232 is a versatile peripheral device designed to interface between any

microprocessor or microcontroller to a wide variety of LCD segment or dot matrix displays

(see Figure 3). It can directly drive any static or multiplexed LCD containing up to four

backplanes and up to 160 segments.

The display configurations possible with the PCA85232 depend on the required number of

active backplane outputs. A selection of display configurations is given in Table 4.

All of the display configurations given in Table 4 can be implemented in a typical system

as shown in Figure 4.

dot matrix

7-segment with dot

14-segment with dot and accent

013aaa312

Fig 3. Example of displays suitable for PCA85232

Table 4.

Selection of possible display configurations

Number of

Backplanes

Icons

Digits/Characters

Dot matrix/

Elements

7-segment

14-segment

4

3

2

1

640

480

320

160

80

60

40

20

40

30

20

10

640 dots (4 × 160)

480 dots (3 × 160)

320 dots (2 × 160)

160 dots (1 × 160)

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

V

DD

t

r

SDAACK

R ≤

2C

B

V

DD

V

LCD

160 segment drives

4 backplanes

SDA

SCL

HOST

MICRO-

PROCESSOR/

MICRO-

LCD PANEL

PCA85232

(up to 640

elements)

OSC

CONTROLLER

A0 A1 SA0 V

SS

013aaa284

V

SS

Fig 4. Typical system configuration

The host microprocessor or microcontroller maintains the 2-line I²C-bus communication

channel with the PCA85232.

Biasing voltages for the multiplexed LCD waveforms are generated internally, removing

the need for an external bias generator. The internal oscillator is selected by connecting

pin OSC to V_SS. The only other connections required to complete the system are the

power supplies (V_DD, V_SS, and V_LCD) and the LCD panel selected for the application.

7.1 Power-On Reset (POR)

At power-on the PCA85232 resets to the following starting conditions:

• All backplane and segment outputs are set to V_LCD

• The selected drive mode is 1:4 multiplex with ¹⁄₃bias

• Blinking is switched off

• Input and output bank selectors are reset

• The I²C-bus interface is initialized

• The data pointer and the subaddress counter are cleared (set to logic 0)

• The display is disabled

• If internal oscillator is selected (pin OSC connected to V_SS), then there is no clock

signal on pin CLK

Remark: Do not transfer data on the I²C-bus for at least 1 ms after a power-on to allow

the reset action to complete.

7.2 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of

three impedances connected in series between V_LCDand V_SS. The center impedance is

bypassed by switch if the ¹⁄₂bias voltage level for the 1:2 multiplex drive mode

configuration is selected.

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

7.3 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by the

mode-set command from the command decoder. The biasing configurations that apply to

the preferred modes of operation, together with the biasing characteristics as functions of

V

_LCDand the resulting discrimination ratios (D) are given in Table 5.

Table 5.

Biasing characteristics

Number of:

LCD drive

mode

LCD bias

configuration

V_off(RMS)V_on(RMS)

------------------------ ----------------------- D = ------------------------

V_LCDV_LCDV_off(RMS)

V_on(RMS)

Backplanes Levels

static

1

2

3

4

2

3

4

static

0

1

∞

1

1:2 multiplex

1:3 multiplex

1:4 multiplex

⁄

2

0.354

0.333

0.791

0.745

0.638

0.577

2.236

1.915

1.732

1

⁄

3

1

⁄

3

1

⁄

3

A practical value for V_LCDis determined by equating V_off(RMS)with a defined LCD

threshold voltage (V_th), typically when the LCD exhibits approximately 10 % contrast. In

the static drive mode a suitable choice is V_LCD> 3V_th.

Multiplex drive modes of 1:3 and 1:4 with ¹⁄₂bias are possible but the discrimination and

hence the contrast ratios are smaller.

1

Bias is calculated by ------------ , where the values for a are

1 + a

a = 1 for ¹⁄₂bias

a = 2 for ¹⁄₃bias

The RMS on-state voltage (V_on(RMS)) for the LCD is calculated with Equation 1:

a²+ 2a + n

n × (1 + a)²

V_on(RMS)

=

-----------------------------

(1)

V

LCD

where the values for n are

n = 1 for static drive mode

n = 2 for 1:2 multiplex drive mode

n = 3 for 1:3 multiplex drive mode

n = 4 for 1:4 multiplex drive mode

The RMS off-state voltage (V_off(RMS)) for the LCD is calculated with Equation 2:

a²– 2a + n

n × (1 + a)²

V_off(RMS)

=

-----------------------------

(2)

(3)

V

LCD

Discrimination is the ratio of V_on(RMS)to V_off(RMS)and is determined from Equation 3:

(a + 1)²+ (n – 1)

V_on(RMS)

D =

=

-------------------------------------------

----------------------

(a – 1)²+ (n – 1)

V_off(RMS)

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with

¹⁄₂bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with

21

¹⁄₂bias is ---------- = 1.528 .

3

The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V_LCD

as follows:

• 1:3 multiplex (¹⁄₂bias): V_LCD

• 1:4 multiplex (¹⁄₂bias): V_LCD

=

6 × V_off(RMS)= 2.449V_off(RMS)

(4 × 3)

---------------------

= 2.309V_off(RMS)

3

These compare with V_LCD= 3V_off(RMS)when ¹⁄₃bias is used.

It should be noted that V_LCDis sometimes referred as the LCD operating voltage.

7.3.1 Electro-optical performance

Suitable values for V_on(RMS)and V_off(RMS)are dependant on the LCD liquid used. The

RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of

the pixel.

For any given liquid, there are two threshold values defined. One point is at 10 % relative

transmission (at V_low) and the other at 90% relative transmission (at V_high), see Figure 5.

For a good contrast performance, the following rules should be followed:

V

_on(RMS)≥ V_high

_off(RMS)≤ V_low

(4)

(5)

V

_on(RMS)and V_off(RMS)are properties of the display driver and are affected by the selection

of a, n (see Equation 1 to Equation 3) and the V_LCDvoltage.

V_lowand V_highare properties of the LCD liquid and can be provided by the module

manufacturer.

It is important to match the module properties to those of the driver in order to achieve

optimum performance.

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

100 %

90 %

10 %

V

RMS

[V]

V

low

V

high

OFF

SEGMENT

GREY

SEGMENT

ON

SEGMENT

001aam358

Fig 5. Electro-optical characteristic: relative transmission curve of the liquid

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

7.4 LCD drive mode waveforms

7.4.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD.

Backplane and segment drive waveforms for this mode are shown in Figure 6.

T

fr

LCD segments

V

LCD

BP0

Sn

V

SS

state 1

(on)

state 2

(off)

V

LCD

V

SS

V

LCD

Sn+1

V

SS

(a) Waveforms at driver.

V

LCD

0 V

state 1

−V

LCD

V

LCD

state 2

0 V

−V

LCD

(b) Resultant waveforms

at LCD segment.

013aaa207

V_state1(t) = V_Sn(t) − V_BP0(t).

V_on(RMS)= V_LCD

.

V_state2(t) = V_(Sn+1)(t) − V_BP0(t).

V_off(RMS)= 0 V.

Fig 6. Static drive mode waveforms

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

7.4.2 1:2 multiplex drive mode

When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The

PCA85232 allows the use of ¹⁄₂bias or ¹⁄₃bias in this mode as shown in Figure 7 and

Figure 8.

T

fr

V

LCD

LCD segments

V

/2

BP0

BP1

Sn

LCD

SS

state 1

V

LCD

state 2

V

LCD

SS

V

LCD

V

SS

LCD

Sn+1

V

SS

(a) Waveforms at driver.

V

LCD

/2

LCD

0 V

−V

state 1

/2

LCD

−V

LCD

V

LCD

/2

LCD

0 V

state 2

−V

/2

LCD

−V

(b) Resultant waveforms

at LCD segment.

013aaa208

V_state1(t) = V_Sn(t) − V_BP0(t).

V_on(RMS)= 0.791V_LCD

V_state2(t) = V_Sn(t) − V_BP1(t).

V_off(RMS)= 0.354V_LCD

.

Fig 7. Waveforms for the 1:2 multiplex drive mode with ¹⁄₂bias

PCA85232

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

T

fr

V

LCD

LCD segments

2V

/3

LCD

BP0

BP1

Sn

V

/3

LCD

SS

state 1

state 2

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+1

V

/3

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

LCD

/3

V

/3

LCD

0 V

−V

state 1

/3

LCD

−2V

LCD

−V

LCD

V

LCD

2V

LCD

/3

V

LCD

/3

0 V

−V

state 2

/3

LCD

−2V

LCD

−V

LCD

(b) Resultant waveforms

at LCD segment.

013aaa209

V_state1(t) = V_Sn(t) − V_BP0(t).

V_on(RMS)= 0.745V_LCD

V_state2(t) = V_Sn(t) − V_BP1(t).

V_off(RMS)= 0.333V_LCD

.

Fig 8. Waveforms for the 1:2 multiplex drive mode with ¹⁄₃bias

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

7.4.3 1:3 multiplex drive mode

When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as

shown in Figure 9.

T

fr

V

LCD

LCD segments

2V

/3

LCD

BP0

BP1

BP2

Sn

V

/3

LCD

SS

state 1

state 2

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+1

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+2

V

/3

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

LCD

/3

V

LCD

/3

state 1

0 V

−V

/3

LCD

−2V

LCD

−V

LCD

V

LCD

2V

LCD

/3

V

LCD

/3

state 2

0 V

−V

/3

LCD

−2V

LCD

−V

LCD

(b) Resultant waveforms

at LCD segment.

013aaa210

V_state1(t) = V_Sn(t) − V_BP0(t).

V_on(RMS)= 0.638V_LCD

V_state2(t) = V_Sn(t) − V_BP1(t).

V_off(RMS)= 0.333V_LCD

.

Fig 9. Waveforms for the 1:3 multiplex drive mode with ¹⁄₃bias

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

7.4.4 1:4 multiplex drive mode

When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as

shown in Figure 10.

T

fr

V

LCD

LCD segments

2V

/3

LCD

BP0

BP1

BP2

V

LCD

SS

state 1

state 2

V

LCD

2V

LCD

/3

V

LCD

SS

V

LCD

2V

LCD

/3

V

LCD

SS

V

LCD

2V

/3

LCD

BP3

Sn

V

LCD

SS

V

LCD

2V

LCD

/3

V

LCD

SS

V

LCD

2V

/3

LCD

Sn+1

V

LCD

SS

V

LCD

2V

/3

LCD

Sn+2

Sn+3

V

LCD

SS

V

LCD

2V

LCD

/3

V

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

LCD

/3

V

/3

LCD

state 1

0 V

−V

/3

LCD

−2V

LCD

/3

LCD

−V

V

LCD

2V

LCD

/3

V

/3

LCD

0 V

−V

state 2

/3

LCD

−2V

LCD

/3

LCD

−V

(b) Resultant waveforms

at LCD segment.

013aaa211

V_state1(t) = V_Sn(t) − V_BP0(t).

V_on(RMS)= 0.577V_LCD

V_state2(t) = V_Sn(t) − V_BP1(t).

V_off(RMS)= 0.333V_LCD

.

Fig 10. Waveforms for the 1:4 multiplex drive mode with ¹⁄₃bias

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

7.5 Oscillator

The internal logic and the LCD drive signals of the PCA85232 are timed by a frequency

f_clkwhich either is derived from the built-in oscillator frequency f_osc:

f_osc

f_clk

=

(6)

-------

64

or equals an external clock frequency f_clk(ext)

:

f_clk= f_clk(ext)

(7)

Remark: A clock signal must always be supplied to the device; removing the clock may

freeze the LCD in a DC state, which is not suitable for the liquid crystal.

7.5.1 Internal clock

The internal oscillator is enabled by connecting pin OSC to V_SS. In this case the output

from pin CLK provides the clock signal for cascaded PCA85232 in the system. However,

the clock signal is only available at pin CLK, if the display is enabled. The display is

enabled using the display enable bit (see Table 10).

The output clock frequency is like specified in Table 19 with parameter f_clk.

7.5.2 External clock

Connecting pin OSC to V_DDenables an external clock source. Pin CLK then becomes the

external clock input.

7.6 Timing and frame frequency

The timing of the PCA85232 organizes the internal data flow of the device. This includes

the transfer of display data from the display RAM to the display segment outputs.

In cascaded applications, the synchronization signal (SYNC) maintains the correct timing

relationship between the PCA85232 in the system.

When the internal clock is used, the clock frequency can be programmed by software

such that the frame frequency can be chosen in the range of 117 Hz to 176 Hz (see

Table 16). The internal oscillator is calibrated within an accuracy of ±5.1 % (at

V

_DD= 5.0 V; T_amb= 30 °C).

The timing also generates the LCD frame frequency derived from an integer division of f_clk

(see Table 16).

7.7 Display register

The display register holds the display data while the corresponding multiplex signals are

generated.

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Product data sheet

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LCD driver for low multiplex rates

7.8 Segment outputs

The LCD drive section includes 160 segment outputs (S0 to S159) which must be

connected directly to the LCD. The segment output signals are generated in accordance

with the multiplexed backplane signals and with data resident in the display register.

When less than 160 segment outputs are required the unused segment outputs must be

left open-circuit.

7.9 Backplane outputs

The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane

output signals are generated in accordance with the selected LCD drive mode.

• In the 1:4 multiplex drive mode BP0 to BP3 must be connected directly to the LCD.

If less than four backplane outputs are required the unused outputs can be left

open-circuit.

• In 1:3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

• In 1:2 multiplex drive mode BP0 and BP2, BP1 and BP3 respectively carry the same

signals and may also be paired to increase the drive capabilities.

• In static drive mode the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements.

The pins for the four backplanes BP0 to BP3 are available on both pin bars of the chip. In

applications it is possible to use either the pins for the backplanes

• on the top pin bar

• on the bottom pin bar

• or both of them to increase the driving strength of the device.

When using all backplanes available they may be connected to the respective sibling

(BP0 on the top pin bar with BP0 on the bottom pin bar and so on).

7.10 Display RAM

The display RAM is a static 160 × 4 bit RAM which stores LCD data. There is a one-to-one

correspondence between

• the bits in the RAM bitmap and the LCD elements

• the RAM columns and the segment outputs

• the RAM rows and the backplane outputs.

A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;

similarly, a logic 0 indicates the off-state.

The display RAM bit map, Figure 11, shows the rows 0 to 3 which correspond with the

backplane outputs BP0 to BP3, and the columns 0 to 159 which correspond with the

segment outputs S0 to S159. In multiplexed LCD applications the segment data of the

first, second, third, and fourth row of the display RAM are time-multiplexed with BP0,

BP1, BP2, and BP3 respectively.

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PCA85232

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LCD driver for low multiplex rates

columns

display RAM addresses/segment outputs (S)

155 156 157 158 159

0

1

2

3

4

rows

0

1

2

3

display RAM rows/

backplane outputs

(BP)

013aaa220

The display RAM bitmap shows the direct relationship between the display RAM addresses and

the segment outputs; and between the bits in a RAM word and the backplane outputs.

Fig 11. Display RAM bitmap

When display data is transmitted to the PCA85232 the received display bytes are stored

in the display RAM in accordance with the selected LCD drive mode. The data is stored as

it arrives and does not wait for the acknowledge cycle as with the commands. Depending

on the current multiplex drive mode, data is stored singularly, in pairs, triples, or

quadruples. To illustrate the filling order, an example of a 7-segment numeric display

showing all drive modes is given in Figure 12; the RAM filling organization depicted

applies equally to other LCD types.

The following applies to Figure 12:

• In static drive mode the eight transmitted data bits are placed in row 0 as one byte.

• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into

row 0 and 1 as two successive 4-bit RAM words.

• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as

three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is

not recommended to use this bit in a display because of the difficult addressing. This

last bit may, if necessary, be controlled by an additional transfer to this address but

care should be taken to avoid overwriting adjacent data because always full bytes are

transmitted.

• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples

into row 0, 1, 2, and 3 as two successive 4-bit RAM words.

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7.11 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte, or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load-data-pointer command (see Table 8). Following this command, an

arriving data byte is stored at the display RAM address indicated by the data pointer. The

filling order is shown in Figure 12.

After each byte is stored, the content of the data pointer is automatically incremented by a

value dependent on the selected LCD drive mode:

• In static drive mode by eight

• In 1:2 multiplex drive mode by four

• In 1:3 multiplex drive mode by three

• In 1:4 multiplex drive mode by two

If an I²C-bus data access is terminated early then the state of the data pointer is unknown.

The data pointer should be re-written prior to further RAM accesses.

7.12 Subaddress counter

The storage of display data is conditioned by the content of the subaddress counter.

Storage is allowed only when the content of the subaddress counter matches with the

hardware subaddress applied to A0 and A1. The subaddress counter value is defined by

the device-select command (see Table 13). If the content of the subaddress counter and

the hardware subaddress do not match then data storage is inhibited but the data pointer

is incremented as if data storage had taken place. The subaddress counter is also

incremented when the data pointer overflows.

The storage arrangements described lead to extremely efficient data loading in cascaded

applications. When a series of display bytes are sent to the display RAM, automatic

wrap-over to the next PCA85232 occurs when the last RAM address is exceeded.

Subaddressing across device boundaries is successful even if the change to the next

device in the cascade occurs within a transmitted character.

The hardware subaddress must not be changed whilst the device is being accessed on

the I²C-bus interface.

7.13 Output bank selector

The output bank selector (see Table 14) selects one of the four rows per display RAM

address for transfer to the display register. The actual row selected depends on the

particular LCD drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by

the contents of row 1, row 2, and then row 3

• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially

• In 1:2 multiplex mode, rows 0 and 1 are selected

• In static mode, row 0 is selected

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The PCA85232 includes a RAM bank switching feature in the static and 1:2 multiplex

drive modes. In the static drive mode, the bank-select command may request the contents

of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex

mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives

the provision for preparing display information in an alternative bank and to be able to

switch to it once it is assembled.

7.14 Input bank selector

The input bank selector loads display data into the display RAM in accordance with the

selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode

or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see

Table 14). The input bank selector functions independently to the output bank selector.

7.15 Blinker

The display blinking capabilities of the PCA85232 are very versatile. The whole display

can blink at frequencies selected by the blink-select command (see Table 15). The blink

frequencies are fractions of the clock frequency. The ratios between the clock and blink

frequencies depend on the blink mode in which the device is operating (see Table 6).

Table 6.

Blink frequencies

Assuming that f_clk= 3.500 kHz.

Blink mode

Operating mode ratio

Blink frequency

blinking off

off

1

-

~4.56 Hz

f_clk

--------

768

f_blink

=

2

3

~2.28 Hz

~1.14 Hz

f_clk

=

-----------

1536

f_clk

=

-----------

3072

An additional feature is for an arbitrary selection of LCD elements to blink. This applies to

the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. By means of the output bank selector, the displayed RAM

banks are exchanged with alternate RAM banks at the blink frequency. This mode can

also be specified by the blink-select command (see Table 15).

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD elements can blink selectively by changing the display RAM data at fixed time

intervals.

The entire display can blink at a frequency other than the nominal blinking frequency. This

can be effectively performed by resetting and setting the display enable bit E at the

required rate using the mode-set command (see Table 10).

7.16 Characteristics of the I²C-bus

The I²C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

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By connecting pin SDAACK to pin SDA on the PCA85232, the SDA line becomes fully

I²C-bus compatible. In COG applications where the track resistance from the SDAACK

pin to the system SDA line can be significant, possibly a voltage divider is generated by

the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As a

consequence it may be possible that the acknowledge generated by the PCA85232 can’t

be interpreted as logic 0 by the master. In COG applications where the acknowledge cycle

is required, it is therefore necessary to minimize the track resistance from the SDAACK

pin to the system SDA line to guarantee a valid LOW level.

By separating the acknowledge output from the serial data line (having the SDAACK open

circuit) design efforts to generate a valid acknowledge level can be avoided. However, in

that case the I²C-bus master has to be set up in such a way that it ignores the

acknowledge cycle.²

The following definition assumes SDA and SDAACK are connected and refers to the pair

as SDA.

7.16.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 13).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 13. Bit transfer

7.16.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change

of the data line, while the clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP

condition (P). The START and STOP conditions are shown in Figure 14.

SDA

SCL

SDA

SCL

S

P

START condition

STOP condition

mbc622

Fig 14. Definition of START and STOP conditions

2. For further information, please consider the NXP application note: Ref. 1 “AN10170”.

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7.16.2 System configuration

A device generating a message is a transmitter; a device receiving a message is the

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves. The system configuration is shown in Figure 15.

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

SDA

SCL

mga807

Fig 15. System configuration

7.16.3 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

• A slave receiver which is addressed must generate an acknowledge after the

reception of each byte.

• Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I²C-bus is shown in Figure 16.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from

master

1

2

8

9

S

clock pulse for

acknowledgement

START

condition

mbc602

Fig 16. Acknowledgement on the I²C-bus

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7.16.4 I²C-bus controller

The PCA85232 acts as an I²C-bus slave receiver. It does not initiate I²C-bus transfers or

transmit data to an I²C-bus master receiver. The only data output from the PCA85232 are

the acknowledge signals from the selected devices. Device selection depends on the

I²C-bus slave address, on the transferred command data, and on the hardware

subaddress.

In single device applications, the hardware subaddress inputs A0 and A1 are normally tied

to V_SSwhich defines the hardware subaddress 0. In multiple device applications

A0 and A1 are tied to V_SSor V_DDin accordance with a binary coding scheme such that no

two devices with a common I²C-bus slave address have the same hardware subaddress.

7.16.5 Input filters

To enhance noise immunity in electrical adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

7.16.6 I²C-bus protocol

Two I²C-bus slave addresses (0111 000 and 0111 001) are reserved for the

PCA85232.The entire I²C-bus slave address byte is shown in Table 7.

Table 7.

I²C slave address byte

Slave address

Bit

7

6

5

4

3

2

1

0

MSB

LSB

R/W

0

1

0

SA0

The PCA85232 is a write-only device and will not respond to a read access, therefore bit 0

should always be logic 0. Bit 1 of the slave address byte, that a PCA85232 will respond to,

is defined by the level tied to its SA0 input (V_SSfor logic 0 and V_DDfor logic 1).

Having two reserved slave addresses allows the following on the same I²C-bus:

• Up to 8 PCA85232 on the same I²C-bus for very large LCD applications

• The use of two types of LCD multiplex on the same I²C-bus

The I²C-bus protocol is shown in Figure 17. The sequence is initiated with a START

condition (S) from the I²C-bus master which is followed by one of two possible PCA85232

slave addresses available. All PCA85232 with the corresponding SA0 level acknowledge

in parallel to the slave address, but all PCA85232 with the alternative SA0 level ignore the

whole I²C-bus transfer.

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R/W = 0

slave address

control byte

RAM/command byte

S

A

0

M

S

B

L

S

B

C

O

R

S

0

1

0

A

P

A

EXAMPLES

a) transmit two bytes of RAM data

S

A

0

S

0

1

0

A

0

1

0

RAM DATA

COMMAND

RAM DATA

A

P

A

b) transmit two command bytes

S

0

1

0

A

0

A

0

1

COMMAND

RAM DATA

A

P

c) transmit one command byte and two RAM date bytes

S

0

1

0

A

0

A

1

0

RAM DATA

A

P

mgl752

Fig 17. I²C-bus protocol

After acknowledgement, a control byte follows which defines if the next byte is RAM or

command information. The control byte also defines if the next byte is a control byte or

further RAM or command data.

Table 8.

Control byte description

Bit

Symbol Value

Description

7

CO

continue bit

0

last control byte

control bytes continue

register selection

command register

data register

1

6

RS

0

1

5 to 0

-

not relevant

MSB

7

LSB

6

5

4

3

2

1

0

CO RS

not relevant

mgl753

Fig 18. Control byte format

In this way it is possible to configure the device and then fill the display RAM with little

overhead.

The command bytes and control bytes are also acknowledged by all addressed

PCA85232 connected to the bus.

The display bytes are stored in the display RAM at the address specified by the data

pointer and the subaddress counter; see Section 7.11 and Section 7.12.

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The acknowledgement after each byte is made only by the (A0 and A1) addressed

PCA85232. After the last (display) byte, the I²C-bus master issues a STOP condition (P).

Alternatively a START may be asserted to RESTART an I²C-bus access.

7.17 Command decoder

The command decoder identifies command bytes that arrive on the I²C-bus. The

commands available to the PCA85232 are defined in Table 9.

Table 9.

Definition of PCA85232 commands

Operation code

Command

Reference

Bit

7

1

0

1

6

1

0

1

5

0

1

4

0

1

0

3

2

1

0

mode-set

E

B

M[1:0]

Table 10

Table 11

Table 12

Table 13

Table 14

Table 15

Table 16

load-data-pointer-MSB

load-data-pointer-LSB

device-select

bank-select

P[7:4]

P[3:0]

0

1

0

1

0

A[1:0]

I

0

O

blink-select

AB

BF[1:0]

frequency-prescaler

F[2:0]

Table 10. Mode-set command bit description

Bit

7 to 4

3

Symbol

Value

Description

-

1100

fixed value

E

display status

0^[1]

1

disabled (blank)^[2]

enabled

2

B

LCD bias configuration^[3]

¹⁄₃bias

¹⁄₂bias

0^[1]

1

1 to 0

M[1:0]

LCD drive mode selection

static; BP0

01

10

1:2 multiplex; BP0, BP1

1:3 multiplex; BP0, BP1, BP2

1:4 multiplex; BP0, BP1, BP2, BP3

11

00^[1]

[1] Power-on and reset value.

[2] The possibility to disable the display allows implementation of blinking under external control; the enable bit

determines also whether the internal clock signal is available at the CLK pin (see Section 7.5.1).

[3] Not applicable for static drive mode.

Table 11. Load-data-pointer-MSB command bit description

Bit

Symbol

-

Value

Description

7 to 4

3 to 0

0000

0000^[1]to

1001

fixed value

P[7:4]

P7 to P4 defines the first 4 (most significant) bits of

the data pointer that indicates one of the 160 display

RAM addresses

[1] Power-on and reset value.

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Table 12. Load-data-pointer-LSB command bit description

Bit

Symbol

-

Value

Description

7 to 4

3 to 0

0100

0000^[1]to

1111

fixed value

P[3:0]

P3 to P0 defines the last 4 (least significant) bits of the

data pointer that indicates one of the 160 display RAM

addresses

[1] Power-on and reset value.

Table 13. Device-select command bit description

Bit

Symbol

-

Value

Description

7 to 2

1 to 0

111000

00^[1]to 11

fixed value

A[1:0]

two bits of immediate data, bits A0 to A1, are

transferred to the subaddress counter to define

one of four hardware subaddresses (see Table 20)

[1] Power-on and reset value.

Table 14. Bank-select command bit description

Bit

Symbol Value

Description

Static

1:2 multiplex^[1]

7 to 2

1

-

I

111110

fixed value

input bank selection; storage of arriving display data

0^[2]

1

RAM bit 0

RAM bit 2

RAM bits 0 and 1

RAM bits 2 and 3

0

O

output bank selection; retrieval of LCD display data

0^[2]

1

RAM bit 0

RAM bit 2

RAM bits 0 and 1

RAM bits 2 and 3

[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.

[2] Power-on and reset value.

Table 15. Blink-select command bit description

Bit

7 to 3

2

Symbol Value

Description

-

11110

fixed value

AB

blink mode selection

0^[1]

1

normal blinking^[2]

alternate RAM bank blinking^[3]

1 to 0

BF[1:0]

blink frequency selection

00^[1]

01

off

1

10

2

11

3

[1] Power-on and reset value.

[2] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.

[3] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.

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Table 16. Frame-frequency prescaler

Bit

Symbol Value

Description

Nominal frame frequency^[1]Equation

7 to 4

3 to 0

-

11101

000

fixed value

F[2:0]

defines the division factor for the frame frequency (f_fr)

117 Hz

126 Hz

137 Hz

146 Hz

156 Hz

167 Hz

176 Hz

146 Hz

f_clk

----- -------

64

80 24

f_fr

=

×

001

010

011^[2]

100

101

110

111

f_clk

64

----- -------

×

74 24

f_clk

64

----- -------

×

68 24

f_clk

-------

24

f_clk

----- -------

64

60 24

×

f_clk

64

----- -------

×

56 24

f_clk

64

----- -------

×

53 24

f_clk

-------

24

[1] Nominal frame frequency calculated for an internal operating frequency of 3.5 kHz.

[2] Power-on and reset value.

7.18 Display controller

The display controller executes the commands identified by the command decoder. It

contains the status registers of the PCA85232 and co-ordinates their effects. The

controller is also responsible for loading display data into the display RAM as required by

the filling order.

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8. Internal circuitry

V

DD

LCD

S0 to S159,

BP0 to BP3

V

SS

DD

SDAACK, SCL,

SDA, T3, V

LCD

SYNC, T1,

T2, A0, A1,

OSC, CLK,

SA0

V

SS

013aaa221

Fig 19. Device protection diagram

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9. Limiting values

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(V_LCD) is on while the IC supply voltage (V_DD) is off, or vice versa. This may cause unwanted

display artifacts. To avoid such artifacts, V_LCDand V_DDmust be applied or removed together.

Table 17. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol Parameter

Conditions

Min

−0.5

−50

−0.5

−50

−0.5

Max

+6.5

+50

Unit

V

V_DD

I_DD

supply voltage

supply current

mA

V

V_LCD

LCD supply voltage

+9.0

+50

I_DD(LCD)LCD supply current

mA

V

V_i

input voltage

on pins CLK, SYNC,

SA0, OSC, SDA, SCL,

A0, A1, T1, T2, and T3

+6.5

I_I

input current

−10

+10

mA

V

V_O

output voltage

on pins S0 to S159 and −0.5

+9.0

BP0 to BP3

on pins SDAACK,

CLK, SYNC

−0.5

+6.5

V

I_O

output current

−10

+10

mA

mW

V

I_SS

ground supply current

total power dissipation

power dissipation per output

−50

+50

P_tot

P/out

V_ESD

-

400

100

[2]

electrostatic discharge

voltage

HBM

MM

±4500

[3]

[4]

[5]

-

±250

200

V

I_lu

latch-up current

-

mA

°C

T_stg

T_oper

storage temperature

operating temperature

−65

−40

+150

+95

[1] Stresses above these values listed may cause permanent damage to the device.

[2] Pass level; Human Body Model (HBM) according to Ref. 6 “JESD22-A114”.

[3] Pass level; Machine Model (MM), according to Ref. 7 “JESD22-A115”.

[4] Pass level; latch-up testing, according to Ref. 8 “JESD78” at maximum ambient temperature

(T_amb(max)= 95 °C).

[5] According to the NXP store and transport requirements (see Ref. 10 “NX3-00092”) the devices have to be

stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products

deviant conditions are described in that document.

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10. Static characteristics

Table 18. Static characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 1.8 V to 8.0 V; T_amb= −40 °C to +95 °C; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Supplies

V_DD

supply voltage

1.8

-

5.5

8.0

30

80

60

80

V

V_LCD

I_DD

LCD supply voltage

supply current

1.8

V

[1][2][3]

[1][3]

f_clk(ext)= 3.500 kHz

-

μA

with internal oscillator running

f_clk(ext)= 3.500 kHz

[1][2][4]

[1][4]

I_DD(LCD)LCD supply current

with internal oscillator running

Logic

V_I

input voltage

on pins SDA and SCL

all other input pins

−0.5

-

+5.5

V

−0.5

V_DD+ 0.5 V

V_IH

V_IL

V_O

HIGH-level input voltage on pins CLK, SYNC, OSC, A0, A1,

SA0, SCL, and SDA

0.7V_DD

-

V

LOW-level input voltage

on pins CLK, SYNC, OSC, A0, A1,

SA0, SCL, and SDA

-

0.3V_DD

V

output voltage

on pins CLK and SYNC

on pin SDAACK

−0.5

0.8V_DD

V_SS

-

V_DD+ 0.5 V

+5.5

V_DD

0.2V_DD

-

V

V_OH

V_OL

I_OH

HIGH-level output voltage on pin SYNC, CLK

V

LOW-level output voltage on pin SYNC, CLK, SDAACK

V

HIGH-level output current output source current;

V_OH= 4.6 V; V_DD= 5 V; on pin CLK

1.5

mA

I_OL

LOW-level output current output sink current;

on pins CLK and SYNC

V_OL= 0.4 V; V_DD= 5 V

on pin SDAACK

1.5

-

mA

V_DD≤ 2 V; V_OL= 0.2V_DD

3

-

mA

V

2 V < V_DD< 3 V; V_OL= 0.4 V

V_DD≥ 3 V; V_OL= 0.4 V

3

-

6

-

V_POR

I_L

power-on reset voltage

1.0

−1

1.3

-

1.6

+1

leakage current

V_I= V_DDor V_SS; on pin OSC,

μA

CLK, A0, A1, SA0, SDA, and SCL

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Table 18. Static characteristics …continued

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 1.8 V to 8.0 V; T_amb= −40 °C to +95 °C; unless otherwise specified.

Symbol Parameter

LCD outputs

Conditions

Min

Typ

Max

Unit

[5][6]

ΔV_O

output voltage variation

output resistance

on pins BP0 to BP3 and S0 to S159

V_LCD= 5 V

−30

-

+30

mV

R_O

on pins BP0 to BP3

on pins S0 to S159

-

1.5

2.0

5

kΩ

[1] LCD outputs are open-circuit; inputs at V_SSor V_DD; I²C-bus inactive; V_LCD= 8.0 V, V_DD= 5.0 V and RAM written with all logic 1.

[2] External clock with 50 % duty factor.

[3] For typical values, see Figure 20

[4] For typical values, see Figure 21

[5] Variation between any 2 backplanes on a given voltage level; static measured.

[6] Variation between any 2 segments on a given voltage level; static measured.

001aal525

25

I

DD

(μA)

20

(1)

15

10

5

(2)

0

1

2

3

4

5

6

V

DD

(V)

(1) I_DDinternal is measured with the internal oscillator.

(2) I_DDexternal is measured with an external clock.

T_amb= 30 °C; 1:4 multiplex; V_LCD= 8 V; all RAM written with logic 1; no display connected.

Fig 20. I_DDwith respect to V_DD

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

001aal526

70

I

DD(LCD)

(μA)

50

30

10

1

3

5

7

9

V

LCD

(V)

T_amb= 30 °C; 1:4 multiplex; all RAM written with logic 1; no display connected; f_clk= 3.5 kHz.or

_clk(ext)= 3.500 kHz.

f

Fig 21. I_DD(LCD)with respect to V_LCD

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

11. Dynamic characteristics

Table 19. Dynamic characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 1.8 V to 8.0 V; T_amb= −40 °C to +95 °C; unless otherwise specified.

Symbol

Parameter

Conditions

Min Typ Max Unit

[1][2][3]

[4]

f_clk

clock frequency

on pin CLK;

V_DD= 5 V ± 0.5 V

3050 3500 4052 Hz

f_clk(ext)

t_clk(H)

t_clk(L)

Δf_fr

external clock frequency

HIGH-level clock time

LOW-level clock time

frame frequency variation

700

100

-

5000 Hz

external clock source used

V_DD= 5 V ± 0.5 V

-

μs

f_fr= 146 Hz; T_amb= 30 °C

f_fr= 135 Hz; T_amb= 95 °C

f_fr= 157 Hz; T_amb= −40 °C

−5.1

−6.2

−7.8

-

+5.1

%

-

+6.9

-

+7.6

%

t_{PD(SYNC_N)}SYNC propagation delay

30

-

ns

μs

t_{SYNC_NL}

SYNC LOW time

100

-

t_PD(drv)

driver propagation delay

V_LCD= 5 V

10

Timing characteristics: I²C-bus^[5]

f_SCL

t_BUF

SCL clock frequency

-

400 kHz

bus free time between a STOP and START

condition

1.3

-

μs

t_HD;STA

t_SU;STA

t_VD;ACK

t_LOW

t_HIGH

t_f

hold time (repeated) START condition

set-up time for a repeated START condition

data valid acknowledge time

LOW period of the SCL clock

HIGH period of the SCL clock

fall time

0.6

-

μs

-

0.9

-

1.3

0.6

-

of both SDA and SCL signals

0.3

t_r

rise time

-

C_b

capacitive load for each bus line

data set-up time

-

400 pF

t_SU;DAT

t_HD;DAT

t_SU;STO

t_SP

200

0

-

ns

μs

ns

data hold time

-

set-up time for STOP condition

0.6

-

pulse width of spikes that must be

suppressed by the input filter

50

[1] Typical output duty factor: 50 % measured at the CLK output pin.

[2] For the respective frame frequency f_frsee Table 16.

[3] For the characteristics of V_DDat a fixed temperature or of the temperature at a fixed V_DD, see Figure 22 and Figure 23.

[4] For f_CLK(ext)> 4 kHz it is recommended to use an external pull-up resistor between pin SYNC and pin V_DD. The value of the resistor

should be between 100 kΩ and 1 MΩ.

[5] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V_ILand V_IHwith an

input voltage swing of V_SSto V_DD

.

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

001aal527

3540

f

clk

(Hz)

3500

3460

3420

3380

3340

1

2

3

4

5

6

V

DD

(V)

T_amb= 30 °C.

Fig 22. Typical clock frequency (f_clk) with respect to V_DD

001aal481

170

f

fr

(Hz)

7.6 %

7.8 %

160

max

typ

150

140

130

120

5.1 %

6.9 %

6.2 %

min

−60

−40

−20

0

20

40

60

80

Temperature (°C)

100

Condition: V_DD= 5 V ± 0.5 V; frame frequency prescaler = 011; 146 Hz typical.

The frame frequency (f_fr) is calculated from the clock frequency (f_clk) according to the equations

described in Table 16.

Fig 23. Frame frequency variation

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

1 / f

CLK

t

clk(L)

clk(H)

0.7 V

0.3 V

DD

CLK

DD

0.7 V

0.3 V

DD

SYNC

DD

t

PD(SYNC_N)

t

SYNC_NL

0.5 V

BP0 to BP3,

and S0 to S159

(V

DD

= 5 V)

0.5 V

t

001aah848

PD(drv)

Fig 24. Driver timing waveforms

t

SU;DAT

f

r

70 %

30 %

70 %

30 %

SDA

SCL

cont.

t

HD;DAT

VD;ACK

t

f

t

HIGH

t

r

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

t

HD;STA

t

LOW

th

9

clock

1 / f

S

SCL

st

1

clock cycle

t

BUF

SDA

SCL

t

VD;ACK

t

SU;STO

SU;STA

HD;STA

SP

70 %

30 %

Sr

P

S

th

9

clock

013aaa110

Fig 25. I²C-bus timing waveforms when SDA and SDAACK are connected

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PCA85232

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LCD driver for low multiplex rates

12. Application information

12.1 Pull-up resistor sizing on I²C-bus

12.1.1 Max value of pull-up resistor

The bus capacitance (C_b) is the total capacitance of wire, connections, and pins. This

capacitance on pin SDA limits the maximum value of the pull-up resistor (R_PU) due to the

specified rise time.

According to the I²C-bus specification the rise time (t_r) is defined between the V_DDrelated

input threshold of V_IL= 0.3V_DDand V_IH= 0.7V_DD. The value for t_r(max)is 300 ns.

t_rwill be calculated with Equation 8:

t_r= t2 – t1

(8)

whereas t1 and t2 are the time since the charging started. The values for t1 and t2 are

derivatives of the functions V(t1) and V(t2):

C

V(t1) = 0.3V_DD= V_DD(1 – e^{-t1 ⁄ R}

)

(9)

PU

b

C

V(t2) = 0.7V_DD= V_DD(1 – e^{-t2 ⁄ R}

(10)

PU

b

with the results of

t1 = –R_PUC_b× ln(0.7)

t2 = –R_PUC_b× ln(0.3)

(11)

(12)

(13)

t_r= –R_PUC_b× ln(0.3) + R_PUC_b× ln(0.7)

R_PU(max)is a function of the rise time (t_r) and the bus capacitance (C_b) and will be

calculated with Equation 14:

t_r

300 × 10^–9

0.8473C_b

----------------------

R_PU(max)

=

(14)

-------------------------

0.8473C_b

12.1.2 Min value of pull-up resistor

The supply voltage limits the minimum value of resistor R_PUdue to the specified minimum

sink current (see value of I_OLon pin SDAACK in Table 18). R_PU(min)as a function of V_DDis

calculated with Equation 15:

V_DD– V_OL

R_PU(min)

=

(15)

--------------------------

I_OL

The designer now has the minimum and maximum value of R_PU. The values for R_PU(max)

and R_PU(min)are shown in Figure 26 and Figure 27.

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

001aak441

6

R

PU(max)

(kΩ)

5

4

3

2

1

0

20

60

100

140

180

220

260

300

340

380

420

460

500

(pF)

C

b

Fig 26. Values for R_PU(max)

001aak440

6

R

PU(min)

(kΩ)

5

4

3

2

1

0

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V

6

(V)

DD

Fig 27. Values for R_PU(min)

12.2 SDA and SDAACK configuration

The Serial DAta line (SDA) and the I²C-bus acknowledge line (SDAACK) are split. Both

lines can be connected together to facilitate a single line SDA.

SDA

SDAACK

two wire mode

single wire mode

013aaa111

Fig 28. SDA, SDAACK configurations

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

12.3 Cascaded operation

In large display configurations, up to 8 PCA85232 can be distinguished on the same

I²C-bus by using the 2-bit hardware subaddress (A0 and A1) and the programmable

I²C-bus slave address (SA0).

Table 20. Addressing cascaded PCA85232

Cluster

Bit SA0

Pin A1

Pin A0

Device

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

2

1

When cascaded PCA85232 are synchronized, they can share the backplane signals from

one of the devices in the cascade. Such an arrangement is cost-effective in large LCD

applications since the backplane outputs of only one device need to be through-plated to

the backplane electrodes of the display. The other PCA85232 of the cascade contribute

additional segment outputs but their backplane outputs are left open-circuit (see

Figure 29).

For display sizes that are not multiple of 640 elements, a mixed cascaded system can be

considered containing only devices like PCA85232 and PCA85133. Depending on the

application, one must take care of the software commands compatibility and pin

connection compatibility.

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCA85232. This synchronization is guaranteed after the Power-On Reset (POR). The

only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by

noise in adverse electrical environments, or by the definition of a multiplex mode when

PCA85232 with different SA0 levels are cascaded). SYNC is organized as an input/output

pin; the output selection being realized as an open-drain driver with an internal pull-up

resistor. A PCA85232 asserts the SYNC line at the onset of its last active backplane signal

and monitors the SYNC line at all other times. Should synchronization in the cascade be

lost, it will be restored by the first PCA85232 to assert SYNC. The timing relationship

between the backplane waveforms and the SYNC signal for the various drive modes of

the PCA85232 are shown in Figure 31.

When using an external clock signal with high frequencies (f_clk(ext)> 4 kHz) it is

recommended to have an external pull-up resistor between pin SYNC and pin V_DD(see

Table 19). This resistor should be present even when no cascading configuration is used!

When using it in a cascaded configuration, care must be taken not to route the SYNC

signal to close to noisy signals.

The contact resistance between the SYNC pads of cascaded devices must be controlled.

If the resistance is too high, the device will not be able to synchronize properly. This is

particularly applicable to COG applications. Table 21 shows the limiting values for contact

resistance.

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

Table 21. SYNC contact resistance

Number of devices

Maximum contact resistance

2

6000 Ω

2200 Ω

1200 Ω

3 to 5

6 to 8

In the cascaded applications, the OSC pin of the PCA85232 with subaddress 0 is

connected to V_SSso that this device uses its internal clock to generate a clock signal at

the CLK pin. The other PCA85232 devices are having the OSC pin connected to V_DD

,

meaning that these devices are ready to receive external clock, the signal being provided

by the device with subaddress 0.

In the case that the master is providing the clock signal to the slave devices, care must be

taken that the sending of display enable or disable will be received by both, the master

and the slaves at the same time. When the display is disabled the output from pin CLK is

disabled too. The disconnection of the clock may result in a DC component for the display.

Alternatively, the schematic can be also constructed such that all the devices have OSC

pin connected to V_DDand thus an external CLK being provided for the system (all devices

connected to the same external CLK).

A configuration where SYNC is connected but all PCA85232 are using the internal clock

(OSC pin tied to V_SS) is not recommended and may lead to display artifacts!

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

V

LCD

DD

SDA

SCL

segment drivers

PCA85232

LCD PANEL

SYNC

CLK

(2)

OSC

backplanes

(open-circuit)

A0

V

A1

SA0 V

SS

V

LCD

DD

t

r

R ≤

V

2C

DD

LCD

b

SDA

SCL

HOST

MICRO-

PROCESSOR/

MICRO-

segment drivers

backplanes

PCA85232

SYNC

(1)

CONTROLLER

CLK

OSC

013aaa285

A0

A1

SA0 V

SS

V

SS

(1) Is master (OSC connected to V_SS).

(2) Is slave (OSC connected to V_DD).

Fig 29. Cascaded configuration with two PCA85232 using the internal clock of the master

PCA85232

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

V

LCD

DD

SDA

SCL

segment drives

PCA85133

LCD PANEL

SYNC

CLK

(2)

OSC

backplanes

(open-circuit)

A0 A1 A2 SA0 V

SS

V

LCD

DD

t

r

R ≤

V

LCD

2C

DD

b

SDA

SCL

HOST

MICRO-

PROCESSOR/

MICRO-

segment drives

backplanes

PCA85232

SYNC

(1)

CONTROLLER

CLK

OSC

013aaa286

A0

A1

SA0 V

SS

V

SS

(1) Is master (OSC connected to V_SS).

(2) Is slave (OSC connected to V_DD).

Fig 30. Cascaded configuration with one PCA85232 and one PCA85133 using the internal

clock of the master

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

1

T

fr

=

f

fr

BP0

SYNC

(a) static drive mode

BP1

(1/2 bias)

BP1

(1/3 bias)

SYNC

(b) 1:2 multiplex drive mode

BP2

(1/3 bias)

SYNC

(c) 1:3 multiplex drive mode

BP3

(1/3 bias)

SYNC

(d) 1:4 multiplex drive mode

001aaj498

Fig 31. Synchronization of the cascade for the various PCA85232 drive modes

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

13. Bare die outline

Bare die; 197 bumps; 6.5 x 1.16 x 0.40 mm

PCA85232U

X

D

166

61

+y

+x

E

0

S1

C1

0

Marking code: PC85132/232-1

167

197 1

60

Y

A

b

A

2

e

1

A

1

L

detail Y

detail X

0

1

2 mm

scale

Dimensions

(1)

L

Unit

max

A

2

b

D

E

e

1

0.018

mm nom 0.40 0.015 0.380 0.0338 6.5

min 0.012

1.16 0.054 0.2025 0.090

Note

1. Dimension not drawn to scale.

pca85232_do

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

10-02-03

PCA85232U

Fig 32. Bare die outline of PCA85232

PCA85232

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

Table 22. Bump locations

All x/y coordinates represent the position of the center of each bump with respect to the center

(x/y = 0) of the chip; see Figure 32.

Symbol

SDAACK

SDA

SCL

CLK

V_DD

SYNC

OSC

T1

Bump

1

X (μm)

−1165.3

−1111.3

−1057.3

−854.8

−800.8

−746.8

−575.8

−521.8

−467.8

−316.2

−204.1

−150.1

−96.1

Y (μm)

−481.5

Symbol

S68

S69

S70

S71

S72

S73

S74

S75

S76

S77

S78

S79

BP0

BP2

BP1

BP3

S80

S81

S82

S83

S84

S85

S86

S87

S88

S89

S90

S91

S92

S93

S94

S95

S96

S97

S98

S99

S100

S101

S102

Bump

100

101

102

103

104

105

106

107

108

109

110

111

X (μm)

750.2

Y (μm)

481.5

2

696.2

3

642.2

4

588.2

5

534.2

6

480.2

7

426.2

8

372.2

9

318.2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

264.2

210.2

156.2

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

86.8

6.9

32.8

119.4

−21.2

203.1

−75.2

T2

286.8

−190.7

−244.7

−298.7

−352.7

−406.7

−460.7

−514.7

−568.7

−622.7

−676.7

−730.7

−784.7

−838.7

−892.7

−946.7

−1000.7

−1054.7

−1108.7

−1224.2

−1278.2

−1332.2

−1386.2

−1440.2

T3

389.9

T3

443.9

T3

497.9

A0

640.5

A1

724.2

SA0

V_SS

807.9

893.0

V_SS

947.0

V_SS

1001.0

1107.2

1161.2

1215.2

1303.4

1357.4

1411.4

1465.4

1519.4

1573.4

1627.4

1681.4

1735.4

1789.4

V_LCD

BP2

BP0

S0

S1

S2

S3

S4

S5

S6

S7

PCA85232

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PCA85232

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LCD driver for low multiplex rates

Table 22. Bump locations …continued

All x/y coordinates represent the position of the center of each bump with respect to the center

(x/y = 0) of the chip; see Figure 32.

Symbol

S8

Bump

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

X (μm)

1843.4

1897.4

1951.4

2005.4

2059.4

2113.4

2167.4

2221.4

2363.9

2417.9

2471.9

2525.9

2579.9

2633.9

2687.9

2741.9

2795.9

2849.9

2903.9

2957.9

3011.9

3067.7

3013.7

2959.7

2905.7

2851.7

2797.7

2743.7

2689.7

2635.7

2520.2

2466.2

2412.2

2358.2

2304.2

2250.2

2196.2

2142.2

2088.2

Y (μm)

−481.5

481.5

Symbol

S103

S104

S105

S106

S107

S108

S109

S110

S111

S112

S113

S114

S115

S116

S117

S118

S119

S120

S121

S122

S123

S124

S125

S126

S127

S128

S129

S130

S131

S132

S133

S134

S135

S136

S137

S138

S139

S140

S141

Bump

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

X (μm)

Y (μm)

481.5

−481.5

−1494.2

−1548.2

−1602.2

−1656.2

−1710.2

−1764.2

−1818.2

−1872.2

−1926.2

−1980.2

−2034.2

−2088.2

−2142.2

−2284.7

−2338.7

−2392.7

−2446.7

−2500.7

−2554.7

−2608.7

−2662.7

−2716.7

−2770.7

−2824.7

−2878.7

−2932.7

−2986.7

−3040.7

−3025.2

−2971.2

−2917.2

−2863.2

−2809.2

−2755.2

−2701.2

−2647.2

−2593.2

−2539.2

−2485.2

S9

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

S25

S26

S27

S28

S29

S30

S31

S32

S33

S34

S35

S36

S37

S38

S39

S40

S41

S42

S43

S44

S45

S46

481.5

PCA85232

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

Table 22. Bump locations …continued

All x/y coordinates represent the position of the center of each bump with respect to the center

(x/y = 0) of the chip; see Figure 32.

Symbol

S47

S48

S49

S50

S51

S52

S53

S54

S55

S56

S57

S58

S59

S60

S61

S62

S63

S64

S65

S66

S67

Bump

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

X (μm)

2034.2

1891.7

1837.7

1783.7

1729.7

1675.7

1621.7

1567.7

1513.7

1459.7

1405.7

1351.7

1297.7

1243.7

1189.7

1135.7

1081.7

1027.7

973.7

Y (μm)

481.5

Symbol

S142

S143

S144

S145

S146

S147

S148

S149

S150

S151

S152

S153

S154

S155

S156

S157

S158

S159

BP3

Bump

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

X (μm)

Y (μm)

−481.5

−2431.2

−2377.2

−2234.7

−2180.7

−2126.7

−2072.7

−2018.7

−1964.7

−1910.7

−1856.7

−1802.7

−1748.7

−1694.7

−1640.7

−1586.7

−1532.7

−1478.7

−1424.7

−1370.7

−1316.7

858.2

BP1

804.2

The dummy pins are connected to the segments shown (see Table 23) but are not tested.

Table 23. Dummy bumps

All x/y coordinates represent the position of the center of each bump with respect to the center

(x/y = 0) of the chip; see Figure 32.

Symbol

D1

Connected to pin

X (μm)

−3079.2

3065.9

3121.7

−3094.7

Y (μm)

−481.5

481.5

S131

S28

D2

D3

S29

D4

S130

481.5

The alignment marks are shown in Table 24.

Table 24. Alignment marking

All x/y coordinates represent the position of the REF point (see Figure 33) with respect to the center

(x/y = 0) of the chip; see Figure 32.

Symbol

S1

Size (μm)

X (μm)

Y (μm)

−47.25

121.5 × 121.5

−2733.75

2603.7

C1

PCA85232

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Product data sheet

Rev. 1 — 8 December 2010

47 of 54

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

REF

S1

C1

001aah849

Fig 33. Alignment marks

PCA85232

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Product data sheet

Rev. 1 — 8 December 2010

48 of 54

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

14. Packing information

Table 25. Tray dimensions (see Figure 34)

Symbol

Description

Value

A

B

C

D

E

F

x

pocket pitch in x direction

pocket pitch in y direction

pocket width in x direction

pocket width in y direction

tray width in x direction

tray width in y direction

8.8 mm

3.6 mm

6.65 mm

1.31 mm

50.8 mm

number of pockets, x direction

5

y

number of pockets, y direction 12

A

C

D

B

F

y

E

x

001aah890

Fig 34. Tray details

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

marking code

001aaj643

Fig 35. Tray alignment

15. Abbreviations

Table 26. Abbreviations

Acronym

AEC

COG

DC

Description

Automotive Electronics Council

Chip-On-Glass

Direct Current

HBM

I²C

Human Body Model

Inter-Integrated Circuit

Integrated Circuit

IC

ITO

Indium Tin Oxide

LCD

LSB

MM

Liquid Crystal Display

Least Significant Bit

Machine Model

MSB

POR

RC

Most Significant Bit

Power-On Reset

Resistance and Capacitance

Random Access Memory

Root Mean Square

Serial CLock line

RAM

RMS

SCL

SDA

Serial DAta line

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Product data sheet

Rev. 1 — 8 December 2010

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

16. References

[1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD

drivers

[2] AN10706 — Handling bare die

[3] AN10853 — ESD and EMC sensitivity of IC

[4] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[6] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[7] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model

(MM)

[8] JESD78 — IC Latch-Up Test

[9] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[10] NX3-00092 — NXP store and transport requirements

[11] UM10204 — I²C-bus specification and user manual

17. Revision history

Table 27. Revision history

Document ID

Release date

20101208

Data sheet status

Change notice

Supersedes

PCA85232 v.1

Product data sheet

-

PCA85232

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Product data sheet

Rev. 1 — 8 December 2010

51 of 54

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

18. Legal information

18.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

suitable for use in medical, military, aircraft, space or life support equipment,

18.2 Definitions

nor in applications where failure or malfunction of an NXP Semiconductors

product can reasonably be expected to result in personal injury, death or

severe property or environmental damage. NXP Semiconductors accepts no

liability for inclusion and/or use of NXP Semiconductors products in such

equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

18.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. The product is not designed, authorized or warranted to be

PCA85232

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 8 December 2010

52 of 54

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

systems after third party sawing, handling, packing or assembly of the die. It

is the responsibility of the customer to test and qualify their application in

which the die is used.

All die sales are conditioned upon and subject to the customer entering into a

written die sale agreement with NXP Semiconductors through its legal

department.

Bare die — All die are tested on compliance with their related technical

specifications as stated in this data sheet up to the point of wafer sawing and

are handled in accordance with the NXP Semiconductors storage and

transportation conditions. If there are data sheet limits not guaranteed, these

will be separately indicated in the data sheet. There are no post-packing tests

performed on individual die or wafers.

18.4 Trademarks

NXP Semiconductors has no control of third party procedures in the sawing,

handling, packing or assembly of the die. Accordingly, NXP Semiconductors

assumes no liability for device functionality or performance of the die or

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

19. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PCA85232

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Product data sheet

Rev. 1 — 8 December 2010

53 of 54

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

20. Contents

1

2

3

4

5

General description. . . . . . . . . . . . . . . . . . . . . . 1

12.1

Pull-up resistor sizing on I²C-bus. . . . . . . . . . 37

Max value of pull-up resistor . . . . . . . . . . . . . 37

Min value of pull-up resistor. . . . . . . . . . . . . . 37

SDA and SDAACK configuration . . . . . . . . . . 38

Cascaded operation. . . . . . . . . . . . . . . . . . . . 39

12.1.1

12.1.2

12.2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

12.3

13

14

15

16

17

Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 44

Packing information . . . . . . . . . . . . . . . . . . . . 49

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 50

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Revision history . . . . . . . . . . . . . . . . . . . . . . . 51

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7

7.1

7.2

7.3

7.3.1

7.4

7.4.1

7.4.2

7.4.3

7.4.4

7.5

7.5.1

7.5.2

7.6

Functional description . . . . . . . . . . . . . . . . . . . 6

Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 7

LCD bias generator . . . . . . . . . . . . . . . . . . . . . 7

LCD voltage selector . . . . . . . . . . . . . . . . . . . . 8

Electro-optical performance . . . . . . . . . . . . . . . 9

LCD drive mode waveforms . . . . . . . . . . . . . . 11

Static drive mode . . . . . . . . . . . . . . . . . . . . . . 11

1:2 multiplex drive mode. . . . . . . . . . . . . . . . . 12

1:3 multiplex drive mode. . . . . . . . . . . . . . . . . 14

1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 15

Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 16

External clock . . . . . . . . . . . . . . . . . . . . . . . . . 16

Timing and frame frequency. . . . . . . . . . . . . . 16

Display register. . . . . . . . . . . . . . . . . . . . . . . . 16

Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 17

Backplane outputs . . . . . . . . . . . . . . . . . . . . . 17

Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 17

Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Subaddress counter . . . . . . . . . . . . . . . . . . . . 20

Output bank selector . . . . . . . . . . . . . . . . . . . 20

Input bank selector . . . . . . . . . . . . . . . . . . . . . 21

Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Characteristics of the I²C-bus. . . . . . . . . . . . . 21

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

18

Legal information . . . . . . . . . . . . . . . . . . . . . . 52

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 52

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 53

18.1

18.2

18.3

18.4

19

20

Contact information . . . . . . . . . . . . . . . . . . . . 53

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.7

7.8

7.9

7.10

7.11

7.12

7.13

7.14

7.15

7.16

7.16.1

7.16.1.1 START and STOP conditions . . . . . . . . . . . . . 22

7.16.2

7.16.3

7.16.4

7.16.5

7.16.6

7.17

System configuration . . . . . . . . . . . . . . . . . . . 23

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 23

I²C-bus controller . . . . . . . . . . . . . . . . . . . . . . 24

Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 24

Command decoder. . . . . . . . . . . . . . . . . . . . . 26

Display controller . . . . . . . . . . . . . . . . . . . . . . 28

7.18

8

Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 29

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 30

Static characteristics. . . . . . . . . . . . . . . . . . . . 31

Dynamic characteristics . . . . . . . . . . . . . . . . . 34

Application information. . . . . . . . . . . . . . . . . . 37

9

10

11

12

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 8 December 2010

Document identifier: PCA85232


型号：	PCA85232DA
厂家：	NXP
描述：	LCD driver for low multiplex rates 低复用率的LCD驱动器驱动器 CD
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