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PCA8576CH/Q900/1 [NXP]

Universal LCD driver for low multiplex rates; 低复用率的通用LCD驱动器
PCA8576CH/Q900/1
型号： PCA8576CH/Q900/1
厂家： NXP    NXP
描述：

Universal LCD driver for low multiplex rates
低复用率的通用LCD驱动器

驱动器 CD
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PCA8576C  
Universal LCD driver for low multiplex rates  
Rev. 1 — 22 July 2010  
Product data sheet  
1. General description  
The PCA8576C is a peripheral device which interfaces to almost any Liquid Crystal  
Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or  
multiplexed LCD containing up to four backplanes and up to 40 segments and can easily  
be cascaded for larger LCD applications. The PCA8576C is compatible with most  
microprocessors or microcontrollers and communicates via a two-line bidirectional  
I2C-bus. Communication overheads are minimized by a display RAM with  
auto-incremented addressing and by hardware subaddressing.  
AEC-Q100 compliant for automotive applications.  
2. Features and benefits  
„ Single-chip LCD controller and driver  
„ 40 segment drives:  
‹ Up to twenty 7-segment alphanumeric characters  
‹ Up to ten 14-segment alphanumeric characters  
‹ Any graphics of up to 160 elements  
„ Versatile blinking modes  
„ No external components required (even in multiple device applications)  
„ Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing  
„ Selectable display bias configuration: static, 1⁄2, or 1⁄3  
„ Internal LCD bias generation with voltage-follower buffers  
„ 40 × 4-bit RAM for display data storage  
„ Auto-incremented display data loading across device subaddress boundaries  
„ Display memory bank switching in static and duplex drive modes  
„ Wide logic LCD supply range:  
‹ From 2 V for low-threshold LCDs  
‹ Up to 6 V for guest-host LCDs and high-threshold twisted nematic LCDs  
„ Low power consumption  
„ May be cascaded for large LCD applications (up to 2560 segments possible)  
„ No external components  
„ Separate or combined LCD and logic supplies  
„ Optimized pinning for plane wiring in both and multiple PCA8576C applications  
„ Power-saving mode for extremely low power consumption in battery-operated and  
telephone applications  
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 16.  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Name  
Description  
Version  
PCA8576CH/Q900/1  
LQFP64  
plastic low profile quad flat package;  
SOT314-2  
64 leads; body 10 × 10 × 1.4 mm  
4. Marking  
Table 2.  
Marking codes  
Type number  
PCA8576CH/Q900/1  
Marking code  
PCA8576CQ900  
5. Block diagram  
BP0 BP2 BP1 BP3  
S0 to S39  
40  
V
DD  
BACKPLANE  
OUTPUTS  
DISPLAY SEGMENT OUTPUTS  
DISPLAY LATCH  
LCD  
VOLTAGE  
SELECTOR  
LCD BIAS  
GENERATOR  
SHIFT REGISTER  
V
LCD  
PCA8576C  
CLK  
INPUT  
BANK  
SELECTOR  
DISPLAY  
RAM  
40 × 4 BITS  
OUTPUT  
BANK  
SELECTOR  
TIMING  
BLINKER  
SYNC  
DISPLAY  
CONTROLLER  
OSC  
OSCILLATOR  
POWER-  
ON  
RESET  
DATA  
POINTER  
COMMAND  
DECODER  
V
SS  
SUB-  
ADDRESS  
COUNTER  
SCL  
SDA  
2
INPUT  
FILTERS  
I C-BUS  
CONTROLLER  
SA0  
A0 A1 A2  
013aaa273  
Fig 1. Block diagram of PCA8576C  
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
2 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
6. Pinning information  
6.1 Pinning  
1
2
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
n.c.  
S34  
S35  
S36  
S37  
S38  
S39  
n.c.  
n.c.  
S17  
S16  
S15  
S14  
S13  
S12  
S11  
S10  
S9  
3
4
5
6
7
8
PCA8576CH  
9
n.c.  
10  
11  
12  
13  
14  
15  
16  
SDA  
SCL  
S8  
SYNC  
CLK  
S7  
S6  
V
S5  
DD  
OSC  
A0  
S4  
n.c.  
013aaa274  
Top view. For mechanical details, see Figure 29.  
Fig 2. Pin configuration for LQFP64 (PCA8576CH/Q900/1)  
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
3 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
6.2 Pin description  
Table 3.  
Symbol  
Pin description  
Pin  
Description  
LQFP64  
Type  
(PCA8576CH/Q900/1)  
SDA  
SCL  
10  
input/output I2C-bus serial data input and output  
input  
I2C-bus serial clock input  
11  
SYNC  
CLK  
12  
input/output cascade synchronization input and output  
input/output external clock input/output  
13  
VDD  
14  
supply  
input  
supply voltage  
OSC  
A0 to A2  
SA0  
15  
internal oscillator enable input  
16 to 18  
19  
input  
subaddress inputs  
input  
I2C-bus address input; bit 0  
ground supply voltage  
LCD supply voltage  
VSS  
20  
supply  
supply  
output  
VLCD  
21  
BP0, BP2, 25 to 28  
BP1, BP3  
LCD backplane outputs  
S0 to S39 2 to 7, 29 to 32, 34 to 47, output  
49 to 64  
LCD segment outputs  
n.c.  
1, 8, 9, 22 to 24, 33, 48  
-
not connected; do not connect and do not  
use as feed through  
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
4 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
7. Functional description  
The PCA8576C is a versatile peripheral device designed to interface between any  
microprocessor or microcontroller to a wide variety of LCD segment or dot matrix displays  
(see Figure 3). It can directly drive any static or multiplexed LCD containing up to four  
backplanes and up to 40 segments.  
dot matrix  
7-segment with dot  
14-segment with dot and accent  
013aaa312  
Fig 3. Example of displays suitable for PCA8576C  
The possible display configurations of the PCA8576C depend on the number of active  
backplane outputs required. A selection of display configurations is shown in Table 4. All  
of these configurations can be implemented in the typical system shown in Figure 4.  
Table 4.  
Selection of possible display configurations  
Number of  
Backplanes  
Icons  
Digits/Characters  
Dot matrix/  
Elements  
7-segment  
14-segment  
4
3
2
1
160  
120  
80  
20  
15  
10  
5
10  
7
160 dots (4 × 40)  
120 dots (3 × 40)  
80 dots (2 × 40)  
40 dots (1 × 40)  
5
40  
2
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
5 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
V
DD  
t
r
R≤  
2C  
B
V
DD  
V
LCD  
40 segment drives  
4 backplanes  
SDA  
SCL  
HOST  
MICRO-  
PROCESSOR/  
MICRO-  
CONTROLLER  
LCD PANEL  
PCA8576C  
(up to 160  
elements)  
OSC  
013aaa275  
A0 A1 A2 SA0 V  
SS  
V
SS  
Fig 4. Typical system configuration  
The host microprocessor or microcontroller maintains the 2-line I2C-bus communication  
channel with the PCA8576C.  
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing  
the need for an external bias generator. The internal oscillator is selected by connecting  
pin OSC to VSS. The only other connections required to complete the system are the  
power supplies (pins VDD, VSS, and VLCD) and the LCD panel selected for the application.  
7.1 Power-On-Reset (POR)  
At power-on the PCA8576C resets to the following starting conditions:  
• All backplane and segment outputs are set to VDD  
• The selected drive mode is 1:4 multiplex with 1⁄3 bias  
• Blinking is switched off  
• Input and output bank selectors are reset (as defined in Table 8)  
• The I2C-bus interface is initialized  
• The data pointer and the subaddress counter are cleared  
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow  
the reset action to complete.  
7.2 LCD bias generator  
The full-scale LCD voltage (Voper) is obtained from VDD − VLCD. The LCD voltage may be  
temperature compensated externally through the VLCD supply to pin VLCD  
.
Fractional LCD biasing voltages are obtained from an internal voltage divider comprising  
three series resistors connected between VDD and VLCD. The center resistor can be  
switched out of the circuit to provide a 1⁄2 bias voltage level for the 1:2 multiplex  
configuration.  
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
6 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
7.3 LCD voltage selector  
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the  
selected LCD drive configuration. The operation of the voltage selector is controlled by the  
mode-set command from the command decoder. The biasing configurations that apply to  
the preferred modes of operation, together with the biasing characteristics as functions of  
V
LCD and the resulting discrimination ratios (D) are given in Table 5.  
Table 5.  
Biasing characteristics  
Number of:  
LCD drive  
mode  
LCD bias  
configuration  
Voff(RMS) Von(RMS)  
------------------------ ----------------------- D = ------------------------  
VLCD VLCD Voff(RMS)  
Von(RMS)  
Backplanes Levels  
static  
1
2
2
3
4
2
3
4
4
4
static  
0
1
∞
1
1:2 multiplex  
1:2 multiplex  
1:3 multiplex  
1:4 multiplex  
⁄
2
0.354  
0.333  
0.333  
0.333  
0.791  
0.745  
0.638  
0.577  
2.236  
2.236  
1.915  
1.732  
1
⁄
3
1
⁄
3
1
⁄
3
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD  
threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In  
the static drive mode a suitable choice is VLCD > 3Vth.  
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and  
hence the contrast ratios are smaller.  
1
Bias is calculated by ------------ , where the values for a are  
1 + a  
a = 1 for 1⁄2 bias  
a = 2 for 1⁄3 bias  
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:  
a2 + 2a + n  
n × (1 + a)2  
Von(RMS)  
=
-----------------------------  
(1)  
V
LCD  
where the values for n are  
n = 1 for static drive mode  
n = 2 for 1:2 multiplex drive mode  
n = 3 for 1:3 multiplex drive mode  
n = 4 for 1:4 multiplex drive mode  
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:  
a2 – 2a + n  
n × (1 + a)2  
Voff(RMS)  
=
-----------------------------  
(2)  
(3)  
V
LCD  
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:  
(a + 1)2 + (n – 1)  
Von(RMS)  
----------------------  
D =  
=
-------------------------------------------  
(a – 1)2 + (n – 1)  
Voff(RMS)  
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
7 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with  
1⁄2 bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with  
21  
1⁄2 bias is ---------- = 1.528 .  
3
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD  
as follows:  
• 1:3 multiplex (1⁄2 bias): VLCD  
• 1:4 multiplex (1⁄2 bias): VLCD  
=
=
6 × Voff(RMS) = 2.449Voff(RMS)  
(4 × 3)  
---------------------  
= 2.309Voff(RMS)  
3
These compare with VLCD = 3Voff(RMS) when 1⁄3 bias is used.  
It should be noted that VLCD is sometimes referred as the LCD operating voltage.  
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
8 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
7.4 LCD drive mode waveforms  
7.4.1 Static drive mode  
The static LCD drive mode is used when a single backplane is provided in the LCD.  
Backplane and segment drive waveforms for this mode are shown in Figure 5.  
T
fr  
LCD segments  
V
LCD  
BP0  
Sn  
V
SS  
state 1  
(on)  
state 2  
(off)  
V
LCD  
V
SS  
V
LCD  
Sn+1  
V
SS  
(a) Waveforms at driver.  
V
LCD  
state 1  
0 V  
−V  
LCD  
V
LCD  
state 2  
0 V  
−V  
LCD  
(b) Resultant waveforms  
at LCD segment.  
mgl745  
Vstate1(t) = VSn(t) − VBP0(t).  
Von(RMS) = VLCD  
.
Vstate2(t) = VSn+1(t) − VBP0(t).  
Voff(RMS) = 0 V.  
Fig 5. Static drive mode waveforms  
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
9 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
7.4.2 1:2 Multiplex drive mode  
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The  
PCA8576C allows the use of 1⁄2 bias or 1⁄3 bias (see Figure 6 and Figure 7).  
T
fr  
V
LCD  
LCD segments  
V
V
/ 2  
/ 2  
BP0  
BP1  
Sn  
LCD  
SS  
state 1  
V
LCD  
state 2  
V
V
LCD  
SS  
V
LCD  
V
V
SS  
LCD  
Sn+1  
V
SS  
(a) Waveforms at driver.  
V
V
LCD  
LCD  
/ 2  
0 V  
−V  
state 1  
/ 2  
LCD  
−V  
LCD  
V
V
LCD  
/ 2  
LCD  
0 V  
state 2  
−V  
/ 2  
LCD  
LCD  
−V  
(b) Resultant waveforms  
at LCD segment.  
mgl746  
Vstate1(t) = VSn(t) − VBP0(t).  
Von(RMS) = 0.791VLCD  
.
Vstate2(t) = VSn(t) − VBP1(t).  
Voff(RMS) = 0.354VLCD  
Fig 6. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias  
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
10 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
T
fr  
V
LCD  
2V  
LCD segments  
/ 3  
LCD  
/ 3  
BP0  
BP1  
Sn  
V
V
LCD  
SS  
state 1  
V
LCD  
state 2  
2V  
/ 3  
LCD  
/ 3  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
Sn+1  
V
V
LCD  
SS  
(a) Waveforms at driver.  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
V
LCD  
0 V  
−V  
state 1  
/ 3  
LCD  
−2V  
/ 3  
LCD  
−V  
LCD  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
V
LCD  
0 V  
−V  
state 2  
/ 3  
LCD  
−2V  
/ 3  
LCD  
−V  
LCD  
(b) Resultant waveforms  
at LCD segment.  
mgl747  
Vstate1(t) = VSn(t) − VBP0(t).  
Von(RMS) = 0.745VLCD  
Vstate2(t) = VSn(t) − VBP1(t)  
Voff(RMS) = 0.333VLCD.  
Fig 7. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias  
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
11 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
7.4.3 1:3 Multiplex drive mode  
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as  
shown in Figure 8.  
T
fr  
V
LCD  
2V  
LCD segments  
/ 3  
LCD  
/ 3  
BP0  
BP1  
BP2  
Sn  
V
V
LCD  
SS  
state 1  
state 2  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
Sn+1  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
Sn+2  
V
V
LCD  
SS  
(a) Waveforms at driver.  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
V
LCD  
0 V  
−V  
state 1  
/ 3  
/ 3  
LCD  
−2V  
LCD  
−V  
LCD  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
V
LCD  
0 V  
−V  
state 2  
/ 3  
/ 3  
LCD  
−2V  
LCD  
−V  
LCD  
(b) Resultant waveforms  
at LCD segment.  
mgl748  
Vstate1(t) = VSn(t) − VBP0(t).  
Von(RMS) = 0.638VLCD  
.
Vstate2(t) = VSn(t) − VBP1(t).  
Voff(RMS) = 0.333VLCD.  
Fig 8. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias  
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
12 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
7.4.4 1:4 multiplex drive mode  
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as  
shown in Figure 9.  
T
fr  
V
LCD segments  
LCD  
2V  
/ 3  
LCD  
/ 3  
BP0  
BP1  
BP2  
V
V
LCD  
SS  
state 1  
state 2  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
BP3  
Sn  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
Sn+1  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
Sn+2  
Sn+3  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
V
V
LCD  
SS  
(a) Waveforms at driver.  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
V
LCD  
0 V  
−V  
state 1  
/ 3  
LCD  
−2V  
/ 3  
LCD  
−V  
LCD  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
V
LCD  
0 V  
−V  
state 2  
/ 3  
LCD  
−2V  
/ 3  
LCD  
−V  
LCD  
(b) Resultant waveforms  
at LCD segment.  
mgl749  
Vstate1(t) = VSn(t) − VBP0(t).  
Von(RMS) = 0.577VLCD  
.
Vstate2(t) = VSn(t) − VBP1(t).  
Voff(RMS) = 0.333VLCD.  
Fig 9. Waveforms for the 1:4 multiplex mode with 1⁄3 bias  
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
13 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
7.5 Oscillator  
The internal logic and the LCD drive signals of the PCA8576C are timed by the frequency  
fclk, which equals either the built-in oscillator frequency fosc or the external clock frequency  
fclk(ext)  
.
The clock frequency (fclk) determines the LCD frame frequency (ffr) and the maximum rate  
for data reception from the I2C-bus. To allow I2C-bus transmissions at their maximum data  
rate of 100 kHz, fclk should be chosen to be above 125 kHz.  
7.5.1 Internal clock  
The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the  
output from pin CLK is the clock signal for any cascaded PCA8576C in the system.  
7.5.2 External clock  
Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the  
external clock input.  
Remark: A clock signal must always be supplied to the device. Removing the clock,  
freezes the LCD in a DC state, which is not suitable for the liquid crystal.  
7.6 Timing  
The timing of the PCA8576C sequences the internal data flow of the device. This includes  
the transfer of display data from the display RAM to the display segment outputs. In  
cascaded applications, the synchronization signal (SYNC) maintains the correct timing  
relationship between the PCA8576Cs in the system. The timing also generates the LCD  
frame frequency which is derived as an integer division of the clock frequency (see  
Table 6). The frame frequency is set by the mode-set command (see Table 9) when an  
internal clock is used or by the frequency applied to the pin CLK when an external clock is  
used.  
Table 6.  
LCD frame frequencies [1]  
PCA8576C mode  
Frame frequency  
Nominal frame frequency (Hz)  
Normal-power mode  
69 [2]  
fclk  
------------  
ffr  
=
=
2880  
Power-saving mode  
65 [3]  
fclk  
---------  
480  
ffr  
[1] The possible values for fclk see Table 16.  
[2] For fclk = 200 kHz.  
[3] For fclk = 31 kHz.  
The ratio between the clock frequency and the LCD frame frequency depends on the  
power mode in which the device is operating. In the power-saving mode the reduction  
ratio is six times smaller; this allows the clock frequency to be reduced by a factor of six.  
The reduced clock frequency results in a significant reduction in power consumption.  
PCA8576C  
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The lower clock frequency has the disadvantage of increasing the response time when  
large amounts of display data are transmitted on the I2C-bus. When a device is unable to  
process a display data byte before the next one arrives, it holds the SCL line LOW until  
the first display data byte is stored. This slows down the transmission rate of the I2C-bus  
but no data loss occurs.  
7.7 Display register  
The display register holds the display data while the corresponding multiplex signals are  
generated.  
7.8 Shift register  
The shift register transfers display information from the display RAM to the display register  
while previous data is displayed.  
7.9 Segment outputs  
The LCD drive section includes 40 segment outputs, S0 to S39, which must be connected  
directly to the LCD. The segment output signals are generated based on the multiplexed  
backplane signals and with data residing in the display register. When less than  
40 segment outputs are required, the unused segment outputs should be left open-circuit.  
7.10 Backplane outputs  
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane  
output signals are generated based on the selected LCD drive mode.  
• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.  
If less than four backplane outputs are required the unused outputs can be left as an  
open-circuit.  
• In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two  
adjacent outputs can be tied together to give enhanced drive capabilities.  
• In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same  
signals and can also be paired to increase the drive capabilities.  
• In static drive mode: the same signal is carried by all four backplane outputs and they  
can be connected in parallel for very high drive requirements.  
7.11 Display RAM  
The display RAM is a static 40 × 4-bit RAM which stores LCD data.  
There is a one-to-one correspondence between  
• the bits in the RAM bitmap and the LCD elements  
• the RAM columns and the segment outputs  
• the RAM rows and the backplane outputs.  
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;  
similarly, a logic 0 indicates the off-state.  
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The display RAM bit map Figure 10 shows the rows 0 to 3 which correspond with the  
backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the  
segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,  
second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2,  
and BP3 respectively.  
display RAM addresses (columns)/segment outputs (S)  
0
1
2
3
4
35 36 37 38 39  
0
1
2
3
display RAM bits  
(rows)/  
backplane outputs  
(BP)  
mbe525  
The display RAM bitmap shows the direct relationship between the display RAM column and the  
segment outputs; and between the bits in a RAM row and the backplane outputs.  
Fig 10. Display RAM bit map  
When display data is transmitted to the PCA8576C, the display bytes received are stored  
in the display RAM in accordance with the selected LCD drive mode. The data is stored as  
it arrives and does not wait for an acknowledge cycle as with the commands. Depending  
on the current multiplex drive mode, data is stored singularly, in pairs, triples or  
quadruples. To illustrate the filling order, an example of a 7-segment numeric display  
showing all drive modes is given in Figure 11; the RAM filling organization depicted  
applies equally to other LCD types.  
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx  
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
drive mode  
LCD segments  
LCD backplanes  
display RAM filling order  
transmitted display byte  
columns  
display RAM address/segment outputs (s)  
byte1  
S
n+2  
S
n+3  
S
n+4  
S
n+5  
S
n+6  
a
b
BP0  
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7  
S
f
n+1  
rows  
static  
display RAM  
rows/backplane  
outputs (BP)  
MSB  
LSB  
g
0
1
2
3
c
x
x
x
b
x
x
x
a
x
x
x
f
g
x
x
x
e
x
x
x
d
x
x
x
DP  
x
S
S
n
x
x
x
e
n+7  
c
b
a
f
g
e
d
DP  
c
x
d
DP  
x
columns  
display RAM address/segment outputs (s)  
byte1 byte2  
BP0  
a
S
S
n
1:2  
b
n
n + 1 n + 2 n + 3  
f
n+1  
rows  
MSB  
LSB  
DP  
display RAM  
rows/backplane  
outputs (BP)  
g
0
1
2
3
a
b
x
x
f
e
c
x
x
d
DP  
x
multiplex  
g
x
x
BP1  
a
b
f
g
e c d  
e
S
S
n+2  
c
d
DP  
x
n+3  
columns  
display RAM address/segment outputs (s)  
BP0  
BP1  
byte1  
byte2  
byte3  
S
S
n+1  
a
1:3  
b
n
n + 1 n + 2  
S
n
f
n+2  
rows  
MSB  
LSB  
e
display RAM  
rows/backplane  
outputs (BP)  
0
1
2
3
b
DP  
c
a
d
g
x
f
g
multiplex  
b
DP  
c
a
d
g
f
e
x
x
BP2  
e
c
d
DP  
x
columns  
display RAM address/segment outputs (s)  
byte2 byte3 byte4  
byte1  
byte5  
a
S
S
n
1:4  
b
BP2  
BP3  
n
n + 1  
BP0  
BP1  
f
rows  
display RAM  
rows/backplane  
outputs (BP)  
g
0
1
2
3
a
c
f
MSB  
LSB  
d
multiplex  
e
g
d
e
c
b
a
c
b
DP  
f
e
g
d
DP  
DP  
n+1  
001aaj646  
x = data bit unchanged.  
Fig 11. Relationship between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
The following applies to Figure 11:  
• In the static drive mode, the eight transmitted data bits are placed in row 0 of eight  
successive 4-bit RAM words.  
• In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into  
row 0 and 1 of four successive 4-bit RAM words.  
• In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1, and 2 to  
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is  
not recommended to use this bit in a display because of the difficult addressing. This  
last bit may, if necessary, be controlled by an additional transfer to this address but  
care should be taken to avoid overwriting adjacent data because always full bytes are  
transmitted.  
• In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into  
row 0, 1, 2, and 3 of two successive 4-bit RAM words.  
7.12 Data pointer  
The addressing mechanism for the display RAM is realized using the data pointer. This  
allows the loading of an individual display data byte or a series of display data bytes, into  
any location of the display RAM. The sequence commences with the initialization of the  
data pointer by the load-data-pointer command (see Table 10). After this, the data byte is  
stored starting at the display RAM address indicated by the data pointer (see Figure 11).  
Once each byte is stored, the data pointer is automatically incremented based on the  
selected LCD configuration.  
The contents of the data pointer are incremented as follows:  
• In static drive mode by eight.  
• In 1:2 multiplex drive mode by four.  
• In 1:3 multiplex drive mode by three.  
• In 1:4 multiplex drive mode by two.  
If an I2C-bus data access terminates early, the state of the data pointer is unknown.  
Consequently, the data pointer must be rewritten prior to further RAM accesses.  
7.13 Sub-address counter  
The storage of display data is conditioned by the contents of the subaddress counter.  
Storage is allowed to take place only when the contents of the subaddress counter match  
with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is  
defined by the device-select command (see Table 11). If the contents of the subaddress  
counter and the hardware subaddress do not match then data storage is blocked but the  
data pointer will be incremented as if data storage had taken place. The subaddress  
counter is also incremented when the data pointer overflows.  
The storage arrangements described lead to extremely efficient data loading in cascaded  
applications. When a series of display bytes are sent to the display RAM, automatic  
wrap-over to the next PCA8576C occurs when the last RAM address is exceeded.  
Subaddressing across device boundaries is successful even if the change to the next  
device in the cascade occurs within a transmitted character.  
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7.14 Bank selector  
7.14.1 Output bank selector  
The output bank selector (see Table 12), selects one of the four rows per display RAM  
address for transfer to the display register. The actual row selected depends on the LCD  
drive mode in operation and on the instant in the multiplex sequence.  
• In 1:4 multiplex mode: all RAM addresses of row 0 are selected, followed sequentially  
by the contents of row 1, row 2, and then row 3.  
• In 1:3 multiplex mode: rows 0, 1, and 2 are selected sequentially.  
• In 1:2 multiplex mode: rows 0 and 1 are selected.  
• In the static mode: row 0 is selected.  
The PCA8576C includes a RAM bank switching feature in the static and 1:2 multiplex  
drive modes. In the static drive mode, the bank-select command may request the contents  
of row 2 to be selected for display instead of the contents of row 0. In 1:2 multiplex drive  
mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This  
enables preparation of display information in an alternative bank and the ability to switch  
to it once it has been assembled.  
7.14.2 Input bank selector  
The input bank selector (see Table 12) loads display data into the display RAM based on  
the selected LCD drive configuration. Using the bank-select command, display data can  
be loaded in row 2 into static drive mode or in rows 2 and 3 into 1:2 multiplex drive mode.  
The input bank selector functions independently of the output bank selector.  
7.15 Blinker  
The display blinking capabilities of the PCA8576C are very versatile. The whole display  
can be blinked at frequencies selected by the blink-select command. The blinking  
frequencies are integer fractions of the clock frequency; the ratios between the clock and  
blinking frequencies depend on the mode in which the device is operating (see Table 7).  
Table 7.  
Blink frequencies  
Blinking mode  
Normal-power mode Power-saving mode  
Blink frequency  
ratio  
ratio  
off  
1
-
-
blinking off  
2 Hz  
fclk  
fclk  
----------------  
92160  
----------------  
15360  
fblink  
fblink  
fblink  
=
=
=
fblink  
fblink  
fblink  
=
=
=
2
3
1 Hz  
fclk  
fclk  
-------------------  
184320  
----------------  
30720  
0.5 Hz  
fclk  
fclk  
-------------------  
368640  
----------------  
61440  
An additional feature is for an arbitrary selection of LCD segments to be blinked. This  
applies to the static and 1:2 multiplex drive modes and can be implemented without any  
communication overheads. Using the output bank selector, the displayed RAM banks are  
exchanged with alternate RAM banks at the blinking frequency. This mode can also be  
specified by the blink-select command (see Table 13).  
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In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of  
LCD segments can be blinked by selectively changing the display RAM data at fixed time  
intervals.  
If the entire display needs to be blinked at a frequency other than the nominal blink  
frequency, this can be done using the mode-set command to set and reset the display  
enable bit E at the required rate (see Table 9).  
7.16 Characteristics of the I2C-bus  
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.  
The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must  
be connected to a positive supply via a pull-up resistor when connected to the output  
stages of a device. Data transfer may be initiated only when the bus is not busy.  
7.16.1 Bit transfer  
One data bit is transferred during each clock pulse. The data on the SDA line must remain  
stable during the HIGH period of the clock pulse. Changes in the data line at this time will  
be interpreted as a control signal. Bit transfer is illustrated in Figure 12.  
SDA  
SCL  
data line  
stable;  
data valid  
change  
of data  
allowed  
mba607  
Fig 12. Bit transfer  
7.16.2 START and STOP conditions  
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change  
of the data line, while the clock is HIGH, is defined as the START condition (S).  
A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP  
condition (P). The START and STOP conditions are illustrated in Figure 13.  
SDA  
SCL  
SDA  
SCL  
S
P
START condition  
STOP condition  
mbc622  
Fig 13. Definition of START and STOP conditions  
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7.16.3 System configuration  
A device generating a message is a transmitter and a device receiving a message is the  
receiver. The device that controls the message is the master and the devices which are  
controlled by the master are the slaves. The system configuration is illustrated in  
Figure 14.  
MASTER  
TRANSMITTER/  
RECEIVER  
MASTER  
TRANSMITTER/  
RECEIVER  
SLAVE  
TRANSMITTER/  
RECEIVER  
SLAVE  
RECEIVER  
MASTER  
TRANSMITTER  
SDA  
SCL  
mga807  
Fig 14. System configuration  
7.16.4 Acknowledge  
The number of data bytes transferred between the START and STOP conditions from  
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge  
cycle.  
• A slave receiver, which is addressed, must generate an acknowledge after the  
reception of each byte.  
• A master receiver must generate an acknowledge after the reception of each byte that  
has been clocked out of the slave transmitter.  
• The device that acknowledges must pull-down the SDA line during the acknowledge  
clock pulse, so that the SDA line is stable LOW during the HIGH period of the  
acknowledge related clock pulse (set-up and hold times must be taken into  
consideration).  
• A master receiver must signal an end of data to the transmitter by not generating an  
acknowledge on the last byte that has been clocked out of the slave. In this event, the  
transmitter must leave the data line HIGH to enable the master to generate a STOP  
condition.  
Acknowledgement on the I2C-bus is illustrated in Figure 15.  
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Universal LCD driver for low multiplex rates  
data output  
by transmitter  
not acknowledge  
acknowledge  
data output  
by receiver  
SCL from  
master  
1
2
8
9
S
clock pulse for  
acknowledgement  
START  
condition  
mbc602  
Fig 15. Acknowledgement of the I2C-bus  
7.16.5 PCA8576C I2C-bus controller  
The PCA8576C acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or  
transmit data to an I2C-bus master receiver. The only data output from the PCA8576C are  
the acknowledge signals of the selected devices. Device selection depends on the  
I2C-bus slave address, the transferred command data and the hardware subaddress.  
In single device application, the hardware subaddress inputs A0, A1, and A2 are normally  
tied to VSS which defines the hardware subaddress 0. In multiple device applications  
A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme so that no two  
devices with a common I2C-bus slave address have the same hardware subaddress.  
In the power-saving mode it is possible that the PCA8576C is not able to keep up with the  
highest transmission rates when large amounts of display data are transmitted. If this  
situation occurs, the PCA8576C forces the SCL line LOW until its internal operations are  
completed. This is known as the clock synchronization feature of the I2C-bus and serves  
to slow down fast transmitters. Data loss does not occur.  
7.16.6 Input filter  
To enhance noise immunity in electrically adverse environments, RC low-pass filters are  
provided on the SDA and SCL lines.  
7.17 I2C-bus protocol  
Two I2C-bus slave addresses (0111000 and 0111001) are reserved for the PCA8576C.  
The least significant bit of the slave address that a PCA8576C responds to is defined by  
the level tied at its input SA0. Therefore, two types of PCA8576C can be distinguished on  
the same I2C-bus which allows:  
• Up to 16 PCA8576Cs on the same I2C-bus for very large LCD applications.  
• The use of two types of LCD multiplex on the same I2C-bus.  
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The I2C-bus protocol is shown in Figure 16. The sequence is initiated with a START  
condition (S) from the I2C-bus master which is followed by one of the two PCA8576C  
slave addresses available. All PCA8576Cs with the corresponding SA0 level  
acknowledge in parallel with the slave address but all PCA8576Cs with the alternative  
SA0 level ignore the whole I2C-bus transfer.  
After acknowledgement, one or more command bytes follow which define the status of the  
addressed PCA8576Cs.  
The last command byte is tagged with a cleared most significant bit, the continuation bit C.  
The command bytes are also acknowledged by all addressed PCA8576Cs on the bus.  
After the last command byte, a series of display data bytes may follow. These display  
bytes are stored in the display RAM at the address specified by the data pointer and the  
subaddress counter. Both data pointer and subaddress counter are automatically updated  
and the data is directed to the intended PCA8576C device. The acknowledgement after  
each byte is made only by the (A0, A1, and A2) addressed PCA8576C. After the last  
display byte, the I2C-bus master issues a STOP condition (P).  
acknowledge  
acknowledge by  
by A0, A1 and A2  
all addressed  
selected  
R/W  
0
PCA8576Cs  
PCA8576C only  
slave address  
S
A
0
0
1
1
1
0
0
A C  
A
DISPLAY DATA  
A
COMMAND  
S
P
n ≥ 1 byte(s)  
n ≥ 0 byte(s)  
1 byte  
update data pointers  
and if necessary,  
subaddress counter  
013aaa276  
Fig 16. I2C-bus protocol  
7.18 Command decoder  
The command decoder identifies command bytes that arrive on the I2C-bus. All available  
commands carry a continuation bit C in their most significant bit position as shown in  
Figure 17. When this bit is set logic 1, it indicates that the next byte of the transfer to arrive  
will also represent a command. If this bit is set logic 0, it indicates that the command byte  
is the last in the transfer. Further bytes will be regarded as display data.  
MSB  
LSB  
C
REST OF OPCODE  
msa833  
(1) C = 0; last command  
(2) C = 1; commands continue  
Fig 17. General format of the command byte  
The five commands available to the PCA8576C are defined in Table 8.  
PCA8576C  
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Universal LCD driver for low multiplex rates  
Table 8.  
Definition of PCA8576C commands  
Operation Code  
Command  
Bit  
Reference  
7
6
1
0
1
1
1
5
4
3
2
1
0
mode-set  
C
C
C
C
C
0
LP  
E
B
M[1:0]  
Section 7.18.1  
Section 7.18.2  
Section 7.18.3  
Section 7.18.4  
Section 7.18.5  
load-data-pointer  
device-select  
bank-select  
blink-select  
P[5:0]  
1
1
1
0
1
1
0
1
0
A[2:0]  
0
I
O
AB  
BF[1:0]  
7.18.1 Mode-set command  
Table 9.  
Mode-set command bit description  
Bit  
7
Symbol Value  
Description  
see Figure 17  
fixed value  
C
-
0, 1  
10  
6 to 5  
4
LP  
power dissipation (see Table 6)  
normal-power mode  
power-saving mode  
display status  
0
1
3
E
0
1
disabled[1]  
enabled  
2
B
LCD bias configuration[2]  
1⁄3 bias  
1⁄2 bias  
0
1
1 to 0  
M[1:0]  
LCD drive mode selection  
static; BP0  
01  
10  
11  
00  
1:2 multiplex; BP0, BP1  
1:3 multiplex; BP0, BP1, BP2  
1:4 multiplex; BP0, BP1, BP2, BP3  
[1] The possibility to disable the display allows implementation of blinking under external control.  
[2] Bit B is not applicable for the static LCD drive mode.  
7.18.2 Load-data-pointer command  
Table 10. Load-data-pointer command bit description  
Bit  
7
Symbol Value  
Description  
see Figure 17  
fixed value  
C
0, 1  
0
6
-
5 to 0  
P[5:0]  
000000 to  
100111  
6 bit binary value, 0 to 39; transferred to the data pointer to  
define one of forty display RAM addresses  
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Universal LCD driver for low multiplex rates  
7.18.3 Device-select command  
Table 11. Device-select command bit description  
Bit  
Symbol Value  
Description  
see Figure 17  
fixed value  
7
C
0, 1  
6 to 4  
3 to 0  
-
1100  
A[2:0]  
000 to 111  
3 bit binary value, 0 to 7; transferred to the subaddress  
counter to define one of eight hardware subaddresses  
7.18.4 Bank-select command  
Table 12. Bank-select command bit description  
Bit  
Symbol Value  
Description  
Static  
1:2 multiplex[1]  
7
C
-
0, 1  
see Figure 17  
fixed value  
6 to 2  
1
11110  
I
input bank selection; storage of arriving display data  
0
1
RAM bit 0  
RAM bit 2  
RAM bits 0 and 1  
RAM bits 2 and 3  
0
O
output bank selection; retrieval of LCD display data  
0
1
RAM bit 0  
RAM bit 2  
RAM bits 0 and 1  
RAM bits 2 and 3  
[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.  
7.18.5 Blink-select command  
Table 13. Blink-select command bit description  
Bit  
7
Symbol Value  
Description  
C
0, 1  
see Figure 17  
6 to 3  
2
-
1110  
fixed value  
AB  
blink mode selection  
0
1
normal blinking[1]  
alternate RAM bank blinking[2]  
1 to 0  
BF[1:0]  
blink frequency selection  
00  
01  
10  
11  
off  
1
2
3
[1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.  
[2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.  
7.19 Display controller  
The display controller executes the commands identified by the command decoder. It  
contains the status registers of the PCA8576C and coordinates their effects. The  
controller is also responsible for loading display data into the display RAM as required by  
the filling order.  
PCA8576C  
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PCA8576C  
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Universal LCD driver for low multiplex rates  
8. Internal circuitry  
V
LCD  
V
SS  
BP0 to BP3,  
S0 to S39  
SDA, SCL  
CLK, OSC, A0 to A2,  
SA0,  
SYNC  
V
DD  
013aaa109  
Fig 18. Device protection diagram  
PCA8576C  
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PCA8576C  
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Universal LCD driver for low multiplex rates  
9. Limiting values  
CAUTION  
Static voltages across the liquid crystal display can build up when the LCD supply voltage  
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted  
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.  
Table 14. Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol Parameter  
Conditions  
Min  
Max  
Unit  
V
VDD  
VLCD  
VI  
supply voltage  
LCD supply voltage  
input voltage  
−0.5  
+8.0  
[1]  
VDD − 8.0 VDD  
V
on each of the pins SCL, SDA, −0.5  
+8.0  
V
CLK, SYNC, SA0, OSC and  
A0 to A2  
[1]  
VO  
output voltage  
on each of the pins  
−0.5  
+8.0  
V
S0 to S39 and BP0 to BP3  
II  
input current  
−20  
−25  
−50  
−50  
−50  
-
+20  
+25  
mA  
mA  
mA  
mA  
mA  
mW  
mW  
V
IO  
output current  
IDD  
ISS  
supply current  
+50  
ground supply current  
+50  
IDD(LCD) LCD supply current  
+50  
Ptot  
Po  
total power dissipation  
output power  
400  
-
100  
[2]  
[3]  
[4]  
VESD  
electrostatic discharge  
voltage  
HBM  
-
±4000  
±200  
MM  
-
V
CDM  
all pins  
corner pins  
-
500  
V
-
1000  
150  
V
[5]  
[6]  
Ilu  
latch-up current  
-
mA  
°C  
°C  
Tstg  
Tamb  
storage temperature  
ambient temperature  
−65  
−40  
+150  
+85  
operating device  
[1] Values with respect to VDD  
.
[2] Pass level; Human Body Model (HBM), according to Ref. 5 “JESD22-A114”.  
[3] Pass level; Machine Model (MM), according to Ref. 6 “JESD22-A115”.  
[4] Pass level; Charged-Device Model (CDM), according to Ref. 7 “JESD22-C101”.  
[5] Pass level; latch-up testing according to Ref. 8 “JESD78” at maximum ambient temperature (Tamb(max)).  
[6] According to the NXP store and transport requirements (see Ref. 9 “NX3-00092”) the devices have to be  
stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products  
deviant conditions are described in that document.  
PCA8576C  
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Product data sheet  
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27 of 44  
PCA8576C  
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Universal LCD driver for low multiplex rates  
10. Static characteristics  
Table 15. Static characteristics  
VDD = 2.0 V to 6.0 V; VSS = 0 V; VLCD = VDD − 6.0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Supplies  
VDD  
supply voltage  
2.0  
-
-
-
-
6.0  
V
[1]  
[2]  
VLCD  
IDD  
LCD supply voltage  
supply current:  
VDD − 6.0  
VDD − 2.0 V  
fclk = 200 kHz  
-
-
120  
60  
μA  
IDD(lp)  
low-power mode supply  
current  
VDD = 3.5 V; VLCD = 0 V; fclk = 35 kHz;  
A0, A1 and A2 connected to VSS  
μA  
Logic  
VIL  
LOW-level input voltage  
HIGH-level input voltage  
on pins CLK, SYNC, OSC,  
A0 to A2 and SA0  
VSS  
-
-
-
0.3VDD  
VDD  
V
V
VIH  
on pins CLK, SYNC, OSC,  
A0 to A2 and SA0  
0.7VDD  
VOL  
VOH  
IOL  
LOW-level output voltage  
HIGH-level output voltage  
LOW-level output current  
IOL = 0 mA  
IOH = 0 mA  
-
0.05  
V
VDD − 0.05 -  
-
-
V
output sink current;  
1
-
mA  
VOL = 1.0 V; VDD = 5.0 V;  
on pins CLK and SYNC  
IL  
leakage current  
VI = VDD or VSS; on pins  
−1  
-
+1  
μA  
CLK, SCL, SDA, A0 to A2 and SA0  
IL(OSC)  
Ipd  
leakage current on pin OSC  
pull-down current  
VI = VDD  
−1  
-
+1  
μA  
μA  
VI = 1.0 V; VDD = 5.0 V;  
15  
50  
150  
on pins A0 to A2 and OSC  
RSYNC_N SYNC resistance  
20  
-
50  
1.0  
-
150  
1.6  
7
kΩ  
V
[3]  
[4]  
VPOR  
CI  
power-on reset voltage  
input capacitance  
-
pF  
I2C-bus; pins SDA and SCL  
VIL  
LOW-level input voltage  
HIGH-level input voltage  
VSS  
0.7VDD  
1
-
-
-
0.3VDD  
V
VIH  
6.0  
-
V
IOH(CLK)  
HIGH-level output current on output source current;  
mA  
pin CLK  
VOH = 4.0 V; VDD = 5.0 V  
IOL(SDA)  
LOW-level output current on  
pin SDA  
output sink current;  
VOL = 0.4 V; VDD = 5.0 V  
3
-
-
mA  
PCA8576C  
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PCA8576C  
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Universal LCD driver for low multiplex rates  
Table 15. Static characteristics …continued  
VDD = 2.0 V to 6.0 V; VSS = 0 V; VLCD = VDD − 6.0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.  
Symbol Parameter  
LCD outputs  
Conditions  
Min  
Typ  
Max  
Unit  
VBP  
VS  
voltage on pin BP  
Cbpl = 35 nF; on pins BP0 to BP3  
Csgm = 5 nF; on pins S0 to S39  
−20  
-
-
-
-
+20  
+20  
5
mV  
mV  
kΩ  
kΩ  
voltage on pin S  
−20  
[5]  
[5]  
RBP  
RS  
resistance on pin BP  
resistance on pin S  
VLCD = VDD − 5 V; on pins BP0 to BP3  
VLCD = VDD − 5 V; on pins S0 to S39  
-
-
7.5  
[1] VLCD ≤ VDD − 3 V for 1⁄3 bias.  
[2] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.  
[3] Resets all logic when VDD < VPOR  
.
[4] Periodically sampled, not 100 % tested.  
[5] Outputs measured one at a time.  
10.1 Typical supply current characteristics  
mbe530  
mbe529  
50  
40  
50  
I
−I  
DD(LCD)  
(μA)  
SS  
(μA)  
normal  
mode  
40  
30  
20  
30  
20  
power-saving  
mode  
10  
0
10  
0
0
100  
200  
0
100  
200  
f
fr  
(Hz)  
f (Hz)  
fr  
VDD = 5 V; VLCD = 0 V; Tamb = 25 °C  
VDD = 5 V; VLCD = 0 V; Tamb = 25 °C  
Fig 19. ISS as a function of ffr  
Fig 20. −IDD(LCD) as a function of ffr  
PCA8576C  
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PCA8576C  
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Universal LCD driver for low multiplex rates  
mbe527  
mbe528  
50  
50  
I
SS  
−I  
DD(LCD)  
(μA)  
(μA)  
40  
40  
normal mode  
= 200 kHz  
f
85 °C  
clk  
30  
20  
30  
20  
25 °C  
−40 °C  
power-saving mode  
= 35 kHz  
10  
0
10  
0
f
clk  
0
5
10  
0
5
10  
V
DD  
(V)  
V
DD  
(V)  
VLCD = 0 V; external clock; Tamb = 25 °C  
VLCD = 0 V; external clock; Tamb = 25 °C  
Fig 21. ISS as a function of VDD  
Fig 22. −IDD(LCD) as a function of VDD  
10.2 Typical LCD output characteristics  
mbe532  
mbe526  
2.5  
10  
R
S
R
O(max)  
(kΩ)  
R
O(max)  
2.0  
(kΩ)  
R
S
1.5  
1.0  
R
BP  
1
R
BP  
0.5  
0
−1  
10  
0
3
6
−40  
0
40  
80  
120  
(°C)  
V
DD  
(V)  
T
amb  
VLCD = 0 V; Tamb = 25 °C  
VDD = 5 V; VLCD = 0 V  
Fig 23. RO(max) as a function of VDD  
Fig 24. RO(max) as a function of Tamb  
PCA8576C  
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PCA8576C  
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Universal LCD driver for low multiplex rates  
11. Dynamic characteristics  
Table 16. Dynamic characteristics  
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Timing characteristics: driver timing waveforms (see Figure 25)  
[1]  
fclk  
clock frequency  
normal-power mode;  
VDD = 5 V  
125  
21  
200  
31  
315  
48  
kHz  
kHz  
power-saving mode;  
VDD = 3 V  
tclk(H)  
tclk(L)  
clock HIGH time  
clock LOW time  
1
1
-
-
-
-
-
-
-
μs  
μs  
ns  
μs  
μs  
-
tPD(SYNC_N) SYNC propagation delay  
400  
-
tSYNC_NL  
SYNC LOW time  
1
-
tPD(drv)  
driver propagation delay  
VLCD = 5 V  
30  
[2]  
Timing characteristics: I2C-bus (see Figure 26)  
tBUF  
bus free time between a STOP and START  
condition  
4.7  
-
-
μs  
tHD;STA  
tSU;STA  
tLOW  
tHIGH  
tr  
hold time (repeated) START condition  
set-up time for a repeated START condition  
LOW period of the SCL clock  
HIGH period of the SCL clock  
rise time of both SDA and SCL signals  
fall time of both SDA and SCL signals  
capacitive load for each bus line  
data set-up time  
4.0  
4.7  
4.7  
4.0  
-
-
-
-
-
-
-
-
-
-
-
-
μs  
μs  
μs  
μs  
μs  
μs  
pF  
ns  
ns  
μs  
-
-
-
1
tf  
-
0.3  
Cb  
-
400  
tSU;DAT  
tHD;DAT  
tSU;STO  
250  
0
-
-
-
data hold time  
set-up time for STOP condition  
4.0  
[1] fclk < 125 kHz, I2C-bus maximum transmission speed is derated.  
[2] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an  
input voltage swing of VSS to VDD  
.
PCA8576C  
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PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
1/f  
CLK  
t
t
clk(L)  
clk(H)  
0.7V  
0.3V  
DD  
DD  
CLK  
0.7V  
0.3V  
DD  
DD  
SYNC  
t
t
PD(SYNC_N)  
PD(SYNC_N)  
t
SYNC_NL  
0.5 V  
(V = 5 V)  
BP0 to BP3,  
and S0 to S39  
DD  
0.5 V  
t
PD(drv)  
mce424  
Fig 25. Driver timing waveforms  
SDA  
t
t
t
f
BUF  
LOW  
SCL  
SDA  
t
HD;STA  
t
r
t
t
SU;DAT  
HD;DAT  
t
HIGH  
t
SU;STA  
t
SU;STO  
mga728  
Fig 26. I2C-bus timing waveforms  
PCA8576C  
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Universal LCD driver for low multiplex rates  
12. Application information  
12.1 Cascaded operation  
In large display configurations, up to 16 PCA8576Cs can be recognized on the same  
I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable  
I2C-bus slave address (SA0).  
Table 17. Addressing cascaded PCA8576C  
Cluster  
Bit SA0  
Pin A2  
Pin A1  
Pin A0  
Device  
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
2
1
8
9
10  
11  
12  
13  
14  
15  
Cascaded PCA8576Cs are synchronized. They can share the backplane signals from one  
of the devices in the cascade. Such an arrangement is cost-effective in large LCD  
applications since the backplane outputs of only one device need to be through-plated to  
the backplane electrodes of the display. The other PCA8576Cs of the cascade contribute  
additional segment outputs but their backplane outputs are left open-circuit (see  
Figure 27).  
PCA8576C  
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Product data sheet  
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33 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
V
V
LCD  
DD  
SDA  
40 segment drives  
SCL  
SYNC  
CLK  
LCD PANEL  
PCA8576C  
(up to 2560  
elements)  
BP0 to BP3  
(open-circuit)  
OSC  
A0 A1 A2 SAO V  
SS  
V
LCD  
V
t
DD  
r
≤
R
2C  
b
V
V
LCD  
DD  
40 segment drives  
SDA  
SCL  
HOST  
MICRO-  
PROCESSOR/  
MICRO-  
CONTROLLER  
PCA8576C  
SYNC  
4 backplanes  
BP0 to BP3  
CLK  
OSC  
013aaa277  
A0 A1 A2 SA0 V  
SS  
V
SS  
Fig 27. Cascaded PCA8576C configuration  
The SYNC line is provided to maintain the correct synchronization between all cascaded  
PCA8576Cs. This synchronization is guaranteed after the power-on reset. The only time  
that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in  
adverse electrical environments; or by the defining a multiplex mode when PCA8576Cs  
with differing SA0 levels are cascaded).  
SYNC is organized as an input/output pin; the output selection being realized as an  
open-drain driver with an internal pull-up resistor. A PCA8576C asserts the SYNC line and  
monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is  
restored by the first PCA8576C to assert SYNC. The timing relationship between the  
backplane waveforms and the SYNC signal for the various drive modes of the PCA8576C  
are shown in Figure 28.  
PCA8576C  
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Product data sheet  
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PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
1
T
=
fr  
f
fr  
BP0  
SYNC  
(a) static drive mode.  
BP0  
(1/2 bias)  
BP0  
(1/3 bias)  
SYNC  
(b) 1:2 multiplex drive mode.  
BP0  
(1/3 bias)  
SYNC  
(c) 1:3 multiplex drive mode.  
BP0  
(1/3 bias)  
SYNC  
(d) 1:4 multiplex drive mode.  
mgl755  
Excessive capacitive coupling between SCL or CLK and SYNC will cause erroneous  
synchronization. If this is a problem you can increase the capacitance of the SYNC line (e.g. by an  
external capacitor between SYNC and VDD.) Degradation of the positive edge of the SYNC pulse  
can be countered by an external pull-up resistor.  
Fig 28. Synchronization of the cascade for the various PCA8576C drive modes  
PCA8576C  
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Universal LCD driver for low multiplex rates  
13. Package outline  
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm  
SOT314-2  
y
X
A
48  
33  
Z
49  
32  
E
e
H
A
E
2
E
A
(A )  
3
A
1
w M  
p
θ
b
L
p
pin 1 index  
L
64  
17  
detail X  
1
16  
Z
v
M
A
D
e
w M  
b
p
D
B
H
v
M
B
D
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.  
7o  
0o  
0.20 1.45  
0.05 1.35  
0.27 0.18 10.1 10.1  
0.17 0.12 9.9 9.9  
12.15 12.15  
11.85 11.85  
0.75  
0.45  
1.45 1.45  
1.05 1.05  
1.6  
mm  
0.25  
0.5  
1
0.2 0.12 0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
00-01-19  
03-02-25  
SOT314-2  
136E10  
MS-026  
Fig 29. Package outline SOT314-2 (LQFP64) of PCA8576CH  
PCA8576C  
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PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
14. Handling information  
All input and output pins are protected against ElectroStatic Discharge (ESD) under  
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that  
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent  
standards.  
15. Soldering of SMD packages  
This text provides a very brief insight into a complex technology. A more in-depth account  
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow  
soldering description”.  
15.1 Introduction to soldering  
Soldering is one of the most common methods through which packages are attached to  
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both  
the mechanical and the electrical connection. There is no single soldering method that is  
ideal for all IC packages. Wave soldering is often preferred when through-hole and  
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not  
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high  
densities that come with increased miniaturization.  
15.2 Wave and reflow soldering  
Wave soldering is a joining technology in which the joints are made by solder coming from  
a standing wave of liquid solder. The wave soldering process is suitable for the following:  
• Through-hole components  
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board  
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless  
packages which have solder lands underneath the body, cannot be wave soldered. Also,  
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,  
due to an increased probability of bridging.  
The reflow soldering process involves applying solder paste to a board, followed by  
component placement and exposure to a temperature profile. Leaded packages,  
packages with solder balls, and leadless packages are all reflow solderable.  
Key characteristics in both wave and reflow soldering are:  
• Board specifications, including the board finish, solder masks and vias  
• Package footprints, including solder thieves and orientation  
• The moisture sensitivity level of the packages  
• Package placement  
• Inspection and repair  
• Lead-free soldering versus SnPb soldering  
PCA8576C  
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Product data sheet  
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PCA8576C  
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Universal LCD driver for low multiplex rates  
15.3 Wave soldering  
Key characteristics in wave soldering are:  
• Process issues, such as application of adhesive and flux, clinching of leads, board  
transport, the solder wave parameters, and the time during which components are  
exposed to the wave  
• Solder bath specifications, including temperature and impurities  
15.4 Reflow soldering  
Key characteristics in reflow soldering are:  
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to  
higher minimum peak temperatures (see Figure 30) than a SnPb process, thus  
reducing the process window  
• Solder paste printing issues including smearing, release, and adjusting the process  
window for a mix of large and small components on one board  
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is  
heated to the peak temperature) and cooling down. It is imperative that the peak  
temperature is high enough for the solder to make reliable solder joints (a solder paste  
characteristic). In addition, the peak temperature must be low enough that the  
packages and/or boards are not damaged. The peak temperature of the package  
depends on package thickness and volume and is classified in accordance with  
Table 18 and 19  
Table 18. SnPb eutectic process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (°C)  
Volume (mm3)  
< 350  
235  
≥ 350  
220  
< 2.5  
≥ 2.5  
220  
220  
Table 19. Lead-free process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (°C)  
Volume (mm3)  
< 350  
260  
350 to 2000  
> 2000  
260  
< 1.6  
260  
250  
245  
1.6 to 2.5  
> 2.5  
260  
245  
250  
245  
Moisture sensitivity precautions, as indicated on the packing, must be respected at all  
times.  
Studies have shown that small packages reach higher temperatures during reflow  
soldering, see Figure 30.  
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
38 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
maximum peak temperature  
= MSL limit, damage level  
temperature  
minimum peak temperature  
= minimum soldering temperature  
peak  
temperature  
time  
001aac844  
MSL: Moisture Sensitivity Level  
Fig 30. Temperature profiles for large and small components  
For further information on temperature profiles, refer to Application Note AN10365  
“Surface mount reflow soldering description”.  
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
39 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
16. Abbreviations  
Table 20. Abbreviations  
Acronym  
AEC  
CDM  
DC  
Description  
Automotive Electronics Council  
Charged-Device Model  
Direct Current  
HBM  
I2C  
Human Body Model  
Inter-Integrated Circuit  
Integrated Circuit  
IC  
LCD  
LSB  
MM  
Liquid Crystal Display  
Least Significant Bit  
Machine Model  
MOS  
MSB  
MSL  
PCB  
POR  
RC  
Metal-Oxide Semiconductor  
Most Significant Bit  
Moisture Sensitivity Level  
Printed-Circuit Board  
Power-On Reset  
Resistance-Capacitance  
Random Access Memory  
Root Mean Square  
RAM  
RMS  
SCL  
SDA  
SMD  
Serial Clock Line  
Serial DAta line  
Surface-Mount Device  
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
40 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
17. References  
[1] AN10365 — Surface mount reflow soldering description  
[2] IEC 60134 — Rating systems for electronic tubes and valves and analogous  
semiconductor devices  
[3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena  
[4] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for  
Nonhermetic Solid State Surface Mount Devices  
[5] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body  
Model (HBM)  
[6] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model  
(MM)  
[7] JESD22-C101 — Field-Induced Charged-Device Model Test Method for  
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components  
[8] JESD78 — IC Latch-Up Test  
[9] NX3-00092 — NXP store and transport requirements  
[10] SNV-FA-01-02 — Marking Formats Integrated Circuits  
[11] UM10204 — I2C-bus specification and user manual  
18. Revision history  
Table 21. Revision history  
Document ID  
Release date  
20100722  
Data sheet status  
Change notice  
Supersedes  
PCA8576C v.1  
Product data sheet  
-
-
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
41 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
19. Legal information  
19.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
suitable for use in medical, military, aircraft, space or life support equipment,  
19.2 Definitions  
nor in applications where failure or malfunction of an NXP Semiconductors  
product can reasonably be expected to result in personal injury, death or  
severe property or environmental damage. NXP Semiconductors accepts no  
liability for inclusion and/or use of NXP Semiconductors products in such  
equipment or applications and therefore such inclusion and/or use is at the  
customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
19.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Suitability for use in automotive applications — This NXP  
Semiconductors product has been qualified for use in automotive  
applications. The product is not designed, authorized or warranted to be  
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
42 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
19.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
I2C-bus — logo is a trademark of NXP B.V.  
20. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
PCA8576C  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2010. All rights reserved.  
Product data sheet  
Rev. 1 — 22 July 2010  
43 of 44  
PCA8576C  
NXP Semiconductors  
Universal LCD driver for low multiplex rates  
21. Contents  
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1  
8
9
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 26  
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 27  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
10  
10.1  
10.2  
Static characteristics . . . . . . . . . . . . . . . . . . . 28  
Typical supply current characteristics . . . . . . 29  
Typical LCD output characteristics. . . . . . . . . 30  
11  
Dynamic characteristics. . . . . . . . . . . . . . . . . 31  
Application information . . . . . . . . . . . . . . . . . 33  
Cascaded operation. . . . . . . . . . . . . . . . . . . . 33  
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 36  
Handling information . . . . . . . . . . . . . . . . . . . 37  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4  
12  
12.1  
13  
7
7.1  
7.2  
7.3  
Functional description . . . . . . . . . . . . . . . . . . . 5  
Power-On-Reset (POR) . . . . . . . . . . . . . . . . . . 6  
LCD bias generator . . . . . . . . . . . . . . . . . . . . . 6  
LCD voltage selector . . . . . . . . . . . . . . . . . . . . 7  
LCD drive mode waveforms . . . . . . . . . . . . . . . 9  
Static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9  
1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 10  
1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 12  
1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 13  
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 14  
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Display register. . . . . . . . . . . . . . . . . . . . . . . . 15  
Shift register . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 15  
Backplane outputs . . . . . . . . . . . . . . . . . . . . . 15  
Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Sub-address counter . . . . . . . . . . . . . . . . . . . 18  
Bank selector . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Output bank selector . . . . . . . . . . . . . . . . . . . 19  
Input bank selector . . . . . . . . . . . . . . . . . . . . . 19  
Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Characteristics of the I2C-bus. . . . . . . . . . . . . 20  
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
START and STOP conditions . . . . . . . . . . . . . 20  
System configuration . . . . . . . . . . . . . . . . . . . 21  
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 21  
PCA8576C I2C-bus controller. . . . . . . . . . . . . 22  
Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 22  
Command decoder. . . . . . . . . . . . . . . . . . . . . 23  
Mode-set command . . . . . . . . . . . . . . . . . . . . 24  
Load-data-pointer command. . . . . . . . . . . . . . 24  
Device-select command . . . . . . . . . . . . . . . . . 25  
Bank-select command . . . . . . . . . . . . . . . . . . 25  
Blink-select command . . . . . . . . . . . . . . . . . . 25  
Display controller . . . . . . . . . . . . . . . . . . . . . . 25  
14  
15  
Soldering of SMD packages. . . . . . . . . . . . . . 37  
Introduction to soldering. . . . . . . . . . . . . . . . . 37  
Wave and reflow soldering. . . . . . . . . . . . . . . 37  
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 38  
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 38  
15.1  
15.2  
15.3  
15.4  
7.4  
7.4.1  
7.4.2  
7.4.3  
7.4.4  
7.5  
7.5.1  
7.5.2  
7.6  
7.7  
7.8  
7.9  
7.10  
7.11  
7.12  
7.13  
7.14  
7.14.1  
7.14.2  
7.15  
7.16  
7.16.1  
7.16.2  
7.16.3  
7.16.4  
7.16.5  
7.16.6  
7.17  
7.18  
7.18.1  
7.18.2  
7.18.3  
7.18.4  
7.18.5  
7.19  
16  
17  
18  
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 40  
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Revision history . . . . . . . . . . . . . . . . . . . . . . . 41  
19  
Legal information . . . . . . . . . . . . . . . . . . . . . . 42  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 42  
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
19.1  
19.2  
19.3  
19.4  
20  
21  
Contact information . . . . . . . . . . . . . . . . . . . . 43  
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2010.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 22 July 2010  
Document identifier: PCA8576C  

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