PCA9306FMUTCG [NXP]
Dual Bidirectional I2C-bus and SMBus Voltage-Level Translator; 双路双向I2C总线和SMBus电压电平转换器
| 型号： | PCA9306FMUTCG |
| 厂家： | 
NXP |
| 描述： | Dual Bidirectional I2C-bus and SMBus Voltage-Level Translator |
| 文件： | 总12页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9306
Dual Bidirectional I2C-bus
and SMBus Voltage-Level
Translator
2
The PCA9306 is a dual bidirectional I C−bus and SMBus
voltage−level translator with an enable (EN) input.
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Features
MARKING
DIAGRAMS
• 2−bit Bidirectional Translator for SDA and SCL Lines in
2
Mixed−Mode I C−Bus Applications
8
2
• Standard−Mode, Fast−Mode, and Fast−Mode Plus I C−Bus and
AAF
YWW
AG
TSSOP−8
DT SUFFIX
CASE 948AL
SMBus Compatible
• Less Than 1.5 ns Maximum Propagation Delay to Accommodate
2
Standard−Mode and Fast−Mode I C−Bus Devices and Multiple
Masters
1
8
• Allows Voltage Level Translation Between:
♦ 1.0 V V
♦ 1.2 V V
♦ 1.8 V V
♦ 2.5 V V
♦ 3.3 V V
and 1.8 V, 2.5 V, 3.3 V or 5 V V
and 1.8 V, 2.5 V, 3.3 V or 5 V V
ref(1)
ref(1)
ref(1)
ref(1)
ref(1)
bias(ref)(2)
bias(ref)(2)
US8
US SUFFIX
CASE 493
AK MG
and 3.3 V or 5 V V
bias(ref)(2)
G
and 5 V V
bias(ref)(2)
and 5 V V
bias(ref)(2)
• Provides Bidirectional Voltage Translation With No Direction Pin
1
• Low 3.5 W ON−State Connection Between Input and Output Ports
Provides Less Signal Distortion
1
UQFN8
MU SUFFIX
CASE 523AN
2
• Open−Drain I C−Bus I/O Ports (SCL1, SDA1, SCL2 and SDA2)
AQ MG
8
1
2
• 5 V Tolerant I C−Bus I/O Ports to Support Mixed−Mode Signal
Operation
• High−Impedance SCL1, SDA1, SCL2 and SDA2 Pins for
EN = LOW
P M
1
UDFN8
1.45 x 1.0
CASE 517BZ
• Lock−Up Free Operation
• Flow Through Pinout for Ease of Printed−Circuit Board Trace
Routing
AAF, AK, AQ, P = Specific Device Code
• Packages Offered:
A
Y
= Assembly Location
= Year
♦ TSSOP−8, US8, UQFN8, UDFN8
• ESD Performance: 4000 V Human Body Model,
400 V Machine Model
WW
M
G
= Work Week
= Date Code
= Pb−Free Package
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
August, 2013 − Rev. 5
PCA9306/D
PCA9306
Function Description
The PCA9306 is a dual bidirectional I C−bus and SMBus
voltage−level translator with an enable (EN) input, and is
bus. The PCA9306 has a standard open−collector
configuration of the I C−bus. The size of these pull−up
2
2
resistors depends on the system, but each side of the
translator must have a pull−up resistor. The device is
designed to work with Standard−mode, Fast−mode and Fast
operational from 1.0 V to 3.6 V (V
) and 1.8 V to 5.5 V
ref(1)
(V
).
bias(ref)(2)
2
The PCA9306 allows bidirectional voltage translations
between 1.0 V and 5 V without the use of a direction pin. The
low ON−state resistance (R ) of the switch allows
mode Plus I C−bus devices in addition to SMBus devices.
The maximum frequency is dependent on the RC time
constant, but generally supports > 2 MHz.
on
connections to be made with minimal propagation delay.
When EN is HIGH, the translator switch is on, and the SCL1
and SDA1 I/O are connected to the SCL2 and SDA2 I/O,
respectively, allowing bidirectional data flow between
ports. When EN is LOW, the translator switch is off, and a
high−impedance state exists between ports.
When the SDA1 or SDA2 port is LOW, the clamp is in the
ON−state and a low resistance connection exists between the
SDA1 and SDA2 ports. Assuming the higher voltage is on
the SDA2 port, when the SDA2 port is HIGH, the voltage on
the SDA1 port is limited to the voltage set by VREF1. When
the SDA1 port is HIGH, the SDA2 port is pulled to the drain
The PCA9306 is not a bus buffer that provides both level
translation and physical capacitance isolation to either side
of the bus when both sides are connected. The PCA9306
only isolates both sides when the device is disabled and
provides voltage level translation when active.
pull−up supply voltage (V
) by the pull−up resistors.
pu(D)
This functionality allows a seamless translation between
higher and lower voltages selected by the user without the
need for directional control. The SCL1/SCL2 channel also
functions as the SDA1/SDA2 channel.
The PCA9306 can be used to run two buses, one at
400 kHz operating frequency and the other at 100 kHz
operating frequency. If the two buses are operating at
different frequencies, the 100 kHz bus must be isolated
when the 400 kHz operation of the other bus is required. If
the master is running at 400 kHz, the maximum system
operating frequency may be less than 400 kHz because of
the delays added by the translator.
All channels have the same electrical characteristics and
there is minimal deviation from one output to another in
voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication
of the switch is symmetrical. The translator provides
excellent ESD protection to lower voltage devices, and at the
same time protects less ESD−resistant devices.
2
As with the standard I C−bus system, pull−up resistors are
required to provide the logic HIGH levels on the translator’s
FUNCTIONAL DIAGRAM
Figure 1. Logic Diagram
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2
PCA9306
PIN ASSIGNMENTS
Figure 2. TSSOP−8 / US8 Pinouts
Figure 3. UQFN8 Pinout (Top Thru View)
Figure 4. UDFN8 Pinout (Top Thru View)
Table 1. PIN DESCRIPTION
Pin
GND
Description
Ground
VREF1
SCL1
SDA1
SDA2
SCL2
VREF2
EN
Low−voltage side reference supply voltage for SCL1 and SDA1
Serial clock, low−voltage side; connect to VREF1 through a pull−up resistor
Serial data, low−voltage side; connect to VREF1 through a pull−up resistor
Serial data, high−voltage side; connect to VREF2 through a pull−up resistor
Serial clock, high−voltage side; connect to VREF2 through a pull−up resistor
High−voltage side reference supply voltage for SCL2 and SDA2
Switch enable input; connect to VREF2 and pull−up through a high resistor
Table 2. FUNCTION TABLE
Input EN (Note 1)
Function
Low
Disconnect
High
SCL1 = SCL2; SDA1 = SDA2
1. EN is controlled by the V
logic levels and should be at least 1 V higher than V
for best translator operation.
bias(ref)(2)
ref(1)
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3
PCA9306
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Value
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
128
Unit
V
V
Reference Voltage (Note 2)
Reference Bias Voltage (Note 3)
Input Voltage
ref(1)
bias(ref)(2)
V
V
V
V
IN
I/O
CH
V
Input / Output Pin Voltage
DC Channel Current
V
I
mA
mA
°C
I
IK
DC Input Diode Current V < GND
−50
IN
T
STG
Storage Temperature Range
−65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance (Note 2)
T = 260
°C
L
L
T
T = 150
J
°C
J
q
q
= 150
= 833
°C/W
mW
JA
JA
P
D
Power Dissipation in Still Air at 85°C
Moisture Sensitivity
P
D
MSL
Level 1
F
R
Flammability Rating Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage Human Body Mode (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
> 4000
> 400
N/A
V
I
Latchup Performance Above V and Below GND at 125 °C (Note 6)
100
mA
LATCHUP
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
3. Tested to EIA / JESD22−A114−A.
4. Tested to EIA / JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA / JESD78.
Table 4. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
0
Max
5.5
Unit
V
V
Reference Voltage (1) (Note 7)
VREF1
VREF2
ref(1)
bias(ref)(2)
V
Reference Bias Voltage (2) (Note 7)
0
5.5
V
V
Input / Output Pin Voltage SCL1, SDA1, SCL2, SDA2
Control Pin Input Voltage EN
0
5.5
V
I/O
V
I(EN)
0
5.5
V
I
Pass Switch Current
0
64
mA
°C
sw(pass)
T
A
Operating Free−Air Temperature
−55
+125
7. V
≤ V
−1 V for best results in level shifting applications.
(ref)(1)
bias(ref)(2)
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4
PCA9306
Table 5. DC ELECTRICAL CHARACTERISTICS
T
A
= −555C to +1255C
Typ
(Note 8)
Min
Max
−1.2
5
Symbol
Parameter
Input Clamping Voltage
Conditions
I = −18 mA; V = 0 V
Unit
V
V
IK
I
I(EN)
I
IH
High−Level Input Current
V = 5 V; V
= 0 V
mA
pF
pF
I
I(EN)
C
EN Pin Input Capacitance
V = 3 V or 0 V
I
7.1
4
i(EN)
C
OFF−State I/O Pin Capacitance
SCLn, SDAn
V
O
= 3 V or 0 V; V = 0 V
I(EN)
6
i/O(off)
C
ON−State I/O Pin Capacitance
SCLn, SDAn
V
V
= 3 V or 0 V;
I(EN)
pF
i/O(on)
O
= 3 V
9.3
12.5
(2)(3)
R
ON−State Resistance
SCLn, SDAn
V = 0 V; I = 64 mA
W
ON
I
O
V
I(EN)
V
I(EN)
V
I(EN)
V
I(EN)
= 4.5 V
2.4
3.0
3.8
9.0
5.0
6.0
8.0
20
= 3 V
= 2.3 V
= 1.5 V
V = 2.4 V; I = 15 mA
I
O
V
I(EN)
V
I(EN)
= 4.5 V
4.8
46
7.5
80
= 3 V
V = 1.7 V; I = 15 mA
I(EN)
I
O
V
= 2.3 V
40
80
8. All typical values are at T = 25°C.
A
9. Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals at the indicated current through the switch.
ON−state resistance is determined by the lowest voltage of the two terminals.
10.Guaranteed by design.
Table 6. AC ELECTRICAL CHARACTERISTICS (Translating Down) − Values Guaranteed by Design
T
= −555C to +1255C
A
Load
Condition
Min
Max
Symbol
Parameter
Test Condition
Unit
SEE FIGURE 4 LOAD SWITCH AT S2 POSITION
t
t
t
t
Low−to−High Propagation
Delay, from (input) SCL2 or
SDA2 to (output) SCL1 or
SDA1
V
V
= 3.3 V; V = 3.3 V;
C = 15 pF
0
0
0
0
0
0
0
0
0
0
0
0
0.6
1.2
2.0
0.75
1.5
2.0
0.6
1.2
2.0
0.75
1.5
2.5
ns
PLH
PHL
PLH
PHL
I(EN)
IL
IH
L
= 0 V; V = 1.15 V
M
C = 30 pF
L
C = 50 pF
L
High−to−Low Propagation
Delay, from (input) SCL2 or
SDA2 to (output) SCL1 or
SDA1
C = 15 pF
L
C = 30 pF
L
C = 50 pF
L
Low−to−High Propagation
Delay, from (input) SCL2 or
SDA2 to (output) SCL1 or
SDA1
V
V
= 2.5 V; V = 2.5 V;
C = 15 pF
L
ns
I(EN)
IL
IH
= 0 V; V = 0.75 V
M
C = 30 pF
L
C = 50 pF
L
High−to−Low Propagation
Delay, from (input) SCL2 or
SDA2 to (output) SCL1 or
SDA1
C = 15 pF
L
C = 30 pF
L
C = 50 pF
L
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5
PCA9306
Table 7. AC ELECTRICAL CHARACTERISTICS (Translating Up) − Values Guaranteed by Design
T
A
=
−555C to +1255C
Min
Max
Symbol
Parameter
Test Condition
Load Condition
Unit
SEE FIGURE 4 LOAD SWITCH AT S1 POSITION
t
t
t
t
Low−to−High Propagation
Delay, from (input) SCL1 or
SDA1 to (output) SCL2 or
SDA2
V
V
V
= 3.3 V; V = 2.3 V;
TT
= 1.15 V
0
0
0
0
0
0
0
0
0
0
0
0
0.5
1.0
ns
R = 300 W, C = 15 pF
PLH
PHL
PLH
PHL
I(EN)
IL
M
IH
L
L
= 0 V; V = 3.3 V;
R = 300 W, C = 30 pF
L
L
R = 300 W, C = 50 pF
1.75
0.8
L
L
High−to−Low Propagation
Delay, from (input) SCL1 or
SDA1 to (output) SCL2 or
SDA2
R = 300 W, C = 15 pF
L
L
R = 300 W, C = 30 pF
1.65
2.75
0.5
L
L
R = 300 W, C = 50 pF
L
L
Low−to−High Propagation
Delay, from (input) SCL1 or
SDA1 to (output) SCL2 or
SDA2
V
V
V
= 2.5 V; V = 1.5 V;
ns
R = 300 W, C = 15 pF
I(EN)
IL
M
IH
L
L
= 0 V; V = 2.5 V;
TT
R = 300 W, C = 30 pF
1.0
L
L
= 0.75 V
R = 300 W, C = 50 pF
1.75
1.0
L
L
High−to−Low Propagation
Delay, from (input) SCL1 or
SDA1 to (output) SCL2 or
SDA2
R = 300 W, C = 15 pF
L
L
R = 300 W, C = 30 pF
2.0
L
L
R = 300 W, C = 50 pF
3.3
L
L
V
IH
V
TT
input
V
V
M
M
M
V
V
V
IL
R
L
OH
OL
from output under test
S1
S2 (open)
output
V
V
M
C
L
A. Load Circuit
B. Timing Diagram
S1 = translating up; S2 = translating down.
C includes probe and jig capacitance.
L
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Z = 50 W; t ≤ 2 ns; t ≤ 2 ns.
o
r
f
The outputs are measured one at a time, with one transition per measurement.
Figure 5. Load Circuit for Outputs
ORDERING INFORMATION
Device
†
Package
Shipping
PCA9306DTR2G
TSSOP−8
(Pb−Free)
4000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
PCA9306AMUTCG
PCA9306FMUTCG
UQFN−8
(Pb−Free)
UDFN8
(Pb−Free)
PCA9306USG
NLV9306USG*
US8
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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6
PCA9306
APPLICATION INFORMATION
V
PU(D)
= 3.3 V
(Note 1)
200 kW
V
= 1.8 V
(Note 1)
REF(1)
PCA9306
EN
8
R
PU
R
PU
VREF1
VREF2
2
7
R
PU
R
PU
V
V
CC
CC
SCL1
3
4
6
5
SCL2
SDA2
SCL
SW
SCL
2
2
I C−Bus
MASTER
I C−Bus
DEVICE
SDA1
SDA
SDA
SW
1
GND
GND
GND
1. The applied voltages at V
operation.
and V
should be such that V
is at least 1 V higher than V
for best translator
ref(1)
pu(D)
bias(ref)(2)
ref(1)
Figure 6. Typical Application (Switch Always Enabled)
V
PU(D)
= 3.3 V
3.3 V Enable Signal (Note 2)
OFF ON
200 kW
V
= 1.8 V
(Note 2)
REF(1)
PCA9306
EN
8
R
PU
R
PU
VREF1
VREF2
2
7
R
PU
R
PU
V
V
CC
CC
SCL1
3
4
6
5
SCL2
SDA2
SCL
SW
SCL
2
2
I C−Bus
MASTER
I C−Bus
DEVICE
SDA1
SDA
SDA
SW
1
GND
GND
GND
2. In the Enabled mode, the applied enable voltage and the applied voltage at V
should be such that V
is at least 1 V
ref(1)
bias(ref)(2)
higher than V
for best translator operation.
ref(1)
Figure 7. Typical Application (Switch Enable Control)
Bidirectional Translation
unidirectional or the outputs must be 3−stateable and be
controlled by some direction−control mechanism to prevent
HIGH−to−LOW contentions in either direction. If both
outputs are open−drain, no direction control is needed.
For the bidirectional clamping configuration (higher
voltage to lower voltage or lower voltage to higher voltage),
the EN input must be connected to VREF2 and both pins
pulled to HIGH side V
through a pull−up resistor
The reference supply voltage (V ) is connected to the
ref(1)
pu(D)
(typically 200 kW). This allows VREF2 to regulate the EN
processor core power supply voltage. When VREF2 is
connected through a 200 kW resistor to a 3.3 V to 5.5 V
input. A filter capacitor on VREF2 is recommended. The
2
I C−bus master output can be totem−pole or open−drain
V
pu(D)
power supply, and V
is set between 1.0 V and
ref(1)
2
(pull−up resistors may be required) and the I C−bus device
(V
− 1 V), the output of each SCL1 and SDA1 has a
pu(D)
output can be totem−pole or open−drain (pull−up resistors
are required to pull the SCL2 and SDA2 outputs to Vpu(D)).
However, if either output is totem−pole, data must be
maximum output voltage equal to VREF1, and the output of
each SCL2 and SDA2 has a maximum output voltage equal
to V
.
pu(D)
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7
PCA9306
Table 8. APPLICATION OPERATING CONDITIONS Refer to Figure 6.
(1)
Symbol
Parameter
Conditions
Min
Typ
Max
5
Unit
V
V
Reference Bias Voltage (2)
EN Pin Input Voltage
Reference Voltage (1)
Pass Switch Current
Reference Current
V
V
+ 0.6
2.1
2.1
1.5
14
5
bias(ref)(2)
ref(1)
ref(1)
V
I(EN)
+ 0.6
5
V
V
ref(1)
0
4.4
V
I
mA
mA
°C
sw(pass)
I
ref
Transistor
Operating in free−air
T
amb
Ambient Temperature
−55
+125
11. All typical values are at T
= 25 °C.
amb
Sizing Pull−up Resistor
The following table summarizes resistor reference
voltages and currents at 15 mA, 10 mA, and 3 mA. The
resistor values shown in the +10% column or a larger value
should be used to ensure that the pass voltage of the
transistor would be 350 mV or less. The external driver must
be able to sink the total current from the resistors on both
sides of the PCA9306 device at 0.175 V, although the 15 mA
only applies to current flowing through the PCA9306
device.
The pull−up resistor value needs to limit the current
through the pass transistor when it is in the ON state to about
15 mA. This ensures a pass voltage of 260 mV to 350 mV.
If the current through the pass transistor is higher than
15 mA, the pass voltage also is higher in the ON state. To set
the current through each pass transistor at 15 mA, the
pull−up resistor value is calculated as:
V
PU(D) * 0.35 V
(eq. 1)
RPU
+
0.015 A
Table 9. PULLUP RESISTOR VALUES Calculated for V = 0.35 V; assumes output driver V = 0.175 V at stated current.
OL
OL
Pullup Resistor Value (W)
15 mA
+10% (Note 12)
10 mA
3 mA
+10% (Note 12)
(1)
Nominal
310
197
143
97
Nominal
465
+10%
Nominal
1550
983
V
pu(D)
5 V
341
217
158
106
85
512
325
237
160
127
94
1705
1082
788
3.3 V
2.5 V
1.8 V
1.5 V
1.2 V
295
215
717
145
483
532
77
115
383
422
57
63
85
283
312
12.+10% to compensate for V range and resistor tolerance.
CC
Maximum Frequency Calculation
resistor is needed on the 3.3 V side. The capacitance and line
length of concern is on the 1.8 V side since it is driven
through the ON resistance of the PCA9306. If the line length
on the 1.8 V side is long enough there can be a reflection at
the chip/terminating end of the wire when the transition time
is shorter than the time of flight of the wire because the
PCA9306 looks like a high−impedance compared to the
wire. If the wire is not too long and the lumped capacitance
is not excessive the signal will only be slightly degraded by
the series resistance added by passing through the PCA9306.
If the lumped capacitance is large the rise time will
deteriorate, the fall time is much less affected and if the rise
time is slowed down too much the duty cycle of the clock
will be degraded and at some point the clock will no longer
be useful. So the principle design consideration is to
minimize the wire length and the capacitance on the 1.8 V
side for the clock path. A pull−up resistor on the 1.8 V side
can also be used to trade a slower fall time for a faster rise
time and can also reduce the overshoot in some cases.
The maximum frequency is totally dependent upon the
specifics of the application and the device can operate >
33 MHz. Basically, the PCA9306 behaves like a wire with
the additional characteristics of transistor device physics
and should be capable of performing at higher frequencies
if used correctly.
Here are some guidelines to follow that will help
maximize the performance of the device:
• Keep trace length to a minimum by placing the
PCA9306 close to the processor.
• The trace length should be less than half the time of
flight to reduce ringing and reflections.
• The faster the edge of the signal, the higher the chance
for ringing.
• The higher the drive strength (up to 15 mA), the higher
the frequency the device can use.
In a 3.3 V to 1.8 V direction level shift, if the 3.3 V side
is being driven by a totem pole type driver no pull−up
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8
PCA9306
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL
ISSUE O
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
L
L1
0.50
0.60
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
http://onsemi.com
9
PCA9306
PACKAGE DIMENSIONS
US8
CASE 493−02
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURR.
MOLD FLASH. PROTRUSION AND GATE
BURR SHALL NOT EXCEED 0.140 MM
(0.0055”) PER SIDE.
−X−
A
J
8
5
−Y−
4. DIMENSION “B” DOES NOT INCLUDE
INTER−LEAD FLASH OR PROTRUSION.
INTER−LEAD FLASH AND PROTRUSION
SHALL NOT E3XCEED 0.140 (0.0055”) PER
SIDE.
5. LEAD FINISH IS SOLDER PLATING WITH
THICKNESS OF 0.0076−0.0203 MM.
(300−800 “).
DETAIL E
B
L
6. ALL TOLERANCE UNLESS OTHERWISE
SPECIFIED 0.0508 (0.0002 “).
1
4
R
MILLIMETERS
INCHES
S
DIM
A
B
C
D
F
G
H
J
K
L
M
N
P
MIN
1.90
2.20
0.60
0.17
0.20
MAX
2.10
2.40
0.90
0.25
0.35
MIN
MAX
0.083
0.094
0.035
0.010
0.014
G
P
0.075
0.087
0.024
0.007
0.008
U
C
0.50 BSC
0.40 REF
0.020 BSC
0.016 REF
H
−T−
0.10 (0.004)
T
K
0.10
0.18
0.10
3.20
6
0.004
0.007
0.004
0.126
6
SEATING
D
N
0.00
3.00
0
0.000
0.118
0
PLANE
M
R 0.10 TYP
M
0.10 (0.004)
T
X Y
_
_
_
_
5
10
5
10
_
_
_
_
0.23
0.23
0.37
0.60
0.34
0.33
0.47
0.80
0.010
0.009
0.015
0.024
0.013
0.013
0.019
0.031
V
R
S
U
V
0.12 BSC
0.005 BSC
F
DETAIL E
SOLDERING FOOTPRINT*
3.8
0.15
1.8
0.07
0.50
0.0197
0.30
0.012
1.0
0.0394
mm
inches
ǒ
Ǔ
SCALE 8:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
10
PCA9306
PACKAGE DIMENSIONS
UQFN8, 1.6x1.6, 0.5P
CASE 523AN
ISSUE O
NOTES:
A
B
D
MOLD CMPD
EXPOSED Cu
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
PIN ONE
A3
REFERENCE
E
2X
MILLIMETERS
A1
0.10
C
DETAIL B
DIM MIN
0.45
A1 0.00
MAX
0.60
0.05
OPTIONAL
A
2X
CONSTRUCTION
0.10
C
A3
b
D
0.13 REF
0.15
0.25
TOP VIEW
1.60 BSC
L1
L3
E
e
1.60 BSC
0.50 BSC
A
(A3)
DETAIL B
L
L1
0.35
−−−
0.45
0.15
0.05
C
C
L3 0.25
0.35
b
(0.15)
0.05
(0.10)
SIDE VIEW
SEATING
PLANE
DETAIL A
SOLDERING FOOTPRINT*
C
A1
OPTIONAL
CONSTRUCTION
1.70
0.50
PITCH
8X
L3
1
8X L
e
5
3
1
0.35
1.70
7
8
DETAIL A
8X b
0.10 C A B
7X
0.25
8X
0.53
NOTE 3
C
0.05
BOTTOM VIEW
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
11
PCA9306
PACKAGE DIMENSIONS
UDFN8, 1.45x1, 0.35P
CASE 517BZ
ISSUE O
NOTES:
A B
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. PACKAGE DIMENSIONS EXCLUSIVE OF
BURRS AND MOLD FLASH.
PIN ONE
REFERENCE
E
2X
0.10
C
MILLIMETERS
DIM MIN
MAX
0.55
0.05
A
A1
A3
b
0.45
0.00
0.13 REF
2X
0.10
C
TOP VIEW
SIDE VIEW
0.15
0.25
A3
0.05
C
C
D
1.45 BSC
E
e
1.00 BSC
0.35 BSC
A
L
L1
0.25
0.30
0.35
0.40
0.05
A1
SEATING
PLANE
C
RECOMMENDED
e/2
SOLDERING FOOTPRINT*
7X
e
7X L
8X
0.48
0.22
4
1
8
L1
1.18
5
8X b
1
M
0.10
C A B
0.53
0.35
M
NOTE 3
0.05
C
PKG
PITCH
BOTTOM VIEW
OUTLINE
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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