PCF2127AT/2 [NXP]
IC REAL TIME CLOCK, Timer or RTC;
| 型号： | PCF2127AT/2 |
| 厂家： | 
NXP |
| 描述： | IC REAL TIME CLOCK, Timer or RTC 时钟 光电二极管 外围集成电路 |
| 文件： | 总86页 (文件大小：1156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCF2127AT
Integrated RTC, TCXO and quartz crystal
Rev. 6 — 11 July 2013
Product data sheet
1. General description
The PCF2127AT1 is a CMOS2 Real Time Clock (RTC) and calendar with an integrated
Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz
crystal optimized for very high accuracy and very low power consumption. The
PCF2127AT has 512 bytes of general purpose static RAM, a selectable I2C-bus or
SPI-bus, a backup battery switch-over circuit, a programmable watchdog function, a
timestamp function, and many other features.
2. Features and benefits
Temperature Compensated Crystal Oscillator (TCXO) with integrated capacitors
Typical accuracy: 3 ppm from 15 C to +60 C
Integration of a 32.768 kHz quartz crystal and oscillator in the same package
Provides year, month, day, weekday, hours, minutes, seconds, and leap year
correction
512 bytes of general purpose static RAM
Timestamp function
with interrupt capability
detection of two different events on one multilevel input pin (for example, for tamper
detection)
Two line bidirectional 400 kHz Fast-mode I2C-bus interface (IOL = 3 mA at pin
SDA/CE)
3 line SPI-bus with separate data input and output (maximum speed 6.5 Mbit/s)
Battery backup input pin and switch-over circuitry
Battery backed output voltage
Battery low detection function
Extra power fail detection function with input and output pins
Power-On Reset Override (PORO)
Oscillator stop detection function
Interrupt output and system reset pin (open-drain)
Programmable 1 second or 1 minute interrupt
Programmable countdown timer with interrupt capability
Programmable watchdog timer with interrupt and reset capability
Programmable alarm function with interrupt capability
Programmable square wave open-drain output pin
1. As well as the PCF2129.
2. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 20.
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
Clock operating voltage: 1.2 V to 4.2 V
Low supply current: typical 0.65 A at VDD = 3.0 V and Tamb = 25 C
3. Applications
Electronic metering for electricity, water, and gas
Precision timekeeping
Access to accurate time of the day
GPS equipment to reduce time to first fix
Applications that require an accurate process timing
Products with long automated unattended operation time
4. Ordering information
Table 1.
Ordering information
Type number Package
Name
Description
Version
PCF2127AT
SO20
plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
4.1 Ordering options
Table 2.
Ordering options
Product type number
IC
Sales item (12NC)
Delivery form
revision
PCF2127AT/1[1]
1
935290953512
935290953518
935299867518
tube, dry pack
tape and reel, 13 inch, dry pack
tape and reel, 13 inch, dry pack
PCF2127AT/2
2
[1] Not to be used for new designs. Replacement part is PCF2127AT/2.
5. Marking
Table 3.
Marking codes
Product type number
PCF2127AT/1
Marking code
PCF2127AT
PCF2127AT
PCF2127AT/2
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
2 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
6. Block diagram
INT
TCXO
TEMP
OSCI
Control_1
Control_2
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
DIVIDER
AND
TIMER
32.768 kHz
OSCO
Control_3
CLKOUT
BBS
Seconds
Minutes
internal
power
supply
Hours
1 Hz
V
DD
Days
BATTERY BACK UP
SWITCH-OVER
CIRCUITRY
V
BAT
Weekdays
LOGIC
CONTROL
V
SS
Months
Years
OSCILLATOR
MONITOR
RESET
Second_alarm
Minute_alarm
Hour_alarm
Day_alarm
RST
SPI-BUS
INTERFACE
ADDRESS
REGISTER
Weekday_alarm
CLKOUT_ctl
Watchdg_tim_ctl
Watchdg_tim_val
Timestp_ctl
Sec_timestp
Min_timestp
Hour_timestp
Day_timestp
Mon_timestp
Year_timestp
Aging_offset
RAM_addr_MSB
RAM_addr_LSB
RAM_wrt_cmd
RAM_rd_cmd
SDA/CE
SDO
SERIAL BUS
INTERFACE
SELECTOR
SDI
SCL
IFS
PCF2127AT
2
I C-BUS
INTERFACE
R
PU
TS
SCL
SDO
512 BYTES
STATIC RAM
SDI
SDA/CE
TEMPERATURE
SENSOR
PFI
TEMP
1.25 V
(internal)
PFO
TEST
001aaj675
Fig 1. Block diagram of PCF2127AT
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
3 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
7. Pinning information
7.1 Pinning
1
2
20
19
18
17
16
15
14
13
12
11
SCL
SDI
V
V
DD
BAT
3
SDO
BBS
INT
4
SDA/CE
IFS
5
RST
PFI
PCF2127AT
6
TS
7
CLKOUT
PFO
TEST
n.c.
8
V
SS
9
n.c.
n.c.
10
n.c.
001aaj676
Top view. For mechanical details, see Figure 53.
Fig 2. Pin configuration for SO20 (PCF2127AT)
7.2 Pin description
Table 4.
Pin description of SO20 (PCF2127AT)
Symbol
SCL
Pin
1
Description
combined serial clock input for both I2C-bus and SPI-bus
SDI
2
serial data input for SPI-bus;
connect to pin VSS if I2C-bus is selected
serial data output for SPI-bus, push-pull
combined serial data input and output for the I2C-bus and chip
enable input (active LOW) for the SPI-bus
SDO
3
4
SDA/CE
IFS
5
interface selector input
connect to pin VSS to select the SPI-bus
connect to pin BBS to select the I2C-bus
timestamp input (active LOW) with 200 k internal pull-up resistor
TS
6
(RPU
)
CLKOUT
VSS
7
clock output (open-drain)
8
ground supply voltage
n.c.
9 to 12
13
14
15
16
17
not connected; do not connect; do not use as feed through
do not connect; do not use as feed through
power fail output (open-drain; active LOW)
power fail input
TEST
PFO
PFI
RST
INT
reset output (open-drain; active LOW)
interrupt output (open-drain; active LOW)
PCF2127AT
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
4 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
Table 4.
Pin description of SO20 (PCF2127AT) …continued
Symbol
BBS
Pin
18
Description
output voltage (battery backed)
battery supply voltage (backup)
connect to VSS if battery switch over is not used
supply voltage
VBAT
19
VDD
20
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
5 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8. Functional description
The PCF2127AT is a Real Time Clock (RTC) and calendar with an on-chip Temperature
Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal integrated
into the same package (see Section 8.3.2).
Address and data are transferred by a selectable 400 kHz Fast-mode I2C-bus or a 3 line
SPI-bus with separate data input and output (see Section 9). The maximum speed of the
SPI-bus is 6.5 Mbit/s.
The PCF2127AT has a backup battery input pin and backup battery switch-over circuit
which monitors the main power supply. The backup battery switch-over circuit
automatically switches to the backup battery when a power failure condition is detected
(see Section 8.6.1). Accurate timekeeping is maintained even when the main power
supply is interrupted.
A battery low detection circuit monitors the status of the battery (see Section 8.6.3). When
the battery voltage drops below a certain threshold value, a flag is set to indicate that the
battery must be replaced soon. This ensures the integrity of the data during periods of
battery backup.
8.1 Register overview
The PCF2127AT contains an auto-incrementing address register: the built-in address
register will increment automatically after each read or write of a data byte up to the
register 1Bh. After register 1Bh, the auto-incrementing will wrap around to address 00h
(see Figure 3).
address register
00h
01h
02h
03h
...
auto-increment
19h
1Ah
1Bh
1Ch
1Dh
wrap around
not reachable by auto-inc. - needs to be addressed directly
not reachable by auto-inc. - needs to be addressed directly
001aaj307
Fig 3. Handling address registers
• The first three registers (memory address 00h, 01h, and 02h) are used as control
registers (see Section 8.2).
• The registers at addresses 03h through to 09h are used as counters for the clock
function (seconds up to years). The date is automatically adjusted for months with
fewer than 31 days, including corrections for leap years. The clock can operate in
12-hour mode with an AM/PM indication or in 24-hour mode (see Section 8.9).
• The registers at addresses 0Ah through 0Eh define the alarm function. It can be
selected that an interrupt is generated when an alarm event occurs (see
Section 8.10).
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
6 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
• The register at address 0Fh defines the temperature measurement period and the
clock out mode. The temperature measurement can be selected from every 4 minutes
(default) down to every 30 seconds (see Table 10). CLKOUT frequencies of
32.768 kHz (default) down to 1 Hz for use as system clock, microcontroller clock, and
so on, can be chosen (see Table 11).
• The registers at addresses 10h and 11h are used for the watchdog and countdown
timer functions. The watchdog timer has four selectable source clocks allowing for
timer periods from less than 1 ms to greater than 4 hours (see Table 37). Either the
watchdog timer or the countdown timer can be enabled (see Section 8.11). For the
watchdog timer, it is possible to select whether an interrupt or a pulse on the reset pin
will be generated when the watchdog times out. For the countdown timer, it is only
possible that an interrupt will be generated at the end of the countdown.
• The registers at addresses 12h to 18h are used for the timestamp function. When the
trigger event happens, the actual time is saved in the timestamp registers (see
Section 8.12).
• The register at address 19h is used for the correction of the crystal aging effect (see
Section 8.4.1).
• The registers at addresses 1Ah and 1Bh define the RAM address. The register at
address 1Ch (RAM_wrt_cmd) is the RAM write command; the register at 1Dh
(RAM_rd_cmd) is the RAM read command. Data is transferred to or from the RAM by
the serial interface (see Section 8.5).
• The registers Seconds, Minutes, Hours, Days, Months, and Years are all coded in
Binary Coded Decimal (BCD) format to simplify application use. Other registers are
either bit-wise or standard binary.
When one of the RTC registers is written or read, the content of all counters is temporarily
frozen. This prevents a faulty writing or reading of the clock and calendar during a carry
condition (see Section 8.9.8).
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
7 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
Table 5.
Register overview
Bit positions labeled as - are not implemented and will return a 0 when read. Bit T must always be written with logic 0. Bits
labeled as X are undefined at power-on and unchanged by subsequent resets.
Address Register name
Bit
7
Reset value
6
5
4
3
2
1
0
Control registers
00h
Control_1
EXT_
TEST
T
STOP
TSF1
POR_
OVRD
12_24
MI
SI
0000 0000
01h
02h
Control_2
Control_3
MSF
WDTF TSF2
AF
CDTF
BF
TSIE
BLF
AIE
BIE
CDTIE 0000 0000
PWRMNG[2:0]
BTSE
BLIE
0000 0000
Time and date registers
03h
04h
05h
Seconds
Minutes
Hours
OSF
-
SECONDS (0 to 59)
MINUTES (0 to 59)
1XXX XXXX
- XXX XXXX
- - XX XXXX
- - XX XXXX
- - XX XXXX
- - - - - XXX
- - - X XXXX
XXXX XXXX
-
-
AMPM HOURS (1 to 12) in 12 h mode
HOURS (0 to 23) in 24 h mode
DAYS (1 to 31)
06h
07h
08h
09h
Days
-
-
-
-
-
-
Weekdays
Months
Years
-
-
-
-
WEEKDAYS (0 to 6)
MONTHS (1 to 12)
YEARS (0 to 99)
Alarm registers
0Ah
0Bh
0Ch
Second_alarm
AE_S
AE_M
AE_H
SECOND_ALARM (0 to 59)
MINUTE_ALARM (0 to 59)
1XXX XXXX
1XXX XXXX
1 - XX XXXX
1 - XX XXXX
1 - XX XXXX
Minute_alarm
Hour_alarm
-
-
-
-
AMPM HOUR_ALARM (1 to 12) in 12 h mode
HOUR_ALARM (0 to 23) in 24 h mode
DAY_ALARM (1 to 31)
0Dh
0Eh
Day_alarm
AE_D
Weekday_alarm AE_W
-
-
-
-
-
-
-
WEEKDAY_ALARM (0 to 6) 1 - - - - XXX
CLKOUT control register
0Fh CLKOUT_ctl
Watchdog registers
TCR[1:0]
-
COF[2:0]
-
00 - - - 000
10h
11h
Watchdg_tim_ctl WD_CD[1:0]
TI_TP
TF[1:0]
000 - - - 11
Watchdg_tim_val WATCHDG_TIM_VAL[7:0]
XXXX XXXX
Timestamp registers
12h
13h
14h
15h
Timestp_ctl
Sec_timestp
Min_timestp
Hour_timestp
TSM
TSOFF
-
1_O_16_TIMESTP[4:0]
00 - X XXXX
- XXX XXXX
- XXX XXXX
- - XX XXXX
- - XX XXXX
- - XX XXXX
- - - X XXXX
XXXX XXXX
-
-
-
SECOND_TIMESTP (0 to 59)
MINUTE_TIMESTP (0 to 59)
-
AMPM HOUR_TIMESTP (1 to 12) in 12 h mode
HOUR_TIMESTP (0 to 23) in 24 h mode
DAY_TIMESTP (1 to 31)
16h
17h
18h
Day_timestp
Mon_timestp
Year_timestp
-
-
-
-
-
MONTH_TIMESTP (1 to 12)
YEAR_TIMESTP (0 to 99)
Aging offset register
19h
Aging_offset
-
-
-
-
AO[3:0]
- - - - 1000
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
8 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
Table 5.
Register overview …continued
Bit positions labeled as - are not implemented and will return a 0 when read. Bit T must always be written with logic 0. Bits
labeled as X are undefined at power-on and unchanged by subsequent resets.
Address Register name
Bit
7
Reset value
6
5
4
3
2
1
0
RAM registers
1Ah
1Bh
1Ch
1Dh
RAM_addr_MSB
-
-
-
-
-
-
-
RA8
- - - - - - - 0
0000 0000
XXXX XXXX
XXXX XXXX
RAM_addr_LSB RA[7:0]
RAM_wrt_cmd
RAM_rd_cmd
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
9 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.2 Control registers
The first 3 registers of the PCF2127AT, with the addresses 00h, 01h, and 02h, are used
as control registers.
8.2.1 Register Control_1
Table 6.
Bit
Control_1 - control and status register 1 (address 00h) bit description
Symbol
Value
Description
Reference
[1]
7
EXT_TEST
0
1
0
0
1
normal mode
Section 8.14
external clock test mode
unused
[2]
[1]
6
5
T
-
STOP
RTC source clock runs
RTC clock is stopped;
Section 8.15
RTC divider chain flip-flops are
asynchronously set logic 0;
CLKOUT at 32.768 kHz, 16.384 kHz, or
8.192 kHz is still available
[1]
[1]
4
3
TSF1
0
1
no timestamp interrupt generated
Section 8.12.1
Section 8.8.2
flag set when TS input is driven to an
intermediate level between power supply
and ground;
flag must be cleared to clear interrupt
POR_OVRD
0
1
Power-On Reset Override (PORO) facility
disabled;
set logic 0 for normal operation
Power-On Reset Override (PORO)
sequence reception enabled
[1]
[1]
[1]
2
1
0
12_24
MI
0
1
0
1
0
1
24 hour mode selected
12 hour mode selected
minute interrupt disabled
minute interrupt enabled
second interrupt disabled
second interrupt enabled
Table 23
Section 8.13
SI
[1] Default value.
[2] When writing to the register this bit always has to be set logic 0.
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
10 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.2.2 Register Control_2
Table 7.
Control_2 - control and status register 2 (address 01h) bit description
Bit
Symbol
Value
Description
Reference
[1]
7
MSF
0
1
no minute or second interrupt generated
Section 8.13
flag set when minute or second interrupt
generated;
flag must be cleared to clear interrupt
[1]
6
WDTF
0
1
no watchdog timer interrupt or reset
generated
Section 8.13.4
flag set when watchdog timer interrupt or
reset generated;
flag cannot be cleared by command
(read-only)
[1]
[1]
[1]
5
4
3
TSF2
AF
0
1
no timestamp interrupt generated
flag set when TS input is driven to ground;
flag must be cleared to clear interrupt
no alarm interrupt generated
Section 8.12.1
Section 8.10.6
Section 8.11.4
0
1
flag set when alarm triggered;
flag must be cleared to clear interrupt
no countdown timer interrupt generated
CDTF
0
1
flag set when countdown timer interrupt
generated;
flag must be cleared to clear interrupt
[1]
[1]
[1]
2
1
0
TSIE
AIE
0
1
0
1
0
no interrupt generated from timestamp flag Section 8.13.6
interrupt generated when timestamp flag set
no interrupt generated from the alarm flag
interrupt generated when alarm flag set
Section 8.13.5
CDTIE
no interrupt generated from countdown timer Section 8.13.2
flag
1
interrupt generated when countdown timer
flag set
[1] Default value.
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
11 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.2.3 Register Control_3
Table 8.
Bit
Control_3 - control and status register 3 (address 02h) bit description
Symbol
Value
Description
Reference
[1]
7 to 5 PWRMNG[2:0]
control of the battery switch-over, battery low Section 8.6
detection, and extra power fail detection
functions
[2]
4
BTSE
0
1
no timestamp when battery switch-over
occurs
Section 8.12.4
time-stamped when battery switch-over
occurs
[2]
[2]
3
2
BF
0
1
no battery switch-over interrupt generated
flag set when battery switch-over occurs;
flag must be cleared to clear interrupt
battery status ok;
Section 8.6.1
Section 8.6.3
BLF
0
1
0
no battery low interrupt generated
battery status low;
flag cannot be cleared by command
[2]
[2]
1
0
BIE
no interrupt generated from the battery flag Section 8.13.7
(BF)
1
0
interrupt generated when BF is set
BLIE
no interrupt generated from battery low flag Section 8.13.8
(BLF)
1
interrupt generated when BLF is set
[1] Values see Table 18.
[2] Default value.
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
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PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.3 Register CLKOUT_ctl
Table 9.
CLKOUT_ctl - CLKOUT control register (address 0Fh) bit description
Symbol Value Description
see Table 10 temperature measurement period
unused
see Table 11 CLKOUT frequency selection
Bit
7 to 6 TCR[1:0]
5 to 3 -
-
2 to 0 COF[2:0]
8.3.1 Temperature compensated crystal oscillator
The frequency of tuning fork quartz crystal oscillators is temperature-dependent. In the
PCF2127AT, the frequency deviation caused by temperature variation is corrected by
adjusting the load capacitance of the crystal oscillator.
The load capacitance is changed by switching between two load capacitance values using
a modulation signal with a programmable duty cycle. In order to compensate the spread of
the quartz parameters every chip is factory calibrated.
The frequency accuracy can be evaluated by measuring the frequency of the square
wave signal available at the output pin CLKOUT. However, the selection of
fCLKOUT = 32.768 kHz (default value) leads to inaccurate measurements. Accurate
frequency measurement occurs when fCLKOUT = 16.384 kHz or lower is selected (see
Table 11).
8.3.1.1 Temperature measurement
The PCF2127AT has a temperature sensor circuit used to perform the temperature
compensation of the frequency. The temperature is measured immediately after power-on
and then periodically with a period set by the temperature conversion rate TCR[1:0] in the
register CLKOUT_ctl.
Table 10. Temperature measurement period
TCR[1:0]
Temperature measurement period
[1]
00
01
10
11
4 min
2 min
1 min
30 seconds
[1] Default value.
8.3.2 Clock output
A programmable square wave is available at pin CLKOUT. Operation is controlled by the
COF[2:0] control bits in register CLKOUT_ctl. Frequencies of 32.768 kHz (default) down
to 1 Hz can be generated for use as system clock, microcontroller clock, charge pump
input, or for calibrating the oscillator.
CLKOUT is an open-drain output and enabled at power-on. When disabled, the output is
high-impedance.
The duty cycle of the selected clock is not controlled, however, due to the nature of the
clock generation all but the 32.768 kHz frequencies will be 50 : 50.
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
13 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
Table 11. CLKOUT frequency selection
COF[2:0]
CLKOUT frequency (Hz)
Typical duty cycle[1]
000[2][3]
32768
60 : 40 to 40 : 60
50 : 50
50 : 50
50 : 50
50 : 50
50 : 50
50 : 50
-
001
16384
010
8192
011
4096
100
2048
101
1024
110
1
111
CLKOUT = high-Z
[1] Duty cycle definition: % HIGH-level time : % LOW-level time.
[2] Default value.
[3] The specified accuracy of the RTC can be only achieved with CLKOUT frequencies not equal to
32.768 kHz or if CLKOUT is disabled.
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
14 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.4 Register Aging_offset
Table 12. Aging_offset - crystal aging offset register (address 19h) bit description
Bit
Symbol
Value
Description
7 to 4 -
-
unused
3 to 0 AO[3:0]
see Table 13 aging offset value
8.4.1 Crystal aging correction
The PCF2127AT has an offset register Aging_offset to correct the crystal aging effects3.
The accuracy of the frequency of a quartz crystal depends on its aging. The aging offset
adds an adjustment, positive or negative, in the temperature compensation circuit which
allows correcting the aging effect.
At 25 C, the aging offset bits allow a frequency correction of typically 1 ppm per AO[3:0]
value, from 7 ppm to +8 ppm.
Table 13. Frequency correction at 25C, typical
AO[3:0]
ppm
Decimal
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
+8
+7
+6
+5
+4
+3
+2
+1
0
1
2
3
4
5
6
7
[1]
8
9
1
2
3
4
5
6
7
10
11
12
13
14
15
[1] Default value.
3. For further information, refer to the application note Ref. 3 “AN10857”.
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8.5 General purpose 512 bytes static RAM
The PCF2127AT contains a general purpose 512 bytes static RAM. This integrated SRAM
is battery backed and can therefore be used to store data which is essential for the
application to survive a power outage.
9 bits, RA[8:0], define the RAM address pointer in registers RAM_addr_MSB and
RAM_addr_LSB. The register address pointer increments after each read or write
automatically up to 1Bh and then wraps around to address 00h (see Figure 3 on page 6).
Data is transferred to or from the RAM by the interface. To write to the RAM, the register
RAM_wrt_cmd, to read from the RAM the register RAM_rd_cmd must be addressed
explicitly.
8.5.1 Register RAM_addr_MSB
Table 14. RAM_addr_MSB - RAM address MSB register (address 1Ah) bit description
Bit
7 to 1
0
Symbol
Description
-
unused
RAM address, MSB (9th bit)
RA8
8.5.2 Register RAM_addr_LSB
Table 15. RAM_addr_LSB - RAM address LSB register (address 1Bh) bit description
Bit
Symbol
Description
7 to 0
RA[7:0]
RAM address, LSB (1st to 8th bit)
8.5.3 Register RAM_wrt_cmd
Table 16. RAM_wrt_cmd - RAM write command register (address 1Ch) bit description
Bit
Symbol
Description
7 to 0
-
data to be written into RAM
8.5.4 Register RAM_rd_cmd
Table 17. RAM_rd_cmd - RAM read command register (address 1Dh) bit description
Bit
Symbol
Description
7 to 0
-
data to be read from RAM
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8.5.5 Operation examples
8.5.5.1 Writing to the RAM
1. Set RAM address:
– Select register RAM_addr_MSB (send address 1Ah).
– Set value for bit RA8 (data byte of register 1Ah).
Note: register address will be incremented automatically to 1Bh.
– Set value for array RA[7:0] (data byte of register 1Bh).
2. Send RAM write command:
– Select register RAM_wrt_cmd (send address 1Ch).
3. Write data into the RAM:
– Write n data byte into RAM.
For details, see Figure 44 on page 62.
8.5.5.2 Reading from the RAM
1. Set RAM address:
– Select register RAM_addr_MSB (send address 1Ah).
– Set value for bit RA8 (data byte of register 1Ah).
Note: register address will be incremented automatically to 1Bh.
– Set value for array RA[7:0] (data byte of register 1Bh).
2. Send RAM read command:
– Select register RAM_rd_cmd (send address 1Dh).
3. Read from the RAM:
– Read n data byte from the RAM.
For details, see Figure 45 on page 63.
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8.6 Power management functions
The PCF2127AT has two power supply pins and one power output pin:
• VDD - the main power supply input pin
• VBAT - the battery backup input pin
• BBS - battery backed output voltage pin (equal to the internal power supply)
The PCF2127AT has three power management functions implemented:
• Battery switch-over function
• Battery low detection function
• Extra power fail detection function
The power management functions are controlled by the control bits PWRMNG[2:0] in
register Control_3:
Table 18. Power management control bit description
PWRMNG[2:0]
Function
[1]
000
battery switch-over function is enabled in standard mode;
battery low detection function is enabled;
extra power fail detection function is enabled
battery switch-over function is enabled in standard mode;
battery low detection function is disabled;
001
010
011
100
101
110
111
extra power fail detection function is enabled
battery switch-over function is enabled in standard mode;
battery low detection function is disabled;
extra power fail detection function is disabled
battery switch-over function is enabled in direct switching mode;
battery low detection function is enabled;
extra power fail detection function is enabled
battery switch-over function is enabled in direct switching mode;
battery low detection function is disabled;
extra power fail detection function is enabled
battery switch-over function is enabled in direct switching mode;
battery low detection function is disabled;
extra power fail detection function is disabled
battery switch-over function is disabled - only one power supply (VDD);
battery low detection function is disabled;
[2]
[2]
extra power fail detection function is enabled
battery switch-over function is disabled - only one power supply (VDD);
battery low detection function is disabled;
extra power fail detection function is disabled
[1] Default value.
[2] When the battery switch-over function is disabled, the PCF2127AT works only with the power supply VDD
;
VBAT must be put to ground and the battery low detection function is disabled.
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8.6.1 Battery switch-over function
The PCF2127AT has a backup battery switch-over circuit which monitors the main power
supply VDD. When a power failure condition is detected, it automatically switches to the
backup battery.
One of two operation modes can be selected:
• Standard mode: the power failure condition happens when:
VDD < VBAT AND VDD < Vth(sw)bat
Vth(sw)bat is the battery switch threshold voltage. Typical value is 2.5 V. The battery
switch-over in standard mode works only for VDD > 2.5 V.
• Direct switching mode: the power failure condition happens when VDD < VBAT
.
Direct switching from VDD to VBAT without requiring VDD to drop below Vth(sw)bat
When a power failure condition occurs and the power supply switches to the battery, the
following sequence occurs:
1. The battery switch flag BF (register Control_3) is set logic 1.
2. An interrupt is generated if the control bit BIE (register Control_3) is enabled
(see Section 8.13.7).
3. If the control bit BTSE (register Control_3) is logic 1, the timestamp registers store the
time and date when the battery switch occurred (see Section 8.12.4).
4. The battery switch flag BF is cleared by command; it must be cleared to clear the
interrupt.
The interface is disabled in battery backup operation:
• Interface inputs are not recognized, preventing extraneous data being written to the
device
• Interface outputs are high-impedance
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8.6.1.1 Standard mode
If VDD > VBAT OR VDD > Vth(sw)bat, the internal power supply is VDD
.
If VDD < VBAT AND VDD < Vth(sw)bat, the internal power supply is VBAT
.
backup battery operation
V
DD
V
V
BBS
BBS
V
BAT
internal power supply (= V
)
BBS
V
th(sw)bat
(= 2.5 V)
V
(= 0 V)
DD
BF
INT
cleared via interface
001aaj311
Vth(sw)bat is the battery switch threshold voltage. Typical value is 2.5 V. In standard mode, the
battery switch-over works only for VDD > 2.5 V.
VDD may be lower than VBAT (for example VDD = 3 V, VBAT = 4.1 V).
Fig 4. Battery switch-over behavior in standard mode with bit BIE set logic 1 (enabled)
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8.6.1.2 Direct switching mode
If VDD > VBAT, the internal power supply is VDD
.
.
If VDD < VBAT, the internal power supply is VBAT
The direct switching mode is useful in systems where VDD is higher than VBAT at all times.
This mode is not recommended if the VDD and VBAT values are similar (for example,
VDD = 3.3 V, VBAT 3.0 V). In direct switching mode, the power consumption is reduced
compared to the standard mode because the monitoring of VDD and Vth(sw)bat is not
performed.
backup battery operation
V
DD
V
V
BBS
BBS
V
BAT
internal power supply (= V
)
BBS
V
th(sw)bat
(= 2.5 V)
V
(= 0 V)
DD
BF
INT
cleared via interface
001aaj312
Fig 5. Battery switch-over behavior in direct switching mode with bit BIE set logic 1
(enabled)
8.6.1.3 Battery switch-over disabled: only one power supply (VDD
)
When the battery switch-over function is disabled:
• The power supply is applied on the VDD pin
• The VBAT pin must be connected to ground
• The internal power supply, available at the output pin BBS, is equal to VDD
• The battery flag (BF) is always logic 0
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8.6.1.4 Battery switch-over architecture
The architecture of the battery switch-over circuit is shown in Figure 6.
comparators
logic
switches
V
DD(int)
V
CC
V
DD
V
V
th(sw)bat
V
V
DD
DD(int)
V
LOGIC
BBS
V
CC
(internal
power supply)
th(sw)bat
V
BAT
V
BAT
001aag061
V
DD(int)
Fig 6. Battery switch-over circuit, simplified block diagram
The internal power supply (available on pin BBS) is equal to VDD or VBAT. It has to be
assured that there are decoupling capacitors on the pins VDD, VBAT, and BBS.
8.6.2 Battery backup supply
The VBBS voltage on the output pin BBS is equal to the internal power supply, depending
on the selected battery switch-over function mode:
Table 19. Output pin BBS
Battery switch-over function mode
Conditions
VBBS equals
VDD
standard
VDD > VBAT OR VDD > Vth(sw)bat
VDD < VBAT AND VDD < Vth(sw)bat
VDD > VBAT
VBAT
direct switching
disabled
VDD
VDD < VBAT
VBAT
only VDD available,
VDD
VBAT must be put to ground
The output pin BBS can be used as a supply for external devices with battery backup
needs, such as SRAM (see Ref. 3 “AN10857”). For this case, Figure 7 shows the typical
driving capability when VBBS is driven from VDD
.
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001aaj327
0
V
− V
DD
BBS
(mV)
−200
V
= 4.2 V
DD
−400
−600
−800
V
= 3 V
= 2 V
DD
V
DD
0
2
4
6
8
I
(mA)
BBS
Fig 7. Typical driving capability of VBBS: (VBBS VDD) with respect to the output load
current IBBS
8.6.3 Battery low detection function
The PCF2127AT has a battery low detection circuit which monitors the status of the
battery VBAT
.
When VBAT drops below the threshold value Vth(bat)low (typically 2.5 V), the BLF flag
(register Control_3) is set to indicate that the battery is low and that it must be replaced.
Monitoring of the battery voltage also occurs during battery operation.
An unreliable battery cannot prevent that the supply voltage drops below Vlow (typical
1.2 V) and with that the data integrity gets lost.
When VBAT drops below the threshold value Vth(bat)low, the following sequence occurs (see
Figure 8):
1. The battery low flag BLF is set logic 1.
2. An interrupt is generated if the control bit BLIE (register Control_3) is enabled
(see Section 8.13.8).
3. The flag BLF remains logic 1 until the battery is replaced. BLF cannot be cleared by
command. It is cleared automatically by the battery low detection circuit when the
battery is replaced.
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V
= V
BBS
DD
internal power supply (= V
)
BBS
V
BAT
V
th(bat)low
(= 2.5 V)
V
BAT
BLF
INT
001aaj322
Fig 8. Battery low detection behavior with bit BLIE set logic 1 (enabled)
8.6.4 Extra power fail detection function
The PCF2127AT has an extra power fail detection circuit which compares the voltage at
the power fail input pin PFI to an internal reference voltage equal to 1.25 V.
If VPFI < 1.25 V, the power fail output PFO is driven LOW. PFO is an open-drain, active
LOW output which requires an external pull-up resistor in any application.
The extra power fail detection function is typically used as a low voltage detection for the
main power supply VDD (see Figure 9).
V
DD
R1
R
PU
PCF2127AT
1.25 V
(internal)
15 PFI
14
PFO
R2
V
SS
001aaj678
Fig 9. Typical application of the extra power fail detection function
Usually R1 and R2 should be chosen such that the voltage at pin PFI
• is higher than 1.25 V at start-up
• falls below 1.25 V when VDD falls below a desired threshold voltage, Vth(uvp), defined
by Equation 1:
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R1
-----
R2
Vthuvp
=
+ 1 1.25V
(1)
Vth(uvp) value is usually set to a value that there are several milliseconds before VDD falls
below the minimum operating voltage of the system, in order to allow the microcontroller
to perform early backup operations.
If the extra power fail detection function is not used, pin PFI must be connected to VSS and
pin PFO must be left open circuit.
8.6.4.1 Extra power fail detection when the battery switch over function is enabled
• When the power switches to the backup battery supply VBAT, the power fail
comparator is switched off and the power fail output at pin PFO goes (or remains)
LOW
• When the power switches back to the main VDD, the pin PFO is not driven LOW
anymore and is pulled HIGH through the external pull-up resistance for a certain time
(trec = 15.63 ms to 31.25 ms) and then the power fail comparator is enabled again
For illustration, see Figure 10 and Figure 11.
V
DD
V
th(uvp)
V
BAT
internal power supply (= V
)
BBS
V
V
BBS
BBS
V
th(sw)bat
(= 2.5 V)
V
(= 0 V)
DD
comparator
enabled
comparator
disabled
comparator
enabled
PF0
t
= [15.63 : 31.25] ms
rec
001aaj319
Fig 10. PFO signal behavior when battery switch-over is enabled in standard mode and
Vth(uvp) > (VBAT, Vth(sw)bat
)
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V
DD
V
V
BBS
BBS
internal power supply (= V
)
BBS
V
BAT
V
th(uvp)
V
th(sw)bat
(= 2.5 V)
V
(= 0 V)
DD
comparator
enabled
comparator
disabled
comparator
enabled
PF0
t
rec
001aaj320
Fig 11. PFO signal behavior when battery switch-over is enabled in direct switching
mode and Vth(uvp) < VBAT
8.6.4.2 Extra power fail detection when the battery switch-over function is disabled
If the battery switch-over function is disabled and the power fail comparator is enabled,
the power fail output at pin PFO depends only on the result of the comparison between
V
PFI and 1.25 V:
• If VPFI > 1.25 V, PFO = HIGH (through the external pull-up resistor)
• If VPFI < 1.25 V, PFO = LOW
V
DD
V
th(uvp)
V
th(sw)bat
(= 2.5 V)
comparator always enabled
PF0
001aaj321
Fig 12. PFO signal behavior when battery switch-over is disabled
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8.7 Oscillator stop detection function
The PCF2127AT has an on-chip oscillator detection circuit which monitors the status of
the oscillation: whenever the oscillation stops, a reset occurs and the oscillator stop flag
OSF (in register Seconds) is set logic 1.
• Power-on:
a. The oscillator is not running, the chip is in reset (pin RST is LOW and flag OSF is
logic 1).
b. When the oscillator starts running and is stable after power-on, the chip exits from
reset (pin RST is HIGH).
c. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) by command.
• Power supply failure:
a. When the power supply of the chip (VBBS, see Section 8.6.2) drops below a certain
value (Vlow), typically 1.2 V, the oscillator stops running and a reset occurs.
b. When the power supply returns to normal operation, the oscillator starts running
again, the chip exits from reset.
c. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) by command.
V
DD
V
DD
V
BBS
V
BAT
V
V
BBS
BBS
V
V
th(sw)bat
(= 2.5 V)
battery discharge
internal power supply
BBS
V
low
(= 1.2 V)
V
BAT
V
SS
V
SS
(1)
(2)
OSF
001aaj409
(1) Theoretical state of the signals since there is no power.
(2) The oscillator stop flag (OSF), set logic 1, indicates that the oscillation has stopped and a reset has
occurred since the flag was last cleared (OSF set logic 0). In this case, the integrity of the clock
information is not guaranteed. The OSF flag is cleared by command.
Fig 13. Power failure event due to battery discharge: reset occurs
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8.8 Reset function
The PCF2127AT has a Power-On Reset (POR) and a Power-On Reset Override (PORO)
function implemented.
8.8.1 Power-On Reset (POR)
The POR is active whenever the oscillator is stopped. The oscillator is also considered to
be stopped during the time between power-on and stable crystal resonance (see
Figure 14). This time may be in the range of 200 ms to 2 s depending on temperature and
supply voltage. Whenever an internal reset occurs, the oscillator stop flag is set (OSF set
logic 1).
chip in reset
chip not in reset
V
DD
oscillation
RST
t
013aaa243
Fig 14. Dependency between POR and oscillator
After POR, the following mode is entered:
• 32.768 kHz CLKOUT active
• Power-On Reset Override (PORO) available to be set
• 24 hour mode is selected
• Battery switch-over is enabled
• Battery low detection is enabled
• Extra power fail detection is enabled
The register values after power-on are shown in Table 5.
8.8.2 Power-On Reset Override (PORO)
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a mechanism has been built in to
disable the POR and therefore speed up the on-board test of the device.
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osc stopped
OSCILLATOR
0 = stopped, 1 = running
reset
SCL
RESET
OVERRIDE
0 = override inactive
1 = override active
SDA/CE
CLEAR
0 = clear override mode
1 = override possible
POR_OVRD
001aaj324
Fig 15. Power-On Reset (POR) system
The setting of the PORO mode requires that POR_OVRD in register Control_1 is set
logic 1 and that the signals at the interface pins SDA/CE and SCL are toggled as
illustrated in Figure 16. All timings shown are required minimum.
power up
8 ms
minimum 500 ns
minimum 2000 ns
SDA/CE
SCL
reset override
001aaj326
Fig 16. Power-On Reset Override (PORO) sequence, valid for both I2C-bus and SPI-bus
Once the override mode is entered, the device is immediately released from the reset
state and the set-up operation can commence.
The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be
logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0
during normal operation has no effect except to prevent accidental entry into the PORO
mode.
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8.9 Time and date function
Most of these registers are coded in the Binary Coded Decimal (BCD) format.
8.9.1 Register Seconds
Table 20. Seconds - seconds and clock integrity register (address 03h) bit description
Bit
Symbol
Value
Place value Description
7
OSF
0
1[1]
-
-
clock integrity is guaranteed
clock integrity is not guaranteed:
oscillator has stopped and chip reset
has occurred since flag was last cleared
6 to 4 SECONDS
3 to 0
0 to 5
0 to 9
ten’s place actual seconds coded in BCD format
unit place
[1] Start-up value.
Table 21. Seconds coded in BCD format
Seconds value in Upper-digit (ten’s place)
decimal
Digit (unit place)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
01
02
:
0
0
0
:
0
0
0
:
0
0
0
:
0
0
0
:
0
0
0
:
0
0
1
:
0
1
0
:
09
10
:
0
0
:
0
0
:
0
1
:
1
0
:
0
0
:
0
0
:
1
0
:
58
59
1
1
0
0
1
1
1
1
0
0
0
0
0
1
8.9.2 Register Minutes
Table 22. Minutes - minutes register (address 04h) bit description
Bit
Symbol
Value
-
Place value Description
- unused
7
-
6 to 4 MINUTES
3 to 0
0 to 5
0 to 9
ten’s place actual minutes coded in BCD format
unit place
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8.9.3 Register Hours
Table 23. Hours - hours register (address 05h) bit description
Bit
Symbol
Value
Place value Description
7 to 6 -
-
-
unused
12 hour mode[1]
5
AMPM
0
-
-
indicates AM
indicates PM
1
4
HOURS
0 to 1
0 to 9
ten’s place actual hours coded in BCD format when in
12 hour mode
3 to 0
unit place
24 hour mode[1]
5 to 4 HOURS
3 to 0
0 to 2
0 to 9
ten’s place actual hours coded in BCD format when in
24 hour mode
unit place
[1] Hour mode is set by the bit 12_24 in register Control_1.
8.9.4 Register Days
Table 24. Days - days register (address 06h) bit description
Bit
Symbol
Value
-
Place value Description
unused
7 to 6 -
-
5 to 4 DAYS[1]
0 to 3
0 to 9
ten’s place actual day coded in BCD format
unit place
3 to 0
[1] If the year counter contains a value which is exactly divisible by 4, including the year 00, the RTC
compensates for leap years by adding a 29th day to February.
8.9.5 Register Weekdays
Table 25. Weekdays - weekdays register (address 07h) bit description
Bit
Symbol
Value
-
Description
7 to 3 -
unused
2 to 0 WEEKDAYS
0 to 6
actual weekday value, see Table 26
Although the association of the weekdays counter to the actual weekday is arbitrary, the
PCF2127AT will assume that Sunday is 000 and Monday is 001 for the purposes of
determining the increment for calendar weeks.
Table 26. Weekday assignments
Day[1]
Bit
2
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
Sunday
0
Monday
Tuesday
Wednesday
Thursday
Friday
0
0
0
1
1
Saturday
1
[1] Definition may be reassigned by the user.
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8.9.6 Register Months
Table 27. Months - months register (address 08h) bit description
Bit
Symbol
Value
-
Place value Description
unused
7 to 5 -
-
4
MONTHS
0 to 1
0 to 9
ten’s place actual month coded in BCD format, see
Table 28
3 to 0
unit place
Table 28. Month assignments in BCD format
Month
Upper-digit
(ten’s place)
Digit (unit place)
Bit 4
0
Bit 3
0
Bit 2
Bit 1
0
Bit 0
1
January
February
March
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
April
0
0
0
0
May
0
0
0
1
June
0
0
1
0
July
0
0
1
1
August
September
October
November
December
0
1
0
0
0
1
0
1
1
0
0
0
1
0
0
1
1
0
1
0
8.9.7 Register Years
Table 29. Years - years register (address 09h) bit description
Bit
Symbol
Value
0 to 9
0 to 9
Place value Description
7 to 4 YEARS
3 to 0
ten’s place actual year coded in BCD format
unit place
8.9.8 Setting and reading the time
Figure 17 shows the data flow and data dependencies starting from the 1 Hz clock tick.
During read/write operations, the time counting circuits (memory locations 03h through
09h) are blocked.
This prevents
• Faulty reading of the clock and calendar during a carry condition
• Incrementing the time registers during the read cycle
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1 Hz tick
SECONDS
MINUTES
HOURS
DAYS
12_24 hour mode
LEAP YEAR
CALCULATION
WEEKDAY
MONTHS
YEARS
001aaf901
Fig 17. Data flow of the time function
After this read/write access is completed, the time circuit is released again. Any pending
request to increment the time counters that occurred during the read/write access is
serviced. A maximum of 1 request can be stored; therefore, all accesses must be
completed within 1 second (see Figure 18).
t < 1 s
SLAVE ADDRESS
DATA
DATA
STOP
START
013aaa215
Fig 18. Access time for read/write operations
As a consequence of this method, it is very important to make a read or write access in
one go, that is, setting or reading seconds through to years should be made in one single
access. Failing to comply with this method could result in the time becoming corrupted.
As an example, if the time (seconds through to hours) is set in one access and then in a
second access the date is set, it is possible that the time may increment between the two
accesses. A similar problem exists when reading. A roll-over may occur between reads
thus giving the minutes from one moment and the hours from the next. Therefore it is
advised to read all time and date registers in one access.
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8.10 Alarm function
When one or more of the alarm bit fields are loaded with a valid second, minute, hour, day,
or weekday and its corresponding alarm enable bit (AE_x) is logic 0, then that information
is compared with the actual second, minute, hour, day, and weekday (see Figure 19).
example
check now signal
AE_S
AE_S = 1
SECOND ALARM
=
1
0
SECOND TIME
AE_M
AE_H
AE_D
AE_W
MINUTE ALARM
MINUTE TIME
=
=
=
=
HOUR ALARM
HOUR TIME
(1)
set alarm flag AF
DAY ALARM
DAY TIME
WEEKDAY ALARM
WEEKDAY TIME
013aaa236
(1) Only when all enabled alarm settings are matching.
Fig 19. Alarm function block diagram
The generation of interrupts from the alarm function is described in Section 8.13.5.
8.10.1 Register Second_alarm
Table 30. Second_alarm - second alarm register (address 0Ah) bit description
Bit
Symbol
Value
Place value Description
7
AE_S
0
1[1]
-
-
second alarm is enabled
second alarm is disabled
6 to 4 SECOND_ALARM
3 to 0
0 to 5
0 to 9
ten’s place second alarm information coded in BCD
format
unit place
[1] Default value.
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8.10.2 Register Minute_alarm
Table 31. Minute_alarm - minute alarm register (address 0Bh) bit description
Bit
Symbol
Value
Place value Description
7
AE_M
0
1[1]
-
-
minute alarm is enabled
minute alarm is disabled
6 to 4 MINUTE_ALARM
3 to 0
0 to 5
0 to 9
ten’s place minute alarm information coded in BCD
format
unit place
[1] Default value.
8.10.3 Register Hour_alarm
Table 32. Hour_alarm - hour alarm register (address 0Ch) bit description
Bit
Symbol
Value
Place value Description
7
AE_H
0
1[1]
-
-
-
hour alarm is enabled
hour alarm is disabled
unused
6
-
-
12 hour mode[2]
5
AMPM
0
-
-
indicates AM
indicates PM
1
4
HOUR_ALARM
0 to 1
0 to 9
ten’s place hour alarm information coded in BCD
format when in 12 hour mode
3 to 0
unit place
24 hour mode[2]
5 to 4 HOUR_ALARM
3 to 0
0 to 2
0 to 9
ten’s place hour alarm information coded in BCD
format when in 24 hour mode
unit place
[1] Default value.
[2] Hour mode is set by the bit 12_24 in register Control_1.
8.10.4 Register Day_alarm
Table 33. Day_alarm - day alarm register (address 0Dh) bit description
Bit
Symbol
Value
Place value Description
7
AE_D
0
1[1]
-
-
-
day alarm is enabled
day alarm is disabled
unused
6
-
-
5 to 4 DAY_ALARM
3 to 0
0 to 3
0 to 9
ten’s place day alarm information coded in BCD
format
unit place
[1] Default value.
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8.10.5 Register Weekday_alarm
Table 34. Weekday_alarm - weekday alarm register (address 0Eh) bit description
Bit
Symbol
Value
Description
7
AE_W
0
weekday alarm is enabled
weekday alarm is disabled
unused
1[1]
-
6 to 3 -
2 to 0 WEEKDAY_ALARM
0 to 6
weekday alarm information
[1] Default value.
8.10.6 Alarm flag
When all enabled comparisons first match, the alarm flag AF (register Control_2) is set.
AF will remain set until cleared by command. Once AF has been cleared, it will only be set
again when the time increments to match the alarm condition once more. For clearing the
flags, see Section 8.11.6
Alarm registers which have their alarm enable bit AE_x at logic 1 are ignored.
minutes counter
minute alarm
AF
44
45
45
46
INT when AIE = 1
001aaf903
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 20. Alarm flag timing diagram
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8.11 Timer functions
The PCF2127AT has two different timer functions, a watchdog timer and a countdown
timer. The timers can be selected by using the control bits WD_CD[1:0] in the register
Watchdg_tim_ctl.
• The watchdog timer has four selectable source clocks. It can, for example, be used to
detect a microcontroller with interrupt and reset capability which is out of control (see
Section 8.11.3)
• The countdown timer has four selectable source clocks allowing for countdown
periods from less than 1 ms to more than 4 hours (see Section 8.11.4)
To control the timer functions and timer output, the registers Control_2, Watchdg_tim_ctl,
and Watchdg_tim_val are used.
8.11.1 Register Watchdg_tim_ctl
Table 35. Watchdg_tim_ctl - watchdog timer control register (address 10h) bit description
Bit
Symbol
Value
Description
7 to 6 WD_CD[1:0]
00[1]
watchdog timer disabled;
countdown timer disabled
01
watchdog timer disabled;
countdown timer enabled
if CDTIE is set logic 1, the interrupt pin INT is
activated when the countdown timed out
10
11
watchdog timer enabled;
the interrupt pin INT is activated when timed out;
countdown timer not available
watchdog timer enabled;
the reset pin RST is activated when timed out;
countdown timer not available
5
TI_TP
0[1]
1
the interrupt pin INT is configured to generate a
permanent active signal when MSF and/or CDTF is set
the interrupt pin INT is configured to generate a pulsed
signal when MSF flag and/or CDTF flag is set (see
Figure 25)
4 to 2 -
-
unused
1 to 0 TF[1:0]
timer source clock for watchdog and countdown timer
00
4.096 kHz
64 Hz
01
10
1 Hz
1
11[1]
⁄60 Hz
[1] Default value.
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8.11.2 Register Watchdg_tim_val
Table 36. Watchdg_tim_val - watchdog timer value register (address 11h) bit description
Bit Symbol Value Description
7 to 0 WATCHDG_TIM_VAL[7:0] 00 to FF timer period in seconds:
n
--------------------------------------------------------------
CountdownPeriod =
SourceClockFrequency
where n is the timer value
Table 37. Programmable watchdog or countdown timer
TF[1:0] Timer source
clock frequency
Units Minimum timer
Units Maximum timer
period (n = 255)
Units
period (n = 1)
00
01
10
11
4.096
64
kHz
Hz
244
15.625
1
s
ms
s
62.256
3.984
255
ms
s
1
Hz
s
1
⁄
Hz
60
s
15300
s
60
8.11.3 Watchdog timer function
The watchdog timer function is enabled or disabled by the WD_CD[1:0] bits of the register
Watchdg_tim_ctl (see Table 35).
The two bits TF[1:0] in register Watchdg_tim_ctl determine one of the four source clock
frequencies for the watchdog timer: 4.096 kHz, 64 Hz, 1 Hz, or 1⁄60 Hz (see Table 37).
When the watchdog timer function is enabled, the 8-bit timer in register Watchdg_tim_val
determines the watchdog timer period (see Table 36).
The watchdog timer counts down from the software programmed 8-bit binary value n in
register Watchdg_tim_val. When the counter reaches 1, the watchdog timer flag WDTF
(register Control_2) is set logic 1.
If WDTF is logic 1 and:
• if WD_CD[1:0] = 10 an interrupt will be generated
• if WD_CD[1:0] = 11 a reset will be generated
The counter does not automatically reload.
When WD_CD[1:0] = 10 or WD_CD[1:0] = 11 and the microcontroller unit (MCU) loads a
watchdog timer value n:
• the flag WDTF is reset
• INT or RST is cleared
• the watchdog timer starts again
Loading the counter with 0 will:
• reset the flag WDTF
• clear INT or RST
• stop the watchdog timer
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Remark: WDTF is read only and cannot be cleared by command. WDTF can be cleared
by:
• loading a value in register Watchdg_tim_val
• reading of the register Control_2
Writing a logic 0 or logic 1 to WDTF has no effect.
MCU
watchdog
timer value
n = 1
n
WDTF
INT
001aag062
Counter reached 1, WDTF is set logic 1, and an interrupt is generated.
Fig 21. WD_CD[1:0] = 10: watchdog activates an interrupt when timed out
• When the watchdog timer counter reaches 1, the watchdog timer flag WDTF is set
logic 1
• When a minute or second interrupt occurs, the minute/second flag MSF is set logic 1
(see Section 8.13.1)
MCU
watchdog
timer value
n = 1
n
WDTF
RST
001aag063
t
w(rst)
Counter reached 1, WDTF is set logic 1, reset pulse on the RST pin is generated for a time equal
to tw(rst)
.
Fig 22. WD_CD[1:0] = 11: watchdog activates a reset pulse when timed out
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Table 38. Specification of tw(rst)
WD_CD[1:0]
11
TF[1:0]
00
tw(rst)
244 s
01
15.625 ms
15.625 ms
15.625 ms
10
11
8.11.4 Countdown timer function
The countdown timer function is controlled by the WD_CD[1:0] bits in register
Watchdg_tim_ctl (see Table 35).
The timer counts down from the software programmed 8 bit binary value n in register
Watchdg_tim_val. When the counter reaches 1
• the countdown timer flag CDTF is set
• the counter automatically reloads
• and the next time period starts
Loading the counter with 0 effectively stops the timer.
Reading the timer returns the actual value of the countdown counter.
countdown value, n
timer source clock
countdown counter
WD/CD [1:0]
CDTF
XX
03
03
XX
00
02
01
03
02
01
03
02
01
03
01
INT
n
n
duration of first timer period after
enable may range from n−1 to n+1
001aag071
In this example, it is assumed that the countdown timer flag (CDTF) is cleared before the next
countdown period expires and that INT is set to pulsed mode.
Fig 23. General countdown timer behavior
If a new value of n is written before the end of the actual timer period, this value takes
immediate effect. It is not recommended to change n without first disabling the counter by
setting WD_CD[1:0] = 00. The update of n is asynchronous to the timer clock. Therefore
changing it on the fly could result in a corrupted value loaded into the countdown counter.
This can result in an undetermined countdown period for the first period. The countdown
value n will, however, be correctly stored and correctly loaded on subsequent timer
periods.
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If this mode is enabled and the countdown timer flag CDTF is set, an interrupt signal on
INT will be generated. See Section 8.13.2 for details on how the interrupt can be
controlled.
When starting the countdown timer for the first time, only the first period will not have a
fixed duration. The amount of inaccuracy for the first timer period will depend on the
chosen source clock, see Table 39.
Table 39. First period delay for timer counter
Timer source clock
4.096 kHz
Minimum timer period
Maximum timer period
n + 1
n
64 Hz
n
n + 1
1 Hz
(n 1) + 1⁄64 Hz
(n 1) + 1⁄64 Hz
n + 1⁄64 Hz
n + 1⁄64 Hz
1
⁄60 Hz
At the end of every countdown, the timer sets the countdown timer flag (CDTF). CDTF
may only be cleared by command. The asserted CDTF can be used to generate an
interrupt (INT). The interrupt may be generated as a pulsed signal every countdown
period or as a permanently active signal which follows the condition of CDTF. TI_TP is
used to control this mode selection. The interrupt output may be disabled with the CDTIE
bit, see Table 7.
When reading the timer, the actual countdown value is returned and not the initial value n.
Since it is not possible to freeze the countdown timer counter during read back, it is
recommended to read the register twice and check for consistent results.
8.11.5 Pre-defined timers: second and minute interrupt
PCF2127AT has two pre-defined timers which are used to generate an interrupt either
once per second or once per minute. The pulse generator for the minute or second
interrupt operates from an internal 64 Hz clock. It is independent of the watchdog or
countdown timers. Each of these timers can be enabled by the bits SI (second interrupt)
and MI (minute interrupt) in register Control_1.
8.11.6 Clearing flags
The flags MSF, CDTF, AF and TSFx can be cleared by command. To prevent one flag
being overwritten while clearing another, a logic AND is performed during the write
access. A flag is cleared by writing logic 0 while a flag is not cleared by writing logic1.
Writing logic1 will result in the flag value remaining unchanged.
Four examples are given for clearing the flags. Clearing the flags is made by a write
command:
• Bits labeled with - must be written with their previous values
• WDTF is read only and has to be written with logic 0
Repeatedly rewriting these bits has no influence on the functional behavior.
Table 40. Flag location in register Control_2
Register
Bit
7
6
5
4
3
2
1
0
Control_2
MSF
WDTF
TSF2
AF
CDTF
-
-
-
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Table 41. Example values in register Control_2
Register
Bit
7
6
5
4
3
2
1
0
Control_2
1
0
1
1
1
0
0
0
The following tables show what instruction must be sent to clear the appropriate flag.
Table 42. Example to clear only CDTF (bit 3)
Register
Bit
7
6
5
4
3
2
1
0
[1]
[1]
[1]
Control_2
1
0
1
1
0
-
-
-
[1] The bits labeled as - have to be rewritten with the previous values.
Table 43. Example to clear only AF (bit 4)
Register
Bit
7
6
5
4
3
2
1
0
Control_2
1
0
1
0
1
0[1]
0[1]
0[1]
[1] The bits labeled as - have to be rewritten with the previous values.
Table 44. Example to clear only MSF (bit 7)
Register
Bit
7
6
5
4
3
2
1
0
Control_2
0
0
1
1
1
0[1]
0[1]
0[1]
[1] The bits labeled as - have to be rewritten with the previous values.
Table 45. Example to clear both CDTF and MSF
Register
Bit
7
6
5
4
3
2
1
0
Control_2
0
0
1
1
0
0[1]
0[1]
0[1]
[1] The bits labeled as - have to be rewritten with the previous values.
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8.12 Timestamp function
The PCF2127AT has an active LOW timestamp input pin TS, internally pulled with an
on-chip pull-up resistor to the internal power supply of the device. It also has a timestamp
detection circuit which can detect two different events:
1. Input on pin TS is driven to an intermediate level between power supply and ground.
2. Input on pin TS is driven to ground.
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Fig 24. Timestamp detection with two push-buttons on the TS pin (for example, for
tamper detection)
The timestamp function is enabled by default after power-on and it can be switched off by
setting the control bit TSOFF (register Timestp_ctl).
A most common application of the timestamp function is described in Ref. 3 “AN10857”.
See Section 8.13.6 for a description of interrupt generation from the timestamp function.
8.12.1 Timestamp flag
1. When the TS input pin is driven to an intermediate level between the power supply
and ground, then the following sequence occurs:
a. The actual date and time are stored in the timestamp registers.
b. The timestamp flag TSF1 (register Control_1) is set.
c. If the TSIE bit (register Control_2) is active, an interrupt on the INT pin is
generated.
The TSF1 flag can be cleared by command. Clearing the flag will clear the interrupt.
Once TSF1 is cleared, it will only be set again when a new negative edge on pin TS is
detected.
2. When the TS input pin is driven to ground, the following sequence occurs:
a. The actual date and time are stored in the timestamp registers.
b. In addition to the TSF1 flag, the TSF2 flag (register Control_2) is set.
c. If the TSIE bit is active, an interrupt on the INT pin is generated.
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The TSF1 and TSF2 flags can be cleared by command; clearing both flags will clear
the interrupt. Once TSF2 is cleared, it will only be set again when TS pin is driven to
ground once again.
8.12.2 Timestamp mode
The timestamp function has two different modes selected by the control bit TSM
(timestamp mode) in register Timestp_ctl:
• If TSM is logic 0 (default): in subsequent trigger events without clearing the timestamp
flags, the last timestamp event is stored
• If TSM is logic 1: in subsequent trigger events without clearing the timestamp flags,
the first timestamp event is stored
The timestamp function also depends on the control bit BTSE in register Control_3, see
Section 8.12.4.
8.12.3 Timestamp registers
8.12.3.1 Register Timestp_ctl
Table 46. Timestp_ctl - timestamp control register (address 12h) bit description
Bit
Symbol
Value Description
7
TSM
0[1]
in subsequent events without clearing the timestamp
flags, the last event is stored
1
in subsequent events without clearing the timestamp
flags, the first event is stored
6
5
TSOFF
-
0[1]
1
timestamp function active
timestamp function disabled
-
unused
1
4 to 0 1_O_16_TIMESTP[4:0]
[1] Default value.
⁄16 second timestamp information coded in BCD format
8.12.3.2 Register Sec_timestp
Table 47. Sec_timestp - second timestamp register (address 13h) bit description
Bit
Symbol
Value
Place value Description
- unused
7
-
-
6 to 4 SECOND_TIMESTP 0 to 5
ten’s place second timestamp information coded in
BCD format
3 to 0
0 to 9
unit place
8.12.3.3 Register Min_timestp
Table 48. Min_timestp - minute timestamp register (address 14h) bit description
Bit
Symbol
Value
Place value Description
- unused
7
-
-
6 to 4 MINUTE_TIMESTP 0 to 5
3 to 0 0 to 9
ten’s place minute timestamp information coded in
BCD format
unit place
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8.12.3.4 Register Hour_timestp
Table 49. Hour_timestp - hour timestamp register (address 15h) bit description
Bit
Symbol
Value
Place value Description
7 to 6 -
-
-
unused
12 hour mode[1]
5
AMPM
0
-
-
indicates AM
indicates PM
1
4
HOUR_TIMESTP
0 to 1
0 to 9
ten’s place hour timestamp information coded in BCD
format when in 12 hour mode
3 to 0
unit place
24 hour mode[1]
5 to 4 HOUR_TIMESTP
3 to 0
0 to 2
0 to 9
ten’s place hour timestamp information coded in BCD
format when in 24 hour mode
unit place
[1] Hour mode is set by the bit 12_24 in register Control_1.
8.12.3.5 Register Day_timestp
Table 50. Day_timestp - day timestamp register (address 16h) bit description
Bit
Symbol
Value
-
Place value Description
unused
7 to 6 -
-
5 to 4 DAY_TIMESTP
3 to 0
0 to 3
0 to 9
ten’s place day timestamp information coded in BCD
format
unit place
8.12.3.6 Register Mon_timestp
Table 51. Mon_timestp - month timestamp register (address 17h) bit description
Bit
Symbol
Value
Place value Description
unused
7 to 5 -
-
-
4
MONTH_TIMESTP 0 to 1
0 to 9
ten’s place month timestamp information coded in
BCD format
3 to 0
unit place
8.12.3.7 Register Year_timestp
Table 52. Year_timestp - year timestamp register (address 18h) bit description
Bit
Symbol
Value
0 to 9
0 to 9
Place value Description
7 to 4 YEAR_TIMESTP
3 to 0
ten’s place year timestamp information coded in BCD
format
unit place
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8.12.4 Dependency between Battery switch-over and timestamp
The timestamp function depends on the control bit BTSE in register Control_3:
Table 53. Battery switch-over and timestamp
BTSE BF
Description
[1]
[1]
0
1
-
the battery switch-over does not affect the timestamp registers
If a battery switch-over event occurs:
0
1
the timestamp registers store the time and date when the switch-over occurs;
after this event occurred BF is set logic 1
the timestamp registers are not modified;
in this condition subsequent battery switch-over events or falling edges on pin
TS are not registered
[1] Default value.
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8.13 Interrupt output, INT
SI
MSF:
MINUTE
SECOND FLAG
to interface:
read MSF
SECONDS COUNTER
MINUTES COUNTER
SI/MI
0
MI
SET
CLEAR
1
PULSE
GENERATOR 1
TRIGGER
CLEAR
from interface:
clear MSF
TI_TP
INT pin
CDTF:
COUNTDOWN
TIMER FLAG
to interface:
read CDTF
WD_CD[1:0] = 01
CDTIE
0
1
COUNTDOWN
COUNTER
SET
CLEAR
PULSE
GENERATOR 2
TRIGGER
CLEAR
from interface:
clear CDTF
WDTF:
WATCHDOG
TIMER FLAG
to interface:
read WDTF
WD_CD[1:0] = 00
WD_CD[1:0] = 01
WATCHDOG
COUNTER
SET
CLEAR
MCU loading
watchdog counter
to interface:
read AF
AIE
TSIE
AF: ALARM
FLAG
set alarm
flag, AF
SET
CLEAR
from interface:
clear AF
to interface:
read TSFx
TSFx: TIMESTAMP
FLAG
set timestamp
flag, TSFx
SET
CLEAR
from interface:
clear TSFx
to interface:
read BF
BIE
BF: BATTERY
FLAG
set battery
flag, BF
SET
CLEAR
from interface:
clear BF
to interface:
read BLF
BLIE
BLF: BATTERY
LOW FLAG
set battery
low flag, BLF
SET
CLEAR
from battery
low detection
001aag070
circuit: clear BF
When SI, MI, CDTIE, WD_CD, AIE, TSIE, BIE, BLIE are all disabled, INT will remain high-impedance.
Fig 25. Interrupt block diagram
PCF2127AT has an interrupt output pin INT which is open-drain, active LOW. Interrupts
may be sourced from different places:
• second or minute timer
• countdown timer
PCF2127AT
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• watchdog timer
• alarm
• timestamp
• battery switch-over
• battery low detection
The control bit TI_TP (register Watchdg_tim_ctl) is used to configure whether the
interrupts generated from the second/minute timer (flag MSF in register Control_2) and
the countdown timer (flag CDTF in register Control_2) are pulsed signals or a
permanently active signal. All the other interrupt sources generate a permanently active
interrupt signal which follows the status of the corresponding flags. When the interrupt
sources are all disabled, INT remains high-impedance.
• The flags MSF, CDTF, AF, TSFx, and BF can be cleared by command.
• The flag WDTF is read only. How it can be cleared is explained in Section 8.11.6.
• The flag BLF is read only. It is cleared automatically from the battery low detection
circuit when the battery is replaced.
8.13.1 Minute and second interrupts
Minute and second interrupts are generated by predefined timers. The timers can be
enabled independently from one another by the bits MI and SI in register Control_1.
However, a minute interrupt enabled on top of a second interrupt will not be
distinguishable since it will occur at the same time.
The minute/second flag MSF (register Control_2) is set logic 1 when either the seconds or
the minutes counter increments according to the enabled interrupt (see Table 54). The
MSF flag can be read and cleared by command.
Table 54. Effect of bits MI and SI on pin INT and bit MSF
MI SI Result on INT
Result on MSF
0
1
0
1
0
0
1
1
no interrupt generated
MSF never set
an interrupt once per minute
an interrupt once per second
an interrupt once per second
MSF set when minutes counter increments
MSF set when seconds counter increments
MSF set when seconds counter increments
When MSF is set logic 1:
• If TI_TP is logic 1, the interrupt is generated as a pulsed signal.
• If TI_TP is logic 0, the interrupt is permanently active signal that remains until MSF is
cleared.
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seconds counter
minutes counter
58
59
59
11
00
12
00
01
INT when SI enabled
MSF when SI enabled
INT when only MI enabled
MSF when only MI enabled
001aaf905
In this example, bit TI_TP is logic 1 and the MSF flag is not cleared after an interrupt.
Fig 26. INT example for SI and MI when TI_TP is logic 1
seconds counter
minutes counter
58 59
59 00
11 12
00 01
INT when SI enable
MSF when SI enable
INT when only MI enabled
MSF when only MI enabled
001aag072
In this example, bit TI_TP is logic 0 and the MSF flag is cleared after an interrupt.
Fig 27. INT example for SI and MI when TI_TP is logic 0
The pulse generator for the minute/second interrupt operates from an internal 64 Hz clock
and generates a pulse of 1⁄64 seconds in duration.
8.13.2 Countdown timer interrupts
The generation of interrupts from the countdown timer is controlled by the CDTIE bit
(register Control_2).
The interrupt may be generated as a pulsed signal at every countdown period or as a
permanently active signal which follows the status of the countdown timer flag CDTF. Bit
TI_TP is used to control this bit.
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8.13.3 INT pulse shortening
The pulse generator for the countdown timer interrupt also uses an internal clock, but this
time it is dependent on the selected source clock for the countdown timer and on the
countdown value n. As a consequence, the width of the interrupt pulse varies (see
Table 55).
Table 55. INT operation (bit TI_TP = 1)
Source clock (Hz)
INT period (s)
n = 1 [1]
n > 1
1
1
4096
64
⁄
⁄
8192
4096
1
1
⁄
⁄
128
64
1
1
1
⁄
⁄
64
64
1
1
1
⁄
⁄
⁄
60
64
64
[1] n = loaded countdown value. Timer stopped when n = 0.
If the MSF or CDTF flag (register Control_2) is cleared before the end of the INT pulse,
then the INT pulse is shortened. This allows the source of a system interrupt to be cleared
immediately when it is serviced, that is, the system does not have to wait for the
completion of the pulse before continuing, see Figure 28 and Figure 29. Instructions for
clearing bit MSF and bit CDTF can be found in Section 8.11.6.
seconds counter
MSF
58
59
INT
(1)
SCL
8th clock
instruction
CLEAR INSTRUCTION
001aaf908
(1) Indicates normal duration of INT pulse.
The timing shown for clearing bit MSF is also valid for the non-pulsed interrupt mode, that is,
when TI_TP is logic 0, where the INT pulse may be shortened by setting both bits MI and SI
logic 0.
Fig 28. Example of shortening the INT pulse by clearing the MSF flag
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countdown counter
01
n
CDTF
INT
(1)
SCL
8th clock
instruction
CLEAR INSTRUCTION
001aaf909
(1) Indicates normal duration of INT pulse.
The timing shown for clearing CDTF is also valid for the non-pulsed interrupt mode, that is, when
TI_TP is logic 0, where the INT pulse may be shortened by setting CDTIE logic 0.
Fig 29. Example of shortening the INT pulse by clearing the CDTF flag
8.13.4 Watchdog timer interrupts
The generation of interrupts from the watchdog timer is controlled using the WD_CD[1:0]
bits (register Watchdg_tim_ctl). The interrupt is generated as an active signal which
follows the status of the watchdog timer flag WDTF (register Control_2). No pulse
generation is possible for watchdog timer interrupts.
The interrupt is cleared when the flag WDTF is reset. WDTF is a read only bit and cannot
be cleared by command. Instructions for clearing it can be found in Section 8.11.6.
8.13.5 Alarm interrupts
Generation of interrupts from the alarm function is controlled by the bit AIE (register
Control_2). If AIE is enabled, the INT pin will follow the status of bit AF (register
Control_2). Clearing AF will immediately clear INT. No pulse generation is possible for
alarm interrupts.
minute counter
minute alarm
AF
44
45
45
INT
SCL
8th clock
instruction
CLEAR INSTRUCTION
001aaf910
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 30. AF timing diagram
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8.13.6 Timestamp interrupts
Interrupt generation from the timestamp function is controlled using the TSIE bit (register
Control_2). If TSIE is enabled, the INT pin follows the status of the flags TSFx. Clearing
the flags TSFx immediately clears INT. No pulse generation is possible for timestamp
interrupts.
8.13.7 Battery switch-over interrupts
Generation of interrupts from the battery switch-over is controlled by the BIE bit (register
Control_3). If BIE is enabled, the INT pin follows the status of bit BF in register Control_3
(see Table 53). Clearing BF immediately clears INT. No pulse generation is possible for
battery switch-over interrupts.
8.13.8 Battery low detection interrupts
Generation of interrupts from the battery low detection is controlled by the BLIE bit
(register Control_3). If BLIE is enabled, the INT pin will follow the status of bit BLF
(register Control_3). The interrupt is cleared when the battery is replaced (BLF is logic 0)
or when bit BLIE is disabled (BLIE is logic 0). BLF is read only and therefore cannot be
cleared by command.
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8.14 External clock test mode
A test mode is available which allows on-board testing. In this mode, it is possible to set
up test conditions and control the operation of the RTC.
The test mode is entered by setting bit EXT_TEST logic 1 (register Control_1). Then
pin CLKOUT becomes an input. The test mode replaces the internal clock signal (64 Hz)
with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT
generate an increment of one second.
The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a
maximum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided
down by a 26 divider chain called prescaler (see Table 56). The prescaler can be set into a
known state by using bit STOP. When bit STOP is logic 1, the prescaler is reset to 0.
STOP must be cleared before the prescaler can operate again.
From a stop condition, the first 1 second increment will take place after 32 positive edges
on pin CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment.
Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When
entering the test mode, no assumption as to the state of the prescaler can be made.
Operating example:
1. Set EXT_TEST test mode (register Control_1, EXT_TEST is logic 1).
2. Set bit STOP (register Control_1, STOP is logic 1).
3. Set time registers to desired value.
4. Clear STOP (register Control_1, STOP is logic 0).
5. Apply 32 clock pulses to CLKOUT.
6. Read time registers to see the first change.
7. Apply 64 clock pulses to CLKOUT.
8. Read time registers to see the second change.
Repeat 7 and 8 for additional increments.
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8.15 STOP bit function
The function of the STOP bit is to allow for accurate starting of the time circuits. STOP will
cause the upper part of the prescaler (F9 to F14) to be held in reset and thus no 1 Hz ticks
are generated. The time circuits can then be set and will not increment until the STOP bit
is released. STOP will not affect the CLKOUT signal but the output of the prescaler in the
range of 32 Hz to 1 Hz (see Figure 31).
The lower stages of the prescaler, F0 to F8, are not reset and because the I2C-bus and the
SPI-bus are asynchronous to the crystal oscillator, the accuracy of restarting the time
circuits is between 0 and one 64 Hz cycle (0.484375 s and 0.500000 s), see Table 56 and
Figure 32.
Table 56. First increment of time circuits after stop release
Bit
Prescaler bits[1]
1 Hz tick
Time
Comment
STOP
F0 to F8 - F9 to F14
hh:mm:ss
Clock is running normally
0
010000111-010100
12:45:12
prescaler counting normally
STOP bit is activated by user. F0 to F8 are not reset and values cannot be predicted externally
1
xxxxxxxxx-000000
12:45:12
prescaler is reset; time circuits are frozen
prescaler is reset; time circuits are frozen
prescaler is now running
New time is set by user
1
xxxxxxxxx-000000
08:00:00
STOP bit is released by user
0
0
0
0
:
xxxxxxxxx-000000
xxxxxxxxx-100000
xxxxxxxxx-100000
xxxxxxxxx-110000
:
08:00:00
08:00:00
08:00:00
08:00:00
:
0
0
0
:
111111111-111110
000000000-000001
100000000-000001
:
08:00:00
08:00:01
08:00:01
:
0 to 1 transition of F14 increments the time circuits
0
0
0
:
111111111-111111
000000000-000000
100000000-000000
:
08:00:01
08:00:01
:
0
0
111111111-111110
000000000-000001
08:00:01
08:00:02
0 to 1 transition of F14 increments the time circuits
001aaj479
[1] F0 is clocked at 32.768 kHz.
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LOWER PRESCALER
UPPER PRESCALER
128 Hz
32768 Hz
16384 Hz
8192 Hz
4096 Hz
64 Hz
F
0
F
F
F
F
F
F
F
14
1
2
8
9
10
13
1 Hz tick
OSC
RES
RES
RES
RES
stop
001aaj342
Fig 31. STOP bit functional diagram
64 Hz
stop released
0 ms - 15.625 ms
001aaj343
Fig 32. STOP bit release timing
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9. Interfaces
The PCF2127AT has an I2C-bus or SPI-bus interface using the same pins. The selection
is done by using the interface selection pin IFS (see Table 57).
Table 57. Interface selection input pin IFS
Pin
Connection
VSS
Bus interface
Reference
Section 9.1
Section 9.2
IFS
SPI-bus
I2C-bus
BBS
V
V
DD
DD
SCL
SDI
R
PU
R
PU
SCL
SDA
SDO
CE
V
SCL
DD
1
20
19
18
17
16
15
14
13
12
11
V
SCL
SDI
DD
1
2
3
4
5
6
7
8
9
20
SDI
2
3
4
5
6
7
8
9
19
SDO
BBS
SDO
BBS
18
17
16
15
14
13
12
11
SDA/CE
IFS
SDA/CE
IFS
PCF2127AT
PCF2127AT
V
SS
V
SS
10
10
V
SS
V
SS
001aaj679
001aaj680
To select the SPI-bus interface, pin IFS has to be
connected to pin VSS
To select the I2C-bus interface, pin IFS has to be
connected to pin BBS.
.
a. SPI-bus interface selection
b. I2C-bus interface selection
Fig 33. Interface selection
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9.1 SPI-bus interface
Data transfer to and from the device is made by a 3 line SPI-bus (see Table 58). The data
lines for input and output are split. The data input and output line can be connected
together to facilitate a bidirectional data bus (see Figure 34). The SPI-bus is initialized
whenever the chip enable line pin SDA/CE is inactive.
SDI
SDI
SDO
SDO
two wire mode
single wire mode
001aai560
Fig 34. SDI, SDO configurations
Table 58. Serial interface
Symbol
Function
Description
[1]
SDA/CE
chip enable input;
active LOW
when HIGH, the interface is reset;
input may be higher than VDD
SCL
SDI
serial clock input
when SDA/CE is HIGH, input may float;
input may be higher than VDD
serial data input
when SDA/CE is HIGH, input may float;
input may be higher than VDD
;
input data is sampled on the rising edge of SCL
push-pull output;
SDO
serial data output
drives from VSS to VBBS
;
output data is changed on the falling edge of SCL
[1] The chip enable must not be wired permanently LOW.
9.1.1 Data transmission
The chip enable signal is used to identify the transmitted data. Each data transfer is a
whole byte, with the Most Significant Bit (MSB) sent first.
The transmission is controlled by the active LOW chip enable signal SDA/CE. The first
byte transmitted is the command byte. Subsequent bytes will be either data to be written
or data to be read (see Figure 35).
data bus
SDA/CE
COMMAND
DATA
DATA
DATA
013aaa311
Fig 35. Data transfer overview
The command byte defines the address of the first register to be accessed and the
read/write mode. The address counter will auto increment after every access and will
reset to zero after the last valid register is accessed. The R/W bit defines if the following
bytes will be read or write information.
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Table 59. Command byte definition
Bit
Symbol
Value
Description
7
R/W
data read or write selection
write data
0
1
read data
6 to 5
4 to 0
SA
01
subaddress;
other codes will cause the device to ignore data
transfer
RA
00h to 1Dh register address
R/W
SA
addr 03h
seconds data 45
minutes data 10
BCD
BCD
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
SCL
SDI
SDA/CE
address
counter
xx
03
04
05
001aaj348
In this example, the Seconds register is set to 45 seconds and the Minutes register to 10 minutes.
Fig 36. SPI-bus write example
R/W
SA
addr 08h
months data 11
years data 06
BCD
BCD
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
0
SCL
SDI
SDO
SDA/CE
address
counter
xx
08
09
0A
001aaj349
In this example, the registers Months and Years are read. The pins SDI and SDO are not connected together. For this
configuration, it is important that pin SDI is never left floating. It must always be driven either HIGH or LOW. If pin SDI is left
open, high IDD currents may result.
Fig 37. SPI-bus read example
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9.2 I2C-bus interface
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines are
connected to a positive supply by a pull-up resistor. Data transfer is initiated only when the
bus is not busy.
9.2.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line remains
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as control signals (see Figure 38).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mbc621
Fig 38. Bit transfer
9.2.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is defined as the START condition S. A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition P (see Figure 39).
SDA
SCL
SDA
SCL
S
P
START condition
STOP condition
mbc622
Fig 39. Definition of START and STOP conditions
Remark: For the PCF2127AT, a repeated START is not allowed. Therefore a STOP has
to be released before the next START.
9.2.3 System configuration
A device generating a message is a transmitter; a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves.
The PCF2127AT can act as a slave transmitter and a slave receiver.
PCF2127AT
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SDA
SCL
MASTER
TRANSMITTER
RECEIVER
SLAVE
TRANSMITTER
RECEIVER
MASTER
MASTER
SLAVE
RECEIVER
TRANSMITTER
TRANSMITTER
RECEIVER
mba605
Fig 40. System configuration
9.2.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is illustrated in Figure 41.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
Fig 41. Acknowledgement on the I2C-bus
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9.2.5 I2C-bus protocol
After a start condition, a valid hardware address has to be sent to a PCF2127AT device.
The appropriate I2C-bus slave address is 1010001. The entire I2C-bus slave address byte
is shown in Table 60.
Table 60. I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
0
MSB
LSB
R/W
1
0
1
0
0
0
1
The R/W bit defines the direction of the following single or multiple byte data transfer (read
is logic 1, write is logic 0).
For the format and the timing of the START condition (S), the STOP condition (P), and the
acknowledge bit (A) refer to the I2C-bus specification Ref. 11 “UM10204” and the
characteristics table (Table 65). In the write mode, a data transfer is terminated by sending
either a STOP condition or the START condition of the next data transfer.
acknowledge
acknowledge
acknowledge
from PCF2127AT
from PCF2127AT
from PCF2127AT
S
1
0
1
0
0
0
1
0
A
A
A
P/S
slave address
register address
00h to 1Dh
0 to n
data bytes
write bit
START/
STOP
001aaj719
Fig 42. Bus protocol, writing to registers
acknowledge
acknowledge
from PCF2127AT
from PCF2127AT
set register
address
S
1
0
1
0
0
0
1
0
A
A
P
slave address
register address
00h to 1Dh
write bit
STOP
acknowledge
from PCF2127AT
acknowledge
from master
no acknowledge
LAST DATA BYTE
read register
data
S
1
0
1
0
0
0
1
1
A
DATA BYTE
A
A
P
slave address
0 to n data bytes
read bit
001aaj721
Fig 43. Bus protocol, reading from registers
PCF2127AT
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PCF2127AT
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Integrated RTC, TCXO and quartz crystal
acknowledge
acknowledge
from PCF2127AT
from PCF2127AT
S
1
0
1
0
0
0
1
0
A
register address 1Ah
A
slave address
write bit
set RAM
address
acknowledge
acknowledge
from PCF2127AT
from PCF2127AT
data byte 1Ah
A
data byte 1Bh
A
acknowledge
acknowledge
from PCF2127AT
from PCF2127AT
RAM write
command
P/S
1
0
1
0
0
0
1
0
A
register address 1Ch
A
slave address
write bit
acknowledge
from PCF2127AT
write data
to RAM
data byte (RAM address)
A
P
0 to n
data bytes
001aaj720
Fig 44. Bus protocol, writing to RAM
PCF2127AT
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PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
acknowledge
acknowledge
from PCF2127AT
from PCF2127AT
S
1
0
1
0
0
0
1
0
A
register address 1Ah
A
slave address
write bit
set RAM
address
acknowledge
acknowledge
from PCF2127AT
from PCF2127AT
data byte 1Ah
A
data byte 1Bh
A
acknowledge
from PCF2127AT
acknowledge
from PCF2127AT
RAM
read command
P/S
1
0
1
0
0
0
1
0
A
register address 1Dh
A
slave address
write bit
acknowledge
from PCF2127AT
acknowledge
from master
P/S
1
0
1
0
0
0
1
1
A
data byte
A
read data
from RAM
slave address
0 to n
data bytes
read bit
no acknowledge
last data byte
A
P
001aaj722
Fig 45. Bus protocol, reading from RAM
PCF2127AT
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PCF2127AT
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Integrated RTC, TCXO and quartz crystal
10. Internal circuitry
V
V
DD
SCL
SDI
BAT
BBS
SDO
INT
RST
PFI
SDA/CE
IFS
TS
CLKOUT
PFO
V
SS
TEST
PCF2127AT
001aaj677
Fig 46. Device diode protection diagram of PCF2127AT
11. Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
PCF2127AT
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Integrated RTC, TCXO and quartz crystal
12. Limiting values
Table 61. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
0.5
50
0.5
10
0.5
10
10
0.5
-
Max
+6.5
+50
Unit
V
VDD
IDD
Vi
supply voltage
supply current
input voltage
input current
output voltage
output current
mA
V
+6.5
+10
II
mA
V
VO
IO
+6.5
+10
mA
mA
V
at pin SDA/CE
+20
VBAT
Ptot
battery supply voltage
total power dissipation
+6.5
300
mW
V
[1]
[2]
[3]
[4]
VESD
electrostatic discharge
voltage
HBM
CDM
-
3500
1250
200
-
V
Ilu
latch-up current
-
mA
C
C
Tstg
Tamb
storage temperature
ambient temperature
55
40
+85
operating device
+85
[1] Pass level; Human Body Model (HBM) according to Ref. 7 “JESD22-A114”.
[2] Pass level; Charged-Device Model (CDM), according to Ref. 8 “JESD22-C101”.
[3] Pass level; latch-up testing according to Ref. 9 “JESD78” at maximum ambient temperature (Tamb(max)).
[4] According to the store and transport requirements (see Ref. 12 “UM10569”) the devices have to be stored
at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %.
PCF2127AT
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NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
13. Static characteristics
Table 62. Static characteristics
VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
[1]
supply voltage
1.8
1.8
-
-
4.2
4.2
-
V
V
V
V
VBAT
battery supply voltage
calibration supply voltage
low voltage
-
VDD(cal)
Vlow
3.3
1.2
-
-
IDD
supply current
interface active;
supplied by VDD
SPI-bus (fSCL = 6.5 MHz)
I2C-bus (fSCL = 400 kHz)
-
-
-
-
800
200
A
A
interface inactive (fSCL = 0 Hz)[2];
TCR[1:0] = 00 (see Table 9 on page 13)
PWRMNG[2:0] = 111 (see Table 18 on page 18);
TSOFF = 1 (see Table 46 on page 44);
COF[2:0] = 111 (see Table 11 on page 14)
VDD = 2.0 V
VDD = 3.3 V
VDD = 4.2 V
-
-
-
500
700
800
-
nA
nA
nA
1500
-
PWRMNG[2:0] = 111 (see Table 18 on page 18);
TSOFF = 1 (see Table 46 on page 44);
COF[2:0] = 000 (see Table 11 on page 14)
VDD = 2.0 V
VDD = 3.3 V
VDD = 4.2 V
-
-
-
600
-
-
-
nA
nA
nA
850
1050
PWRMNG[2:0] = 000 (see Table 18 on page 18);
TSOFF = 0 (see Table 46 on page 44);
COF[2:0] = 111 (see Table 11 on page 14)
[3]
VDD or VBAT = 2.0 V
VDD or VBAT = 3.3 V
VDD or VBAT = 4.2 V
-
-
-
1800
2150
2350
-
nA
nA
nA
[3]
[3]
-
3500
PWRMNG[2:0] = 000 (see Table 18 on page 18);
TSOFF = 0 (see Table 46 on page 44);
COF[2:0] = 000 (see Table 11 on page 14)
[3]
VDD or VBAT = 2.0 V
VDD or VBAT = 3.3 V
VDD or VBAT = 4.2 V
-
-
-
-
1900
2300
2600
50
-
nA
nA
nA
nA
[3]
[3]
-
-
IL(bat)
battery leakage current
VDD is active supply;
VBAT = 3.0 V
100
PCF2127AT
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Integrated RTC, TCXO and quartz crystal
Table 62. Static characteristics …continued
VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Power management
Vth(sw)bat
battery switch threshold
-
2.5
-
V
voltage
Vth(bat)low
Vth(PFI)
Inputs[4]
VI
low battery threshold voltage
threshold voltage on pin PFI
-
-
2.5
-
-
V
V
1.25
input voltage
0.5
-
-
-
VDD + 0.5
0.25VDD
0.3VDD
V
V
V
VIL
LOW-level input voltage
-
-
Tamb = 20 C to +85 C;
VDD > 2.0 V
VIH
ILI
HIGH-level input voltage
input leakage current
0.7VDD
-
-
V
VI = VDD or VSS
post ESD event
-
0
-
-
A
A
pF
1
-
+1
7
[5]
Ci
input capacitance
output voltage
-
Outputs
VO
on pins CLKOUT, INT, RST,
PFO, referring to external pull-up
0.5
0.5
-
-
5.5
V
on pin SDO
V
BBS + 0.5 V
IOL
LOW-level output current
output sink current;
VOL = 0.4 V
[6]
on pin SDA/CE
3
17
-
-
-
-
mA
mA
mA
on all other outputs
1.0
1.0
IOH
HIGH-level output current
output leakage current
output source current;
on pin SDO; VOH = 3.8 V;
VDD = 4.2 V
-
ILO
VO = VDD or VSS
post ESD event
-
0
-
-
A
A
1
+1
[1] For reliable oscillator start-up at power-on: VDD(po)min = VDD(min) + 0.3 V.
[2] Timer source clock = 1
60 Hz, level of pins SDA/CE, SDI, and SCL is VDD or VSS
⁄
.
[3] When the device is supplied by the VBAT pin instead of the VDD pin, the current values for IBAT will be as specified for IDD under the same
conditions.
[4] The I2C-bus and the SPI-bus interface of PCF2127AT are 5 V tolerant.
[5] Tested on sample basis.
[6] For further information, see Figure 47.
PCF2127AT
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Integrated RTC, TCXO and quartz crystal
13.1 Current consumption characteristics, typical
001aal763
22
I
OL
(mA)
18
14
10
6
1.5
2.5
3.5
4.5
V
(V)
DD
Typical value; VOL = 0.4 V.
Fig 47. IOL on pin SDA/CE
001aaj432
2.0
I
DD
(μA)
1.6
1.2
0.8
0.4
0
V
V
= 3 V
= 2 V
DD
DD
−40
−20
0
20
40
60
80
100
Temperature (°C)
CLKOUT disabled; PWRMNG[2:0] = 111; TSOFF = 1; TS input floating.
Fig 48. IDD as a function of temperature
PCF2127AT
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PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
001aaj433
2.0
I
DD
(μA)
1.6
1.2
0.8
0.4
0
CLKOUT enabled at
32 kHz
CLKOUT OFF
1.8
2.2
2.6
3.0
3.4
3.8
4.2
V
(V)
DD
a. PWRMNG[2:0] = 111; TSOFF = 1; Tamb = 25 C; TS input floating
001aaj434
4.0
I
DD
(μA)
3.2
CLKOUT enabled at
32 kHz
2.4
1.6
0.8
0
CLKOUT OFF
1.8
2.2
2.6
3.0
3.4
3.8
4.2
V
(V)
DD
b. PWRMNG[2:0] = 000; TSOFF = 0; Tamb = 25 C; TS input floating
Fig 49. IDD as a function of VDD
PCF2127AT
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NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
13.2 Frequency characteristics
Table 63. Frequency characteristics
VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = +25 C, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
fo
output frequency
on pin CLKOUT;
-
32.768
-
kHz
VDD or VBAT = 3.3 V;
COF[2:0] = 000;
AO[3:0] = 1000
f/f
frequency stability
V
DD or VBAT = 3.3 V
[1][2]
[1][2]
Tamb = 15 C to +60 C
-
-
3
5
5
ppm
ppm
Tamb = 25 C to 15 C
and
10
Tamb = +60 C to +65 C
[3]
fxtal/fxtal relative crystal frequency variation crystal aging, first year;
-
-
-
3
ppm
VDD or VBAT = 3.3 V
f/V
frequency variation with voltage
on pin CLKOUT
1
-
ppm/V
[1] 1 ppm corresponds to a time deviation of 0.0864 seconds per day.
[2] Only valid if CLKOUT frequencies are not equal to 32.768 kHz or if CLKOUT is disabled.
[3] Not production tested. Effects of reflow soldering are not included (see Ref. 3 “AN10857”).
013aaa593
40
Frequency
stability
(ppm)
± 5 ppm
± 5 ppm
± 3 ppm
0
-40
-80
(1)
(2)
-40
-20
0
20
40
60
80
100
Temperature (°C)
(1) Typical temperature compensated frequency response.
(2) Uncompensated typical tuning-fork crystal frequency.
Fig 50. Typical characteristic of frequency with respect to temperature
PCF2127AT
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Integrated RTC, TCXO and quartz crystal
14. Dynamic characteristics
14.1 SPI-bus timing characteristics
Table 64. SPI-bus characteristics
DD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = 40 C to +85 C, unless otherwise specified. All timing values are valid within the
operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS to VDD
V
.
Symbol
Parameter
Conditions
VDD = 1.8 V
VDD = 4.2 V
Unit
Min
Max
Min
Max
Pin SCL
fclk(SCL)
SCL clock frequency
SCL time
register read/write access
RAM write access
RAM read access
-
2.0
-
6.5
MHz
MHz
MHz
ns
-
2.0
-
6.5
-
1.11
-
6.25
tSCL
register read/write access
RAM write access
RAM read access
800
800
900
100
100
450
400
400
450
-
-
140
140
160
70
70
80
70
70
80
-
-
-
-
ns
-
-
ns
tclk(H)
clock HIGH time
clock LOW time
register read/write access
RAM write access
RAM read access
-
-
ns
-
-
ns
-
-
ns
tclk(L)
register read/write access
RAM write access
RAM read access
-
-
ns
-
-
ns
-
-
ns
tr
rise time
fall time
for SCL signal
100
100
100
100
ns
tf
for SCL signal
-
-
ns
Pin SDA/CE
tsu(CE_N)
th(CE_N)
trec(CE_N)
tw(CE_N)
Pin SDI
tsu
CE_N set-up time
CE_N hold time
60
40
100
-
-
30
25
30
-
-
ns
ns
ns
s
-
-
CE_N recovery time
CE_N pulse width
-
-
0.99
0.99
set-up time
hold time
set-up time for SDI data
hold time for SDI data
70
70
-
-
20
20
-
-
ns
ns
th
Pin SDO
td(R)SDO
SDO read delay time
CL = 50 pF
register read access
-
225
410
90
-
-
55
55
25
-
ns
ns
ns
ns
RAM read access
-
-
[1]
tdis(SDO)
SDO disable time
-
-
tt(SDI-SDO) transition time from SDI to
SDO
to avoid bus conflict
0
0
[1] No load value; bus will be held up by bus capacitance; use RC time constant with application values.
PCF2127AT
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Integrated RTC, TCXO and quartz crystal
t
w(CE_N)
CE
t
rec(CE_N)
t
t
r
su(CE_N)
t
t
t
h(CE_N)
f
clk(SCL)
80%
SCL
20%
t
clk(L)
t
clk(H)
WRITE
t
su
t
h
SDI
R/W
SA2
RA0
b7
b6
b0
high-Z
SDO
READ
SDI
b7
b6
b0
t
t(SDI-SDO)
t
d(R)SDO
t
dis(SDO)
high-Z
SDO
b7
b6
b0
013aaa152
Fig 51. SPI-bus timing
PCF2127AT
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Integrated RTC, TCXO and quartz crystal
14.2 I2C interface timing characteristics
Table 65. I2C-bus characteristics
All timing characteristics are valid within the operating supply voltage and ambient temperature
range and reference to 30 % and 70 % with an input voltage swing of VSS to VDD (see Figure 52).
Symbol Parameter
Standard mode
Fast-mode (Fm)
Unit
Min
Max
Min
Max
Pin SCL
[1]
fSCL
SCL clock frequency
0
100
-
0
400
-
kHz
tLOW
LOW period of the SCL
clock
4.7
1.3
s
tHIGH
HIGH period of the SCL
clock
4.0
-
0.6
-
s
Pin SDA/CE
tSU;DAT data set-up time
tHD;DAT data hold time
Pins SCL and SDA/CE
250
0
-
-
100
0
-
-
ns
ns
tBUF
bus free time between a
4.7
-
1.3
-
s
STOP and START
condition
tSU;STO set-up time for STOP
condition
4.0
4.0
4.7
-
-
-
0.6
0.6
0.6
-
-
-
s
s
s
tHD;STA hold time (repeated)
START condition
tSU;STA set-up time for a
repeated START
condition
[2][3][4]
[2][3][4]
[5]
tr
rise time of both SDA
and SCL signals
-
1000
300
20 + 0.1Cb 300
20 + 0.1Cb 300
ns
ns
s
tf
fall time of both SDA and
SCL signals
-
tVD;ACK data valid acknowledge
time
0.1
3.45
0.1
0.9
[6]
[7]
tVD;DAT data valid time
300
-
-
75
-
-
ns
ns
tSP
pulse width of spikes
that must be suppressed
by the input filter
50
50
[1] The minimum SCL clock frequency is limited by the bus time-out feature which resets the serial bus
interface if either the SDA or SCL is held LOW for a minimum of 25 ms. The bus time-out feature must be
disabled for DC operation.
[2] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of
the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
[3] Cb is the total capacitance of one bus line in pF.
[4] The maximum tf for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage,
tf is 250 ns. This allows series protection resistors to be connected between the SDA/CE pin, the SCL pin,
and the SDA/SCL bus lines without exceeding the maximum tf.
[5] tVD;ACK is the time of the acknowledgement signal from SCL LOW to SDA (out) LOW.
[6]
tVD;DAT is the minimum time for valid SDA (out) data following SCL LOW.
[7] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
PCF2127AT
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Product data sheet
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PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
BIT 0
LSB
(R/W)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
PROTOCOL
t
t
t
SU;STA
LOW
HIGH
1 / f
SCL
SCL
SDA
t
t
t
BUF
r
f
t
t
t
t
t
HD;STA
SU;DAT
HD;DAT
VD;DAT
SU;STO
mbd820
Fig 52. I2C-bus timing diagram; rise and fall times refer to 30 % and 70 %
15. Application information
For information about application configuration, see Ref. 3 “AN10857”.
PCF2127AT
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Product data sheet
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PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
16. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 53. Package outline SOT163-1 (SO20)
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
75 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
17. Packing information
17.1 Carrier tape information
TOP VIEW
P0
Ø D0
W
B0
A0
K0
P1
direction of feed
Ø D1
Original dimensions are in mm.
Figure not drawn to scale.
013aaa699
Fig 54. Tape and reel details for PCF2127AT
Table 66. Carrier tape dimensions of PCF2127AT
Symbol
Description
Value
Unit
Compartments
A0
B0
K0
P1
D1
pocket width in x direction
pocket width in y direction
pocket depth
10.8 to 10.9
13.3 to 13.4
2.70 to 2.85
12.0
mm
mm
mm
mm
mm
pocket hole pitch
pocket hole diameter
1.5 to 2.05
Overall dimensions
W
tape width
24.0
mm
mm
mm
D0
P0
sprocket hole diameter
sprocket hole pitch
1.5 to 1.55
4.0
18. Soldering
For information about soldering, see Ref. 3 “AN10857”.
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
76 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
19. Footprint information
13.40
0.60 (20×)
1.50
8.00 11.00 11.40
1.27 (18×)
solder lands
sot163-1_fr
occupied area
placement accuracy 0.25
Dimensions in mm
Fig 55. Footprint information for reflow soldering of SO20 package
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
77 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
20. Abbreviations
Table 67. Abbreviations
Acronym
AM
Description
Ante Meridiem
BCD
CDM
CMOS
DC
Binary Coded Decimal
Charged Device Model
Complementary Metal-Oxide Semiconductor
Direct Current
GPS
HBM
I2C
Global Positioning System
Human Body Model
Inter-Integrated Circuit
Integrated Circuit
IC
LSB
Least Significant Bit
MCU
MSB
PM
Microcontroller Unit
Most Significant Bit
Post Meridiem
POR
PORO
PPM
RAM
RC
Power-On Reset
Power-On Reset Override
Parts Per Million
Random Access Memory
Resistance-Capacitance
Real Time Clock
RTC
SCL
SDA
SPI
Serial CLock line
Serial DAta line
Serial Peripheral Interface
Static Random Access Memory
Temperature Compensated Xtal Oscillator
crystal
SRAM
TCXO
Xtal
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
78 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
21. References
[1] AN10365 — Surface mount reflow soldering description
[2] AN10853 — Handling precautions of ESD sensitive devices
[3] AN10857 — Application and soldering information for PCF2127A and PCF2129A
TCXO RTC
[4] IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[6] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices
[7] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[8] JESD22-C101 — Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[9] JESD78 — IC Latch-Up Test
[10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[11] UM10204 — I2C-bus specification and user manual
[12] UM10569 — Store and transport requirements
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
79 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
22. Revision history
Table 68. Revision history
Document ID
PCF2127AT v.6
Modifications:
PCF2127AT v.5
PCF2127AT v.4
PCF2127AT v.3
PCF2127A v.2
PCF2127A v.1
Release date
20130711
Data sheet status
Change notice
Supersedes
Product data sheet
-
PCF2127AT v.5
• Adjusted rise and fall time values of the SPI-bus in Table 64
20130128
20121207
20121004
20100507
20100121
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
-
-
-
-
-
PCF2127AT v.4
PCF2127AT v.3
PCF2127A v.2
PCF2127A v.1
-
PCF2127AT
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Product data sheet
Rev. 6 — 11 July 2013
80 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
23. Legal information
23.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
23.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
23.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
81 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
23.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
I2C-bus — logo is a trademark of NXP B.V.
24. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCF2127AT
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Product data sheet
Rev. 6 — 11 July 2013
82 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
25. Tables
Table 1. Ordering information. . . . . . . . . . . . . . . . . . . . . .2
Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2
Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 4. Pin description of SO20 (PCF2127AT) . . . . . . .4
Table 5. Register overview . . . . . . . . . . . . . . . . . . . . . . .8
Table 6. Control_1 - control and status register 1
(address 00h) bit description . . . . . . . . . . . . . .10
Table 7. Control_2 - control and status register 2
(address 01h) bit description . . . . . . . . . . . . . .11
Table 8. Control_3 - control and status register 3
(address 02h) bit description . . . . . . . . . . . . . .12
Table 9. CLKOUT_ctl - CLKOUT control register
(address 0Fh) bit description . . . . . . . . . . . . . .13
Table 10. Temperature measurement period . . . . . . . . . .13
Table 11. CLKOUT frequency selection. . . . . . . . . . . . . .14
Table 12. Aging_offset - crystal aging offset register
(address 19h) bit description . . . . . . . . . . . . . .15
Table 13. Frequency correction at 25 °C, typical . . . . . . .15
Table 14. RAM_addr_MSB - RAM address MSB register
(address 1Ah) bit description . . . . . . . . . . . . . .16
Table 15. RAM_addr_LSB - RAM address LSB register
(address 1Bh) bit description . . . . . . . . . . . . . .16
Table 16. RAM_wrt_cmd - RAM write command register
(address 1Ch) bit description . . . . . . . . . . . . . .16
Table 17. RAM_rd_cmd - RAM read command register
(address 1Dh) bit description . . . . . . . . . . . . . .16
Table 18. Power management control bit description . . .18
Table 19. Output pin BBS. . . . . . . . . . . . . . . . . . . . . . . . .22
Table 20. Seconds - seconds and clock integrity
register (address 03h) bit description . . . . . . . .30
Table 21. Seconds coded in BCD format . . . . . . . . . . . .30
Table 22. Minutes - minutes register (address 04h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 23. Hours - hours register (address 05h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 24. Days - days register (address 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 25. Weekdays - weekdays register (address 07h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 26. Weekday assignments . . . . . . . . . . . . . . . . . . .31
Table 27. Months - months register (address 08h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 28. Month assignments in BCD format. . . . . . . . . .32
Table 29. Years - years register (address 09h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 30. Second_alarm - second alarm register
(address 0Ah) bit description . . . . . . . . . . . . . .34
Table 31. Minute_alarm - minute alarm register
register (address 10h) bit description . . . . . . . 37
Table 36. Watchdg_tim_val - watchdog timer value
register (address 11h) bit description. . . . . . . . 38
Table 37. Programmable watchdog or countdown timer . 38
Table 38. Specification of tw(rst) . . . . . . . . . . . . . . . . . . . . 40
Table 39. First period delay for timer counter . . . . . . . . . 41
Table 40. Flag location in register Control_2 . . . . . . . . . . 41
Table 41. Example values in register Control_2 . . . . . . . 42
Table 42. Example to clear only CDTF (bit 3) . . . . . . . . . 42
Table 43. Example to clear only AF (bit 4). . . . . . . . . . . . 42
Table 44. Example to clear only MSF (bit 7) . . . . . . . . . . 42
Table 45. Example to clear both CDTF and MSF . . . . . . 42
Table 46. Timestp_ctl - timestamp control register
(address 12h) bit description . . . . . . . . . . . . . . 44
Table 47. Sec_timestp - second timestamp register
(address 13h) bit description . . . . . . . . . . . . . . 44
Table 48. Min_timestp - minute timestamp register
(address 14h) bit description . . . . . . . . . . . . . . 44
Table 49. Hour_timestp - hour timestamp register
(address 15h) bit description . . . . . . . . . . . . . . 45
Table 50. Day_timestp - day timestamp register
(address 16h) bit description . . . . . . . . . . . . . . 45
Table 51. Mon_timestp - month timestamp register
(address 17h) bit description . . . . . . . . . . . . . . 45
Table 52. Year_timestp - year timestamp register
(address 18h) bit description . . . . . . . . . . . . . . 45
Table 53. Battery switch-over and timestamp . . . . . . . . . 46
Table 54. Effect of bits MI and SI on pin INT and bit
MSF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 55. INT operation (bit TI_TP = 1) . . . . . . . . . . . . . . 50
Table 56. First increment of time circuits after stop
release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 57. Interface selection input pin IFS. . . . . . . . . . . . 56
Table 58. Serial interface. . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 59. Command byte definition . . . . . . . . . . . . . . . . . 58
Table 60. I2C slave address byte. . . . . . . . . . . . . . . . . . . 61
Table 61. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 62. Static characteristics . . . . . . . . . . . . . . . . . . . . 66
Table 63. Frequency characteristics . . . . . . . . . . . . . . . . 70
Table 64. SPI-bus characteristics . . . . . . . . . . . . . . . . . . 71
Table 65. I2C-bus characteristics. . . . . . . . . . . . . . . . . . . 73
Table 66. Carrier tape dimensions of PCF2127AT . . . . . 76
Table 67. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 68. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 80
(address 0Bh) bit description . . . . . . . . . . . . . .35
Table 32. Hour_alarm - hour alarm register
(address 0Ch) bit description . . . . . . . . . . . . . .35
Table 33. Day_alarm - day alarm register
(address 0Dh) bit description . . . . . . . . . . . . . .35
Table 34. Weekday_alarm - weekday alarm register
(address 0Eh) bit description . . . . . . . . . . . . . .36
Table 35. Watchdg_tim_ctl - watchdog timer control
PCF2127AT
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
83 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
26. Figures
Fig 1. Block diagram of PCF2127AT . . . . . . . . . . . . . . . .3
Fig 2. Pin configuration for SO20 (PCF2127AT) . . . . . . .4
Fig 3. Handling address registers . . . . . . . . . . . . . . . . . .6
Fig 4. Battery switch-over behavior in standard mode
with bit BIE set logic 1 (enabled) . . . . . . . . . . . . .20
Fig 5. Battery switch-over behavior in direct switching
mode with bit BIE set logic 1 (enabled) . . . . . . . .21
Fig 6. Battery switch-over circuit, simplified block
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Fig 37. SPI-bus read example. . . . . . . . . . . . . . . . . . . . . 58
Fig 38. Bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Fig 39. Definition of START and STOP conditions . . . . . 59
Fig 40. System configuration. . . . . . . . . . . . . . . . . . . . . . 60
Fig 41. Acknowledgement on the I2C-bus. . . . . . . . . . . . 60
Fig 42. Bus protocol, writing to registers. . . . . . . . . . . . . 61
Fig 43. Bus protocol, reading from registers . . . . . . . . . . 61
Fig 44. Bus protocol, writing to RAM. . . . . . . . . . . . . . . . 62
Fig 45. Bus protocol, reading from RAM. . . . . . . . . . . . . 63
Fig 46. Device diode protection diagram of PCF2127AT 64
Fig 47. IOL on pin SDA/CE . . . . . . . . . . . . . . . . . . . . . . . 68
Fig 48. IDD as a function of temperature . . . . . . . . . . . . . 68
Fig 49. IDD as a function of VDD. . . . . . . . . . . . . . . . . . . . 69
Fig 50. Typical characteristic of frequency with respect
to temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Fig 7. Typical driving capability of VBBS: (VBBS - VDD
)
with respect to the output load current IBBS . . . . .23
Fig 8. Battery low detection behavior with bit BLIE set
logic 1 (enabled) . . . . . . . . . . . . . . . . . . . . . . . . .24
Fig 9. Typical application of the extra power fail
detection function. . . . . . . . . . . . . . . . . . . . . . . . .24
Fig 10. PFO signal behavior when battery switch-over
is enabled in standard mode and
Vth(uvp) > (VBAT, Vth(sw)bat). . . . . . . . . . . . . . . . . . .25
Fig 11. PFO signal behavior when battery switch-over is
enabled in direct switching mode and
Fig 51. SPI-bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Fig 52. I2C-bus timing diagram; rise and fall times refer
to 30 % and 70 % . . . . . . . . . . . . . . . . . . . . . . . . 74
Fig 53. Package outline SOT163-1 (SO20) . . . . . . . . . . 75
Fig 54. Tape and reel details for PCF2127AT . . . . . . . . . 76
Fig 55. Footprint information for reflow soldering of
Vth(uvp) < VBAT. . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Fig 12. PFO signal behavior when battery switch-over is
disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Fig 13. Power failure event due to battery discharge:
reset occurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Fig 14. Dependency between POR and oscillator . . . . . .28
Fig 15. Power-On Reset (POR) system. . . . . . . . . . . . . .29
Fig 16. Power-On Reset Override (PORO) sequence,
valid for both I2C-bus and SPI-bus . . . . . . . . . . .29
Fig 17. Data flow of the time function. . . . . . . . . . . . . . . .33
Fig 18. Access time for read/write operations . . . . . . . . .33
Fig 19. Alarm function block diagram. . . . . . . . . . . . . . . .34
Fig 20. Alarm flag timing diagram . . . . . . . . . . . . . . . . . .36
Fig 21. WD_CD[1:0] = 10: watchdog activates an
interrupt when timed out . . . . . . . . . . . . . . . . . . .39
Fig 22. WD_CD[1:0] = 11: watchdog activates a reset
pulse when timed out. . . . . . . . . . . . . . . . . . . . . .39
Fig 23. General countdown timer behavior . . . . . . . . . . .40
Fig 24. Timestamp detection with two push-buttons
on the TS pin (for example, for tamper detection)43
Fig 25. Interrupt block diagram . . . . . . . . . . . . . . . . . . . .47
Fig 26. INT example for SI and MI when TI_TP is
logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Fig 27. INT example for SI and MI when TI_TP is
logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Fig 28. Example of shortening the INT pulse by
SO20 package . . . . . . . . . . . . . . . . . . . . . . . . . . 77
clearing the MSF flag. . . . . . . . . . . . . . . . . . . . . .50
Fig 29. Example of shortening the INT pulse by
clearing the CDTF flag. . . . . . . . . . . . . . . . . . . . .51
Fig 30. AF timing diagram . . . . . . . . . . . . . . . . . . . . . . . .51
Fig 31. STOP bit functional diagram . . . . . . . . . . . . . . . .55
Fig 32. STOP bit release timing. . . . . . . . . . . . . . . . . . . .55
Fig 33. Interface selection . . . . . . . . . . . . . . . . . . . . . . . .56
Fig 34. SDI, SDO configurations . . . . . . . . . . . . . . . . . . .57
Fig 35. Data transfer overview. . . . . . . . . . . . . . . . . . . . .57
Fig 36. SPI-bus write example. . . . . . . . . . . . . . . . . . . . .58
PCF2127AT
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
84 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
27. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
8.8.1
8.8.2
8.9
Power-On Reset (POR) . . . . . . . . . . . . . . . . . 28
Power-On Reset Override (PORO) . . . . . . . . 28
Time and date function. . . . . . . . . . . . . . . . . . 30
Register Seconds. . . . . . . . . . . . . . . . . . . . . . 30
Register Minutes . . . . . . . . . . . . . . . . . . . . . . 30
Register Hours. . . . . . . . . . . . . . . . . . . . . . . . 31
Register Days . . . . . . . . . . . . . . . . . . . . . . . . 31
Register Weekdays . . . . . . . . . . . . . . . . . . . . 31
Register Months. . . . . . . . . . . . . . . . . . . . . . . 32
Register Years . . . . . . . . . . . . . . . . . . . . . . . . 32
Setting and reading the time . . . . . . . . . . . . . 32
Alarm function . . . . . . . . . . . . . . . . . . . . . . . . 34
Register Second_alarm . . . . . . . . . . . . . . . . . 34
Register Minute_alarm. . . . . . . . . . . . . . . . . . 35
Register Hour_alarm . . . . . . . . . . . . . . . . . . . 35
Register Day_alarm . . . . . . . . . . . . . . . . . . . . 35
Register Weekday_alarm. . . . . . . . . . . . . . . . 36
Alarm flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Timer functions. . . . . . . . . . . . . . . . . . . . . . . . 37
Register Watchdg_tim_ctl . . . . . . . . . . . . . . . 37
Register Watchdg_tim_val . . . . . . . . . . . . . . . 38
Watchdog timer function . . . . . . . . . . . . . . . . 38
Countdown timer function . . . . . . . . . . . . . . . 40
Pre-defined timers: second and minute
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.9.7
8.9.8
8.10
8.10.1
8.10.2
8.10.3
8.10.4
8.10.5
8.10.6
8.11
4
4.1
5
6
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
8.1
8.2
Functional description . . . . . . . . . . . . . . . . . . . 6
Register overview. . . . . . . . . . . . . . . . . . . . . . . 6
Control registers . . . . . . . . . . . . . . . . . . . . . . . 10
Register Control_1 . . . . . . . . . . . . . . . . . . . . . 10
Register Control_2 . . . . . . . . . . . . . . . . . . . . . 11
Register Control_3 . . . . . . . . . . . . . . . . . . . . . 12
Register CLKOUT_ctl. . . . . . . . . . . . . . . . . . . 13
Temperature compensated crystal oscillator . 13
Temperature measurement . . . . . . . . . . . . . . 13
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Register Aging_offset . . . . . . . . . . . . . . . . . . . 15
Crystal aging correction . . . . . . . . . . . . . . . . . 15
General purpose 512 bytes static RAM . . . . . 16
Register RAM_addr_MSB . . . . . . . . . . . . . . . 16
Register RAM_addr_LSB . . . . . . . . . . . . . . . . 16
Register RAM_wrt_cmd . . . . . . . . . . . . . . . . . 16
Register RAM_rd_cmd . . . . . . . . . . . . . . . . . . 16
Operation examples . . . . . . . . . . . . . . . . . . . . 17
Writing to the RAM . . . . . . . . . . . . . . . . . . . . . 17
Reading from the RAM. . . . . . . . . . . . . . . . . . 17
Power management functions . . . . . . . . . . . . 18
Battery switch-over function . . . . . . . . . . . . . . 19
Standard mode . . . . . . . . . . . . . . . . . . . . . . . . 20
Direct switching mode . . . . . . . . . . . . . . . . . . 21
Battery switch-over disabled: only one power
supply (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Battery switch-over architecture . . . . . . . . . . . 22
Battery backup supply . . . . . . . . . . . . . . . . . . 22
Battery low detection function. . . . . . . . . . . . . 23
Extra power fail detection function . . . . . . . . . 24
Extra power fail detection when the battery
8.2.1
8.2.2
8.2.3
8.3
8.3.1
8.3.1.1
8.3.2
8.4
8.11.1
8.11.2
8.11.3
8.11.4
8.11.5
8.4.1
8.5
interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Clearing flags. . . . . . . . . . . . . . . . . . . . . . . . . 41
Timestamp function . . . . . . . . . . . . . . . . . . . . 43
Timestamp flag. . . . . . . . . . . . . . . . . . . . . . . . 43
Timestamp mode . . . . . . . . . . . . . . . . . . . . . . 44
Timestamp registers. . . . . . . . . . . . . . . . . . . . 44
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.5.1
8.5.5.2
8.6
8.6.1
8.6.1.1
8.6.1.2
8.6.1.3
8.11.6
8.12
8.12.1
8.12.2
8.12.3
8.12.3.1 Register Timestp_ctl . . . . . . . . . . . . . . . . . . . 44
8.12.3.2 Register Sec_timestp. . . . . . . . . . . . . . . . . . . 44
8.12.3.3 Register Min_timestp . . . . . . . . . . . . . . . . . . . 44
8.12.3.4 Register Hour_timestp . . . . . . . . . . . . . . . . . . 45
8.12.3.5 Register Day_timestp. . . . . . . . . . . . . . . . . . . 45
8.12.3.6 Register Mon_timestp . . . . . . . . . . . . . . . . . . 45
8.12.3.7 Register Year_timestp . . . . . . . . . . . . . . . . . . 45
8.12.4
Dependency between Battery switch-over
8.6.1.4
8.6.2
8.6.3
8.6.4
8.6.4.1
and timestamp . . . . . . . . . . . . . . . . . . . . . . . . 46
Interrupt output, INT. . . . . . . . . . . . . . . . . . . . 47
Minute and second interrupts. . . . . . . . . . . . . 48
Countdown timer interrupts . . . . . . . . . . . . . . 49
INT pulse shortening . . . . . . . . . . . . . . . . . . . 49
Watchdog timer interrupts . . . . . . . . . . . . . . . 51
Alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 51
Timestamp interrupts . . . . . . . . . . . . . . . . . . . 52
Battery switch-over interrupts . . . . . . . . . . . . 52
Battery low detection interrupts . . . . . . . . . . . 52
8.13
8.13.1
8.13.2
8.13.3
8.13.4
8.13.5
8.13.6
8.13.7
8.13.8
switch over function is enabled. . . . . . . . . . . . 25
Extra power fail detection when the battery
switch-over function is disabled . . . . . . . . . . . 26
Oscillator stop detection function . . . . . . . . . . 27
Reset function . . . . . . . . . . . . . . . . . . . . . . . . 28
8.6.4.2
8.7
8.8
continued >>
PCF2127AT
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 6 — 11 July 2013
85 of 86
PCF2127AT
NXP Semiconductors
Integrated RTC, TCXO and quartz crystal
8.14
8.15
External clock test mode . . . . . . . . . . . . . . . . 53
STOP bit function . . . . . . . . . . . . . . . . . . . . . . 54
9
9.1
9.1.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SPI-bus interface . . . . . . . . . . . . . . . . . . . . . . 57
Data transmission. . . . . . . . . . . . . . . . . . . . . . 57
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 59
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
START and STOP conditions . . . . . . . . . . . . . 59
System configuration . . . . . . . . . . . . . . . . . . . 59
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 60
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 61
10
11
12
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 64
Safety notes . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 65
13
13.1
13.2
Static characteristics. . . . . . . . . . . . . . . . . . . . 66
Current consumption characteristics, typical . 68
Frequency characteristics. . . . . . . . . . . . . . . . 70
14
14.1
14.2
Dynamic characteristics . . . . . . . . . . . . . . . . . 71
SPI-bus timing characteristics . . . . . . . . . . . . 71
I2C interface timing characteristics . . . . . . . . . 73
15
16
17
17.1
18
19
20
21
22
Application information. . . . . . . . . . . . . . . . . . 74
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 75
Packing information . . . . . . . . . . . . . . . . . . . . 76
Carrier tape information . . . . . . . . . . . . . . . . . 76
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Footprint information . . . . . . . . . . . . . . . . . . . 77
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 78
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 80
23
Legal information. . . . . . . . . . . . . . . . . . . . . . . 81
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 81
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 82
23.1
23.2
23.3
23.4
24
25
26
27
Contact information. . . . . . . . . . . . . . . . . . . . . 82
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 July 2013
Document identifier: PCF2127AT
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