PCF50732H_技术文档

INTEGRATED CIRCUITS

DATA SHEET

PCF50732

Baseband and audio interface for

GSM

1999 May 03

Objective speciﬁcation

File under Integrated Circuits, IC17

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

CONTENTS

14

15

16

17

18

LIMITING VALUES

THERMAL CHARACTERISTICS

DC CHARACTERISTICS

1

2

3

4

5

6

7

8

FEATURES

APPLICATIONS

AC CHARACTERISTICS

GENERAL DESCRIPTION

ORDERING INFORMATION

QUICK REFERENCE DATA

BLOCK DIAGRAM

FUNCTIONAL CHARACTERISTICS

18.1

18.2

18.3

18.4

18.5

18.6

Baseband transmit (BSI to TXI/Q)

Baseband receive (RXI/Q to BSI)

Voice band transmit (microphone to ASI)

Voice band receive (ASI to earphone)

Auxiliary digital-to-analog converters

Auxiliary analog-to-digital converters:

AUXADC1, AUXADC2, AUXADC3 and

AUXADC4

PINNING

FUNCTIONAL DESCRIPTION

8.1

8.2

General

Baseband and voice band reference voltages

9

BASEBAND CODEC

18.7

18.8

Typical total current consumption

Typical output loads

9.1

9.2

9.3

Baseband transmit path

Baseband receive path

Baseband Serial Interface (BSI)

19

APPLICATION INFORMATION

19.1

19.2

Wake-up procedure from Sleep mode

Microphone input connection and test set-up

10

VOICE BAND CODEC

10.1

10.2

10.3

Voice band receive path

Voice band transmit path

Voice band digital circuitry

20

PACKAGE OUTLINES

SOLDERING

21

21.1

Introduction to soldering surface mount

packages

11

AUXILIARY FUNCTIONS

11.1

11.2

Automatic Gain Control (AGC): AUXDAC1

Automatic Frequency Control (AFC):

AUXDAC2

Power ramping: AUXDAC3

Auxiliary analog-to-digital converter (AUXADC)

21.2

21.3

21.4

21.5

Reflow soldering

Wave soldering

Manual soldering

Suitability of surface mount IC packages for

wave and reflow soldering methods

11.3

11.4

12

CONTROL SERIAL INTERFACE (CSI)

22

23

DEFINITIONS

12.1

12.2

The serial interface

Control Serial Interface (CSI) timing

characteristics

LIFE SUPPORT APPLICATIONS

12.3

13

Control register block

VOICE BAND SIGNAL PROCESSOR (VSP)

13.1

13.2

13.3

13.4

Hardware description

VSP assembler language

Descriptions of the VSP instruction set

The assembler/emulator

1999 May 03

2

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

• The digital Baseband Serial Interface (BSI), which

exchanges baseband data between the PCF50732 and

the digital signal processor. The interface also includes

signals to power-up and power-down the baseband

transmit (TX) and receive (RX) paths.

1

FEATURES

• Low power and low voltage device in 0.25 micron

CMOS technology; supply voltage: analog 2.7 V

(typical) and digital 1.5 V (typical)

• Compatible with GSM phase 2 and DCS1800

The voice band CODEC is a complete analog front-end

circuit. It consists of four parts:

recommendations

• Complete in-phase and quadrature component interface

paths between the Digital Signal Processor (DSP) and

RF circuitry

• The receive path, which converts a digital signal to an

analog signal for an earpiece, an external loudspeaker

or a buzzer

• Complete linear PCM CODEC for audio signal

• The transmit path, which receives the analog external

signal from a microphone and converts it into a digital

signal

conversion between earphone/microphone and DSP

• Four auxiliary analog inputs for measurement purposes

(e.g. battery monitoring)

• The Voice band Signal Processor (VSP), which filters

the voice band data

• Three auxiliary analog outputs for control purposes

(i.e. AFC, AGC and power ramping control)

• The digital Audio Serial Interface (ASI), which

connects the digital linear PCM signals of the receive

and transmit paths to an external DSP. The voice band

data is coded in 16-bit linear PCM twos complement

words.

• Separate baseband, audio and control serial interfaces

• Voice band Signal Processor (VSP) for flexible audio

data processing.

2

APPLICATIONS

The auxiliary Analog-to-Digital Converter (ADC)

section consists of four input channels specified for battery

management applications.

The CMOS integrated circuit PCF50732, Baseband and

audio interface for GSM, is dedicated to wireless

telephone handsets conforming to the GSM

recommendations phases 1 and 2, DCS1800 and

PCS1900.

The auxiliary Digital-to-Analog Converter (DAC)

section consists of three DACs for Automatic Gain Control

(AGC), for Automatic Frequency Control (AFC) and for

power ramping.

The Control Serial Interface (CSI) is used to program a

set of control registers, to store the power amplifier

ramping characteristics into the dedicated RAM and to

transmit auxiliary ADC values to the DSP. It also controls

switches, modes and power status of the different parts of

the IC.

3

GENERAL DESCRIPTION

The baseband CODEC is a complete interface circuit

between the RF part in a mobile communication handset

and the Digital Signal Processor (DSP). It consists of three

parts:

• The receive path, which transforms the quadrature

signals from the RF (I/Q) to digital signals

• The transmit path, which transforms a bitstream to

analog quadrature signals for the RF devices

4

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME

DESCRIPTION

VERSION

PCF50732H

LQFP48

plastic low proﬁle quad ﬂat package; 48 leads; body 7 × 7 × 1.4 mm

SOT313-2

1999 May 03

3

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

5

QUICK REFERENCE DATA

SYMBOL

V_DDD

V_DDA

I_DDA

PARAMETER

CONDITIONS

MIN.

1.0

TYP. MAX. UNIT

digital supply voltage

analog supply voltage

analog supply current

1.5

2.7

3.5

2.75

−

V

_DDA≥ V_DDD

2.5

V

V_DDD= 1.5 V; V_DDA= 2.7 V;

RXON active

−

mA

P_av

average power consumption

total standby current

V_DDD= 1.5 V; V_DDA= 2.7 V; note 1

−

15

−

mW

µA

I_stb(tot)

f_clk

−

10

−

master clock frequency

−

13.0

+27

−

MHz

°C

T_amb

operating ambient temperature

−40

+85

Note

1. Without load on audio outputs EARP, EARN, AUXSP and BUZ.

1999 May 03

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Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

6

BLOCK DIAGRAM

V

handbook, full pagewidth

DDD

7

DDA(bb)

25

DDA(vb)

37

DDA(vbo)

47

DDA(ref)

34

REFERENCE

VOLTAGES AND

CURRENTS

36

V

PCF50732

ref

10

10-BIT

DAC

LP

19

16

TXON

BIEN

GMSK

MODULATOR

10

10-BIT

DAC

15

17

BIOCLK

BDIO

BSI

23

24

QP

QN

ADC

DIGITAL

FILTER

20

18

21

22

27

28

29

30

RXON

BOEN

IP

2

IN

M

U

X

AUXADC1

AUXADC2

AUXADC3

AUXADC4

13

9

AUXST

CCLK

10

33

32

31

DAC3

CTL

64 × 10-BIT

SRAM

AUXDAC3

10-BIT

AUXDAC3

10

11

12

14

CEN

CSI

CDI

12

8

AUXDAC2

12-BIT

AUXDAC2

AUXDAC1

CDO

AMPCTRL

AUXDAC1

8-BIT

40

41

38

39

MICP

M

2

VOICE BAND

SIGNAL

PROCESSOR

MICN

DECIMATION

4

3

2

1

MICADC

U

X

ACLK

AFS

ADI

FILTER

AUXMICP

AUXMICN

ASI

46

45

EARP

EARN

OUTPUT

AMPLIFIER

NOISE

SHAPER

EARDAC

1 MHz

ADO

IRAM

44

43

OUTPUT

AMPLIFIER

AUXSP

BUZ

6

5

CLOCK

GENERATOR

MCLK

OUTPUT

AMPLIFIER

RESET

8

26

42

35

SSA(ref)

48

V

SSA(vbo)

MGR988

V

V V

SSA(vb)

SSD

SSA(bb)

Fig.1 Block diagram.

5

1999 May 03

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

7

PINNING

SYMBOL

DESCRIPTION

ACTIVE ACTIVE

NR. TYPE⁽¹⁾

I_DD

LEVEL

EDGE

ADO

ADI

1

2

3

O/TS

−

1.5 mA audio digital interface PCM data output to DSP

I

−

audio digital interface PCM data input from DSP

AFS

rising

audio digital interface PCM frame synchronization signal

from DSP

ACLK

4

5

6

I

−

LOW

−

rising

−

audio digital interface PCM clock signal from DSP

asynchronous reset input

RESET

MCLK

rising

low-swing master clock input; f_clk= 13 MHz; integrated

capacitive coupling

V_DDD

V_SSD

CCLK

CEN

7

8

P

−

digital power supply

G

−

digital ground

9

I

falling

control bus clock input from DSP

control bus data enable from DSP

control bus data input from DSP

10

11

12

13

I

LOW

−

CDI

I

O/TS

I

CDO

AUXST

−

1.5 mA control bus data output to DSP

HIGH

−

status control signal for activation of AUXDAC1,

AUXDAC2 and MCLK input

AMPCTRL 14

O

O/TS

O

−

1.5 mA general purpose output pin

BIOCLK

BIEN

BDIO

BOEN

TXON

RXON

IP

15

16

17

18

19

20

21

22

3 mA baseband interface data clock

LOW

−

1.5 mA baseband transmit interface data enable signal

1.5 mA baseband interface data I/O from/to DSP

1.5 mA baseband receive interface data enable signal

I/O

O

LOW

HIGH

−

I

−

baseband transmit path activation signal

I

baseband receive path activation signal

I/O

(I) baseband differential positive input/output to IF circuit

IN

−

(I) baseband differential negative input/output to

IF circuit

QP

QN

23

24

I/O

−

(Q) baseband differential positive input/output to

IF circuit

(Q) baseband differential negative input/output to

IF circuit

V_DDA(bb)

V_SSA(bb)

25

26

P

G

I

−

baseband power supply (analog)

baseband ground (analog)

AUXADC1 27

AUXADC2 28

AUXADC3 29

AUXADC4 30

AUXDAC1 31

AUXDAC2 32

auxiliary ADC input 1 for battery voltage measurement

auxiliary ADC input 2

I

auxiliary ADC input 3

I

auxiliary ADC input 4

O

auxiliary DAC output for AGC; max. load 50 pF // 2 kΩ

auxiliary DAC output for AFC; max. load 50 pF // 10 kΩ

1999 May 03

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Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

SYMBOL

DESCRIPTION

ACTIVE ACTIVE

NR. TYPE⁽¹⁾

I_DD

LEVEL

EDGE

AUXDAC3 33

O

−

auxiliary DAC output for power ramping; maximum load

50 pF, ±600 µA

V_DDA(ref)

V_SSA(ref)

V_ref

34

35

36

37

P

G

I/O

P

I

−

reference voltage power supply (analog)

reference voltage ground (analog)

band gap reference voltage noise decoupling

voice band voltage power supply

V_DDA(vb)

AUXMICP 38

AUXMICN 39

auxiliary microphone differential positive input

auxiliary microphone differential negative input

microphone differential positive input

microphone differential negative input

voice band ground

I

MICP

40

41

42

43

44

45

46

47

48

I

MICN

I

V_SSA(vb)

BUZ

G

O

P

G

buzzer output

AUXSP

EARN

EARP

auxiliary speaker output

earphone differential negative output

earphone differential positive output

voice band output buffer voltage power supply (analog)

voice band output buffer ground (analog)

V_DDA(vbo)

V_SSA(vbo)

Note

1. O/TS = 3-state output.

1999 May 03

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Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

handbook, full pagewidth

V

1

2

36

35

34

33

ADO

ADI

ref

SSA(ref)

DDA(ref)

AFS

3

4

ACLK

AUXDAC3

5

32 AUXDAC2

31 AUXDAC1

RESET

MCLK

6

PCF50732

V

7

AUXADC4

30

29 AUXADC3

AUXADC2

DDD

V

8

SSD

CCLK

CEN

CDI

9

28

27 AUXADC1

10

11

12

V

26

25

SSA(bb)

DDA(bb)

CDO

MGR989

Fig.2 Pin configuration.

8

1999 May 03

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

8

FUNCTIONAL DESCRIPTION

8.2

Baseband and voice band reference voltages

This chapter gives a brief overview of the device.

The detailed functional description can be found in the

following chapters:

The reference voltage V_refis generated on-chip by a band

gap voltage reference circuit and is available at pin V_ref.

As V_refis used as reference for most of the internal analog

circuitry, noise must be kept as low as possible by

connecting an external decoupling capacitor at this pin.

Chapter 9 “Baseband CODEC”

Chapter 10 “Voice band CODEC”

Chapter 11 “Auxiliary functions”

The voltage at V_refis buffered to generate the baseband

and voice band reference voltage V_refas well as internal

references for the different functions, such as the auxiliary

and the transmit DACs.

Chapter 12 “Control Serial Interface (CSI)”

Chapter 13 “Voice band Signal Processor (VSP)”.

8.1

General

9

BASEBAND CODEC

As low power consumption in mobile telephones is a very

important issue, all the circuit parts in the PCF50732 can

be powered-on/off either by means of the external signals

AUXST, TXON or RXON, or by programming the

respective register bits in the Control Serial Interface

(CSI).

The baseband CODEC is a complete interface circuit

between the RF part in a mobile communication handset

and the digital signal processor. It consists of three parts:

• The transmit path, which converts a bitstream to

analog quadrature signals for the RF devices

The most important signal for the digital and analog circuit

functions in the PCF50732 is the DAC enable signal

AUXST, which allows to activate AUXDAC1 (AGC) and

AUXDAC2 (AFC), as well as the low-swing master clock

input MCLK. AUXST must be active (HIGH) and V_DDA

must be stable (see also Section 18.1) to allow the

master clock to access different circuit parts after a reset

(RESET active). AUXDAC1 and AUXDAC2 are only

activated if their related power-on bit is set. AUXDAC1 is

default off, AUXDAC2 is default on.

• The receive path, which transforms the quadrature

signals of the IF chip (I/Q) to digital signals

• The digital baseband serial interface, which

exchanges baseband data between the PCF50732 and

the DSP. The interface also includes signals to

power-up and power-down the baseband transmit

(TX) and receive (RX) paths.

9.1

Baseband transmit path

The baseband transmit path consists of three parts:

RESET must be active during at least 3 MCLK cycles, with

AUXST active, to ensure a correct initialisation of all the

digital circuitry of the PCF50732. Since RESET is

asynchronous even small spikes of a few nanoseconds

can cause partial resets.

• GMSK modulator: generation of a Gaussian Minimum

Shift Keying (GMSK) signal

• 10-bit DACs: digital-to-analog converters for the

I and Q components of the GMSK signal

• Low-pass filters: analog reconstruction low-pass filters

for the output of the DACs.

For power supply noise interference reduction, a pair of

power supply and ground pins are provided for the:

• Baseband analog: V_DDA(bb)/V_SSA(bb)

The requirements of the transmit path of a GSM terminal

are given by “GSM recommendation 05.05”:

• Voice band analog: V_DDA(vb)/V_SSA(vb)

• Phase RMS error <5°

• Phase peak error <20°

• Amplitude error < ±1 dB.

• Voice band output drivers: V_DDA(vbo)/V_SSA(vbo)

• DC reference voltages and currents: V_DDA(ref)/V_SSA(ref)

• Digital circuitry: V_DDD/V_SSD

.

Nevertheless the performance of the PCF50732 is far

better than these figures indicate; see Section 18.1.

All V_SSpins are connected internally. V_DDDis the digital

supply. V_DDA(bb), V_DDA(vb), V_DDA(vbo), and V_DDA(ref)are

analog supplies, and are referred to as V_DDAthroughout

this document. These analog supplies must be connected

externally.

1999 May 03

9

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

The baseband receive section can be switched between

two modes of operation:

9.1.1

GMSK MODULATOR

The input signal of the GMSK modulator is a bitstream

coming from the baseband serial interface, with a

sampling frequency of 270.833 kHz. Typically 148 bits are

modulated during a normal burst, and 88 bits during an

access burst. Using this bitstream, the GMSK modulator

generates digital I and Q components as described in

“GSM recommendation 05.04”.

• ZIF (zero IF) mode for radio sections, which convert the

receive signal down to baseband. In this mode the ADC

is sampled at 6.5 MHz, the decimation filter samples

down by a factor of 24 with a pass band as specified in

Fig.3. The serial interface output BDIO delivers

2 × 12-bit values for I and Q components at

270.833 kHz.

This is done in three steps:

• NZIF (near zero IF) mode for radio sections, which

converts the receive signal down to a centre frequency

of 100 kHz. In this mode the ADC is sampled at 13 MHz,

the decimation filter samples down by a factor of 24 with

a pass band as specified in Fig.3. The serial interface

output BDIO delivers 2 × 12-bit values for I and Q

components at 541.667 kHz.

1. First the incoming bitstream is differentially encoded

by an EXOR operation on the actual bit and the

previous bit

2. The instantaneous phase (ϕ) is calculated using a

gaussian filter with an impulse response of 4 taps

3. A look-up table provides the cosine (I component) and

the sine values (Q component) of the phase (ϕ).

9.2.1

RECEIVE ADC

The look-up table also interpolates the signal to a

16 times higher frequency (4.333 MHz).

The receive ADCs are Σ∆ analog-to-digital converters that

convert differential input signals into1-bit data streams with

a sampling frequency of 6.5 or 13 MHz.

9.1.2

10-BIT DACS

The two 10-bit DACs are working at a sampling rate of

4.3333 MHz. They convert the digital I and Q components

of the GMSK modulator to differential analog

I and Q signals.

9.2.2

DIGITAL DECIMATION FILTER

Digital filtering is required for:

• Suppression of out-of-band noise produced by the

Σ∆ ADC

9.1.3

LOW-PASS FILTER

• Decimation of the sampling rate (6.5 or 13 MHz) by 24

• System level filtering.

The analog output signals of the DACs are filtered by

analog reconstruction low-pass filters.

The digital filtering is performed by a digital FIR filter with a

group delay for this running average filter of approximately

23 or 11.5 µs respectively. The filter uses twos

complement arithmetic.

These filters remove high frequency components of the

DAC output signals and attenuate components around the

4.3333 MHz sampling frequency. The low-pass filters

have a cut-off frequency of approximately 300 kHz, with

very linear phase behaviour in the pass band.

9.2

Baseband receive path

The baseband receive path consists of two parts:

• Receive ADC: Σ∆ analog-to-digital converters

• Decimation filter: digital decimation filters for I and Q.

1999 May 03

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Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

MBL025

20

handbook, full pagewidth

gain

(dB)

0

−20

NZIF

ZIF

−40

−60

−80

−100

0

100

200

300

400

500

600

f (kHz)

3

Fig.3 Transfer functions for the baseband receive filter.

BIEN0 must be at least 10 quarterbits long to allow settling

of the analog filters. Bits are clocked out of the DSP by the

falling edge and clocked into the PCF50732 by the rising

edge of BIOCLK. After the BIEN1 period has elapsed,

BIEN is set HIGH again and transmission from the DSP

ends. Logic 1s are modulated whenever BIEN is HIGH

and the baseband transmit (BBTX) block is active. Values

for BIEN0 and BIEN1 can be set in the Burst control

register.

9.3

Baseband Serial Interface (BSI)

9.3.1

OVERVIEW

The digital part of the baseband consists of a receive

section and a transmit section. The receive section is a

FIR filter that reduces the 6.5 MHz (13 MHz for

NZIF mode) bitstream from the sigma-delta converters

into 2 × 12-bit values at 270.833 kHz (541.667 kHz for

NZIF mode).

Figure 5 shows the timing for the BSI data transmission.

In power-down the de-asserted value of BIOCLK is high-Z

and BIEN is HIGH. Typical connection to the system DSP

is defined in Table 1.

The transmit section converts the 270.833 kHz data

stream from the DSP into a GMSK signal sampled at

4.333 MHz. The 10-bit I and Q signals are then fed into

two 10-bit DACs. The power ramping signal is also

generated by the transmit section with the 10-bit

AUXDAC3 block.

Table 1 Connection of BSI transmit signals to

PCF5087X

9.3.2

TRANSMIT PATH BLOCK DESCRIPTION

PCF50732

PCF5087X

9.3.2.1

Transmit serial interface

I/O

The power-up of the BSI transmit path is controlled via the

TXON pin. When TXON is pulled HIGH, the transmit path

recovers from power-down. The MCLK/48 = 270.833 kHz

output signal BIOCLK is activated. When the BIEN0 period

has elapsed the output signal BIEN goes LOW and the bits

to be transmitted are clocked out of the DSP.

TXON

BDIO

I

RFSIG[y]

SIOXD

O

I/O

I

I/O

O

BIEN

SOXEN_N

SIOXCLK

BIOCLK

O

I

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Baseband and audio interface for GSM

PCF50732

After TXON goes HIGH and a time equal to RU quarterbit

periods has elapsed, power ramp-up is done.

9.3.2.2

Power ramping controller

The PCF50732 fully supports all multislot modes which do

not require full duplex operation or more than two

consecutive transmit bursts. In this specification double

burst mode is used for all supported multislot modes while

single burst mode supports the normal GSM modes.

After a time period equal to RD quarterbits has elapsed

power ramp-down is initiated.

The AUXDAC3 output is also shown in Fig.4.

Values for RU (ramp-up) and RD (ramp-down) can be set

in the Burst control register of the control serial interface.

RD must be greater than RU + 32. RU and RD range

from 0 to 4000 QB (quarterbit). The register offers the

possibility to enter codes up to 4095.

The power ramping controller drives the power amplifier

output envelope.

In each transmit (TX) burst one ramp-up and one

ramp-down will be carried out. In multislot mode one

intermediate ramp will be carried out in addition to ramp-up

and ramp-down. Each ramp consists of 16 discrete step

values that are sent to the DAC3. Each step’s duration is

2 quarterbits which translates into 8-bit long ramps.

The DAC3 output is in 3-state whenever it is powered

down. The ramping step values are stored in a 64 × 10-bit

RAM as shown in Table 2.

The GMSK modulator is active for a period of 2 clock

cycles after the ramp-down or for the length of the TXON

burst, whichever is longer.

Multislot (high speed switched data mode) can be selected

by setting the appropriate bit in the Burst control register.

In multislot mode an intermediate ramping step is done.

This intermediate step is started after a time period equal

to RM quarterbits has elapsed. A value for RM

In order to initialize AUXDAC3 it is necessary to write into

the RAM all 32 (or 48 in multislot mode) DAC3 output

values. Filling the RAM is normally done by writing a

logic 0 to the address sub-register of the Burst control

register, after which 32 or 48 values, depending on

multislot mode, can be written into the data sub-register of

the Burst control register. Writing to the DAC3 RAM is only

possible when the DAC3 is powered off.

(intermediate ramp) is also set using the Burst control

register. The following conditions must be true:

RU + 32 < RM and RM + 32 < RD.

Table 2 AUXDAC3 RAM contents

RAM ADDRESS

DATA

Total number of CSI-accesses is therefore 33 for a normal

burst and 49 for a double burst.

0 to 15

16 to 31

32 to 47

48 to 64

ramp-up data

intermediate ramp data

ramp-down data

not used

An autoincrement feature will store these data into the

correct RAM positions.

The value after power-up of DAC3 will always be equal to

the value of RAM location 47.

Table 3 Power ramping timing characteristics

AUXDAC3 timing is controlled by the Burst control

register. This contains the following sub-registers:

SYMBOL

VALUE

12t₁

COMMENTS⁽¹⁾

t₀

one quarterbit (QB)

0 to 4000 QB

• The RU register containing the delay in number of

quarterbit cycles from the assertion of TXON to the start

of the power-up ramping; default value is 0

t_ru

RU register

RM register

RD register

32t₀

t_im

t_rd

RU + 32 to 4000 QB

RM + 32 to 4000 QB

8 bits; 32 QB

• The RM register containing the delay in number of

quarterbit cycles from the assertion of TXON to the start

of the intermediate power ramp; default value is 0. RM

is only used in case of multislot mode

t

_rup, t_rim, t_rdo

Note

1. QB: Quarterbit, usually referred to the time needed for

• The RD register containing the delay in number of

quarterbit cycles from the assertion of TXON to the start

of the power-down ramping; default value is 0

one quarter of a GSM baseband bit, i.e. a frequency of

1

⁄

₁₂× 13 MHz.

• DAC3 burst RAM address register

• DAC3 burst RAM data register

• Single/double burst mode register: normal mode or

multislot mode selection flag.

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Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

handbook, full pagewidth

TXON

(1)

APE_DAC3

t

im

t

ru

AUXDAC3

t

rd

0

15

15 31

31 47

ADDRESS

AUXDAC3

RAM

47

15

31

47

t

MGR995

rup

rim

rdo

RU

RM

RD

(1) APE_DAC3: Analog Power Enable signal for the AUXDAC3.

Fig.4 Power ramping timing characteristics (multislot mode).

Bits are clocked out of the PCF50732 by the falling edge,

and clocked into the DSP by the rising edge of BIOCLK.

In normal bursts 148 I/Q pairs are read from the

PCF50732.

9.3.3

RECEIVER PATH BLOCK DESCRIPTION

9.3.3.1

Receive serial interface

The baseband serial interface sends the digital signal of

the receive path to a digital signal processor. It also takes

the digital bitstream from the digital signal processor and

transmits it via the baseband CODEC.

When RXON goes LOW, the last pair of I and Q values will

be sampled and transferred to the baseband processor

(both I and Q components). BIOCLK stops after additional

16 BIOCLK cycles. The receive path is powered down

again. In power-down the BIOCLK output is put in 3-state

and the BOEN output is HIGH.

The baseband reception and transmission are active in

bursts. A normal burst has a length of 548 µs. The frame

rate of bursts is 4.615 ms. Using a normal traffic channel,

one burst for each frame is transmitted and two bursts are

received. To save as much power as possible, the transmit

path and the receive path of the PCF50732 are in

power-up mode only during the transmission or reception

bursts respectively.

The output format is 2 × 12-bit I/Q (twos complement).

Transmission occurs MSB first, I followed by Q. The serial

clock signal BIOCLK will run at 6.5 MHz, or 13 MHz in the

NZIF mode. Figure 6 shows the timing of the BSI data

reception.

The power-up of the receive section is controlled via the

RXON pin or RXON bit. When RXON is driven HIGH, the

receive section recovers from power-down and the output

clock BIOCLK is activated. After a settling delay of 52 µs

(ZIF mode, analog circuitry + decimation filter settling

time), BOEN goes LOW to transfer the first 12-bit

I and Q words. The settling time is only 26 µs in NZIF

mode.

An automatic offset compensation mechanism is provided

in order to achieve the required performance. This

mechanism will short the receive (RX) inputs internally and

measure the resulting offset value. This offset value will be

subtracted from all subsequent I/Q output words.

The offset inherent to the device can thereby be reduced

to a few millivolts. Default value for both I- and Q-offset is

zero.

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Philips Semiconductors

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PCF50732

Offset compensation measurement can be done on three

channels separately: baseband receive I channel,

baseband receive Q channel and AUXADC channel. All

AUXADC channels use the same offset compensation

value. Starting an offset measurement is done by writing a

logic 1 into the offset trigger register for each channel that

needs calibration. If the value ‘7’ (decimal) is written into

the offset trigger register offsets will be measured for I, Q

and AUXADC channels.

Table 4 Connection of BSI receive signals to the

PCF5087X

PCF50732

PCF5087X

I/O

RXON

BDIO

I

RFSIG[z]

SIOXD

O

I/O

I

I/O

O

BOEN

BIOCLK

SIXEN_N

SIOXCLK

O

I

Offsets can also be read or written directly. Each offset

measurement is implemented internally as an AUXADC

measurement and takes approximately 100 µs.

Offsets from −256 up to 255 can be compensated.

9.3.4

BASEBAND SERIAL INTERFACE (BSI) TIMING CHARACTERISTICS

intermediate ramp

32 QB

handbook, full pagewidth

t

43

ramp-up

32 QB

t

42

ramp-down

32 QB

trail

t

44

2 BIOCLK

clocks

t

40

data

(1)

TXI/Q

data

logic 1s

data

logic 1s

AUXDAC3

t

7

high-Z

BIOCLK

BDIO

high-Z

(2)

d.c.

t

d.c.

B(0) B(1)

B(n)

t

39

9

t

10

BIEN

t

5

TXON

MGR990

t

6

(1) TXI/Q = transmit I or Q.

(2) d.c. = don’t care; will be overwritten with logic 1.

Fig.5 Timing of the baseband serial interface transmit path; for the timing values see Table 5

1999 May 03

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Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

t

16t

1

handbook, full pagewidth

12

high-Z

BIOCLK

I11

I0

Q11

Q0

BDIO

t

14

t

13

BOEN

RXON

t

15

MGR991

t

548 µs

11

Fig.6 Timing of the baseband serial interface receive path; for the timing values see Table 5.

Table 5 BSI timing characteristics

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Master clock

t₁

t₂

t₃

t₄

MCLK cycle time

MCLK LOW time

MCLK HIGH time

RESET LOW time

−

76.9

−

ns

30

3t₁

¹⁄₂t₁

−

ns

Baseband Serial Interface (BSI) transmit path (see Fig.5)

t₅

BIEN0 value

10

t₅

−

511

4000

−

QB

ns

t₆

BIEN1 value

−

t₇

BIOCLK cycle time

data set-up time

−

48t₁

−

t₉

20

−

ns

t₁₀

t₃₉

t₄₀

t₄₂

t₄₃

t₄₄

data hold time

−

ns

BIOCLK active after TXON rising edge

analog TX and GMSK power-up time

ramp-up value

−

t₁

ns

−

17.4

3940

3980

QB

0

−

intermediate ramp value

ramp-down value

32 + t₄₂

−

normal mode

32 + t₄₂

32 + t₄₃

−

4020

QB

double burst mode

1999 May 03

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Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Baseband Serial Interface (BSI) receive path (see Fig.6)

t₁₁

analog power-up and ﬁlter settling time

ZIF mode

−

52

26

−

µs

NZIF mode

µs

t₁₂

BIOCLK cycle time

ZIF mode

−

2t₁

t₁

−

ns

NZIF mode

t₁₃

t₁₄

t₁₅

BOEN LOW after falling clock edge

BIOCLK falling edge to data valid

BOEN HIGH after falling clock edge

15

−

Linearity of receiver equipment (to earpiece) at

10 VOICE BAND CODEC

EARPGA = 0 dB and a volume control (VOLPGA and

EARAMP or AUXAMP) of −12 dB, signal-to-total harmonic

distortion ratio according to “GSM recommendation

II.11.10 V.4.16.1”.

The voice band CODEC is a complete analog front-end

circuit. It consists of three parts:

• The receive path, which converts a digital linear PCM

signal to an analog signal for an earpiece, an external

loudspeaker or a buzzer

10.1.1 RXVOL

• The transmit path, which receives an analog signal

from a microphone or an auxiliary input and converts it

into a digital linear PCM signal

RXVOL controls the volume of the voice band receive

path. In conjunction with EARAMP, AUXAMP and

BUZAMP it allows a gain variation from +6 to −30 dB in

64 steps; see Table 25. RXVOL also provides a mute

selection of the three outputs EARP/EARN, AUXSP and

BUZ respectively. At RESET the volume is automatically

set to −12 dB.

• The digital Audio Serial Interface (ASI), which

connects the digital linear PCM signals of the receive

and transmit paths to a digital signal processor.

Various functions and characteristics of the voice band

CODEC can be selected by programming the

corresponding control registers in the Control register

block (see also Tables 11, 22, 23, 24 and 25).

10.1.2 RXPGA

RXPGA controls the gain of the voice band receive path

within a range of −24 to +12 dB in 64 steps for calibration

purposes.

10.1 Voice band receive path

The voice band receive path consists of the following

parts:

10.1.3 RXFILTER

RXFILTER is a digital band-pass filter with a pass band

from 300 to 3400 Hz. It is realized by a programmable

structure (voice band signal processor).

• The receive part of the voice band signal processor

• NOISE SHAPER: 3rd order digital Σ∆ modulator,

generates a bit stream at 1 MHz to drive the EARDAC

• EARDAC: digital-to-analog converter including

low-pass filter for high frequency noise content of noise

shaper

10.1.4 EARDAC

EARDAC is a DAC operating at a sampling frequency of

1 MHz. It converts the bitstream input to a sampled

differential analog signal and low-pass filters the output

signal at the same time.

• EARAMP: amplifier for an earpiece

• AUXAMP: amplifier for an auxiliary loudspeaker

• BUZAMP: amplifier for a buzzer output.

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Philips Semiconductors

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PCF50732

Values are specified for a standard electret microphone

with a sensitivity of −64 ±3 dB for high gain or for an

external microphone with an amplifier sensitivity of

−26 ±3 dB (0 dB ≡ 1 V/0.1 Pa = 1 V/µbar; at 1 kHz).

10.1.5 EARAMP

EARAMP is an amplifier, capable of driving a standard

earpiece with a minimum impedance of 8 Ω in

single-ended mode or 16 Ω in differential mode.

10.2.2 MICADC

10.1.6 AUXAMP

MICADC is a Σ∆ A/D converter which generates a 1 MHz

bitstream.

AUXAMP is an amplifier for connection to an external

loudspeaker amplifier of minimum 8 Ω (hands-free car kit).

An ‘auxiliary speaker external amplifier control’ output

pin (AMPCTRL) can be used to switch on/off an external

amplifier (hands-free car kit). The status of AMPCTRL is

programmable via the Control Serial Interface; its default

value is on.

10.2.3 DECIMATOR AND TXFILTER

The DECIMATOR is a digital filter, which performs a signal

processing to a lower sampling rate at the output

compared to the input.

The bitstream with a sampling frequency of 1 MHz is

low-pass filtered and down-sampled to 40 kHz by a FIR

filter.

10.1.7 BUZAMP

BUZAMP is an amplifier for connection to an external

buzzer of minimum 8 Ω. It has the same output

characteristics as the AUXAMP and can hence be used as

a second auxiliary output amplifier. It is switched on/off by

a dedicated control bit in the Control register block.

A digital high-pass filter and a digital low-pass filter (both

IIR filters) process the 14-bit input samples to achieve a

band-pass with a pass band from 300 to 3400 Hz. These

filters run on the on-chip voice band signal processor (see

Fig.7). It’s program is down-loaded into the instruction

memory (IRAM) via the CSI (see Table 26).

10.2 Voice band transmit path

The output of the TXFILTER is down-sampled to a

sampling frequency of 8 kHz with a word length of 16 bits.

The voice band transmit path consists of the following

parts:

• MICMUX: microphone input multiplexer

• MICADC: Σ∆ analog-to-digital converter

10.2.4 TXPGA

TXPGA adapts the analog signals coming from MICMUX

within a range of −30 to +6 dB. It is designed for calibration

purposes.

• DECIMATOR: decimates the incoming bit stream from

1 MHz to 40 kHz

• TXFILTER: band-pass filter for the digital transmit signal

and down-sampling

10.2.5 SIDEPGA

• TXPGA/LIM: fine-programmable gain for calibration,

limiter

SidePGA loops part of the voice band transmit signal back

into the receive path. There are 64 gain steps from mute to

+6 dB.

• SidePGA: voice band sidetone programmable gain

amplifier.

10.3 Voice band digital circuitry

Linearity of transmitter equipment, signal-to-total harmonic

distortion ratio according to “GSM recommendation

II.11.10 V.4.16.1”.

The voice band digital circuitry is responsible for

converting a 16-bit PCM signal at 8 kHz sample rate to and

from a 1-bit 1 MHz signal. It also contains a band-pass

filter for 300 to 3400 Hz and a sidetone engine. Various

volume settings are calculated inside this block. Figure 7

shows the block diagram of the voice band signal

processor.

10.2.1 MICMUX

MICMUX is used to select between a differential signal at

pins MICP/MICN and a differential signal at pins

AUXMICP/AUXMICN.

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PCF50732

handbook, full pagewidth

VOICE BAND SIGNAL PROCESSOR

ADI

ACLK

AFS

TXPGA/LIM

DECIMATOR

TX_BS

(transmit bitstream)

ASI

RX/TX

FILTER

SidePGA

ADO

1-bit, 1 MHz

16-bit, 8 kHz

NOISE

SHAPER

RX_BS

(receive bitstream)

RXPGA/LIM

RRAM

RXVOL

MGR992

IRAM

Fig.7 Block diagram of the voice band signal processor.

Pin ADO is put in 3-state after the LSB of the transmit

word, independent of the length of the AFS pulse. If the

channel position 0 (see Section 10.3.2.1) is selected, then

the MSB must be output directly after AFS becomes a

logic 1, even if no rising edge on ACLK has been given yet.

10.3.1 VOLUME CONTROL BLOCK

The volume control block contains the RXPGA, SidePGA,

TXPGA and both limiter blocks. The possible settings can

be found in the description of the CSI block. All digital

volume control blocks, i.e. RXPGA, SidePGA, and

TXPGA, will allow settings from +6 to −30 dB and mute in

64 steps. However, not all combinations of settings for

these blocks will be meaningful. The limiter will always clip

signals with overflow to the maximum or minimum

allowable value.

The following modes of operation are programmable:

channel position and ACLK clock mode.

10.3.2.1 Channel position mode

Depending on a programmable register value n

(n = 0 to 15) one of 16 channels can be selected (see

Table 22). The ASI can add a delay of 16 × n-bit clocks

between the assertion of AFS and the start of the MSB of

the PCM values. This delay is independently

10.3.2 AUDIO SERIAL INTERFACE (ASI) BLOCK

The ASI is the voice band serial interface which provides

the connection for the exchange of PCM data in both

receive and transmit directions, between the baseband

digital signal processor and the PCF50732. The data is

coded in 16-bit linear PCM twos complement words.

programmable for transmit and receive mode.

10.3.2.2 ACLK clock mode

A frame start is defined by the first falling edge of ACLK

after a rising AFS. This first falling edge is used to clock in

the first data bit on both the baseband and the DSP device.

Single or double clock mode can be selected. Double clock

mode implies two clock pulses per data bit and is used for

communication with IOM2 compatible devices. In double

clock mode data must be output on the first rising edge and

be read on the last falling edge.

Data on pin ADI is clocked in (MSB first) on the falling edge

of the ACLK clock. Data is clocked out (MSB first) on pin

ADO on the rising edge of the ACLK clock.

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Philips Semiconductors

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PCF50732

Table 6 Pin connection of the audio serial interface to the PCF5087X

PCF50732

PCF5087X

I/O

ADI

ADO

ACLK

AFS

I

O

I

DD

DU

O

I

DCL

FSC

O

I

handbook, full pagewidth

AFS

word

ADI

t

rpdc

word

ADO

MGR993

t

tpdc

t_rpdc: receive path data channel delay.

t_tpdc: transmit path data channel delay.

Fig.8 Frame structure of the Audio Serial Interface (ASI).

1999 May 03

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PCF50732

10.3.2.3 Audio Serial Interface (ASI) timing characteristics

handbook, full pagewidth

AFS

t

41

t

17

t

16

42

ACLK

t

40

t

21

LSB

MSB

first slot

first bit

high-Z

last slot

last bit

first slot

second bit

last slot

last bit

ADO

ADI

single

clock

mode

t

19

20

18

MSB

LSB

last slot

last bit

first slot

first bit

first slot

second bit

last slot

last bit

t

21

MSB

LSB

high-Z

last slot

last bit

first slot

first bit

slot 1

bit 2

last slot

last bit

ADO

ADI

double

clock

mode

t

19

20

LSB

MSB

last slot

last bit

first slot

first bit

slot 1

bit 2

last slot

last bit

MGR994

Fig.9 Timing of the Audio Serial Interface (ASI).

Table 7 ASI timing characteristics

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

t₁₆

t₁₇

t₁₈

t₁₉

t₂₀

t₂₁

t₄₀

frame sync (AFS) set-up time to falling edge of ACLK

frame sync (AFS) hold time from falling edge of ACLK

ACLK rising edge to data (ADO) valid

data (ADI) set-up time to falling edge of ACLK

data (ADI) hold time from falling edge of ACLK

ﬁrst data valid (ADO) after AFS rising edge

ACLK period

70

40

−

ns

−30

50

80

0

+30

−

60

single clock mode

0.5

−

7.8

3.9

−

µs

ns

double clock mode

t₄₁

t₄₂

AFS period

125

ACLK LOW before AFS rising edge

40

−

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PCF50732

11 AUXILIARY FUNCTIONS

11.3 Power ramping: AUXDAC3

The auxiliary functions part consists of three

digital-to-analog converters (DACs) and a 4 input

analog-to-digital converter (ADC) with a 12-bit range.

The DACs are for:

AUXDAC3 is a 10-bit binary coded digital-to-analog

converter designed for power ramping purposes.

AUXDAC3 is default off. The power ramping behaviour is

described in Section 9.3.2.2.

• Automatic Gain Control (AGC): AUXDAC1

• Automatic Frequency Control (AFC): AUXDAC2

• Power ramping: AUXDAC3.

11.4 Auxiliary analog-to-digital converter (AUXADC)

The AUXADC is specified for voltage and temperature

measurements. It contains 4 input channels required for

∆T and ∆V measurements, as well as battery type

recognition:

11.1 Automatic Gain Control (AGC): AUXDAC1

The AUXDAC1 is an 8-bit binary coded, guaranteed

monotonic digital-to-analog converter.

• ∆T: battery temperature, ambient temperature

(measured across sensor)

The status of AUXDAC1 is controlled by the signal AUXST

and a power-up bit in the Power control register. The signal

that switches the external VCXO can also be used to

control the AUXST pin of the PCF50732. The AUXDAC1

output is floating in Power-down mode (AUXST = LOW).

The input MCLK is then deactivated.

• ∆V: peak battery voltage, battery voltage during transmit

burst.

Five 12-bit registers are available in which results of

auxiliary analog-to-digital conversions can be stored.

Two registers are dedicated to the input AUXADC1 and

one to each of AUXADC2, AUXADC3 and AUXADC4.

When AUXST goes HIGH, AUXDAC1 is powered-up and

the converted value of the corresponding register in the

control register block is available at the AUXDAC1 output

pin.

The AUXADC1 input can be used for battery voltage

measurement. In the AUXADC1A register the voltage

during a transmit time slot can be stored. The AUXADC1B

register can store the voltage during other time slots. If a

read request to one of these registers is executed by

loading its address into the Read request register, the

actual contents of the addressed register are given to the

control interface and a new measurement is performed in

the next appropriate time slot.

If a write access to the AUXDAC1 register occurs, the DAC

is activated with the new content of the DAC register (see

Table 14 and 15). The AUXDAC1 must be powered-up by

setting the correct bit in the Power control register. At reset

AUXDAC1 is powered-down.

A multiplexer connects each of the AUXADC inputs to a

channel of the receive ADC depending on read access to

the corresponding register.

11.2 Automatic Frequency Control (AFC):

AUXDAC2

The AUXDAC2 is a 12-bit binary coded, guaranteed

monotonic digital-to-analog converter. This DAC is used to

control the frequency of an external master clock VCXO.

Thus an auxiliary analog-to-digital conversion is only

possible, if the baseband receive section is not in use

(RXON is LOW). At each read request to one of the

AUXADC registers, a flag is set in the AUXADC flag

register indicating that an analog-to-digital conversion is to

be performed. When one of the registers AUXADC1B,

AUXADC2, AUXADC3, or AUXADC4 is being read, the

baseband interface verifies that RXON is LOW, indicating

that no receive burst is currently active. The baseband

receive path is then powered up. After the ADC settling

time has elapsed (see POST_AUXADCin Chapter 18), valid

data is available and stored in the corresponding register.

The status of AUXDAC2 is controlled by the signal AUXST

and a power-up bit in the Power control register. The signal

that switches the external VCXO can also be used to

control the AUXST pin of the PCF50732. The AUXDAC2

output is floating in Power-down mode (AUXST = LOW).

When AUXST goes HIGH, AUXDAC2 is powered-up and

the converted value of the corresponding register in the

control register block is available at the AUXDAC2 output

pin.

The default value for AUXDAC2 is 1.1 V which

corresponds to a 800H code in the AUXDAC2 register.

At reset AUXDAC2 is powered on.

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PCF50732

After conversion the corresponding bit in the AUXADC flag

register is reset (see Table 18). If RXON is activated

during an auxiliary analog-to-digital conversion cycle, the

auxiliary conversion is interrupted and restarted when

RXON returns LOW, indicating no receive burst activity.

The PCF50732 waits for a rising edge of TXON, and

powers up the receive path. After the settling time of the

ADC added to the programmed AUXADC conversion

delay (in 48 MCLK cycles) has elapsed, valid data is

available and stored in the AUXADC1A register.

When register AUXADC1A is read, a battery voltage

measurement during a transmission burst is executed.

handbook, full pagewidth

1440

output code

(LSB)

gain tolerance

offset

at 0 V

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

(V)

2.0

V

in

MGR996

Fig.10 Typical transfer characteristics of AUXADC (output code as function of differential input voltage).

1999 May 03

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Philips Semiconductors

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PCF50732

If the device address is equal to the chip address, the

programmed information on CDI (DB11 to DB00) is loaded

into the addressed register (RA3 to RA0) when CEN

returns inactive HIGH.

12 CONTROL SERIAL INTERFACE (CSI)

The Control Serial Interface block is used to set and read

the status bits inside the PCF50732. It is also used to read

data from the auxiliary ADCs and to write data into the

auxiliary DACs. Finally, the block is used to write the power

ramping curve into a 64 × 10-bit static RAM. It should be

noted that only 48 of the 64 addresses can be accessed;

see Table 2.

The dummy bit in front is needed for compatibility with

older baseband devices.

Reading a register is accomplished by writing the address

of the required register into the read request register.

The next time CEN goes LOW, the requested data will be

shifted out, together with the register and device address.

12.1 The serial interface

A 4-line bidirectional serial interface is used to control the

circuit. It allows access to each register of the control

register block (read and/or write). The 4 lines are:

Table 8 Pin connection of the CSI to the PCF5087X

PCF50732

PCF5087X

• Data in (CDI)

• Data out (CDO)

• Clock (CCLK)

• Enable (CEN).

I/O

CDI

CDO

CCLK

CEN

I

O

I

RFDO

RFDI

O

I

RFCLK

RFE_N2

O

Table 8 lists the normal connections to the PCF5087X.

I

The data sent to or from the device is loaded in bursts

framed by CEN. Clock edges and data bits are ignored

until CEN goes active (LOW). Each data word consists of

21 bits that comprises a 4-bit device address, a 4-bit

register address, a 12-bit data word and a dummy bit; see

Table 9. The 21 bits are transmitted with MSB first.

Figure 5 shows the valid timing for data transmission on

the control interface.

Table 9 Bit mapping of the 21-bit words

BIT CONTENT DESCRIPTION

00 to 03 ADD0 to ADD3 device address; for the

PCF50732 this is ‘1001’

(= 9 decimal)

04 to 07 RA0 to RA3

register address

Data is read in from the CDI pin on the rising edge of the

CCLK clock and output on CDO on the falling edge of the

CCLK clock. Data is written into the registers on the rising

edge of CEN.

08 to 19 DB00 to DB11 data value

20 dummy don’t care

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PCF50732

12.2 Control Serial Interface (CSI) timing characteristics

handbook, full pagewidth

CCLK

t

27

22

24

CEN

t

26

t

25

38

dummy

MSB(#19)

ADD0(#0)

CDI

t

23

high-Z

dummy

MSB(#19)

CDO

t

MGR997

37

Fig.11 Timing diagram of the Control Serial Interface (CSI).

Table 10 CSI timing characteristics

For the timing diagram see Fig.11.

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

ns

t₂₂

t₂₃

t₂₄

t₂₅

t₂₆

t₂₇

t₃₇

t₃₈

CEN set-up time

20

−

CDO data valid after falling clock edge

CCLK cycle time

−

50

−

ns

100

20

30

−

data set-up time to rising edge of CCLK

data hold time from rising edge of CCLK

CEN hold time

−

CDO 3-state after CEN HIGH

CEN HIGH time

30

−

50

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PCF50732

12.3 Control register block

This section describes the different registers that are implemented in the PCF50732. An overview is given in Table 11.

Tables 12 to 29 describe all the registers of the PCF50732.

Table 11 Control register block overview

ADDRESS

ACCESS

REGISTER NAME

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

W

R/W

R

Read request register

AUXDAC1 (AGC) value register

AUXDAC2 (AFC) value register

Burst control register

AUXADC control register

AUXADC channel 1 register A (AUXADC1A); note 1

AUXADC channel 1 register B (AUXADC1B); note 1

AUXADC channel 2 register (AUXADC2); note 1

AUXADC channel 3 register (AUXADC3); note 1

AUXADC channel 4 register (AUXADC4); note 1

Voice band control register

R

R/W

Voice band volume register

Power control register

RAM interface register

Baseband receive control register

Test mode register; note 2

Notes

1. See description in Section 11.4.

2. Do not use this register.

12.3.1 READ REQUEST REGISTER

Table 12 Read request register

X = don’t care during a read/or write access.

VALUE

6

ADDRESS

REGISTER NAME

11

10

9

8

7

5

4

3

2

1

0

0000

Read request register

X

r3

r2

r1

r0

s3

s2

s1

s0

Table 13 Read request registers value description

VALUE OF

SYMBOL

r3 to r0

DESCRIPTION

Address of the register to be read.

Subaddress that might be needed. The subaddress bits are right

Read request register

s3 to s0

aligned, meaning that the subaddress always starts with bit ‘s0’ (LSB);

e.g. in case of two subaddress bits, ‘s1’ and ‘s0’ are used.

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PCF50732

12.3.2 AUXDAC1 (AGC) VALUE AND AUXDAC2 (AFC) VALUE REGISTERS

Table 14 Registers overview

X = don’t care during a read/or write access.

VALUE

6

ADDR.

REGISTER NAME

11

10

9

8

7

5

4

3

2

1

0

0001 AUXDAC1 (AGC) value register

0010 AUXDAC2 (AFC) value register

X

b7 b6 b5 b4 b3 b2 b1 b0

b11

b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Table 15 AUXDAC1 (AGC) value and AUXDAC2 (AFC) value registers value description

VALUE OF

SYMBOL

DESCRIPTION

AUXDAC1 (AGC) value register b7 to b0

input value to the 8-bit AUXDAC1 (fed directly into the DAC); the default

value is 85H

AUXDAC2 (AFC) value register b11 to b0 input value to the 8-bit AUXDAC2 (fed directly into the DAC); the default

value is 800H

12.3.3 BURST CONTROL REGISTER

The Burst control register controls the timing of the transmit burst (TX-burst). The ‘lo’-registers contain the lower 8 bits,

the ‘hi’-registers the upper 4 bits of a 12-bit delay value. Therefore, each register has a programmable range

from 0 to 4095. Not all combinations of values might make sense e.g. ramp-down before ramp-up.

Table 16 Burst control register (address 001 and subaddresses)

X = don’t care during a read/or write access.

SUBADDRESS

VALUE

FUNCTION

11

(s3)

10

(s2)

9

(s1)

8

(s0)

7

6

5

4

3

2

1

0

RU-lo

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

b7

X

b6

X

b5

X

b4

X

b3

b2

b1

b9

b1

b9

b1

b9

b1

b9

b1

b9

X

b0

b8

b0

b8

b0

b8

b0

b8

b0

b8

b0

a0

d0

RU-hi

b11 b10

b3 b2

b11 b10

b3 b2

b11 b10

b3 b2

b11 b10

b3 b2

b11 b10

RM-lo

b7

X

b6

X

b5

X

b4

X

RM-hi

RD-lo

b7

X

b6

X

b5

X

b4

X

RD-hi

BIEN0-lo

BIEN0-hi

BIEN1-lo

BIEN1-hi

Single/double burst mode⁽¹⁾

DAC3 burst RAM address⁽¹⁾

DAC3 burst RAM data⁽¹⁾

b7

X

b6

X

b5

X

b4

X

b7

X

b6

X

b5

X

b4

X

a5

d5

a4

d4

a3

d3

a2

d2

a1

d1

d9⁽²⁾d8⁽²⁾

d7

d6

Notes

1. The programming is described in Section 9.3.2.2.

2. The subaddress positions bit 9 (s1) and bit 8 (s0) do not apply to the DAC3 burst RAM data register.

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Table 17 Burst control registers value description

VALUE OF

DESCRIPTION

Value RU, consisting of RU-lo (least signiﬁcant byte) and RU-hi (most signiﬁcant byte), is the delay

RU

measured in quarterbits (¹⁄₁₂MCLK) between the rising edge of TXON and the start of the ramp-up on

AUXDAC3. After this delay, the ﬁrst 16 values of the AUXDAC3 RAM are sent to AUXDAC3. Shifting out

is done at ¹⁄₂₄MCLK.

RM

RD

Value RM, consisting of RM-lo (least signiﬁcant byte) and RM-hi (most signiﬁcant byte), is the delay

measured in quarterbits between the rising edge of TXON and the start of the intermediate ramp in a

double burst ramp. The RM value is only used in multislot mode. RM must be greater than RU + 32.

Value RD, consisting of RD-lo (least signiﬁcant byte) and RD-hi (most signiﬁcant byte), is the delay

measured in quarterbits between the rising edge of TXON and the start of the ramp-down on AUXDAC3.

RD must be greater than RU + 32, or in case of multislot mode, greater than RM + 32.

BIEN0

BIEN1

Value BIEN0, consisting of BIEN0-lo (least signiﬁcant byte) and BIEN0-hi (most signiﬁcant byte), is the

delay measured in quarterbits between the rising edge of TXON and the falling edge of BIEN.

Value BIEN1, consisting of BIEN1-lo (least signiﬁcant byte) and BIEN1-hi (most signiﬁcant byte), is the

delay measured in quarterbits between the rising edge of TXON and the rising edge of BIEN. BIEN1

must be greater than BIEN0.

12.3.4 AUXADC CONTROL REGISTER

Table 18 AUXADC control register (address 0100 and subaddresses)

X = don’t care during a read/or write access.

SUBADDRESS

FUNCTION

VALUE

11

10

9

8

7

6

5

4

3

2

1

0

(s2) (s1) (s0)

AUXADC conversion delay

value register

0

X

b6

b5

b4

b3

b2

b1

b0

AUXADC ﬂag register

0

1

0

1

0

X

Qoff Ioff auxoff ﬂag 4 ﬂag 3 ﬂag 2 ﬂag 1B ﬂag 1A

9-bit signed offset compensation value

AUXADC offset value

register

I channel offset value

register

1

0

1

0

1

9-bit signed offset compensation value

Q channel offset value

register

Offset trigger register

X

Q-off

I-off

Aux

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Table 19 AUXADC control registers value description

VALUE OF

DESCRIPTION

AUXADC conversion delay

value register

The 7-bit value (b6 to b0) denotes the delay measured in 48MCLK units between the

rising edge of TXON and the conversion on AUXADC1A. The normal power-on

settling time is added to this delay. Default value is 0.

AUXADC ﬂag register

The AUXADC ﬂag register returns the status of the AUXADC converters. If an

auxiliary A/D conversion is pending, the ﬂag of the corresponding AUXADC will be

set. The ﬂag register is read only.

AUXADC offset value register The offset value registers contain signed 9-bit offset compensation values. These

values are subtracted automatically from all baseband receive (BBRX) and AUXADC

I channel offset value register

measurements to compensate for offset errors. The compensation values can be

Q channel offset value register

read and written and have a default value of 0. It can also be measured by the device

Offset trigger register

itself.

A write to the Offset trigger register will trigger an offset measurement for each of the

channels (Q-off, I-off or AUXADC) selected.

Offset measurements are special cases of AUXADC measurements and are done

sequentially. Each calibration measurement takes approximately 100 µs. The Offset

trigger register is write only.

12.3.5 AUXADC REGISTERS

Table 20 AUXADC registers overview

VALUE

ADDR.

REGISTER NAME

11 10

9

8

7

6

5

4

3

2

1

0

0101 AUXADC channel 1 register A (AUXADC1A)

0110 AUXADC channel 1 register B (AUXADC1B)

0111 AUXADC channel 2 register (AUXADC2)

1000 AUXADC channel 3 register (AUXADC3)

1001 AUXADC channel 4 register (AUXADC4)

b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Table 21 AUXADC registers value description

VALUE OF

DESCRIPTION

AUXADC1A 12-bit result of the A/D conversion on AUXADC channel 1, measured during a transmission burst

AUXADC1B 12-bit result of the A/D conversion on AUXADC channel 1, measured outside a transmission burst

AUXADC2

AUXADC3

AUXADC4

12-bit result of the A/D conversion on AUXADC channel 2

12-bit result of the A/D conversion on AUXADC channel 3

12-bit result of the A/D conversion on AUXADC channel 4

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12.3.6 VOICE BAND CONTROL REGISTER

The Voice band control register is used to control the following functionality of the voice band CODEC:

• Analog input source: microphone (MICAMP) or auxiliary (AUXMIC) input

• Analog output device: earphone (EARAMP), auxiliary (AUXAMP) or buzzer (BUZAMP) output; this register allows

individual control of all three output amplifiers

• EARAMP output mode: single-ended (EARP) or differential (EARN/EARP). This selects the input source for the

EARAMP-N amplifier. In single-ended mode EARAMP-N will be at V_ref, in differential mode it will carry the output signal

• General purpose output pin: AMPCTRL

• Receive and transmit path delay values

• ASI clock mode

• TX gain boost (MICHI).

Table 22 Voice band control register (address 1010 and subaddresses)

X = don’t care during a read/or write access.

SUBADDRESS

11 10

VALUE

FUNCTION

FUNCTION SETTING

9

8

7

6

5

4

3

2

1

0

(s2) (s1) (s0)

0

1

0

1

MICAMP (default)

AUXMIC

Select input source

0

don’t care

X

0

X

0

X

0

EARAMP-P off

EARAMP-P on (default)

X EARAMP-N off

1

X EARAMP-N on (default)

X AUXAMP off (default)

X AUXAMP on

Select output ampliﬁer

1

don’t care

X

1

X

X BUZAMP off (default)

X BUZAMP on

1

0

1

0

1

a

0

1

0

1

single-ended

EARAMP output mode

AMPCTRL pin polarity

0

1

0

1

don’t care

differential (default)

active LOW

don’t care

active HIGH (default)

Receive path data channel

Transmit path data channel

1

0

1

d

c

b

don’t care

4-bit delay value (default = 0)

single clock (default)

double clock

7 dB

ASI clock mode

1

0

1

don’t care

TX gain boost (MICHI)

35 dB (default)

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12.3.7 VOICE BAND VOLUME REGISTER

Voice band gain settings can be independently programmed for: TXPGA, RXPGA, RXVOL and SidePGA.

Table 23 Voice band volume register (address 1011 and subaddresses)

X = don’t care during a read/or write access.

SUBADDRESS

11 10

VALUE

SELECTED

RANGE

DEFAULT

SETTING

FUNCTION

9

8

7

6

5

4

3

2

1

0

(s2) (s1) (s0)

TXPGA gain

0

1

0

1

0

1

0

1

0

1

X

a

b

c

d

X

e

X

f

−24 to +12 dB

−30 to +6 dB

0 dB

RXPGA gain

RXVOL gain

f

−12 dB

SidePGA gain

f

mute

Band gap setting level

Experimental bits

X

−100 to +75 mV 0 mV offset

dir pll

dc vbch hclk bgb −

pll on, all

others off

Table 24 Voice band volume registers value description

VALUE

TXPGA gain

REMARKS

DESCRIPTION

microphone calibration

earphone calibration

TXPGA and RXPGA settings use the 6-bit binary ﬁxed point value

‘ab.cdef’ as a multiplier for each PCM-sample. This results in a

control range of +12 to −24 dB. See note 1a.

RXPGA gain

RXVOL gain

customer volume control

RXVOL and SidePGA settings use the 6-bit binary ﬁxed point

value ‘a.bcdef’ as a multiplier for each PCM-sample. This results

in a control range of +6 to −30 dB (and mute). See note 1b.

SidePGA gain

−

Experimental bits

−

• dir: bypass clock buffer

• pll: clock optimizer

• dc: bypass clock capacitor

• vbch: voice band chopping

• hclk: 26 MHz master clock input

• bgb: band gap boost

do not use

Band gap setting level

Note

1. Possible gain settings are listed in Table 25 or can be calculated using the following formulae (‘n’ is an integer that

represents the value that is written into the register; n = 0 to 63):

n

16

a) RXPGA and TXPGA: gain = 20 × log------ ; add 6.02 dB to each gain for RXPGA and TXPGA settings.

n

b) RXVOL and SidePGA: gain = 20 × log------

32

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12.3.7.1 Possible gain selections for voice band blocks: RXPGA, TXPGA, RXVOL and SidePGA

Table 25 shows the possible gain selections for the voice band blocks RXPGA, TXPG, RXVOL and SidePGA. It should

be noted that not all possible combinations of these volume settings are meaningful; setting RXPGA, SidePGA and

RXVOL to maximum will result in clipping of the output signal.

Table 25 Gain selections

GAIN (dB)

BINARY

CODE

BINARY

CODE

RXPGA/TXPGA RXVOL/SidePGA

111111

111110

111101

111100

111011

111010

111001

111000

110111

110110

110101

110100

110011

110010

110001

110000

101111

101110

101101

101100

101011

101010

101001

101000

100111

100110

100101

100100

100011

100010

100001

100000

11.88

11.74

11.60

11.46

11.31

11.17

11.01

10.86

10.70

10.54

10.38

10.22

10.05

9.88

5.88

5.74

5.60

5.46

5.31

5.17

5.01

4.86

4.70

4.54

4.38

4.22

4.05

3.88

3.70

3.52

3.34

3.15

2.96

2.77

2.57

2.36

2.15

1.94

1.72

1.49

1.26

1.02

0.78

0.53

0.27

0.00

011111

011110

011101

011100

011011

011010

011001

011000

010111

010110

010101

010100

010011

010010

010001

010000

001111

001110

001101

001100

001011

001010

001001

001000

000111

000110

000101

000100

000011

000010

000001

000000

5.72

5.44

−0.28

−0.56

−0.86

−1.16

−1.48

−1.80

−2.14

−2.50

−2.87

−3.25

−3.66

−4.08

−4.53

−5.00

−5.49

−6.02

−6.58

−7.18

−7.82

−8.52

−9.28

−10.10

−11.02

−12.04

−13.20

−14.54

−16.12

−18.06

−20.56

−24.08

−30.10

off

5.14

4.84

4.52

4.20

3.86

3.50

3.13

2.75

2.34

1.92

1.47

1.00

9.70

0.51

9.52

0.00

9.34

−0.58

−1.18

−1.82

−2.52

−3.28

−4.10

−5.02

−6.04

−7.20

−8.54

−10.12

−12.06

−14.56

−18.08

−24.10

off

9.15

8.96

8.77

8.57

8.36

8.15

7.94

7.72

7.49

7.26

7.02

6.78

6.53

6.27

6.00

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12.3.8 POWER CONTROL REGISTER

The Power control register is used to control power-up and power-down of the different sections of the device. Changing

the power status is accomplished by addressing the device as shown in Table 26 and setting bit 0 (= a) according to the

required state:

a = 0 → power-down

a = 1 → power-up.

Setting the baseband RX or TX flag is functionally equivalent to setting RXON or TXON respectively (logical

OR function). The CSI is also accessible when the band gap is powered down. Therefore no reset is required to power-up

after total power-down.

Table 26 Power control register (address 1100 and subaddresses)

SUBADDRESS

11 10

VALUE

DEFAULT

FUNCTION

9

8

7

6

5

4

3

2

1

0

VALUE

STATUS

(s3) (s2) (s1) (s0)

AUXDAC1

AUXDAC2

AUXDAC3

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

a

0

1

0

1

0

1

off

on

off

on

off

on

Voice band transmit

Voice band receive

V_ref

don’t care

Baseband receive

Baseband transmit

Complete device

Normal operation is to write an address into the VSP

instruction RAM program counter and write low and high

bytes of the 16-bit instructions into their respective

locations. No auto-increment is foreseen, i.e. the address

register must be updated by the user. Writing to the IRAM

is only possible when voice band transmit and receive

sections are both powered off. If this is not the case write

actions are ignored.

12.3.9 RAM INTERFACE REGISTER

The RAM interface register is a general purpose

communication channel between the serial interface CSI

and the voice band signal processor. None of the

processor registers have default values.

The Voice band control register is used to communicate

with the voice band signal processor. Register functions

with subaddress ‘00’ to ‘11’ can be used to program the

Instruction RAM (IRAM) when the voice band processor is

not running, i.e. when voice band receive and transmit

sections are both powered down.

Reading back from the IRAM is not straightforward due to

the need for an extra clock pulse when accessing RAMs;

when reading back the contents of RAM locations 1, 2, 3

and 4 actual output is ‘undefined’ as 1, 2, 3, etc.

The IRAM registers are used to write into the voice band

instruction RAM.

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Table 27 RAM interface register (address 1101 and subaddresses)

X = don’t care during a read/or write access.

SUBADDRESS

FUNCTION

VALUE

11

10

9

8

7

6

5

4

3

2

1

0

(s1)

(s0)

VSP instruction RAM data low-byte

VSP instruction RAM data high-byte

VSP instruction RAM program counter

VSP interface register

0

1

0

1

0

1

X

d7 d6 d5 d4 d3 d2 d1 d0

a8 a7 a6 a5 a4 a3 a2 a1 a0

x9 x8 x7 x6 x5 x4 x3 x2 x1 x0

12.3.10 BASEBAND RECEIVE CONTROL REGISTER

Normal bandwidth refers to an input signal bandwidth of 100 kHz used for ZIF operation, double bandwidth is 200 kHz

used for NZIF operation. Normal sampling refers to a sampling rate of ¹⁄₂MCLK, double sampling refers to sampling at

MCLK.

Table 28 Baseband receive control register (address 1110)

VALUE

OUTPUT

RATE

FUNCTION

11

10

9

8

7

6

5

4

3

2

1

0

Normal bandwidth;

normal sampling (ZIF)

double sampling; note 2

Double bandwidth;

0

1

271 kHz⁽¹⁾

135 kHz

don’t care

normal sampling (NZIF)

double sampling

0

1

0

1

542 kHz

271 kHz

Notes

1. Default value.

2. Do not use this function.

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12.3.11 TEST MODE REGISTER

Only test mode 8 (TM8) is available to the end user. It is used to mark baseband-I (BB-I) samples with a logic 0 and

baseband-Q (BB-Q) samples with a logic 1 on the LSB of the 12-bit value.

Table 29 Test mode register (address 1111)

VALUE

TEST

FUNCTION

MODE

11 10

9

8

7

6

5

4

3

2

1

0

NM

normal mode (default)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

TM1

TM2

TM3

TM4

TM5

TM6

TM7

TM8

TM9

baseband transmit (BBTX) I digital

baseband receive (BBRX) digital

voice band (VB) loop digital

voice band transmit/receive (VBTX/RX) digital

CSI

baseband (BB) DACs

don’t care

voice band receive (VBRX) DAC current sources

I/Q marking test

voice band signal processor test mode

TM10 VSP signature output mode

TM11 MCLK input reﬂected on BDIO

TM12 baseband bitstream output

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No buffering is foreseen for these samples, which means

that the VSP program is responsible for proper spacing in

time of the input- and output samples. Failure to ensure

proper spacing will result in heavily distorted signals.

13 VOICE BAND SIGNAL PROCESSOR (VSP)

13.1 Hardware description

The VSP used in the PCF50732 is a 30-bit fixed point VSP

with separate data and instruction areas. The data path

consists of two guard bits, 16 data bits before and 12 data

bits behind the binary point for a total of 30 bits. Twos

complement notation is used inside the data path.

Intermediate results from calculations are stored in a

64 × 30-bit wide data RAM. Data and Programmable Gain

Amplifier (PGA) settings are read in via 7 input ports and

written back into 3 output ports.

Synchronization to the 8 kHz frame-sync signals AFS is

also done under program control. The VSP program must

ensure that noise shaper and FIR filter are properly reset

before actual operation is started.

A VSP-emulator and a VSP-assembler have been written

in order to facilitate program development. The assembler

generates a stream of 16-bit words that need to be loaded

into the instruction RAM. This is done by repeated writes

to the VSP control register. The sequence would be as

follows:

The instruction path uses a 16-bit format with the 4 MSBs

designating the opcode and the trailing 12 bits used to

describe the operand. The VSP has 12 major instructions;

some instructions use two opcodes (operation codes). The

addressing range is 9 bits wide, allowing for a total of

512 instructions, which is more than adequate for the filter

types it is intended to calculate. Some room is available for

Built-In Self Test (BIST). The ALU consists of a 30-bit

subtractor, a 30-bit adder and a 30 × 16-bit ‘modified

booth’-type parallel multiplier.

1. Write address into the VSP instruction RAM program

counter register

2. Write the upper 8 bits into the VSP instruction RAM

data high-byte register

3. Write the lower 8 bits into the VSP instruction RAM

data low-byte register.

This sequence should be repeated until the VSP is fully

programmed. Programming can only be done when the

VSP is not active. The VSP program counter will be set to

location 0 and operation starts after enabling voice band

transmit or voice band receive. See also the CSI

description in Chapter 12.

The VSP’s accumulator has built-in overrange checking

and will limit values to their minimum (in case of underflow)

or maximum (in case of overflow) value.

The VSP engine is designed to operate at 4 MIPS on a

8 kHz PCM signal.

All instructions take one clock-cycle to complete. It should

be noted that since the noise shaper operates at a sample

rate of 32 kHz and the voice band filter operates at a

sample rate of 40 kHz it is necessary to transfer 4 samples

to the receive output and to read 5 samples from transmit

input for each frame.

1999 May 03

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Philips Semiconductors

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PCF50732

INPUT PORTS

handbook, full pagewidth

(from ADI) (from FIR)

RAM/ROM

512 × 30-BIT

CTE in

RX in

TX in

CSI in TXPGA RXPGA RXVOL SidePGA

(9.0)

or

(0.12)

(1)

(16.0)

(12.0)

(2.4)

(1.5)

PC

INPUT SELECTOR

(18.12)

(6.0)

(18.12)

FLAGS

ALU

(2.0)

RAM

64 × 30-BIT

(18.12)

AFS

INDEX

(6.0)

ACCUMULATOR

(18.12)

OUTPUT REGISTER

(16.0)

(12.0)

CSI out

RX out

TX out

(to ADO)

(to NOISE SHAPER)

MGR998

OUTPUT PORTS

The program ROM and program counter are not shown.

(1) (x.y) designates a x + y bits wide data stream with x bits

before and y bits after the binary point.

Fig.12 Voice band Signal Processor (VSP) block diagram.

1999 May 03

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Philips Semiconductors

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PCF50732

13.2 VSP assembler language

The stack for return addresses is only one entry deep which means that nesting of subroutines is not possible.

Table 30 VSP instruction set

X = don’t care during a read/or write access. For the description of the bit symbols see notes 1 to 8.

MNEMONIC

INSTRUCTION

I3 I2 I1 I0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

LDA

Load accumulator

0

m3 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0

m3 m2 m1 m0 d8 d7 d6 d5 d4 d3 d2 d1 d0

STO

RTN

ADD

Store accumulator

0

1

0

1

m2 m1 m0

X

d5 d4 d3 d2 d1 d0

Return from subroutine

Add to accumulator

X

m3 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0

m3 m2 m1 m0 d8 d7 d6 d5 d4 d3 d2 d1 d0

m3 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0

m3 m2 m1 m0 d8 d7 d6 d5 d4 d3 d2 d1 d0

m3 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0

m3 m2 m1 m0 d8 d7 d6 d5 d4 d3 d2 d1 d0

SUB

MUL

Subtract from

accumulator

0

1

0

1

0

Multiply with accumulator

JMFS

JMFC

JSFS

JSFC

Jump if ﬂag set

1

0

1

0

1

0

1

f2

f1

f0 a8 a7 a6 a5 a4 a3 a2 a1 a0

Jump if ﬂag clear

Jump subroutine if ﬂag set

Jump subroutine if ﬂag

clear

STF

IDX

Set/clear ﬂag

1

0

1

f2

f1

f0

X

d0

Index operations

im2 im1 im0

i5 i4 i3 i2 i1 i0

Notes

1. c11 to c0 denotes a 12-bit twos complement coefficient between −1 and +1.

2. m3 to m0 denotes a 4-bit instruction mode descriptor.

3. f2 to f0 denotes a 3-bit flag descriptor.

4. a8 to a0 denotes a 9-bit address.

5. i5 to i0 denotes a 6-bit index register value.

6. a8 to a0 denotes a 9-bit address.

7. X is a don’t care bit.

8. im2 to im0 denotes a 3-bit instruction mode descriptor for the IDX operator.

1999 May 03

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Philips Semiconductors

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PCF50732

Table 31 Mode descriptions

ASSEMBLER

SHORT HAND

m3

m2

m1

m0

MODE NAME

register

OPERAND

R(d5 to d0)

RANGE

0

1

0

1

0

1

0

1

0

1

0

register 0 to 63

r

i

register indexed

port

R((d5 to d0) + index) register 0 to 63

P(d2 to d0)

d8 to d0

index

ports 0 to 7

p

s

i

small integer

index

−256 to +255; note 1

0 to 63; note 1

bits 11 to 0 form a 12-bit twos complement coefﬁcient between −1 and +1

c

Note

1. Value range in increments of 1.

Table 32 Index mode descriptions

im2

im1

im0

NAME

store

OPERAND

0

1

0

1

0

index = d5 to d0

increment

accu

index = (d5 to d0) + index

index = accu

Table 33 Flag descriptions

f2

f1

f0

NAME

ALW

DESCRIPTION

REMARKS

TYPE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

always set

ﬂag is clear in VSP test mode; used to initiate BIST system

INZ

EQ0

EQ1

SYNC

A

set if index not zero used to implement loops

set if accu is all 0

set if accu is all 1

PCM sync signal

user ﬂag A

used to sync VSP to external PCM signal

user

B

user ﬂag B

C

user ﬂag C

used to reset noise shaper and FIR ﬁlter

Table 34 Port descriptions

P2

P1

P0

NAME

DIRECTION

RANGE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive (RX)

read/write

read

−32768 to +32767 (16 bits)

−2048 to +2047 (12 bits)

ﬁxed 0

Transmit (TX)

CSI

ZERO

TXPGA

RXPGA

RXVOL

SidePGA

read

0 to 63 (−24 to +12 dB)

0 to 63 (−20 to +6 dB)

read

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PCF50732

• f.l. = a 3-bit flag descriptor

• addr = a 9-bit address

13.3 Descriptions of the VSP instruction set

13.3.1 CONVENTIONS

• stack = a one entry deep return address stack

• PC = a 9-bit program counter

In the descriptions of the VSP instruction set:

• A = the 30-bit accumulator

• o.a. = the 9-bit old address

• I = the 6-bit index register

• s.i. = small integer

• r.a. = a 6-bit register address

• p.n. = a 3-bit port number (address)

• coeff = a 12-bit coefficient

• X = don’t care during a read/or write access.

13.3.2 LDA INSTRUCTION

The LDA (Load accumulator) instruction is used to load data into the VSP’s accumulator. Flags affected are

EQ0 and EQ1.

Table 35 LDA instruction

15 14 13 12 11 10 9 8 7 6 5 4 3

2

1

0

OPERATION ASSEMBLER

NAME

0

1

0

coefﬁcient

coeff → A

LDA c <coeff> load coefﬁcient

0

1

0

1

0

0 X X X

1 X X X

register address

R(r.a.) → A

LDA r <r.a.>

load register

R(r.a. + I) → A LDA i <r.a.>

load register indexed

0 X X X X X X port number P(p.n.) → A

LDA p <p.n.> load port

1

small integer

s.i. → A

I → A

LDA s <s.i.>

LDA x

load integer

load index

0 X X X X X X

X

13.3.3 STO INSTRUCTION

The STO (Store accumulator) instruction is used to store data into register RAM or output ports. No flags are affected.

Table 36 STO instruction

15 14 13 12 11 10 9 8 7 6 5 4 3

2

1

0

OPERATION ASSEMBLER

A → R(r.a.) STO r <r.a.>

A → R(r.a. + I) STO i <r.a.>

NAME

0

1

0

1

0 X X X

1 X X X

register address

store register

store register indexed

0 X X X X X X port number A → P(p.n.)

STO p <p.n.> store port

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PCF50732

13.3.4 ADD INSTRUCTION

The ADD (Add to accumulator) instruction is used to add data to the VSP’s accumulator. Flags affected are

EQ0 and EQ1.

Table 37 ADD instruction

15 14 13 12 11 10 9 8

7

6

5

4

3

2

1

0

OPERATION

ASSEMBLER

NAME

0

1

0

1

0

coefﬁcient

A + coeff → A

ADD c <coeff> add coefﬁcient

0

0 X X X

1 X X X

register address

A + R(r.a.) → A

ADD r <r.a.>

add register

A + R(r.a. + I) → A ADD i <r.a.>

add register

indexed

0

1

0

1

0

0 X X X X X X port number A + P(p.n.) → A

ADD p <p.n.> add port

1

small integer

A + s.i. → A

A + I → A

ADD s <s.i.>

ADD x

add integer

add index

0 X X X X X X

X

13.3.5 SUB INSTRUCTION

The SUB (Subtract from accumulator) instruction is used to subtract data from the VSP’s accumulator. Flags affected

are EQ0 and EQ1.

Table 38 SUB instruction

15 14 13 12 11 10 9 8

7

6

5

4

3

2

1

0

OPERATION

ASSEMBLER

NAME

0

1

coefﬁcient

A − coeff → A

SUB c <coeff> subtract

coefﬁcient

0

1

0

0 X X X

1 X X X

register address

A − R(r.a.) → A

SUB r <r.a.>

subtract register

A − R(r.a. + I) → A SUB i <r.a.>

subtract register

indexed

0

1

0

1

0

0 X X X X X X port number A − P(p.n.) → A

SUB p <p.n.> subtract port

1

small integer

A − s.i. → A

A − I → A

SUB s <s.i.>

SUB x

subtract integer

subtract index

0 X X X X X X

X

13.3.6 MUL INSTRUCTION

The MUL (Multiply with accumulator) instruction is used to multiply data with the VSP’s accumulator. Flags affected are

EQ0 and EQ1. The second operand of the multiplication is restricted to 16-bit; e.g. R(r.a.).

Table 39 MUL instruction

15 14 13 12 11 10 9 8

7

6

5

4

3

2

1

0

OPERATION

ASSEMBLER

NAME

1

0

1

coefﬁcient

A × coeff → A

MUL c <coeff> multiply

coefﬁcient

1

0

0 X X X

1 X X X

register address

A × R(r.a.) → A

MUL r <r.a.>

multiply register

A × R(r.a. + I) → A MUL i <r.a.>

multiply register

indexed

1

0

1

0

0 X X X X X X port number A × P(p.n.) → A

MUL p <p.n.> multiply port

1

small integer

A × s.i. → A

A × I → A

MUL s <s.i.>

MUL x

multiply integer

multiply index

0 X X X X X X

X

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PCF50732

13.3.7 JMFS INSTRUCTION

The JMFS (Jump if flag set) is used for conditional jumps. The jump is carried out when the flag is set, otherwise the PC

is simply incremented.

Table 40 JMFS instruction

15 14 13 12 11 10 9

ﬂag

8

7

6

5

4

3

2

1

0

OPERATION

<addr> → PC

ASSEMBLER

1

0

1

0

address

JMFS <f.l.> <addr>

13.3.8 JMFC INSTRUCTION

The JMFC (Jump if flag clear) is used for conditional jumps. The jump is carried out when the flag is clear, otherwise the

PC is incremented.

Table 41 JMFC instruction

15 14 13 12 11 10

ﬂag

9

8

7

6

5

4

3

2

1

0

OPERATION

ASSEMBLER

1

0

1

address

<addr> → PC

JMFC <f.l.> <addr>

13.3.9 JSFS INSTRUCTION

The JSFS (Jump subroutine if flag set) is used for conditional call to a subroutine. The jump is carried out when the flag

is set, otherwise the PC is incremented. Note that the return stack is just one entry deep, so nesting of subroutines is not

allowed.

Table 42 JSFS instruction

15 14 13 12 11 10

ﬂag

9

8

7

6

5

4

3

2

1

0

OPERATION

ASSEMBLER

<o.a> → stack

<addr> → PC

JSFS <f.l.> <addr>

1

0

address

13.3.10 JSFC INSTRUCTION

The JSFC (Jump subroutine if flag clear) is used for conditional jumps to a subroutine. The jump is carried out when the

flag is clear, otherwise the PC is incremented. It should be noted that the return stack is just one entry deep, so nesting

of subroutines is not allowed.

Table 43 JSFC instruction

15 14 13 12 11 10

ﬂag

9

8

7

6

5

4

3

2

1

0

OPERATION

ASSEMBLER

<o.a> → stack

<addr> → PC

JSFC <f.l.> <addr>

1

address

13.3.11 RTN INSTRUCTION

The RTN (Return from subroutine) is used to return from a subroutine.

Table 44 RTN instruction

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

OPERATION

ASSEMBLER

0

1

X

stack → PC

RTN

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PCF50732

13.3.12 STF INSTRUCTION

The STF (Set/clear flag) instruction is used to set or clear the user flags A, B or C. System flags cannot be set or reset

under program control.

Table 45 STF instruction

15 14 13 12 11 10

ﬂag

9

8

7

6

5

4

3

2

1

0

OPERATION

ASSEMBLER

1

0

X

value <value> → <f.l.> STF <f.l.> <value>

13.3.13 IDX INSTRUCTION

The IDX (Index operations) instruction is used to store and increment/decrement index values. It should be noted that

additions to the index register is done in modulo 64. A ‘decrement index register by one’ could therefore be programmed

as ‘IDX + 63’. The ‘IDX A’ instruction loads the 6 bits to the left of the binary point into the index register, i.e. it stores the

integer part modulo 64 into I.

Table 46 IDX instruction

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

OPERATION

ASSEMBLER

IDX = <value>

1

0

1

0

1

0

1

0

X

value

<value> → I

I + <value> → I

A → I

IDX + <value>

IDX A

X

13.4 The assembler/emulator

A 2-pass assembler and an emulator was made to assist with the development of VSP programs. The software programs

are written in ‘C’ and currently run under NT, HPUX and LINUX operating systems. The assembler reads assembler

source files and produces a log file, sets of VHDL or Verilog stimuli and an output file containing CSI instructions that,

when loaded, will load the executable into the VSP RAM.

Requirements for the assembler source code are:

• One instruction or pseudo instruction (see Table 47) per line

• No empty lines

• A maximum of 512 instructions

• Operation always starts at instruction 0.

Table 47 Assembler pseudo instructions

MNEMONIC

INSTRUCTION

{<.>< ><label>}

DEFINITION

. label

Deﬁnes a location inside the source code. Is usually used as

an argument to JMF/JSF instructions.

deﬁne

include

--

{<deﬁne>< ><label> < ><value> Deﬁnes a variable and assigns a value to it. These variables

can then be referenced in the assembler instructions.

{<include>< ><ﬁle name>}

Reads in another source code ﬁle and then continues with the

current ﬁle.

{<-->< ><comment>

Deﬁnes a comment; the rest of the line is skipped.

1999 May 03

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PCF50732

14 LIMITING VALUES

In accordance with Absolute Maximum Rating System (IEC 134).

SYMBOL

V_DD

I_DD

I_I1

PARAMETER

MIN.

−0.5

MAX.

+3.3

UNIT

supply voltage

supply current

V

−

30

mA

V

DC current into any pin; except EARP/EARN, AUXSP and BUZ −10

+10

I_I2

DC current into pins EARP/EARN, AUXSP and BUZ

input voltages on all inputs

−100

+100

V_DD+ 0.5

800

V_I

−0.5

−

P_tot

T_amb

T_stg

total power dissipation

mW

°C

operating ambient temperature

storage temperature

−40

−65

+85

+150

°C

15 THERMAL CHARACTERISTICS

SYMBOL

R_th(j-a)

PARAMETER

CONDITIONS

VALUE

UNIT

thermal resistance from junction to ambient in free air

80

K/W

16 DC CHARACTERISTICS

T_amb= −40 to +85 °C; V_SS= 0 V (ground pins must be interconnected externally); V_DDA≥ V_DDD

;

V_DDA(bb)= V_DDA(vb)= V_DDA(vbo)= V_DDA(ref)= V_DDA= 2.5 to 2.75 V (supply pins must be interconnected externally);

all voltages with respect to V_SSunless otherwise speciﬁed.

SYMBOL

I_stb(tot)

P_av

PARAMETER

total standby current

CONDITIONS

MIN.

TYP.

10

MAX.

UNIT

µA

−

average power consumption

V_DDD= 1.5 V;

_DDA= 2.7 V; without load

15

mW

V

on audio outputs EARP,

EARN, AUXSP and BUZ

Digital power supply: V_DDD

V_DDDdigital supply voltage

1.0

1.5

2.75

V

Digital inputs: CCLK, CEN, CDI, TXON, RXON, AUXST, ADI, AFS, ACLK and RESET

V_IL

V_IH

I_LI

LOW-level input voltage

HIGH-level input voltage

input leakage current

0.0

−

0.3V_DDD

V_DDD

−

V

0.7V_DDD

−

V

−

±1

µA

Digital outputs: BIEN, BOEN, ADO and AMPCTRL

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

I_sink= 1.5 mA

−

0.2V_DDD

V

I_source= 1.5 mA

0.7V_DDD

−

Digital output: BIOCLK

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

I_sink= 1.5 mA

−

0.2V_DDD

V

I_source= 1.5 mA

0.7V_DDD

−

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PCF50732

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Digital bidirectional pins: CDO and BDIO

V_IL

V_IH

I_LI

LOW-level input voltage

HIGH-level input voltage

input leakage current

0.0

−

0.3V_DDD

V_DDD

−

V

0.7V_DDD

−

V

−

±1

−

µA

V

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

I_sink= 1.5 mA

I_source= 1.5 mA

−

0.2V_DDD

−

0.7V_DDD

−

V

Low-swing clock input: MCLK

I_LIinput leakage current

Analog power supplies: V_DDA(bb), V_DDA(vb), V_DDA(vbo)and V_DDA(ref)

−

±1

−

µA

V_DDA

I_DDA

analog supply voltage

analog supply current

2.5

2.7

3.5

2.75

V

V_DDD= 1.5 V;

_DDA= 2.7 V;

−

mA

V

RXON active

Analog reference pin: V_ref

V_ref

DC reference level

input source/sink current

no external load

−

1.25

0.1

−

V

I_I(ref)

µA

Analog output pins: IP, IN, QP and QN

V_bias(TXIQ)DC bias level

Analog input pins: MICP and MICN

V_ref(MIC)DC input reference level

Analog input pins: AUXMICP and AUXMICN

V_ref(AUXMIC)DC input reference level

Analog output pins: EARP and EARN

V_bias(EAR)DC bias level

Analog output pin: AUXSP

V_bias(AUX)DC bias level

Analog output pin: BUZ

1.175

1.25

0.5V_ref

V_ref

1.325

V

−

V_ref

V_bias(BUZ)

DC bias level

V_ref

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PCF50732

17 AC CHARACTERISTICS

V_DDD= 1.0 to 2.75 V; V_DDA= 2.5 to 2.75 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

f_clk

master clock frequency

−

13.0

−

MHz

Digital input pins: CCLK, CEN, CDI, TXON, RXON, AUXST, ADI, AFS, ACLK and RESET

C_i

input capacitance

−

5.0

pF

Digital output pins: BIOCLK, BIEN, BOEN, ADO and AMPCTRL

t_dLHO

t_dHLO

output rise time

output fall delay

output load = 10 pF

−

10

−

ns

Digital bidirectional pins: CDO and BDIO

C_i

input capacitance

output rise time

output fall delay

−

5.0

10

−

pF

ns

t_dLHO

t_dHLO

output load = 20 pF

Low-swing clock input: MCLK

V_MCLK

input amplitude

duty cycle

note 1

0.1

40

−

0.5V_DDD

60

V

δ_MCLK

%

Analog output pins: IP, IN, QP and QN

t_st(TXIQ)

output settling time

output load = 10 pF // 10 kΩ,

to 1 LSB, for 0.8 to 2.2 V

−

9.6

−

µs

R_o(TXIQ)

output resistance

f < 100 kHz

105

Ω

Analog input pins: IP, IN, QP and QN

R_i(RXIQ)

C_i(RXIQ)

input resistance

differential

200

−

kΩ

input capacitance

−

5

pF

Analog input pins: AUXADC1, AUXADC2, AUXADC3 and AUXADC4

R_i(AUXADC)input resistance

Analog input pins: MICP and MICN

R_i(eq)(MIC)equivalent input resistance

Analog input pin: AUXMICP and AUXMICN

R_{i(eq)(AUXMIC)}equivalent input resistance

Analog output pins: EARP and EARN

R_o(EARAMP)output resistance

Analog output pin: AUXSP

−

1

−

MΩ

kΩ

Ω

differential

200

0

220

−

320

−

f = 1 kHz

1

R_o(AUXAMP)

output resistance

0

−

1

Ω

Analog output pin: BUZ

R_o(BUZ)

output resistance

0

−

1

Ω

Note

1. Input MCLK is internally AC coupled; the signal must not go below V_SSor above V_DDD

.

1999 May 03

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PCF50732

18 FUNCTIONAL CHARACTERISTICS

18.1 Baseband transmit (BSI to TXI/Q)

V_DDA= 2.5 to 2.75 V; T_amb= −40 to +85 °C.

SYMBOL

RES_TXIQ

PARAMETER

resolution of TX DACs

CONDITIONS

MIN.

TYP.

10

55

270.833 −

MAX. UNIT

−

bit

S/N_TXIQ

signal-to-noise TX DACs

input sampling frequency

−

dB

kHz

V

FSIN_TXIQ

V_O(TXIQ)(p-p)

−

output signal amplitude (peak-to-peak

value)

note 1

0.9

1.0

1.1

V_DC(TXIQ)

output DC level

1.15

1.25

1.35

V

AMAT_TXIQ

output amplitude matching between

I and Q TX paths

note 1

−1.75

−0.15

−4.5

−

+1.75

%

+0.15 dB

VOFS_TXIQ

differential DC offset voltage between

IP/IN or QP/QN

+4.5

mV

FRESP_TXIQ

frequency response of random output

signal

f = 0 to 100 kHz

f = 200 kHz

f = 250 kHz

f = 400 kHz

f = 600 kHz

f = 1200 kHz

f > 1800 kHz

note 2

−3

−

dB

µs

ns

−

−30

−33

−60

−70

−

MPEI_TXIQ

AGD_TXIQ

GDL_TXIQ

maximum phase effect instance

absolute group delay

22

10

100

−

note 1

−

group delay linearity

measured at full-scale;

10 kHz < f < 100 kHz;

load: 10 pF // 10 kΩ

−

GDMAT_TXIQ

group delay matching of I and Q TX paths

40

ns

PMAT_TXIQ

phase matching of I and Q TX paths

note 1

−

0.5

1.5

−

deg

PTERMS_TXIQRMS phase trajectory error

PTEPEAK_TXIQpeak phase trajectory error

random input pattern;

notes 1 and 3

0.8

3.0

Notes

1. Measured at full-scale; load: 10 pF // 10 kΩ; f = 67 kHz.

2. Not tested. Defined between the rising edge of BIOCLK which latches a data bit at BDIO to its corresponding

maximum phase change on the analog outputs ITX and QTX.

3. Not tested.

1999 May 03

46

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

18.2 Baseband receive (RXI/Q to BSI)

V_DDA= 2.5 to 2.75 V; T_amb= −40 to +85 °C; all values valid for ZIF and NZIF modes.

SYMBOL

PARAMETER

resolution

signal to noise ratio

CONDITIONS

I and Q word length at BSI

MIN.

TYP.

12

MAX. UNIT

RES_RXIQ

S/N_RXIQ

−

bit

dB

V

−

66

−

V_ICM(RXIQ)

input common mode (IP + IN)/2; (QP + QN)/2; referred to V_SS

voltage

1.0

1.25

1.5

V_IDM(RXIQ)

FSIN_RXIQ

input differential

voltage

(IP − IN); (QP − QN)

−1.5

−

1.5

V

input sampling

frequency

Baseband receive control register = 0X

Baseband receive control register = 1X

Baseband receive control register = 00 or 11

Baseband receive control register = 10

Baseband receive control register = 0X; note 1

f = 0 to 70 kHz; V_IDM(RXIQ)= 150 mV (p-p)

f = 90 kHz; V_IDM(RXIQ)= 150 mV (p-p)

f = 100 kHz; V_IDM(RXIQ)= 150 mV (p-p)

f = 200 kHz; V_IDM(RXIQ)= 150 mV (p-p)

f > 220 kHz; V_IDM(RXIQ)= 150 mV (p-p)

−

6.5

−

MHz

kHz

13

FSOUT_RXIQoutput sample rate

270.833

541.667

FRESP_RXIQfrequency response

−0.8

0

+0.3 dB

−

−3.5

−5.5

−

dB

−

−35

−45

−

Baseband receive control register = 1X;

note 1 and 2

f = 0 to 140 kHz; V_IDM(RXIQ)= 150 mV (p-p)

f = 180 kHz; V_IDM(RXIQ)= 150 mV (p-p)

f = 200 kHz; V_IDM(RXIQ)= 150 mV (p-p)

f = 400 kHz; V_IDM(RXIQ)= 150 mV (p-p)

f > 440 kHz; V_IDM(RXIQ)= 150 mV (p-p)

−0.8

0

+0.3 dB

−

−3.5

−5.5

−

dB

−

−35

−45

−

DYN_RXIQ

dynamic signal range

ZIF mode

f = 20 Hz to 135 kHz

60

40

−

68

−

dB

LSB

dB

NZIF mode

f = 20 Hz to 270 kHz

68

SINAD_RXIQsignal to noise and

distortion ratio

f = 20.0 kHz; V_IDM(RXIQ)= 2 V (p-p)

f = 67.7 kHz; V_IDM(RXIQ)= 2 V (p-p)

f = 20 kHz; V_IDM(RXIQ)= 150 mV (p-p)

f = 67.7 kHz; V_IDM(RXIQ)= 150 mV (p-p)

−

65

−

40

−

40

OPC

output code in BDIO for maximum input amplitude

−

±1440

70

PSRR_RXIQ

power supply ripple

rejection

applying a 100 mV (p-p)/217 Hz sine wave on

top of the analog power supply

−

GERR_RXIQgain error

referenced to maximum amplitude

−6

−

+6

%

−0.5

−3

+0.5 dB

+3

+0.25 dB

ns

GMAT_RXIQgain matching error

at maximum input level

%

−0.25 −

GDMAT_RXIQgroup delay matching measured at full-scale; 10 kHz < f < 100 kHz;

−

5

of I and Q RX paths

output load = 10 pF // 10 kΩ

1999 May 03

47

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

SYMBOL

PARAMETER

offset error

CONDITIONS

before compensation

MIN.

TYP.

MAX. UNIT

OFFS_RXIQ

−40

−5

−

+40

+5

mV

after compensation

POST_RXIQ

power-on settling

time

including decimation ﬁlter

ZIF mode

NZIF mode

ﬁlter group delay

ZIF mode

−

52

26

−

µs

FGD_RXIQ

−

23

−

µs

NZIF mode

11.5

Notes

1. Reference level is full-scale input at 67 kHz.

2. This will not be tested.

1999 May 03

48

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

18.3 Voice band transmit (microphone to ASI)

V_DDA= 2.5 to 2.75 V; T_amb= −40 to +85 °C.

SYMBOL

PARAMETER

CONDITIONS

MIN. TYP. MAX.

UNIT

bit

RES_MICADCresolution of ADC

−

13

−

FSIN_MICADCinternal sampling

frequency

1000 −

kHz

GRAN_TXPGAcalibration gain range

−24

0

+12

dB

GSTP_TXPGAcalibration gain step

size

see Table 25

−

64

−

steps

GTOL_VBTX

gain tolerance of coder at TXPGA = 0 dB

−1.5

−

+1.0 dB

FRESP_VBTXdigital ﬁlter frequency

response of

f < 100 Hz

−

−20

−10

+1

0

dB

100 Hz < f < 200 Hz

f = 300 Hz to 3.3 kHz

f = 3.3 to 3.4 kHz

f ≥ 4 kHz

−

implemented standard

VSP software (version:

vb5_all)

−1

−1.5

−

−20

−

FREJ_VBTX

out-of-band rejection

f = 4.6 kHz

40

45

50

f = 6 to 30 kHz

−

Microphone/auxiliary signal path

V_IN(rms)

nominal input level

(RMS value)

TXPGA = 0 dB, MICHI = 1

−

−35

−7

−

dBm

TXPGA = 0 dB, MICHI = 0

psophometrically weighted⁽¹⁾; T_amb= 25 °C

−

dBm

dBm0p⁽²⁾

N_IDLE

idle noise level

(pin ADO)

−75

THD

total harmonic distortion f = 1 kHz; PGA = −4 dB; ADO = +2 dBm0

−

1

−

2

%

SINAD

signal-to-noise and

distortion

ADO = 3 dBm0

30

40

45

40

30

25

−

dB

LSB

ADO = 0 dBm0

ADO = −10 dBm0

ADO = −20 dBm0

ADO = −30 dBm0

ADO = −40 dBm0

ADO = −45 dBm0

PSCT_VBTX

power supply crosstalk applying a 100 mV (p-p)/217 Hz sine wave

on top of the analog power supply

Audio Serial Interface (ASI)

FASOUT

PCM output bit rate

128

−

2048 kbits/s

− kHz

FSYNC_AFS

PCM frame

−

8

synchronization

frequency at pin AFS

Notes

1. Psophometrical weighting: a frequency weighting curve described in “ITU recommendation O.41”.

2. The unit dBm0p: 0 dBm0p is generally defined as −3.14 dBFS, where dBFS denotes dB full scale, i.e. a signal with

an amplitude covering the complete range of digital values. The suffix ‘p’ refers to psophometrical weighting.

1999 May 03

49

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

18.4 Voice band receive (ASI to earphone)

V_DDA= 2.5 to 2.75 V; T_amb= −40 to +85 °C

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

bit

RES_EARDACresolution of DAC

−

13

−

FSIN_EARDACinternal sampling

frequency

1000

kHz

GRAN_VOL

GSTP_VOL

GRAN_PGA

GSTP_PGA

GTOL_VBRX

gain step range

gain step size

−30

−

−12

64

−

+6

−

dB

digital steps; see Table 25

steps

dB

calibration PGA range

gain step size

−24

−

+12

−

64

−

steps

dB

gain tolerance of

decoder

−1

+1

GMUTE_VBRXmute attenuation of

decoder

40

−

dB

FRESP_VBRXdigital ﬁlter frequency

response of

f = 0 to 100 Hz

−

−20

+1.0

−18

dB

f = 300 to 3300 Hz

f = 3300 to 3400 Hz

f = 4000 Hz

−1.0

−2.0

−

implemented standard

VSP software (version:

vb5_all)

FREJ_VBRX

out-of-band rejection

f = 4600 Hz

f = 28.6 kHz

38

40

−

dB

Audio Serial Interface (ASI)

FASIN

PCM input bit rate

128

−

2048

kbits/s

kHz

FSYNC_AFS

PCM frame

−

8

−

synchronization

frequency at pin AFS

Earphone output: EARP and EARN

V_ref(EAR)

DC reference level

−

V_ref

2

−

V

V_o(EAR)(p-p)

output voltage

(peak-to-peak value)

load: 16 Ω differential

load: 8 Ω single-ended

V

1.5

100

V

I_o(EAR)peak

output source/sink

current

mA

GAIN_EARVOLnominal gain from ASI

to EARP/EARN

GRAN_VOL= −12 dB; load 32 Ω

differential

−13

−19

+5

−12

−18

−

−11

−17

+41

dB

single-ended

GRAN_SIDVOLtotal sidetone gain

(from MICP/MICN to

EARP/EARN)

THD_EAR

IDLN_EAR

total harmonic distortion GRAN_EARVOL= −12 dB

−

1

%

dBmp⁽²⁾

idle noise at

EARP/EARN

psophometrically weighted⁽¹⁾;

GRAN_EARPGA= 0 dB

−72

1999 May 03

50

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

SINAD_EAR

signal-to-noise and

distortion ratio from ASI

to earphone

psophometrically weighted⁽¹⁾

at 3 dBm0 input signal level

at 0 dBm0 input signal level

30

35

−

dB

at −10 dBm output signal level 45

at −20 dBm output signal level 42

at −30 dBm output signal level 40

at −40 dBm output signal level 30

at −45 dBm output signal level 25

PSRR_EAR

power supply ripple

rejection at

applying a 100 mV (p-p)/217 Hz 70

sine wave on top of the analog

power supply

EARP/EARN

Auxiliary output: AUXSP

V_ref(AUXSP)DC reference level

V_o(AUXSP)output voltage

−

V_ref

−

V

load: 16 Ω with 47 µF in series

−

V

_ref±1

to ground

load: 8 Ω with 100 µF in series

to ground

−

V

_ref±0.77

−

V

I_o(AUXSP)peakoutput source/sink

current

load: 16 Ω with 47 µF in series to

ground

−

62.5

mA

dB

GAIN_AUXSP

nominal gain from ASI

to AUXSP

load: 16 Ω with 47 µF in series

to ground; GRAN_VOL= −12 dB

−19

−18

−17

Buzzer output: BUZ

V_ref(BUZ)DC reference level

V_o(BUZ)

−

V_ref

−

V

output voltage

load: 8 Ω with 100 µF in series

to ground

V

_ref− 0.77 −

V

I_o(BUZ)peak

output source/sink

current

100

−

mA

GAIN_BUZ

nominal gain from ASI

to BUZ

load: 8 Ω with 100 µF in series

to ground; GRAN_VOL= −12 dB

−19

−18

−17

dB

Notes

1. Psophometrical weighting: a frequency weighting curve described in “ITU recommendation O.41”.

2. The unit dBmp: 0 dBmp refers to a voltage of a signal of 1 mW across a 600 Ω load. The suffix ‘p’ refers to

psophometrical weighting.

1999 May 03

51

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

18.5 Auxiliary digital-to-analog converters

V_DDA= 2.5 to 2.75 V; T_amb= −40 to +85 °C.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

AUXDAC1

RES_DAC1

resolution

−

8

−

bit

VOMIN_DAC1

VOMAX_DAC1

VDEF_DAC1

MON_DAC1

INL_DAC1

minimum output voltage

maximum output voltage

register value: 000H

register value: 0FFH

0

−

0.15

2.3

−

V

2.1

−

2.2

V

output voltage after reset register value: 085H

monotonicity range

integral non-linearity⁽¹⁾

1.147

V

−

8

−

bit

−5.0

−1.0

−80

−

+5.0

+1.0

+80

−

LSB

mV

µs

DNL_DAC1

differential non-linearity⁽²⁾

−

OFFS_DAC1

FSST_DAC1

LSBST_DAC1

offset error

−

full-scale settling time

one LSB settling time

load: 50 pF // 2 kΩ, to V_SS

see Fig.13a

;

40

8

−

AUXDAC2

RES_DAC2

resolution

−

12

−

bit

VOMIN_DAC2

VOMAX_DAC2

VDEF_DAC2

MON_DAC2

INL_DAC2

minimum output voltage

maximum output voltage

register value: 000H

register value: FFFH

0

0.15

2.32

−

V

2.1

−

2.2

1.1

12

±10

−

V

output voltage after reset register value: 800H

monotonicity range

integral non-linearity⁽¹⁾

V

−

bit

−

LSB

mV

µs

ms

DNL_DAC2

differential non-linearity⁽²⁾

−1.0

−25

−

+2.0

+25

−

OFFS_DAC2

FSST_DAC2

LSBST_DAC2

POST_DAC2

offset error

−

full-scale settling time

one LSB settling time

power-on settling time

load: 50 pF // 10 kΩ, to

V_SS; see Fig.13b

40

8

−

see Section 18.1

−

4

AUXDAC3

RES_DAC3

resolution

−

10

−

bit

VOMIN_DAC3

VOMAX_DAC3

MON_DAC3

INL_DAC3

minimum output voltage

maximum output voltage

monotonicity range

integral non-linearity⁽¹⁾

differential non-linearity⁽²⁾

offset error

register value: 000H

register value: 3FFH

0

0.15

2.3

−

V

2.1

−

2.2

10

−

V

bit

−5.0

−1.0

−40

1

+5.0

+1.0

+40

15

LSB

mV

µs

DNL_DAC3

−

OFFS_DAC3

FSST_DAC3

LSBST_DAC3

SSC_DAC3

−

full-scale settling time

one LSB settling time

output source/sink current

load: 50 pF // 1 kΩ, to V_SS

see Fig.13c

;

10

2.5

−

µs

−

2.5

mA

Notes

1. INL: the difference of the output to the best fit line. INL_(i)= [V_(i)− (a + i × b)]/1 LSB; INL = (INL_(i)(max)− INL_(i)(min))/2.

2. DNL is the difference between individual code width and average code width (1 LSB); maximum and minimum

specified. DNL_(i)= [(V_{(i + 1)}− V_(i)− 1 LSB)/1 LSB]; DNL_(min)> −1 is equivalent to monotonicity V_{(i + 1)}> V_(i).

1999 May 03

52

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

18.6 Auxiliary analog-to-digital converters: AUXADC1, AUXADC2, AUXADC3 and AUXADC4

V_DDA= 2.5 to 2.75 V; T_amb= −40 to +85 °C.

SYMBOL

PARAMETER

resolution

input voltage

CONDITIONS

coded in 12 bits

MIN.

TYP.

MAX.

UNIT

RES_AUXADC

VIN_AUXADC

−

1440

−

LSB

V

0.0

−20

−

2.0

20

−

VIN_AUXADCMINV_infor output code 0

−

mV

V

VIN_AUXADCMAXV_infor output code +1820

after offset compensation

2.0

1.0

2.5

−

R_i(AUXADC)

input resistance

−

MΩ

mV

dB

INL_AUXADC

integral non-linearity

differential non-linearity

gain error

−

DNL_AUXADC

GERR_AUXADC

OFFS_AUXADC

POST_AUXADC

−

V_i= V_ref

−0.5

−3

−

+ 0.5

3

offset error after compensation

power-on settling time

−

LSB

µs

170

−

18.7 Typical total current consumption

The typical total current consumption values for the chip in different modes; T_amb= 25 °C.

TOTAL CURRENT (mA)

ACTIVITY

REMARKS

NOTE 1

NOTE 2

Baseband

transmit

receive

3.96

5.14

4.79

4.04

5.41

4.94

baseband transmit + references + MCLK + BSI

baseband receive + references + MCLK + BSI

Voice band transmit and receive

voice band transmit and receive + references

+ 13 MHz + auxiliary DAC2; note 3

Voice band transmit and receive

baseband transmit

7.32

8.52

2.75

7.51

8.91

2.86

voice band transmit and receive + baseband transmit

+ references + 13 MHz + CSI + auxiliary DACs 2 and 3

baseband receive

voice band transmit and receive + baseband receive

+ references + 13 MHz + auxiliary DAC 2

Auxiliary ADC function

auxiliary ADC + CSI + references + 13 MHz + auxiliary

DAC2

Auxiliary DAC1

Auxiliary DAC2

Auxiliary DAC3

2.35

1.55

4.35

2.49

1.59

4.56

auxiliary DACs 1 and 2 + references + 13 MHz

auxiliary DAC2 + references + 13 MHz

auxiliary DACs 3 and 2 + CSI + baseband transmit

+ references + 13 MHz

Idle with MCLK running

Idle no MCLK; references on

Idle

0.23

0.18

0.01

0.24

0.19

0.01

references + 13 MHz clock

references; see Section 19.1.1 “Possibility 1”

all blocks in power-down, no 13 MHz clock

Notes

1. V_DDD= 2.3 V; V_DDA= 2.65 V; external interface current is not included.

2. V_DDD= 2.6 V; V_DDA= 2.65 V; external interface current is not included.

3. For a signal at the earpiece differential output of amplitude ‘A’ across a load resistance of ‘R’, the current ‘I’ must be

4 A

added, where: I =

.

-- ---

π R

1999 May 03

53

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

18.8 Typical output loads

Figure 13 illustrates the typical loads for the outputs: AUXDAC1, AUXDAC2, AUXDAC3, EARP, EARN, AUXSP and

BUZ.

andbook, halfpage

handbook, halfpage

AUXDAC1

AUXDAC2

50

pF

2

kΩ

50

pF

10

kΩ

V

SSA

MBL023

MBL024

a. AUXDAC1.

b. AUXDAC2.

handbook, halfpage

EARP

or

handbook, halfpage

AUXDAC3

AUXSP

800 µH

16 Ω

50

pF

1

kΩ

100 pF

V

SSA

EARN

MBH602

MBL020

c. AUXDAC3.

d. EARP/EARN or AUXSP.

16 Ω

ndbook, halfpage

handbook, halfpage

AUXSP

or

BUZ

8 Ω

AUXSP

or

BUZ

47 µF

100 µF

V

SS

MGS172

MBL021

e. AUXSP or BUZ; R = 8 Ω.

f. AUXSP or BUZ; R = 16 Ω.

Fig.13 Typical output loads.

1999 May 03

54

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

19 APPLICATION INFORMATION

handbook, full pagewidth

BUS

RFCLK

G14

RFDO

G11

RFDI

G13

RFE_N1

F13

RFE_N2

F11

V

DDD

68 nF

DDA

68 nF

DDA(vbo)

68 nF

CLOCK

DATA

EN

17

16

18

AUXST

7

34 37

47

25

RFSIG[x]

13

CCLK

CDI

9

IA

IB

IP

OM5178

21

7

11

10

12

IN

CEN

CDO

22

8

QA

QB

QP

23

QN

24

9

PCF5087X

10

BIOCLK

BIEN

SIOXCLK

SOXEN_N

SIOXD

H13

15

16

AUXDAC1

27

28

J13

J11

H14

13 MHz ON

BDIO

AUXDAC2

AUXDAC3

17

18

VCXO

SIXEN_N

BOEN

13 MHz

PA-CONTROL

CIRCUITRY

29

RFSIG[y]

RFSIG[z]

TXON

RXON

AUXADC1

AUXADC2

AUXADC3

AUXADC4

19

20

31

32

33

30

CHARGER

BATTERY VOLTAGE

BATTERY TEMPERATURE

AMBIENT TEMPERATURE

BATTERY TYPE

PCF50732

EXTERNAL

IOM2

microphone

supply

FSC

DCL

DU

AFS

ACLK

ADO

ADI

B11

A11

D11

B10

3

4

1

2

AUXMICP

AUXMICN

38

39

DD

microphone

AMPCTRL

MCLK

supply

MICP

MICN

14

6

41

40

CKI

L7

EARP

K14 K12

46

RSTO_N

RST_N

RESET

EARN

45

44

5

system

reset

V

AUXSP

ref

36

68

nF

BUZ

43

8

26 35 42 48

MGS173

(1) 10 nF can be used instead of 100 nF for high-pass filtering.

Fig.14 Application diagram.

55

1999 May 03

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

A down-counter increases the band gap output drive

capability for 32768 MCLK cycles which equals

approximately 2.5 ms. After that time the voltage at V_ref

has reached ±0.5 mV of its final value. The timing diagram

illustrates the situation (see Fig.15). Other points to note

for this possibility:

19.1 Wake-up procedure from Sleep mode

Apart from being the status control signal of AUXDAC1,

AUXDAC2 and the MCLK input, AUXST also starts a

down-counter at each rising edge which controls the

output drive capability of pin V_ref. This is important for the

following considerations. For current consumption

reduction during Sleep mode there are two possibilities as

shown in Section 19.1.1 and 19.1.2.

• As long as V_DDDis not switched off, all registers keep

their values.

• As long as V_DDA(bb)is not stable, the internal master

clock is not running, because the first stage of the clock

generator is supplied by V_DDA.

19.1.1 POSSIBILITY 1

Program every block into power-down via CSI except for

the band gap, then pull AUXST LOW to switch off the clock

internally. This results in a I_DD(total)= 60 µA (typical). Since

the band gap hasn’t been programmed into power-down,

the only active reference is V_ref. After a rising edge of

AUXST, POST_DACis in the order of 1.5 ms.

• All digital signals MUST remain stable for t_MCLKafter

AUXST has gone HIGH. This is necessary to avoid any

timing violations in the digital part of the PCF50732

caused by an unstable MCLK clock input.

• The previously mentioned 2.5 ms for t_BGare only valid

for C_Vref= 68 nF ±10% or less. The maximum of value

68 nF is highly recommended for good noise and power

supply rejection figures.

19.1.2 POSSIBILITY 2

If AUXST is also used to switch off the analog power

supply, all references are shut down. The power-up time in

this case is measured from the point where the MCLK

clock input has valid levels or V_DDAhas settled to its final

value (the latter of the two signals sets the reference

point).

POST

DAC

(4 ms)

handbook, full pagewidth

t

MCLK

t

BG

t

VDD

(2.5 ms)

V

DDA

V

ref

MCLK

AUXST

AUXDAC1/

AUXDAC2

MGR999

t_VDD: settling time until V_DDA(bb)has reached 95% of its final value. It is assumed that t_MCLK> t_VDD; otherwise t_BGand POST_DACare related to t_VDD

t_MCLK: settling time until MCLK clock has reached at least 100 mV (peak-to-peak) level and a frequency of 13 MHz ±10 kHz.

t_BG: settling time until voltage at V_refhas reached ±0.5 mV of its final value for C_Vref= 68 nF ±10%.

.

POST_DAC: settling time until AUXDAC1 and AUXDAC2 has reached the previously programmed value ±2 LSBs.

Fig.15 Possible timing of wake-up sequence.

1999 May 03

56

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

19.2 Microphone input connection and test set-up

microphone

supply

handbook, halfpage

2 kΩ

handbook, halfpage

MICP

MICN

100 nF

(1)

100 nF

MICN

2 kΩ

MGS171

MBL022

(1) 10 nF can be used instead of 100 nF for high-pass filtering.

a. Microphone input connection.

b. Microphone input test set-up.

Fig.16 Microphone input connection and test set-up.

1999 May 03

57

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

20 PACKAGE OUTLINE

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c

y

X

36

25

A

E

37

24

Z

E

e

H

E

A

2

A

(A )

3

A

1

w M

p

θ

pin 1 index

b

L

p

L

13

48

detail X

1

12

Z

v M

D

A

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.60

mm

0.25

0.5

1.0

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

94-12-19

97-08-01

SOT313-2

1999 May 03

58

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

If wave soldering is used the following conditions must be

observed for optimal results:

21 SOLDERING

21.1 Introduction to soldering surface mount

packages

• Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable

for surface mount ICs, or for printed-circuit boards with

high population densities. In these situations reflow

soldering is often used.

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

The footprint must incorporate solder thieves at the

downstream end.

21.2 Reﬂow soldering

• For packages with leads on four sides, the footprint must

be placed at a 45° angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Several methods exist for reflowing; for example,

infrared/convection heating in a conveyor type oven.

Throughput times (preheating, soldering and cooling) vary

between 100 and 200 seconds depending on heating

method.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 230 °C.

21.4 Manual soldering

21.3 Wave soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering

method was specifically developed.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

1999 May 03

59

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

21.5 Suitability of surface mount IC packages for wave and reﬂow soldering methods

SOLDERING METHOD

PACKAGE

WAVE

REFLOW⁽¹⁾

BGA, SQFP

not suitable

suitable

HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable⁽²⁾

PLCC⁽³⁾, SO, SOJ

LQFP, QFP, TQFP

SSOP, TSSOP, VSO

suitable

not recommended⁽³⁾⁽⁴⁾

not recommended⁽⁵⁾

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

22 DEFINITIONS

Data sheet status

Objective speciﬁcation

Preliminary speciﬁcation

Product speciﬁcation

This data sheet contains target or goal speciﬁcations for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

23 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

1999 May 03

60

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

NOTES

1999 May 03

61

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

NOTES

1999 May 03

62

Philips Semiconductors

Objective speciﬁcation

Baseband and audio interface for GSM

PCF50732

NOTES

1999 May 03

63

Philips Semiconductors – a worldwide company

Argentina: see South America

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +31 40 27 82785, Fax. +31 40 27 88399

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Philippines: Philips Semiconductors Philippines Inc.,

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Tel. +1 800 234 7381, Fax. +1 800 943 0087

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Slovakia: see Austria

Slovenia: see Italy

Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

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Indonesia: PT Philips Development Corporation, Semiconductors Division,

Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,

Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,

TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874

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MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

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Tel. +381 11 62 5344, Fax.+381 11 63 5777

For all other countries apply to: Philips Semiconductors,

Internet: http://www.semiconductors.philips.com

International Marketing & Sales Communications, Building BE-p, P.O. Box 218,

5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

SCA63

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

465008/00/01/pp64

Date of release: 1999 May 03

Document order number: 9397 750 04998


型号：	PCF50732H
厂家：	NXP
描述：	Baseband and audio interface for GSM 基带和GSM音频接口电信集成电路电信电路 GSM
文件：	总64页 (文件大小：325K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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