PCF8533U/2/F2,026_技术文档

PCF8533

Universal LCD driver for low multiplex rates

Rev. 6 — 1 October 2012

Product data sheet

1. General description

The PCF8533 is a peripheral device which interfaces to almost any Liquid Crystal Display

(LCD)¹with low multiplex rates. It generates the drive signals for any static or multiplexed

LCD containing up to four backplanes and up to 80 segments and can easily be cascaded

for larger LCD applications. The PCF8533 is compatible with most microcontrollers and

communicates via the two-line bidirectional I²C-bus. Communication overheads are

minimized by a display RAM with auto-incremental addressing, by hardware

subaddressing and by display memory switching (static and duplex drive modes).

2. Features and benefits

 Single-chip LCD controller and driver

 Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing

 Selectable display bias configuration: static, ¹⁄₂, or ¹⁄₃

 Internal LCD bias generation with voltage follower buffers

 80 segment outputs allowing to drive:

 40 7-segment alphanumeric characters

 20 14-segment alphanumeric characters

 Any graphics of up to 320 elements

 80  4 bit RAM for display data storage

 Auto-incremental display data loading across device subaddress boundaries

 Display memory bank switching in static and duplex drive modes

 Versatile blinking modes

 Independent supplies possible for LCD and logic voltages

 Wide power supply range: from 1.8 V to 5.5 V

 Wide LCD supply range: from 2.5 V for low threshold LCDs up to 6.5 V for high

threshold twisted nematic LCDs

 Low power consumption

 400 kHz I²C-bus interface

 May be cascaded for large LCD applications (up to 5120 elements possible)

 No external components required

 Compatible with Chip-On-Glass (COG) technology

 Manufactured using silicon gate CMOS process

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 17.

PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

99 bumps; 5.28 x 1.4 x 0.38 mm

Version

PCF8533U/2/F2

bare die

PCF8533-2

3.1 Ordering options

Table 2.

Ordering options

Type number

IC

revision

Sales item (12NC)

Delivery form

chip with hard bumps in tray

PCF8533U/2/F2^[2]

2

935262345026

[1] Bump hardness see Table 26.

[2] Not to be used for new designs. Replacement part PCF85133U/2DA/1 for industrial parts and

PCA85133U/2DA/Q1 for automotive parts.

4. Marking

Table 3.

Marking codes

Type number

Marking code

PCF8533U/2/F2

PC8533-2

PCF8533

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Product data sheet

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

5. Block diagram

BP0 BP1 BP2 BP3

S0 to S79

80

V

LCD

BACKPLANE

OUTPUTS

DISPLAY SEGMENT OUTPUTS

DISPLAY REGISTER

LCD

VOLTAGE

SELECTOR

OUTPUT BANK SELECT

AND BLINK CONTROL

DISPLAY

CONTROL

LCD BIAS

GENERATOR

V

SS

DISPLAY

RAM

PCF8533

CLK

BLINKER

CLOCK SELECT

TIMEBASE

AND TIMING

SYNC

COMMAND

DECODE

DATA POINTER AND

AUTO INCREMENT

WRITE DATA

CONTROL

POWER-ON

RESET

OSC

OSCILLATOR

SCL

SDA

2

INPUT

FILTERS

SUBADDRESS

COUNTER

I C-BUS

CONTROLLER

A0 A1 A2

SA0

SDAACK

V

DD

mgl743

Fig 1. Block diagram of PCF8533

PCF8533

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

6. Pinning information

6.1 Pinning

PCF8533U

y

x

0,0

mgl759

Viewed from active side. For mechanical details, see Figure 28.

Fig 2. Pin configuration for PCF8533U

6.2 Pin description

Table 4.

Symbol

SDAACK

SDA

Pin description overview

Type

Description

1

output

I²C-bus acknowledge

I²C-bus serial data

I²C-bus serial clock

clock input/output

supply voltage

2 and 3

input/output

input

SCL

4 and 5

CLK

6

7

8

9

input/output

supply

V_DD

SYNC

OSC

input/output

input

cascade synchronization

oscillator select

A0, A1 and A2

SA0

10 to 12

13

input

subaddress

input

I²C-bus slave address

ground supply voltage

LCD supply voltage

LCD backplane output

[1]

V_SS

14

supply

V_LCD

15

supply

BP0, BP1, BP2 and BP3 17, 99, 16 and output

98

S0 to S79

18 to 97

output

-

LCD segment output

dummy pins

D1, D2, D3, D4, D5, D6,

D7, D8

[1] The substrate (rear side of the die) is at V_SSpotential and should be electrically isolated.

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

7. Functional description

The PCF8533 is a versatile peripheral device designed to interface between any

microcontroller to a wide variety of LCD segment or dot-matrix displays. It can directly

drive any static or multiplexed LCD containing up to four backplanes and up to

80 segments.

7.1 Commands of PCF8533

The five commands available to the PCF8533 are defined in Table 5.

Table 5.

Definition of commands

Operation code

Command

Bit

Reference

7

1

0

1

6

5

4

3

2

1

0

mode-set

1

0

E

B

M[1:0]

Table 6

Table 7

Table 8

Table 9

Table 10

load-data-pointer

device-select

bank-select

blink-select

P[6:0]

1

0

1

0

1

0

A[2:0]

0

I

O

AB

BF[1:0]

7.1.1 Command: mode-set

The mode-set command allows configuring the multiplex mode, the bias levels and

enabling or disabling the display.

Table 6.

Bit

Mode-set command bit description

Symbol Value

Description

7 to 4

3

-

1100

fixed value

E

display status^[1]

disabled (blank)^[3]

enabled

0^[2]

1

2

B

LCD bias configuration^[4]

¹⁄₃bias

¹⁄₂bias

0^[2]

1

1 to 0

M[1:0]

LCD drive mode selection

static; 1 backplane

1:2 multiplex; 2 backplanes

1:3 multiplex; 3 backplanes

1:4 multiplex; 4 backplanes

01

10

11

00^[2]

[1] The possibility to disable the display allows implementation of blinking under external control.

[2] Default value.

[3] The display is disabled by setting all backplane and segment outputs to V_LCD

.

[4] Not applicable for static drive mode.

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.1.2 Command: load-data-pointer

The load-data-pointer command defines the display RAM address where the following

display data will be sent to.

Table 7.

Load-data-pointer command bit description

See Section 7.6.1.

Bit

7

Symbol Value

Description

-

0

fixed value

6 to 0

P[6:0]

0000000^[1]data pointer

to 1001111

7-bit binary value of 0 to 79, transferred to the data pointer to

define one of 80 display RAM addresses

[1] Default value.

7.1.3 Command: device-select

The device-select command allows defining the subaddress counter value.

Table 8.

Device-select command bit description

See Section 7.6.2.

Bit

Symbol Value

Description

7 to 3

2 to 0

-

11100

fixed value

A[2:0]

000^[1]to 111 device selection

3-bit binary value of 0 to 7, transferred to the subaddress

counter to define one of 8 hardware subaddresses

[1] Default value.

7.1.4 Command: bank-select

The bank-select command controls where data is written to RAM and where it is displayed

from.

Table 9.

Bank-select command bit description

See Section 7.6.5.1 and Section 7.6.5.2.

Bit

Symbol Value

Description^[1]

Static

1:2 multiplex

7 to 2

1

-

I

111110

fixed value

Input bank selection: storage of arriving display data

0^[2]

1

RAM row 0

RAM row 2

RAM rows 0 and 1

RAM rows 2 and 3

0

O

Output bank selection: retrieval of LCD display data

0^[2]

1

RAM row 0

RAM row 2

RAM rows 0 and 1

RAM rows 2 and 3

[1] The bank-select command has no effect in 1:3 or 1:4 multiplex drive modes.

[2] Default value.

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Product data sheet

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.1.5 Command: blink-select

The blink-select command allows configuring the blink mode and the blink frequency.

Table 10. Blink-select command bit description

See Section 7.1.5.1.

Bit

7 to 3

2

Symbol Value

Description

-

11110

fixed value

blink mode selection^[1]

AB

0^[2]

1

normal blinking

blinking by alternating display RAM banks

1 to 0

BF[1:0]

blink mode selection^[3]

00^[2]

01

off

1

10

2

11

3

[1] Only normal blinking can be selected in multiplexer 1:3 or 1:4 drive modes.

[2] Default value.

[3] For the blink frequency, see Table 11.

7.1.5.1 Blinking

The display blink capabilities of the PCF8533 are very versatile. The whole display can

blink at frequencies selected by the blink-select command (see Table 10). The blink

frequencies are fractions of the clock frequency. The ratios between the clock and blink

frequencies depend on the blink mode selected (see Table 11).

Table 11. Blink frequencies

Blink mode

Normal operating

mode ratio

Nominal blink frequency of f_clkUnit

(typical f_clk= 1.536 kHz)

Off

1

-

blinking off

2

Hz

f_clk

--------

768

2

3

1

Hz

f_clk

-----------

1536

0.5

f_clk

-----------

3072

An additional feature is for an arbitrary selection of LCD segments to blink. This applies to

the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. With the output bank selector, the displayed RAM banks are

exchanged with alternate RAM banks at the blink frequency. This mode can also be

specified by the blink-select command.

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD segments can blink by selectively changing the display RAM data at fixed time

intervals.

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Product data sheet

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

The entire display can blink at a frequency other than the typical blink frequency. This can

be effectively performed by resetting and setting the display enable bit E at the required

rate using the mode-set command (see Table 6).

7.2 Power-On Reset (POR)

At power-on, the PCF8533 resets to the following starting conditions:

1. All backplane outputs are set to V_LCD

.

2. All segment outputs are set to V_LCD

.

3. The selected drive mode is: 1:4 multiplex with ¹⁄₃bias.

4. Blinking is switched off.

5. Input and output bank selectors are reset.

6. The I²C-bus interface is initialized.

7. The data pointer and the subaddress counter are cleared (set to logic 0).

8. The display is disabled (bit E = 0, see Table 6).

Remark: Do not transfer data on the I²C-bus for at least 1 ms after a power-on to allow

the reset action to complete.

7.3 Possible display configurations

The display configurations possible with the PCF8533 depend on the required number of

active backplane outputs. A selection of display configurations is given in Table 12.

All of the display configurations given in Table 12 can be implemented in a typical system

as shown in Figure 4.

dot matrix

7-segment with dot

14-segment with dot and accent

013aaa312

Fig 3. Example of displays suitable for PCF8533

PCF8533

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

Table 12. Selection of possible display configurations

Number of

Backplanes

Icons

Digits/Characters

7-segment^[1]

Dot matrix/

Elements

14-segment^[2]

4

3

2

1

320

240

160

80

40

30

20

10

20

15

10

5

320 (4  80)

240 (3  80)

160 (2  80)

80 (1  80)

[1] 7 segment display has 8 elements including the decimal point.

[2] 14 segment display has 16 elements including decimal point and accent dot.

V

DD

t

r

SDAACK

R

≤

2C

b

V

DD

LCD

SDA

SCL

HOST

MICRO-

PROCESSOR/

MICRO-

80 segment drives

4 backplanes

LCD PANEL

PCF8533

(up to 320

elements)

OSC

CONTROLLER

mgl744

A0 A1 A2 SA0

V

SS

V

SS

Fig 4. Typical system configuration

The host microcontroller maintains the 2-line I²C-bus communication channel with the

PCF8533. The internal oscillator is enabled by connecting pin OSC to pin V_SS. The

appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.

The only other connections required to complete the system are the power supplies (V_DD

,

V_SS, and V_LCD) and the LCD panel chosen for the application.

7.3.1 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider of three

impedances connected between pins V_LCDand V_SS. The center impedance is bypassed

by switch if the ¹⁄₂bias voltage level for the 1:2 multiplex drive mode configuration is

selected.

7.3.2 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by the

mode-set command from the command decoder. The biasing configurations that apply to

the preferred modes of operation, together with the biasing characteristics as functions of

V

_LCDand the resulting discrimination ratios (D) are given in Table 13.

Discrimination is a term which is defined as the ratio of the on and off RMS voltage across

a segment. It can be thought of as a measurement of contrast.

PCF8533

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

Table 13. Biasing characteristics

LCD drive

mode

Number of:

LCD bias

configuration

V_offRMSV_onRMS

------------------------ ----------------------- D = ------------------------

V_LCDV_LCDV_offRMS

V_onRMS

Backplanes Levels

static

1

2

3

4

2

3

4

static

0

1



1

⁄

1:2 multiplex

1:3 multiplex

1:4 multiplex

0.354

0.333

0.791

0.745

0.638

0.577

2.236

1.915

1.732

2

1

⁄

3

1

⁄

3

1

⁄

3

A practical value for V_LCDis determined by equating V_off(RMS)with a defined LCD

threshold voltage (V_th(off)), typically when the LCD exhibits approximately 10 % contrast. In

the static drive mode, a suitable choice is V_LCD> 3V_th(off)

.

Multiplex drive modes of 1:3 and 1:4 with ¹⁄₂bias are possible but the discrimination and

hence the contrast ratios are smaller.

1

Bias is calculated by ------------ , where the values for a are

1 + a

a = 1 for ¹⁄₂bias

a = 2 for ¹⁄₃bias

The RMS on-state voltage (V_on(RMS)) for the LCD is calculated with Equation 1:

a²+ 2a + n

n  1 + a²

V_onRMS

=

-----------------------------

(1)

V

LCD

where the values for n are

n = 1 for static drive mode

n = 2 for 1:2 multiplex drive mode

n = 3 for 1:3 multiplex drive mode

n = 4 for 1:4 multiplex drive mode

The RMS off-state voltage (V_off(RMS)) for the LCD is calculated with Equation 2:

a²– 2a + n

n  1 + a²

V_offRMS

=

-----------------------------

(2)

(3)

V

LCD

Discrimination is the ratio of V_on(RMS)to V_off(RMS)and is determined from Equation 3:

a²+ 2a + n

V_onRMS

D =

=

---------------------------

----------------------

a²– 2a + n

V_offRMS

Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with

¹⁄₂bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with

21

¹⁄₂bias is ---------- = 1.528 .

3

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V_LCD

as follows:

• 1:3 multiplex (¹⁄₂bias): V_LCD

• 1:4 multiplex (¹⁄₂bias): V_LCD

=

6  V_offRMS= 2.449V_offRMS

4  3

---------------------

= 2.309V_offRMS

3

These compare with V_LCD= 3V_offRMSwhen ¹⁄₃bias is used.

_LCDis sometimes referred as the LCD operating voltage.

V

7.3.2.1 Electro-optical performance

Suitable values for V_on(RMS)and V_off(RMS)are dependent on the LCD liquid used. The

RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of

the pixel.

For any given liquid, there are two threshold values defined. One point is at 10 % relative

transmission (at V_th(off)) and the other at 90 % relative transmission (at V_th(on)), see

Figure 5. For a good contrast performance, the following rules should be followed:

V

_onRMS V_thon

_offRMS V_thoff

(4)

(5)

V

_on(RMS)and V_off(RMS)are properties of the display driver and are affected by the selection

of a, n (see Equation 1 to Equation 3) and the V_LCDvoltage.

V_th(off)and V_th(on)are properties of the LCD liquid and can be provided by the module

manufacturer. V_th(off)is sometimes named V_th. V_th(on)is sometimes named saturation

voltage V_sat

.

It is important to match the module properties to those of the driver in order to achieve

optimum performance.

100 %

90 %

10 %

V

[V]

RMS

V

th(off)

V

th(on)

OFF

SEGMENT

GREY

SEGMENT

ON

SEGMENT

013aaa494

Fig 5. Electro-optical characteristic: relative transmission curve of the liquid

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.3.3 LCD drive mode waveforms

7.3.3.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD. The

backplane (BPn) and segment drive (Sn) waveforms for this mode are shown in Figure 6.

T

fr

LCD segments

V

LCD

BP0

Sn

V

SS

state 1

(on)

state 2

(off)

V

LCD

V

SS

V

LCD

Sn+1

V

SS

(a) Waveforms at driver.

V

LCD

state 1

0 V

−V

LCD

V

LCD

state 2

0 V

−V

LCD

(b) Resultant waveforms

at LCD segment.

mgl745

V_state1(t) = V_Sn(t)  V_BP0(t).

_on(RMS)= V_LCD

V

.

V_state2(t) = V_(Sn+1)(t)  V_BP0(t).

V_off(RMS)= 0 V.

Fig 6. Static drive mode waveforms

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.3.3.2 1:2 multiplex drive mode

The 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This

mode allows fractional LCD bias voltages of ¹⁄₂bias or ¹⁄₃bias as shown in Figure 7 and

Figure 8.

T

fr

V

LCD

LCD segments

V

/ 2

BP0

BP1

Sn

LCD

SS

state 1

V

LCD

state 2

V

LCD

SS

V

LCD

V

SS

LCD

Sn+1

V

SS

(a) Waveforms at driver.

V

LCD

/ 2

0 V

−V

state 1

/ 2

LCD

−V

LCD

V

LCD

/ 2

LCD

0 V

state 2

−V

/ 2

LCD

−V

(b) Resultant waveforms

at LCD segment.

mgl746

V_state1(t) = V_Sn(t)  V_BP0(t).

_on(RMS)= 0.791V_LCD

V_state2(t) = V_Sn(t)  V_BP1(t).

V_off(RMS)= 0.354V_LCD

V

.

Fig 7. Waveforms for the 1:2 multiplex drive mode with ¹⁄₂bias

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PCF8533

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Universal LCD driver for low multiplex rates

T

fr

V

LCD

2V

LCD segments

/ 3

LCD

/ 3

BP0

BP1

Sn

V

LCD

SS

state 1

V

LCD

state 2

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

Sn+1

V

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

0 V

−V

state 1

/ 3

LCD

−2V

−V

/ 3

LCD

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

0 V

−V

state 2

/ 3

LCD

−2V

−V

/ 3

LCD

(b) Resultant waveforms

at LCD segment.

mgl747

V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= 0.745V_LCD

.

V_state2(t) = V_Sn(t)  V_BP1(t).

V_off(RMS)= 0.333V_LCD

.

Fig 8. Waveforms for the 1:2 multiplex drive mode with ¹⁄₃bias

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.3.3.3 1:3 multiplex drive mode

The 1:3 multiplex drive mode is used when three backplanes are provided in the LCD as

shown in Figure 9.

T

fr

V

LCD

2V

LCD segments

/ 3

LCD

/ 3

BP0

BP1

BP2

Sn

V

LCD

SS

state 1

state 2

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

Sn+1

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

Sn+2

V

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

0 V

−V

state 1

/ 3

LCD

−2V

−V

/ 3

LCD

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

0 V

−V

state 2

/ 3

LCD

−2V

−V

/ 3

LCD

(b) Resultant waveforms

at LCD segment.

mgl748

V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= 0.638V_LCD

.

V_state2(t) = V_Sn(t)  V_BP1(t).

V_off(RMS)= 0.333V_LCD

.

Fig 9. Waveforms for the 1:3 multiplex drive mode with ¹⁄₃bias

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PCF8533

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Universal LCD driver for low multiplex rates

7.3.3.4 1:4 multiplex drive mode

The 1:4 multiplex drive mode is used when four backplanes are provided in the LCD as

shown in Figure 10.

T

fr

V

LCD segments

LCD

2V

/ 3

LCD

/ 3

BP0

BP1

BP2

V

LCD

SS

state 1

state 2

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

BP3

Sn

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

Sn+1

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

Sn+2

Sn+3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

0 V

−V

state 1

/ 3

LCD

−2V

−V

/ 3

LCD

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

0 V

−V

state 2

/ 3

LCD

−2V

−V

/ 3

LCD

(b) Resultant waveforms

at LCD segment.

mgl749

V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= 0.577V_LCD

V_state2(t) = V_Sn(t)  V_BP1(t).

_off(RMS)= 0.333V_LCD

.

V

.

Fig 10. Waveforms for the 1:4 multiplex drive mode with ¹⁄₃bias

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PCF8533

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7.4 Oscillator

The internal logic and the LCD drive signals of the PCF8533 are timed by a frequency f_clk,

which either is derived from the built-in oscillator frequency f_oscor equals an external clock

frequency f_clk(ext)

.

f_osc

f_clk

=

--------

64

The clock frequency f_clkdetermines the LCD frame frequency f_fr(see Table 14) and is

calculated as follows:

f_clk

f_fr

=

-------

24

Table 14. LCD frame frequency

Nominal clock frequency (Hz)

1536

LCD frame frequency (Hz)

64

7.4.1 Internal clock

The internal oscillator is enabled by connecting pin OSC to V_SS. In this case, the output

from pin CLK provides the clock signal for cascaded PCF8533 in the system.

7.4.2 External clock

Pin CLK is enabled as an external clock input by connecting pin OSC to V_DD

.

Remark: A clock signal must always be supplied to the device; removing the clock may

freeze the LCD in a DC state, which is not suitable for the liquid crystal.

7.4.3 Timing

The PCF8533 timing controls the internal data flow of the device. This includes the

transfer of display data from the display RAM to the display segment outputs. In cascaded

applications, the synchronization signal (SYNC) maintains the correct timing relationship

between all PCF8533 in the system. The timing also generates the LCD frame signal (f_fr)

whose frequency is derived as an integer division of the clock frequency f_clk(see

Table 14), applied to pin CLK from either the internal or an external clock.

7.5 Backplane and segment outputs

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7.5.1 Backplane outputs

The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane

output signals are generated based on the selected LCD drive mode.

• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.

If less than four backplane outputs are required, the unused outputs can be left

open-circuit.

• In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

• In 1:2 multiplex drive mode: BP0 and BP2, respectively, BP1 and BP3 carry the same

signals and can also be paired to increase the drive capabilities.

• In static drive mode: The same signal is carried by all four backplane outputs; and

they can be connected in parallel for very high drive requirements.

7.5.2 Segment outputs

The LCD drive section includes 80 segment outputs (S0 to S79) which must be connected

directly to the LCD. The segment output signals are generated in accordance with the

multiplexed backplane signals and with data residing in the display register. When less

than 80 segment outputs are required, the unused segment outputs must be left

open-circuit.

7.6 Display RAM

The display RAM is a static 80  4 bit RAM which stores LCD data.

There is a one-to-one correspondence between

• the bits in the RAM bitmap and the LCD elements

• the RAM columns and the segment outputs

• the RAM rows and the backplane outputs.

A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;

similarly, a logic 0 indicates the off-state.

The display RAM bit map, Figure 11, shows rows 0 to 3 which correspond with the

backplane outputs BP0 to BP3, and columns 0 to 79 which correspond with the segment

outputs S0 to S79. In multiplexed LCD applications the segment data of the first, second,

third and fourth row of the display RAM are time-multiplexed with BP0,

BP1, BP2, and BP3 respectively.

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columns

display RAM addresses/segment outputs (S)

0

1

2

3

4

75 76 77 78 79

rows

0

1

2

3

display RAM rows/

backplane outputs

(BP)

013aaa214

The display RAM bitmap shows the direct relationship between the display RAM addresses and

the segment outputs and between the bits in a RAM word and the backplane outputs.

Fig 11. Display RAM bitmap

When display data is transmitted to the PCF8533, the received display bytes are stored in

the display RAM in accordance with the selected LCD drive mode. The data is stored as it

arrives and depending on the current multiplex drive mode the bits are stored singularly, in

pairs, triples or quadruples. To illustrate the filling order, an example of a 7-segment

display showing all drive modes is given in Figure 12; the RAM filling organization

depicted applies equally to other LCD types.

• In static drive mode the eight transmitted data bits are placed into row 0 as one byte.

• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into

row 0 and 1 as two successive 4-bit RAM words.

• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as

three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is

not recommended to use this bit in a display because of the difficult addressing. This

last bit may, if necessary, be controlled by an additional transfer to this address, but

care should be taken to avoid overwriting adjacent data because always full bytes are

transmitted (see Section 7.6.3).

• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples

into row 0, 1, 2, and 3 as two successive 4-bit RAM words.

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7.6.1 Data pointer

The addressing mechanism for the display RAM is realized using a data pointer. This

allows the loading of an individual display data byte, or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load-data-pointer command (see Table 7). Following this command, an

arriving data byte is stored at the display RAM address indicated by the data pointer. The

filling order is shown in Figure 12. After each byte is stored, the content of the data pointer

is automatically incremented by a value dependent on the selected LCD drive mode:

• In static drive mode by eight

• In 1:2 multiplex drive mode by four

• In 1:3 multiplex drive mode by three

• In 1:4 multiplex drive mode by two

If an I²C-bus data access is terminated early, then the state of the data pointer is

unknown. So, the data pointer must be rewritten before further RAM accesses.

7.6.2 Subaddress counter

The storage of display data is determined by the content of the subaddress counter.

Storage is allowed only when the content of the subaddress counter match with the

hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined

by the device-select command (see Table 8). If the content of the subaddress counter and

the hardware subaddress do not match, then data storage is inhibited but the data pointer

is incremented as if data storage had taken place. The subaddress counter is also

incremented when the data pointer overflows.

The storage arrangements described lead to extremely efficient data loading in cascaded

applications. When a series of display bytes are sent to the display RAM, automatic

wrap-over to the next PCF8533 occurs when the last RAM address is exceeded.

Subaddressing across device boundaries is successful even if the change to the next

device in the cascade occurs within a transmitted character.

The hardware subaddress must not be changed while the device is being accessed on the

I²C-bus interface.

7.6.3 RAM writing in 1:3 multiplex drive mode

In 1:3 multiplex drive mode, the RAM is written as shown in Table 15 (see Figure 12 as

well).

Table 15. Standard RAM filling in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 and so on, are not connected to any elements on the

display.

Display RAM

bits (rows)/

backplane

Display RAM addresses (columns)/segment outputs (Sn)

0

1

2

3

4

5

6

7

8

9

:

outputs (BPn)

0

1

2

3

a7

a6

a5

-

a4

a3

a2

-

a1

a0

-

b7

b6

b5

-

b4

b3

b2

-

b1

b0

-

c7

c6

c5

-

c4

c3

c2

-

c1

c0

-

d7

d6

d5

-

:

-

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If the bit at position BP2/S2 would be written by a second byte transmitted, then the

mapping of the segment bits would change as illustrated in Table 16.

Table 16. Entire RAM filling by rewriting in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 and so on, are connected to elements on the display.

Display RAM

bits (rows)/

backplane

Display RAM addresses (columns)/segment outputs (Sn)

0

1

2

3

4

5

6

7

8

9

:

outputs (BPn)

0

1

2

3

a7

a6

a5

-

a4

a3

a2

-

a1/b7 b4

a0/b6 b3

b1/c7 c4

b0/c6 c3

c1/d7 d4

c0/d6 d3

d1/e7 e4

d0/e6 e3

:

b5

-

b2

-

c5

-

c2

-

d5

-

d2

-

e5

-

e2

-

In the case described in Table 16 the RAM has to be written entirely and BP2/S2, BP2/S5,

BP2/S8 and so on, have to be connected to elements on the display. This can be

achieved by a combination of writing and rewriting the RAM like follows:

• In the first write to the RAM, bits a7 to a0 are written

• The data-pointer (see Section 7.6.1 on page 21) has to be set to the address of bit a1

• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7

and b6

• The data-pointer has to be set to the address of bit b1

• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and

c6

Depending on the method of writing to the RAM (standard or entire filling by rewriting),

some elements remain unused or can be used, but it has to be considered in the module

layout process as well as in the driver software design.

7.6.4 Writing over the RAM address boundary

In all multiplex drive modes, depending on the setting of the data pointer, it is possible to

fill the RAM over the RAM address boundary. If the PCF8533 is part of a cascade, the

additional bits fall into the next device that also generates the acknowledge signal. If the

PCF8533 is a single device or the last device in a cascade, the additional bits will be

discarded and no acknowledge signal will be generated.

7.6.5 Bank selection

7.6.5.1 Output bank selector

The output bank selector (see Table 9) selects one of the four rows per display RAM

address for transfer to the display register. The actual row selected depends on the

selected LCD drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by

the contents of row 1, 2, and then 3

• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially

• In 1:2 multiplex mode, rows 0 and 1 are selected

• In static mode, row 0 is selected

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PCF8533

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The PCF8533 includes a RAM bank switching feature in the static and 1:2 multiplex drive

modes. In the static drive mode, the bank-select command may request the contents of

row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex mode,

the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the

provision for preparing display information in an alternative bank and to be able to switch

to it once it is assembled.

7.6.5.2 Input bank selector

The input bank selector loads display data into the display RAM in accordance with the

selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode

or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see

Table 9). The input bank selector functions independently to the output bank selector.

7.6.5.3 RAM bank switching

The PCF8533 includes a RAM bank switching feature in the static and 1:2 multiplex drive

modes. A bank can be thought of as one RAM row or a collection of RAM rows (see

Figure 13). The RAM bank switching gives the provision for preparing display information

in an alternative bank and to be able to switch to it once it is complete.

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&ꢏꢜ*ꢑꢁ

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ꢅꢆ ꢅꢇ ꢅꢅ ꢅꢈ ꢅꢉ

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Fig 13. RAM banks in static and multiplex driving mode 1:2

There are two banks; bank 0 and bank 1. Figure 13 shows the location of these banks

relative to the RAM map. Input and output banks can be set independently from one

another with the Bank-select command (see Table 9 on page 6). Figure 14 shows the

concept.

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PCF8533

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Universal LCD driver for low multiplex rates

ꢓꢔꢕꢖꢗꢐꢘꢙꢔꢚꢐꢛꢜꢝꢜ ꢗꢓ!ꢔ

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ꢎꢌꢅꢏꢐꢒ

ꢀꢀꢀꢁꢂꢂꢅꢆꢃꢆ

Fig 14. Bank selection

In the static drive mode, the bank-select command may request the contents of row 2 to

be selected for display instead of the contents of row 0. In the 1:2 multiplex mode, the

contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the

provision for preparing display information in an alternative bank and to be able to switch

to it once it is assembled.

In Figure 15 an example is shown for 1:2 multiplex drive mode where the displayed data is

read from the first two rows of the memory (bank 0), while the transmitted data is stored in

the second two rows of the memory (bank 1).

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Fig 15. Example of the Bank-select command with multiplex drive mode 1:2

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8. I²C-bus interface

8.1 Characteristics of the I²C-bus

The I²C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial Data line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

By connecting pin SDAACK to pin SDA on the PCF8533, the SDA line becomes fully

I²C-bus compatible. In COG applications where the track resistance from the SDAACK

pin to the system SDA line can be significant, possibly a voltage divider is generated by

the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As a

consequence, it may be possible that the acknowledge generated by the PCF8533 cannot

be interpreted as logic 0 by the master. In COG applications where the acknowledge cycle

is required, it is therefore necessary to minimize the track resistance from the SDAACK

pin to the system SDA line to guarantee a valid LOW level.

By separating the acknowledge output from the serial data line (having the SDAACK open

circuit) design efforts to generate a valid acknowledge level can be avoided. However, in

that case the I²C-bus master has to be set up in such a way that it ignores the

acknowledge cycle.²

The following definition assumes that SDA and SDAACK are connected and refers to the

pair as SDA.

8.1.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal; see Figure 16.

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 16. Bit transfer

8.1.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START

condition (S).

2. For further information, please consider the NXP application note: Ref. 1 “AN10170”.

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A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP

condition (P).

The START and STOP conditions are shown in Figure 17.

SDA

SCL

SDA

SCL

S

P

START condition

STOP condition

mbc622

Fig 17. Definition of START and STOP conditions

8.1.3 System configuration

A device generating a message is a transmitter; a device receiving a message is a

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves; see Figure 18.

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

SDA

SCL

mga807

Fig 18. System configuration

8.1.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

• A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte.

• A master receiver must generate an acknowledge after the reception of each byte that

has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I²C-bus is illustrated in Figure 19.

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PCF8533

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data output

by transmitter

not acknowledge

acknowledge

data output

by receiver

SCL from

master

1

2

8

9

S

clock pulse for

acknowledgement

START

condition

mbc602

Fig 19. Acknowledgement on the I²C-bus

8.1.5 I²C-bus controller

The PCF8533 acts as an I²C-bus slave receiver. It does not initiate I²C-bus transfers or

transmit data to an I²C-bus master receiver. The only data output from the PCF8533 is the

acknowledge signal of the selected device. Device selection depends on the I²C-bus

slave address, the transferred command data and the hardware subaddress.

In single device applications, the hardware subaddress inputs A0, A1, and A2 are

normally tied to V_SSwhich defines the hardware subaddress 0. In multiple device

applications A0, A1, and A2 are tied to V_SSor V_DDusing a binary coding scheme, so that

no two devices with a common I²C-bus slave address have the same hardware

subaddress.

8.1.6 Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

8.1.7 I²C-bus protocol

Two I²C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8533.

The PCF8533 slave address is illustrated in Table 17.

Table 17. I²C slave address byte

Slave address

Bit

7

6

5

4

3

2

1

0

MSB

LSB

R/W

0

1

0

SA0

The least significant bit of the slave address that a PCF8533 will respond to is defined by

the level tied to its SA0 input. The PCF8533 is a write-only device and will not respond to

a read access. Having two reserved slave addresses allows the following on the same

I²C-bus:

• Up to 16 PCF8533 for very large LCD applications

• The use of two types of LCD multiplex drive modes.

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The I²C-bus protocol is shown in Figure 20. The sequence is initiated with a START

condition (S) from the I²C-bus master which is followed by one of two possible PCF8533

slave addresses available. All PCF8533 whose SA0 inputs correspond to bit 0 of the slave

address respond by asserting an acknowledge in parallel. This I²C-bus transfer is ignored

by all PCF8533 whose SA0 inputs are set to the alternative level.

R/W = 0

slave address

control byte

RAM/command byte

S

A

0

M

S

B

L

S

B

C

O

R

S

0

1

0

A

P

A

EXAMPLES

a) transmit two bytes of RAM data

S

0

1

0

A

0

A

0

1

0

RAM DATA

COMMAND

RAM DATA

A

P

A

b) transmit two command bytes

S

A

0

1

S

0

1

0

A

0

COMMAND

RAM DATA

A

P

c) transmit one command byte and two RAM date bytes

S

A

S

0

1

0

A

0

1

0

RAM DATA

A

P

mgl752

Fig 20. I²C-bus protocol

After acknowledgement, the control byte is sent defining if the next byte is a RAM or

command information. The control byte also defines if the next byte is a control byte or

further RAM or command data (see Figure 21 and Table 18). In this way, it is possible to

configure the device and then fill the display RAM with little overhead.

MSB

LSB

7

6

5

4

3

2

1

0

CO RS

not relevant

mgl753

Fig 21. Control byte format

Table 18. Control byte description

Bit

Symbol Value

Description

7

CO

continue bit

last control byte

0

1

control bytes continue

register selection

command register

data register

6

RS

0

1

5 to 0

-

not relevant

PCF8533

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Product data sheet

Rev. 6 — 1 October 2012

28 of 53

PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

The command bytes and control bytes are also acknowledged by all addressed PCF8533

connected to the bus.

The display bytes are stored in the display RAM at the address specified by the data

pointer and the subaddress counter; see Section 7.6.1 and Section 7.6.2.

The acknowledgement after each byte is made only by the (A0, A1, and A2) addressed

PCF8533. After the last (display) byte, the I²C-bus master asserts a STOP condition (P).

Alternatively a START may be asserted to RESTART an I²C-bus access.

PCF8533

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Product data sheet

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

9. Internal circuitry

V

DD

SS

V

DD

SA0, CLK, SYNC,

OSC, A0, A1, A2

V

SCL, SDA,

SDAACK

SS

LCD

V

SS

BP0, BP1, BP2,

BP3, S0 to S79

LCD

V

SS

V

SS

013aaa281

Fig 22. Device protection diagram

PCF8533

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Product data sheet

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

10. Limiting values

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(V_LCD) is on while the IC supply voltage (V_DD) is off, or vice versa. This may cause unwanted

display artifacts. To avoid such artifacts, V_LCDand V_DDmust be applied or removed together.

Table 19. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

V_LCD

V_i(n)

V_o(n)

I_I

Parameter

Conditions

Min

0.5

Max Unit

supply voltage

+6.5

V

LCD supply voltage

voltage on any input

voltage on any output

input current

0.5

10

50

-

+7.5

+6.5

+7.5

+10

V

V_DD-related inputs

V

V_LCD-related outputs

V

mA

mW

V

I_O

output current

+10

I_DD

supply current

+50

I_SS

ground supply current

LCD supply current

total power dissipation

power dissipation per output

+50

I_DD(LCD)

P_tot

+50

400

P/out

V_ESD

-

100

[1]

[2]

[3]

[4]

electrostatic discharge voltage HBM

MM

-

4500

200

200

-

V

I_lu

latch-up current

-

mA

C

T_stg

T_amb

storage temperature

65

40

+150

+85

ambient temperature

operating device

[1] Pass level; Human Body Model (HBM), according to Ref. 6 “JESD22-A114”.

[2] Pass level; Machine Model (MM), according to Ref. 7 “JESD22-A115”.

[3] Pass level; latch-up testing according to Ref. 8 “JESD78” at maximum ambient temperature (T_amb(max)).

[4] According to the store and transport requirements (see Ref. 11 “UM10569”) the devices have to be stored

at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %.

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Product data sheet

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

11. Static characteristics

Table 20. Static characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 6.5 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Supplies

V_DD

supply voltage

1.8

2.5

1.0

-

5.5

6.5

1.6

5

V

V_LCD

V_POR

I_DD

LCD supply voltage

power-on reset voltage

supply current

-

V

1.3

3

V

[1][2]

[1]

f_clk(ext)= 1536 Hz

A

I_DD(LCD)LCD supply current

-

25

30

Logic

V_I

input voltage

V_SS 0.5 -

V_DD+ 0.5 V

V_IL

LOW-level input voltage

on pins CLK, SYNC, OSC,

A0 to A2, SA0

V_SS

-

0.3V_DD

V

V_IH

HIGH-level input voltage

on pins CLK, SYNC, OSC,

A0 to A2, SA0

0.7V_DD

-

V_DD

V

V_O

V_OH

V_OL

I_L

output voltage

0.5

0.8V_DD

-

V_DD+ 0.5 V

HIGH-level output voltage

LOW-level output voltage

leakage current

-

V

0.2V_DD

+1

V

on pins OSC, CLK, SCL, SDA,

A0 to A2, SA0; V_I= V_DDor V_SS

1

A

I_OL

LOW-level output current

output sink current; on pins

CLK, SYNC; V_OL= 0.4 V;

V_DD= 5 V

1

-

mA

I_OH

HIGH-level output current

input capacitance

output source current; on pin

CLK; V_OH= 4.6 V; V_DD= 5 V

1

-

mA

pF

[3]

C_I

7

I²C-bus^[4]

I_OL(SDA)LOW-level output current on

pin SDA

V_OL= 0.4 V; V_DD= 5 V

3

-

mA

Input on pins SDA and SCL

V_I

input voltage

V_SS 0.5 -

5.5

0.3V_DD

5.5

+1

V

V_IL

V_IH

I_LI

LOW-level input voltage

HIGH-level input voltage

input leakage current

input capacitance

V_SS

-

V

0.7V_DD

V

V_I= V_DDor V_SS

1

A

pF

[3]

C_I

-

7

PCF8533

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Product data sheet

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

Table 20. Static characteristics …continued

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 6.5 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

LCD outputs

Output pins BP0 to BP3 and S0 to S79

[5]

[6]

V_O

output voltage variation

on pins BP0 to BP3;

C_bpl= 35 nF

100

-

+100

mV

on pins S0 to S79;

C_sgm= 5 nF

R_O

output resistance

V_LCD= 5 V

[7]

on pins BP0 to BP3

on pins S0 to S79

-

1.5

6.0

10

k

13.5

[1] LCD outputs are open-circuit; inputs at V_SSor V_DD; external clock with 50 % duty factor; I²C-bus inactive.

[2] For typical values, see Figure 23.

[3] Not tested, design specification only.

[4] The I²C-bus interface of PCF8533 is 5 V tolerant.

[5]

C_bpl= backplane capacitance.

[6] C_sgm= segment capacitance.

[7] Outputs measured individually and sequentially.

001aal523

5

4

3

2

1

0

I

DD

(μA)

2

3

4

5

6

V

(V)

DD

T_amb= 30 C; 1:4 multiplex drive mode; V_LCD= 6.5 V; f_clk(ext)= 1.536 kHz; all RAM written with

logic 1; no display connected; I²C-bus inactive.

Fig 23. Typical I_DDwith respect to V_DD

PCF8533

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Product data sheet

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

12. Dynamic characteristics

Table 21. Dynamic characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 6.5 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Clock

f_clk(int)

f_clk(ext)

t_clk(H)

t_clk(L)

[1][2]

internal clock frequency

external clock frequency

HIGH-level clock time

LOW-level clock time

960

797

130

1536

3046

Hz

s

1536

3046

-

Synchronization: input pin SYNC

t_{PD(SYNC_N)}SYNC propagation delay

-

30

-

ns

t_{SYNC_NL}

Outputs: pins BP0 to BP3 and S0 to S79

t_PD(drv)driver propagation delay

SYNC LOW time

1

s

V_LCD= 5 V

-

30

s

I²C-bus: timing^[3]; see Figure 25

Pin SCL

f_SCL

SCL clock frequency

-

400

kHz

s

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

1.3

0.6

-

t_HIGH

s

Pin SDA

t_SU;DAT

t_HD;DAT

data set-up time

data hold time

100

0

-

ns

Pins SCL and SDA

t_BUF

bus free time between a STOP and

1.3

-

s

START condition

t_SU;STO

t_HD;STA

t_SU;STA

set-up time for STOP condition

hold time (repeated) START condition

0.6

-

s

set-up time for a repeated START

condition

t_r

rise time of both SDA and SCL signals f_SCL= 400 kHz

f_SCL< 125 kHz

-

0.3

1.0

0.3

400

50

s

pF

ns

t_f

fall time of both SDA and SCL signals

capacitive load for each bus line

C_b

t_w(spike)

spike pulse width

on bus

[1] Typical output duty cycle of 50 %.

[2] The corresponding frame frequency is f_fr= f_clk 24 .

[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V_ILand V_IHwith an

input voltage swing of V_SSto V_DD

.

PCF8533

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Product data sheet

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

1 / f

CLK

t

clk(L)

clk(H)

0.7 V

0.3 V

DD

CLK

0.7 V

0.3 V

DD

SYNC

t

PD(SYNC_N)

t

SYNC_NL

0.5 V

BP0 to BP3,

and S0 to S79

(V

= 5 V)

DD

0.5 V

t

001aag591

PD(drv)

Fig 24. Driver timing waveforms

SDA

t

f

BUF

LOW

SCL

SDA

t

HD;STA

t

SU;DAT

r

HD;DAT

t

HIGH

t

SU;STA

t

SU;STO

mga728

Fig 25. I²C-bus timing waveforms

PCF8533

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Product data sheet

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

13. Application information

13.1 Cascaded operation

Large display configurations of up to sixteen PCF8533 can be recognized on the same

I²C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable

I²C-bus slave address (SA0).

Table 22. Addressing cascaded PCF8533

Cluster

Bit SA0

A2

0

Device

A1

0

1

0

1

0

1

0

1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

0

3

1

4

1

5

1

6

1

7

2

1

0

8

0

9

0

10

11

12

13

14

15

0

1

When cascaded PCF8533 are synchronized, they can share the backplane signals from

one of the devices in the cascade. Such an arrangement is cost-effective in large LCD

applications since the backplane outputs of only one device need to be through-plated to

the backplane electrodes of the display. The other PCF8533 of the cascade contribute

additional segment outputs, but their backplane outputs are left open-circuit

(see Figure 26).

PCF8533

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Product data sheet

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

SDAACK

V

LCD

DD

SDA

SCL

80 segment drives

LCD PANEL

SYNC

CLK

PCF8533

(up to 5120

elements)

OSC

BP0 to BP3

(open-circuit)

A0 A1 A2 SA0

V

SS

V

LCD

V

t

r

DD

SDAACK

≤

R

2C

V

LCD

b

DD

SDA

SCL

HOST

MICRO-

80 segment drives

PROCESSOR/

MICRO-

CONTROLLER

SYNC

PCF8533

4 backplanes

BP0 to BP3

CLK

OSC

mgl754

A0 A1 A2 SA0

V

SS

V

SS

Fig 26. Cascaded PCF8533 configuration

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCF8533. This synchronization is guaranteed after the Power-On Reset (POR). The only

time that SYNC is likely to be needed is if synchronization is accidentally lost (for

example, by noise in adverse electrical environments, or by the definition of a multiplex

mode when PCF8533 with different SA0 levels are cascaded).

SYNC is organized as an input/output pin; the output selection being realized as an

open-drain driver with an internal pull-up resistor. A PCF8533 asserts the SYNC line at the

onset of its last active backplane signal and monitors the SYNC line at all other times.

Should synchronization in the cascade be lost, it will be restored by the first PCF8533 to

assert SYNC. The timing relationships between the backplane waveforms and the SYNC

signal for the various drive modes of the PCF8533 are shown in Figure 27.

PCF8533

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

1

T

=

fr

f

fr

BP0

SYNC

(a) static drive mode.

BP0

(1/2 bias)

BP0

(1/3 bias)

SYNC

(b) 1:2 multiplex drive mode.

BP0

(1/3 bias)

SYNC

(c) 1:3 multiplex drive mode.

BP0

(1/3 bias)

SYNC

(d) 1:4 multiplex drive mode.

mgl755

Fig 27. Synchronization of the cascade for the various PCF8533 drive modes

The contact resistance between the SYNC pins of cascaded devices must be controlled. If

the resistance is too high, then the device will not be able to synchronize properly. This is

particularly applicable to COG applications. Table 23 shows the limiting values for contact

resistance.

Table 23. SYNC contact resistance

Number of devices

Maximum contact resistance

2

6000 

2200 

1200 

700 

3 to 5

6 to 10

11 to 16

PCF8533

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Product data sheet

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

14. Bare die outline

Bare die; 99 bumps; 5.28 x 1.4 x 0.38 mm

PCF8533-2

X

D

y

85

30

PC8533-2

E

x

0,0

99 1

29

Y

b

A

e

1

A

1

L

detail Y

detail X

0

1

2 mm

scale

Dimensions

(1)

Unit

A

b

D

E

e

1

L

1

max

mm nom 0.381 0.017 0.050 5.276 1.402

min 0.014 0.047

0.020 0.053

0.289 0.093

0.090

0.08

0.087

Note

1. Dimension not drawn to scale

pcf8533-2_do

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

09-09-08

10-01-28

PCF8533-2

Fig 28. Bare die outline of PCF8533-2

PCF8533

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Product data sheet

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

Table 24. Bump locations

All x/y coordinates represent the position of the centre of each bump with respect to the center

(x/y = 0) of the chip; see Figure 28.

Symbol

SDAACK

SDA

SCL

CLK

V_DD

SYNC

OSC

A0

Bump X (m)

Y (m)

Description

[1]

1

1079.20 594.40

I²C-bus acknowledge output

I²C-bus serial data input

2

839.20

759.20

599.20

519.20

414.80

284.80

4.20

594.40

3

4

I²C-bus serial clock input

5

6

clock input/output

7

supply voltage

8

cascade synchronization input/output

oscillator select

9

119.20

249.20

379.20

581.20

711.20

841.20

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

subaddress input

A1

A2

SA0

V_SS

V_LCD

BP2

BP0

S0

I²C-bus slave address input; bit 0

ground supply voltage

1099.60 594.40

1277.60 594.40

1357.60 594.40

1437.60 594.40

1517.60 594.40

1597.60 594.40

1677.60 594.40

1757.60 594.40

1837.60 594.40

1917.60 594.40

1997.60 594.40

2077.60 594.40

2157.60 594.40

2237.60 594.40

2317.60 594.40

2357.60 594.40

2277.60 594.40

2197.60 594.40

LCD supply voltage

LCD backplane output

LCD segment output

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

2117.60

594.40

2037.60 594.40

1957.60 594.40

1877.60 594.40

1797.60 594.40

1717.60 594.40

1637.60 594.40

PCF8533

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Product data sheet

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

Table 24. Bump locations

All x/y coordinates represent the position of the centre of each bump with respect to the center

(x/y = 0) of the chip; see Figure 28.

Symbol

S22

S23

S24

S25

S26

S27

S28

S29

S30

S31

S32

S33

S34

S35

S36

S37

S38

S39

S40

S41

S42

S43

S44

S45

S46

S47

S48

S49

S50

S51

S52

S53

S54

S55

S56

S57

S58

S59

S60

Bump X (m)

Y (m)

Description

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

1557.60 594.40

1477.60 594.40

1317.60 594.40

1237.60 594.40

LCD segment output

1157.60

594.40

1077.60 594.40

997.60

917.60

837.60

757.60

677.60

597.60

437.60

357.60

277.60

197.60

117.60

37.60

594.40

42.40

122.40

202.40

282.40

362.40

442.40

602.40

682.40

762.40

842.40

922.40

1002.40 594.40

1082.40 594.40

1162.40 594.40

1242.40 594.40

1322.40 594.40

1402.40 594.40

1562.40 594.40

1642.40 594.40

1722.40 594.40

1802.40 594.40

PCF8533

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Product data sheet

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

Table 24. Bump locations

All x/y coordinates represent the position of the centre of each bump with respect to the center

(x/y = 0) of the chip; see Figure 28.

Symbol

S61

S62

S63

S64

S65

S66

S67

S68

S69

S70

S71

S72

S73

S74

S75

S76

S77

S78

S79

BP3

BP1

D1

Bump X (m)

Y (m)

Description

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

-

1882.40 594.40

1962.40 594.40

2042.40 594.40

2122.40 594.40

2202.40 594.40

2282.40 594.40

2362.40 594.40

2322.40 594.40

2242.40 594.40

2162.40 594.40

2082.40 594.40

2002.40 594.40

1922.40 594.40

1842.40 594.40

1762.40 594.40

1682.40 594.40

1602.40 594.40

1522.40 594.40

1442.40 594.40

1362.40 594.40

1282.40 594.40

2469.70 594.40

2549.70 594.40

2517.60 594.40

2437.60 594.40

2442.30 594.40

2522.30 594.40

2554.40 594.40

2474.40 594.40

LCD segment output

LCD backplane output

dummy bump

[2]

D2

-

D3

-

D4

-

D5

-

D6

-

D7

-

D8

-

[1] For most applications SDA and SDAACK are shorted together; see Section 8.1.

[2] The dummy bumps are connected to the adjacent segments but are not tested.

Table 25. Alignment mark locations

Symbol

X (m)

Y (m)

55.0

C1

C2

F

2300.5

2320.2

2208.3

107.0

165.4

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Product data sheet

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

REF

C1

C2

REF

F

mgl756

The positions of the alignment marks are shown in Figure 2 and Figure 28.

Fig 29. Alignment marks of PCF8533

Table 26. Gold bump hardness

Type number

Min

Max

Unit^[1]

PCF8533U/2/F2

60

120

HV

[1] Pressure of diamond head: 10 g to 50 g.

15. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent

standards.

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

16. Packing information

16.1 Tray information

8

ꢌ

4

ꢎ

ꢈ

9:ꢒ

ꢒ:ꢒ

5

$ꢓꢜ

ꢏ

$ꢜꢗꢙꢓꢝꢐ5

ꢉ

ꢒ:%

%

6

7

9

ꢈ

ꢂ

ꢅ

ꢇ

ꢀ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈ

ꢍ

$ꢜꢗꢙꢓꢝꢐꢍ

ꢉꢓ&ꢜꢔꢛꢓ!ꢔꢛꢐꢓꢔꢐ&&

ꢀꢀꢀꢁꢂꢂꢇꢇꢅꢃ

Fig 30. Tray details

Table 27. Description of tray details

Tray details are shown in Figure 30.

Tray details

Dimensions

A

B

C

D

E

F

G

H

J

K

L

M

N

Unit

mm

7.0

2.4

5.38

1.50

50.8

45.72 35.0

5.0

7.9

40.8

3.96

2.18

2.49

Number of pockets

x direction

6

y direction

18

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

marking code

001aaj643

Fig 31. Tray alignment

The orientation of the IC in a pocket is indicated by the position of the IC type name on the

die surface with respect to the chamfer on the upper left corner of the tray. Refer to

Figure 28 for the orientation and position of the type name on the die surface.

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

17. Abbreviations

Table 28. Abbreviations

Acronym

CMOS

COG

DC

Description

Complementary Metal-Oxide Semiconductor

Chip-On-Glass

Direct Current

ESD

HBM

I²C

ElectroStatic Discharge

Human Body Model

Inter-Integrated Circuit bus

Integrated Circuit

IC

ITO

Indium Tin Oxide

LCD

LSB

MM

Liquid Crystal Display

Least Significant Bit

Machine Model

MOS

MSB

POR

RC

Metal-Oxide Semiconductor

Most Significant Bit

Power-On Reset

Resistance-Capacitance

Random Access Memory

Root Mean Square

RAM

RMS

SCL

SDA

Serial CLock line

Serial DAta line

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PCF8533

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Universal LCD driver for low multiplex rates

18. References

[1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD

drivers

[2] AN10706 — Handling bare die

[3] AN10853 — ESD and EMC sensitivity of IC

[4] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[6] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[7] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model

(MM)

[8] JESD78 — IC Latch-Up Test

[9] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[10] UM10204 — I²C-bus specification and user manual

[11] UM10569 — Store and transport requirements

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PCF8533

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Universal LCD driver for low multiplex rates

19. Revision history

Table 29. Revision history

Document ID

PCF8533 v.6

Modifications:

Release date

20121001

Data sheet status

Change notice

Supersedes

Product data sheet

-

PCF8533 v.5

• Removed withdrawn product type

• Adjusted values for I_DDand I_DD(LCD)in Table 20

• Changed tray information (Section 16.1)

• Added ordering options (Section 3.1)

• Enhanced display RAM description (Section 7.6)

• Improved description of bit E (Table 6)

PCF8533 v.5

PCF8533_4

20110629

20100305

20080424

19990730

19990312

Product data sheet

Product specification

-

PCF8533_4

PCF8533_3

PCF8533_2

PCF8533_SDS_1

-

PCF8533_3

PCF8533_2

PCF8533_SDS_1

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

20. Legal information

20.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

20.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

20.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

PCF8533

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Product data sheet

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Bare die — All die are tested on compliance with their related technical

specifications as stated in this data sheet up to the point of wafer sawing and

are handled in accordance with the NXP Semiconductors storage and

transportation conditions. If there are data sheet limits not guaranteed, these

will be separately indicated in the data sheet. There are no post-packing tests

performed on individual die or wafers.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors has no control of third party procedures in the sawing,

handling, packing or assembly of the die. Accordingly, NXP Semiconductors

assumes no liability for device functionality or performance of the die or

systems after third party sawing, handling, packing or assembly of the die. It

is the responsibility of the customer to test and qualify their application in

which the die is used.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

All die sales are conditioned upon and subject to the customer entering into a

written die sale agreement with NXP Semiconductors through its legal

department.

20.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

I²C-bus — logo is a trademark of NXP B.V.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

22. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4. Pin description overview . . . . . . . . . . . . . . . . . .4

Table 5. Definition of commands . . . . . . . . . . . . . . . . . . .5

Table 6. Mode-set command bit description . . . . . . . . . .5

Table 7. Load-data-pointer command bit description . . .6

Table 8. Device-select command bit description . . . . . . .6

Table 9. Bank-select command bit description . . . . . . . .6

Table 10. Blink-select command bit description . . . . . . . .7

Table 11. Blink frequencies . . . . . . . . . . . . . . . . . . . . . . . .7

Table 12. Selection of possible display configurations . . . .9

Table 13. Biasing characteristics . . . . . . . . . . . . . . . . . . .10

Table 14. LCD frame frequency . . . . . . . . . . . . . . . . . . .17

Table 15. Standard RAM filling in 1:3 multiplex drive

mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 16. Entire RAM filling by rewriting in 1:3

multiplex drive mode. . . . . . . . . . . . . . . . . . . . .22

Table 17. I²C slave address byte . . . . . . . . . . . . . . . . . . .28

Table 18. Control byte description . . . . . . . . . . . . . . . . . .29

Table 19. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 20. Static characteristics . . . . . . . . . . . . . . . . . . . .33

Table 21. Dynamic characteristics . . . . . . . . . . . . . . . . . .35

Table 22. Addressing cascaded PCF8533 . . . . . . . . . . .37

Table 23. SYNC contact resistance . . . . . . . . . . . . . . . . .39

Table 24. Bump locations. . . . . . . . . . . . . . . . . . . . . . . . .41

Table 25. Alignment mark locations . . . . . . . . . . . . . . . .43

Table 26. Gold bump hardness . . . . . . . . . . . . . . . . . . . .44

Table 27. Description of tray details . . . . . . . . . . . . . . . . .45

Table 28. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 29. Revision history . . . . . . . . . . . . . . . . . . . . . . . .49

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

23. Figures

Fig 1. Block diagram of PCF8533 . . . . . . . . . . . . . . . . . .3

Fig 2. Pin configuration for PCF8533U . . . . . . . . . . . . . .4

Fig 3. Example of displays suitable for PCF8533 . . . . . .8

Fig 4. Typical system configuration . . . . . . . . . . . . . . . . .9

Fig 5. Electro-optical characteristic: relative

transmission curve of the liquid . . . . . . . . . . . . . .11

Fig 6. Static drive mode waveforms. . . . . . . . . . . . . . . .12

Fig 7. Waveforms for the 1:2 multiplex drive mode

with ¹⁄₂bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Fig 8. Waveforms for the 1:2 multiplex drive mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Fig 9. Waveforms for the 1:3 multiplex drive mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Fig 10. Waveforms for the 1:4 multiplex drive mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Fig 11. Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . .19

Fig 12. Relationships between LCD layout, drive mode,

display RAM filling order, and display data

transmitted over the I²C-bus . . . . . . . . . . . . . . . .20

Fig 13. RAM banks in static and multiplex driving

mode 1:2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Fig 14. Bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Fig 15. Example of the Bank-select command with

multiplex drive mode 1:2 . . . . . . . . . . . . . . . . . . .25

Fig 16. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Fig 17. Definition of START and STOP conditions. . . . . .27

Fig 18. System configuration . . . . . . . . . . . . . . . . . . . . . .27

Fig 19. Acknowledgement on the I²C-bus . . . . . . . . . . . .28

Fig 20. I²C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . . . .29

Fig 21. Control byte format . . . . . . . . . . . . . . . . . . . . . . .29

Fig 22. Device protection diagram. . . . . . . . . . . . . . . . . .31

Fig 23. Typical I_DDwith respect to V_DD. . . . . . . . . . . . . .34

Fig 24. Driver timing waveforms . . . . . . . . . . . . . . . . . . .36

Fig 25. I²C-bus timing waveforms . . . . . . . . . . . . . . . . . .36

Fig 26. Cascaded PCF8533 configuration. . . . . . . . . . . .38

Fig 27. Synchronization of the cascade for the various

PCF8533 drive modes. . . . . . . . . . . . . . . . . . . . .39

Fig 28. Bare die outline of PCF8533-2 . . . . . . . . . . . . . .40

Fig 29. Alignment marks of PCF8533 . . . . . . . . . . . . . . .44

Fig 30. Tray details . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Fig 31. Tray alignment . . . . . . . . . . . . . . . . . . . . . . . . . . .46

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PCF8533

NXP Semiconductors

Universal LCD driver for low multiplex rates

24. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

8.1.2

8.1.3

8.1.4

8.1.5

8.1.6

8.1.7

START and STOP conditions. . . . . . . . . . . . . 26

System configuration . . . . . . . . . . . . . . . . . . . 27

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 27

I²C-bus controller . . . . . . . . . . . . . . . . . . . . . . 28

Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 28

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3

3.1

4

5

9

Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 31

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 32

Static characteristics . . . . . . . . . . . . . . . . . . . 33

Dynamic characteristics. . . . . . . . . . . . . . . . . 35

Application information . . . . . . . . . . . . . . . . . 37

Cascaded operation. . . . . . . . . . . . . . . . . . . . 37

Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 40

Handling information . . . . . . . . . . . . . . . . . . . 44

Packing information . . . . . . . . . . . . . . . . . . . . 45

Tray information . . . . . . . . . . . . . . . . . . . . . . . 45

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 47

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Revision history . . . . . . . . . . . . . . . . . . . . . . . 49

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

10

11

12

13

13.1

14

15

16

16.1

17

18

19

7

7.1

Functional description . . . . . . . . . . . . . . . . . . . 5

Commands of PCF8533. . . . . . . . . . . . . . . . . . 5

Command: mode-set . . . . . . . . . . . . . . . . . . . . 5

Command: load-data-pointer . . . . . . . . . . . . . . 6

Command: device-select . . . . . . . . . . . . . . . . . 6

Command: bank-select. . . . . . . . . . . . . . . . . . . 6

Command: blink-select. . . . . . . . . . . . . . . . . . . 7

Blinking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 8

Possible display configurations . . . . . . . . . . . . 8

LCD bias generator . . . . . . . . . . . . . . . . . . . . . 9

LCD voltage selector . . . . . . . . . . . . . . . . . . . . 9

Electro-optical performance . . . . . . . . . . . . . . 11

LCD drive mode waveforms . . . . . . . . . . . . . . 12

Static drive mode . . . . . . . . . . . . . . . . . . . . . . 12

1:2 multiplex drive mode. . . . . . . . . . . . . . . . . 13

1:3 multiplex drive mode. . . . . . . . . . . . . . . . . 15

1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 16

Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 17

External clock . . . . . . . . . . . . . . . . . . . . . . . . . 17

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Backplane and segment outputs . . . . . . . . . . 17

Backplane outputs . . . . . . . . . . . . . . . . . . . . . 18

Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 18

Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 18

Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Subaddress counter . . . . . . . . . . . . . . . . . . . . 21

RAM writing in 1:3 multiplex drive mode. . . . . 21

Writing over the RAM address boundary . . . . 22

Bank selection . . . . . . . . . . . . . . . . . . . . . . . . 23

Output bank selector . . . . . . . . . . . . . . . . . . . 23

Input bank selector . . . . . . . . . . . . . . . . . . . . . 23

RAM bank switching. . . . . . . . . . . . . . . . . . . . 23

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.1.5.1

7.2

7.3

7.3.1

7.3.2

7.3.2.1

7.3.3

7.3.3.1

7.3.3.2

7.3.3.3

7.3.3.4

7.4

7.4.1

7.4.2

7.4.3

7.5

20

Legal information . . . . . . . . . . . . . . . . . . . . . . 50

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 50

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 51

20.1

20.2

20.3

20.4

21

22

23

24

Contact information . . . . . . . . . . . . . . . . . . . . 51

Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.5.1

7.5.2

7.6

7.6.1

7.6.2

7.6.3

7.6.4

7.6.5

7.6.5.1

7.6.5.2

7.6.5.3

8

I²C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 26

Characteristics of the I²C-bus. . . . . . . . . . . . . 26

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.1

8.1.1

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 1 October 2012

Document identifier: PCF8533


型号：	PCF8533U/2/F2,026
厂家：	NXP
描述：	PCF8533 - Universal LCD driver for low multiplex rates DIE 99-Pin PC 驱动 CD 接口集成电路
文件：	总53页 (文件大小：431K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCF8533U/2/F2,026 [NXP]

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