PCF8534AH/1,518_技术文档

PCF8534A

Universal LCD driver for low multiplex rates

Rev. 6 — 25 July 2011

Product data sheet

1. General description

The PCF8534A is a peripheral device which interfaces to almost any Liquid Crystal

Display (LCD)¹with low multiplex rates. It generates the drive signals for any static or

multiplexed LCD containing up to four backplanes and up to 60 segments. It can be easily

cascaded for larger LCD applications. The PCF8534A is compatible with most

microcontrollers and communicates via the two-line bidirectional I²C-bus. Communication

overheads are minimized by a display RAM with auto-incremented addressing, by

hardware subaddressing, and by display memory switching (static and duplex drive

modes).

• PCF8534AHL/1 should not be used for new design-ins. Replacement part is

PCF85134HL/1

2. Features and benefits

 AEC-Q100 compliant (PCF8534AH/1) for automotive applications

 Single-chip LCD controller and driver

 Selectable backplane drive configurations: static or 2, 3, or 4 backplane multiplexing

 60 segment outputs allowing to drive:

 30 7-segment numeric characters

 15 14-segment alphanumeric characters

 Any graphics of up to 240 elements

 Cascading supported for larger applications

 60  4-bit display data storage RAM

 Wide LCD supply range: from 2.5 V for low threshold LCDs up to 6.5 V for high

threshold twisted nematic LCDs

 Internal LCD bias generation with voltage follower buffers

 Selectable display bias configurations: static, ¹⁄₂, or ¹⁄₃

 Wide logic power supply range: from 1.8 V to 5.5 V

 LCD and logic supplies may be separated

 Low power consumption

 400 kHz I²C-bus interface

 No external components required

 Display memory bank switching in static and duplex drive modes

 Versatile blinking modes

 Silicon gate CMOS process

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19.

PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Delivery form Version

PCF8534AHL/1^[1]LQFP80

plastic low profile quad flat

package; 80 leads;

tape and reel SOT315-1

body 12  12  1.4 mm

PCF8534AU/DA/1 wire bond die 76 bonding pads;

chip in tray

PCF8534AU

2.91  2.62  0.38 mm

[1] Not to be used for new designs. Replacement part is PCF85134HL/1.

4. Marking

Table 2.

Marking codes

Type number

Marking code

PCF8534AHL

PC8534A-1

PCF8534AHL/1

PCF8534AU/DA/1

PCF8534A

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

5. Block diagram

BP0 BP1 BP2 BP3

S0 to S59

60

V

LCD

BACKPLANE

OUTPUTS

DISPLAY SEGMENT OUTPUTS

DISPLAY REGISTER

LCD

VOLTAGE

SELECTOR

OUTPUT BANK SELECT

AND BLINK CONTROL

DISPLAY

CONTROL

LCD BIAS

GENERATOR

V

SS

DISPLAY

RAM

PCF8534A

CLK

BLINKER

CLOCK SELECT

TIMEBASE

AND TIMING

SYNC

COMMAND

DECODE

DATA POINTER AND

AUTO INCREMENT

WRITE DATA

CONTROL

POWER-ON

RESET

OSC

OSCILLATOR

SCL

SDA

2

INPUT

FILTERS

SUBADDRESS

COUNTER

I C-BUS

CONTROLLER

A0 A1 A2

SA0

V

DD

001aah614

Fig 1. Block diagram of PCF8534A

PCF8534A

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

6. Pinning information

6.1 Pinning

1

2

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

S31

S32

S33

S34

S35

S36

S37

S38

S39

S40

S41

S42

S43

S44

S45

S46

S47

S48

S49

S50

S10

S9

S8

S7

S6

S5

S4

S3

S2

S1

S0

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

PCF8534AHL

V

LCD

V

SS

SA0

A2

A1

A0

OSC

SYNC

V

DD

013aaa158

Top view. For mechanical details, see Figure 25.

Fig 2. Pin configuration for SOT315-1 (PCF8534AHL)

PCF8534A

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

C1

64

C2

S51

S52

S53

S54

S55

S56

65

66

67

68

69

43

42

41

40

39

38

37

S30

S29

S28

S27

S26

S25

S24

PCF8534A-1

70

71

72

73

74

75

76

S57

S58

S59

BP0

BP1

BP2

BP3

36

35

34

33

32

31

30

29

28

27

26

25

24

S23

S22

S21

S20

S19

S18

S17

S16

S15

S14

S13

S12

S11

1

SDA

2

SCL

CLK

3

F

Top view

001aai648

Viewed from active side. For mechanical details, see Figure 26.

Fig 3. Pin configuration for the wire bond die (PCF8534AU)

PCF8534A

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

6.2 Pin description

Table 3.

Symbol

Pin description

Type

Description

SOT315-1 Wire bond die

S31 to S59 1 to 29

BP0 to BP3 30 to 33

44 to 72

73 to 76

-

output

-

LCD segment output 31 to 59

LCD backplane output 0 to 3

n.c.

34 to 37

not connected; do not connect and do

not use as feed through

SDA

SCL

CLK

38

39

40

1

2

3

input/output

input

I²C-bus serial data input and output

I²C-bus serial clock input

input/output

external clock input and internal clock

output

V_DD

41

42

4

5

supply

supply voltage

SYNC

input/output

cascade synchronization input and

output (active LOW)

OSC

43

6

input

enable input for internal oscillator

subaddress counter input 0 to 2

I²C-bus slave address input 0

ground

A0 to A2

SA0

44 to 46

47

7 to 9

input

10

input

V_SS

48

11^[1]

12

supply

output

V_LCD

49

input of LCD supply voltage

LCD segment output 0 to 30

S0 to S30

50 to 80

13 to 43

[1] The substrate (rear side of the die) is connected to V_SSand should be electrically isolated.

PCF8534A

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Product data sheet

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6 of 52

PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

7. Functional description

The PCF8534A is a versatile peripheral device designed to interface between any

microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 4). It

can directly drive any static or multiplexed LCD containing up to four backplanes and up to

60 segments.

The display configurations possible with the PCF8534A depend on the required number of

active backplane outputs. A selection of display configurations is given in Table 4.

All of the display configurations given in Table 4 can be implemented in a typical system

as shown in Figure 5.

dot matrix

7-segment with dot

14-segment with dot and accent

013aaa312

Fig 4. Example of displays suitable for PCF8534A

Table 4.

Selection of possible display configurations

Number of

Backplanes

Icons

Digits/Characters

7-segment^[1]

Dot matrix/

Elements

14-segment^[2]

4

3

2

1

240

180

120

60

30

22

15

7

15

11

7

240 (4  60)

180 (3  60)

120 (2  60)

60 (1  60)

3

[1] 7-segment display has eight elements including the decimal point.

[2] 14-segment display has 16 elements including decimal point and accent dot.

PCF8534A

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

V

DD

t

r

R

≤

2C

b

V

DD

LCD

60 segment drives

4 backplanes

SDA

SCL

HOST

MICRO-

PROCESSOR/

MICRO-

LCD PANEL

PCF8534A

(up to 240

elements)

OSC

CONTROLLER

A0 A1 A2 SA0

V

SS

001aah616

V

SS

Fig 5. Typical system configuration

The host microcontroller maintains the 2-line I²C-bus communication channel with the

PCF8534A.

Biasing voltages for the multiplexed LCD waveforms are generated internally, removing

the need for an external bias generator. The internal oscillator is selected by connecting

pin OSC to V_SS. The only other connections required to complete the system are the

power supplies (pins V_DD, V_SS, and V_LCD) and the LCD panel selected for the application.

7.1 Power-On Reset (POR)

At power-on the PCF8534A resets to the following starting conditions:

• All backplane and segment outputs are set to V_LCD

• The selected drive mode is: 1:4 multiplex with ¹⁄₃bias

• Blinking is switched off

• Input and output bank selectors are reset

• The I²C-bus interface is initialized

• The data pointer and the subaddress counter are cleared (set to logic 0)

• Display is disabled

Remark: Do not transfer data on the I²C-bus for at least 1 ms after a power-on to allow

the reset action to complete.

7.2 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of

three impedances connected in series between V_LCDand V_SS. If the ¹⁄₂bias voltage level

for the 1:2 multiplex drive mode configuration is selected, the center impedance is

bypassed by switch. The LCD voltage can be temperature compensated externally, using

the supply to pin V_LCD

.

PCF8534A

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.3 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by the

mode-set command from the command decoder. The biasing configurations that apply to

the preferred modes of operation, together with the biasing characteristics as functions of

V

_LCDand the resulting discrimination ratios (D) are given in Table 5.

Discrimination is a term which is defined as the ratio of the on and off RMS voltage across

a segment. It can be thought of as a measurement of contrast.

Table 5.

Biasing characteristics

Number of:

LCD drive

mode

LCD bias

configuration

V_offRMSV_onRMS

------------------------ ----------------------- D = ------------------------

V_LCDV_LCDV_offRMS

V_onRMS

Backplanes Levels

static

1

2

3

4

2

3

4

static

0

1



1

⁄

1:2 multiplex

1:3 multiplex

1:4 multiplex

0.354

0.333

0.791

0.745

0.638

0.577

2.236

1.915

1.732

2

1

⁄

3

1

⁄

3

1

⁄

3

A practical value for V_LCDis determined by equating V_off(RMS)with a defined LCD

threshold voltage (V_th(off)), typically when the LCD exhibits approximately 10 % contrast. In

the static drive mode a suitable choice is V_LCD> 3V_th(off)

.

Multiplex drive modes of 1:3 and 1:4 with ¹⁄₂bias are possible but the discrimination and

hence the contrast ratios are smaller.

1

Bias is calculated by ------------ , where the values for a are

1 + a

a = 1 for ¹⁄₂bias

a = 2 for ¹⁄₃bias

The RMS on-state voltage (V_on(RMS)) for the LCD is calculated with Equation 1:

a²+ 2a + n

n  1 + a²

V_onRMS

=

-----------------------------

(1)

V

LCD

where the values for n are

n = 1 for static drive mode

n = 2 for 1:2 multiplex drive mode

n = 3 for 1:3 multiplex drive mode

n = 4 for 1:4 multiplex drive mode

The RMS off-state voltage (V_off(RMS)) for the LCD is calculated with Equation 2:

a²– 2a + n

n  1 + a²

V_offRMS

=

-----------------------------

(2)

V

LCD

Discrimination is the ratio of V_on(RMS)to V_off(RMS)and is determined from Equation 3:

PCF8534A

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

a²+ 2a + n

a²– 2a + n

V_onRMS

----------------------

V_offRMS

D =

=

---------------------------

(3)

Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with

¹⁄₂bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with

21

¹⁄₂bias is ---------- = 1.528 .

3

The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V_LCD

as follows:

• 1:3 multiplex (¹⁄₂bias): V_LCD

• 1:4 multiplex (¹⁄₂bias): V_LCD

=

6  V_offRMS= 2.449V_offRMS

4  3

---------------------

= 2.309V_offRMS

3

These compare with V_LCD= 3V_offRMSwhen ¹⁄₃bias is used.

_LCDis sometimes referred as the LCD operating voltage.

V

7.3.1 Electro-optical performance

Suitable values for V_on(RMS)and V_off(RMS)are dependent on the LCD liquid used. The

RMS voltage, at which a pixel is switched on or off, determines the transmissibility of the

pixel.

For any given liquid, there are two threshold values defined. One point is at 10 % relative

transmission (at V_th(off)) and the other at 90 % relative transmission (at V_th(on)), see

Figure 6. For a good contrast performance, the following rules should be followed:

V

_onRMS V_thon

_offRMS V_thoff

(4)

(5)

V

_on(RMS)and V_off(RMS)are properties of the display driver and are affected by the selection

of a, n (see Equation 1 to Equation 3) and the V_LCDvoltage.

V_th(off)and V_th(on)are properties of the LCD liquid and can be provided by the module

manufacturer.

It is important to match the module properties to those of the driver in order to achieve

optimum performance.

PCF8534A

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

100 %

90 %

10 %

V

[V]

RMS

V

th(off)

V

th(on)

OFF

SEGMENT

GREY

SEGMENT

ON

SEGMENT

013aaa494

Fig 6. Electro-optical characteristic: relative transmission curve of the liquid

PCF8534A

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.4 LCD drive mode waveforms

7.4.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD.

Backplane and segment drive waveforms for this mode are shown in Figure 7.

T

fr

LCD segments

V

LCD

BP0

Sn

V

SS

state 1

(on)

state 2

(off)

V

LCD

V

SS

V

LCD

Sn+1

V

SS

(a) Waveforms at driver.

V

LCD

0 V

state 1

−V

LCD

V

LCD

state 2

0 V

−V

LCD

(b) Resultant waveforms

at LCD segment.

013aaa207

V_state1(t) = V_Sn(t)  V_BP0(t).

_on(RMS)= V_LCD

V

.

V_state2(t) = V_{(Sn + 1)}(t)  V_BP0(t).

V_off(RMS)= 0 V.

Fig 7. Static drive mode waveforms

PCF8534A

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.4.2 1:2 Multiplex drive mode

When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The

PCF8534A allows the use of ¹⁄₂bias or ¹⁄₃bias in this mode as shown in Figure 8 and

Figure 9.

T

fr

V

LCD

LCD segments

V

/2

BP0

BP1

Sn

LCD

SS

state 1

V

LCD

state 2

V

/2

LCD

SS

V

LCD

V

SS

LCD

Sn+1

V

SS

(a) Waveforms at driver.

V

LCD

/2

LCD

0 V

−V

state 1

/2

LCD

−V

LCD

V

LCD

/2

LCD

0 V

state 2

−V

/2

LCD

−V

(b) Resultant waveforms

at LCD segment.

013aaa208

V_state1(t) = V_Sn(t)  V_BP0(t).

_on(RMS)= 0.791V_LCD

V_state2(t) = V_Sn(t)  V_BP1(t).

V_off(RMS)= 0.354V_LCD

V

.

Fig 8. Waveforms for the 1:2 multiplex drive mode with ¹⁄₂bias

PCF8534A

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

T

fr

V

LCD

LCD segments

2V

/3

LCD

BP0

BP1

Sn

V

/3

LCD

SS

state 1

V

LCD

state 2

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+1

V

/3

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

/3

LCD

V

/3

LCD

0 V

−V

state 1

/3

LCD

−2V

−V

/3

LCD

V

LCD

2V

/3

LCD

V

/3

LCD

0 V

−V

state 2

/3

LCD

−2V

−V

/3

LCD

(b) Resultant waveforms

at LCD segment.

013aaa209

V_state1(t) = V_Sn(t)  V_BP0(t).

_on(RMS)= 0.745V_LCD

V_state2(t) = V_Sn(t)  V_BP1(t).

V_off(RMS)= 0.333V_LCD

V

.

Fig 9. Waveforms for the 1:2 multiplex drive mode with ¹⁄₃bias

PCF8534A

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.4.3 1:3 Multiplex drive mode

When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as

shown in Figure 10.

T

fr

V

LCD

LCD segments

2V

/3

LCD

BP0

BP1

BP2

Sn

V

/3

LCD

SS

state 1

state 2

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+1

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+2

V

/3

LCD

SS

(a) Waveforms at driver.

V

LCD

2V /3

LCD

V

/3

LCD

state 1

0 V

−V

/3

LCD

−2V

−V

/3

LCD

V

LCD

2V /3

LCD

V

/3

LCD

state 2

0 V

−V

/3

LCD

−2V

−V

/3

LCD

(b) Resultant waveforms

at LCD segment.

013aaa210

V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= 0.638V_LCD

V_state2(t) = V_Sn(t)  V_BP1(t).

_off(RMS)= 0.333V_LCD

.

V

.

Fig 10. Waveforms for the 1:3 multiplex drive mode with ¹⁄₃bias

PCF8534A

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.4.4 1:4 Multiplex drive mode

When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as

shown in Figure 11.

T

fr

V

2V

LCD segments

LCD

/3

BP0

BP1

BP2

V

/3

LCD

SS

state 1

state 2

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

BP3

Sn

V

LCD

SS

V

LCD

2V

LCD

/3

V

LCD

SS

V

LCD

2V

/3

LCD

Sn+1

V

LCD

SS

V

LCD

2V

/3

LCD

Sn+2

Sn+3

V

LCD

SS

V

LCD

2V

LCD

/3

V

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

/3

LCD

V

LCD

state 1

state 2

0 V

LCD

-V

/3

-2V

LCD

-V

V

LCD

2V

LCD

/3

V

LCD

0 V

-V

/3

LCD

-2V

LCD

/3

LCD

-V

(b) Resultant waveforms

at LCD segment.

013aaa211

V_state1(t) = V_Sn(t)  V_BP0(t).

_on(RMS)= 0.577V_LCD

V_state2(t) = V_Sn(t)  V_BP1(t).

V_off(RMS)= 0.333V_LCD

V

.

Fig 11. Waveforms for the 1:4 multiplex drive mode with ¹⁄₃bias

PCF8534A

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Product data sheet

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16 of 52

PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.5 Oscillator

The internal logic and the LCD drive signals of the PCF8534A are timed by the frequency

f_clk. It equals either the built-in oscillator frequency f_oscor the external clock frequency

f_clk(ext). The clock frequency f_clkdetermines the LCD frame frequency (f_fr).

7.5.1 Internal clock

The internal oscillator is enabled by connecting pin OSC to pin V_SS. In this case, the

output from pin CLK is the clock signal for any cascaded PCF8534A in the system.

7.5.2 External clock

Pin CLK is enabled as an external clock input by connecting pin OSC to V_DD

.

Remark: A clock signal must always be supplied to the device. Removing the clock may

freeze the LCD in a DC state, which is not suitable for the liquid crystal.

7.6 Timing

The PCF8534A timing controls the internal data flow of the device. This includes the

transfer of display data from the display RAM to the display segment outputs. In cascaded

applications, the correct timing relationship between each PCF8534A in the system is

maintained by the synchronization signal at pin SYNC. The timing also generates the LCD

frame signal whose frequency is derived from the clock frequency. The frame signal

frequency is a fixed division of the clock frequency from either the internal or an external

clock.

Table 6.

LCD frame frequencies

Operating mode ratio

Frame frequency with respect to f_clk(typical)

f_clk= 1536 Hz

Unit

f_clk

64

Hz

-------

=

f_fr

24

7.7 Display register

The display register holds the display data while the corresponding multiplex signals are

generated.

7.8 Segment outputs

The LCD drive section includes 60 segment outputs (S0 to S59) which should be

connected directly to the LCD. The segment output signals are generated based on the

multiplexed backplane signals and with data resident in the display register. When less

than 60 segment outputs are required, the unused segment outputs must be left

open-circuit.

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7.9 Backplane outputs

The LCD drive section includes four backplane outputs BP0 to BP3 which must be

connected directly to the LCD. The backplane output signals are generated in accordance

with the selected LCD drive mode.

• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.

If less than four backplane outputs are required, the unused outputs can be left

open-circuit.

• In 1:3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

• In 1:2 multiplex drive mode BP0 and BP2, respectively, BP1 and BP3 carry the same

signals and can also be paired to increase the drive capabilities.

• In static drive mode, the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements.

7.10 Display RAM

The display RAM is a static 60  4-bit RAM which stores LCD data. A logic 1 in the RAM

bit map indicates the on-state (V_on(RMS)) of the corresponding LCD element. Similarly, a

logic 0 indicates the off-state (V_off(RMS)). For more information on V_on(RMS)and V_off(RMS)

see Section 7.3.

,

There is a one-to-one correspondence between

• the bits in the RAM bitmap and the LCD elements

• the RAM columns and the segment outputs

• the RAM rows and the backplane outputs.

The display RAM bit map, Figure 12, shows row 0 to row 3 which correspond with the

backplane outputs BP0 to BP3, and column 0 to column 59 which correspond with the

segment outputs S0 to S59. In multiplexed LCD applications, the data of each row of the

display RAM is time-multiplexed with the corresponding backplane (row 0 with BP0, row 1

with BP1, and so on).

columns

display RAM addresses/segment outputs (S)

0

1

2

3

4

55 56 57 58 59

rows

0

1

2

3

display RAM rows/

backplane outputs

(BP)

013aaa212

The display RAM bit map shows the direct relationship between the display RAM addresses and

the segment outputs and between the bits in a RAM word and the backplane outputs.

Fig 12. Display RAM bit map

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When display data is transmitted to the PCF8534A, the display bytes received are stored

in the display RAM in accordance with the selected LCD multiplex drive mode. The data is

stored as it arrives and depending on the current multiplex drive mode, data is stored

singularly, in pairs, triples, or quadruples. To illustrate the filling order, an example of a

7-segment display showing all drive modes is given in Figure 13. The RAM filling

organization depicted applies equally to other LCD types.

The following applies to Figure 13:

• In static drive mode the eight transmitted data bits are placed into row 0 as one byte.

• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into

row 0 and row 1 as two successive 4-bit RAM words.

• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, row

1, and row 2 as three successive 3-bit RAM words, with bit 3 of the third address left

unchanged. It is not recommended to use this bit in a display because of the difficult

addressing. This last bit may, if necessary, be controlled by an additional transfer to

this address. But care should be taken to avoid overwriting adjacent data because

always full bytes are transmitted (see Section 7.10.3).

• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples

into row 0, row 1, row 2, and row 3 as two successive 4-bit RAM words.

7.10.1 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte, or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load-data-pointer command (see Table 12). Following this command,

an arriving data byte is stored at the display RAM address indicated by the data pointer.

The filling order is shown in Figure 13. After each byte is stored, the content of the data

pointer is automatically incremented by a value dependent on the selected LCD drive

mode:

• In static drive mode by eight.

• In 1:2 multiplex drive mode by four.

• In 1:3 multiplex drive mode by three.

• In 1:4 multiplex drive mode by two.

If an I²C-bus data access terminates early, then the state of the data pointer is unknown.

Consequently, the data pointer must be rewritten before further RAM accesses.

7.10.2 Subaddress counter

The storage of display data is determined by the content of the subaddress counter.

Storage is allowed only when the content of the subaddress counter matches with the

hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined

by the device-select command (see Table 13). If the content of the subaddress counter

and the hardware subaddress do not match, then data storage is inhibited but the data

pointer is incremented as if data storage had taken place. The subaddress counter is also

incremented when the data pointer overflows.

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In cascaded applications each PCF8534A in the cascade must be addressed separately.

Initially, the first PCF8534A is selected by sending the device-select command matching

the first hardware subaddress. Then the data pointer is set to the preferred display RAM

address by sending the load-data-pointer command.

Once the display RAM of the first PCF8534A has been written, the second PCF8534A is

selected by sending the device-select command again. This time however the command

matches the hardware subaddress of the second device. Next the load-data-pointer

command is sent to select the preferred display RAM address of the second PCF8534A.

This last step is very important because during writing data to the first PCF8534A, the

data pointer of the second PCF8534A is incremented. In addition, the hardware

subaddress should not be changed while the device is being accessed on the I²C-bus

interface.

7.10.3 RAM writing in 1:3 multiplex drive mode

In 1:3 multiplex drive mode, the RAM is written as shown in Table 7 (see Figure 13 as

well).

Table 7.

Standard RAM filling in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.

Display RAM

bits (rows)/

backplane

Display RAM addresses (columns)/segment outputs (Sn)

0

1

2

3

4

5

6

7

8

9

:

outputs (BPn)

0

1

2

3

a7

a6

a5

-

a4

a3

a2

-

a1

a0

-

b7

b6

b5

-

b4

b3

b2

-

b1

b0

-

c7

c6

c5

-

c4

c3

c2

-

c1

c0

-

d7

d6

d5

-

:

-

If the bit at position BP2/S2 would be written by a second byte transmitted, then the

mapping of the segment bits would change as illustrated in Table 8.

Table 8.

Entire RAM filling by rewriting in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.

Display RAM

bits (rows)/

backplane

Display RAM addresses (columns)/segment outputs (Sn)

0

1

2

3

4

5

6

7

8

9

:

outputs (BPn)

0

1

2

3

a7

a6

a5

-

a4

a3

a2

-

a1/b7 b4

a0/b6 b3

b1/c7 c4

b0/c6 c3

c1/d7 d4

c0/d6 d3

d1/e7 e4

d0/e6 e3

:

b5

-

b2

-

c5

-

c2

-

d5

-

d2

-

e5

-

e2

-

In the case described in Table 8 the RAM has to be written entirely and BP2/S2, BP2/S5,

BP2/S8, and so on, have to be connected to elements on the display. This can be

achieved by a combination of writing and rewriting the RAM like follows:

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• In the first write to the RAM, bits a7 to a0 are written.

• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7

and b6.

• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and

c6.

Depending on the method of writing to the RAM (standard or entire filling by rewriting),

some elements remain unused or can be used. But it has to be considered in the module

layout process as well as in the driver software design.

7.10.4 Bank selector

7.10.4.1 Output bank selector

The output bank selector (see Table 14) selects one of the four rows per display RAM

address for transfer to the display register. The actual row selected depends on the

particular LCD drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by

the contents of row 1, 2, and then 3

• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially

• In 1:2 multiplex mode, rows 0 and 1 are selected

• In static mode, row 0 is selected

The SYNC signal resets these sequences to the following starting points:

• row 3 for 1:4 multiplex

• row 2 for 1:3 multiplex

• row 1 for 1:2 multiplex

• row 0 for static mode

The PCF8534A includes a RAM bank switching feature in the static and 1:2 multiplex

drive modes. In the static drive mode, the bank-select command may request the contents

of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex

mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives

the provision for preparing display information in an alternative bank and to be able to

switch to it once it is assembled.

7.10.4.2 Input bank selector

The input bank selector loads display data into the display data in accordance with the

selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode

or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see

Table 14). The input bank selector functions independently to the output bank selector.

7.11 Blinking

The display blinking capabilities of the PCF8534A are very versatile. The whole display

can blink at frequencies selected by the blink-select command (see Table 15). The blink

frequencies are derived from the clock frequency. The ratio between the clock and blink

frequency depends on the blink mode selected (see Table 9).

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Table 9.

Blink frequencies

Blink mode Operating mode ratio Blink frequency with respect to f_clk(typical)

Unit

f_clk= 1536 Hz

off

1

-

blinking off

Hz

f_clk

--------

768

2

f_blink

=

f_clk

2

3

-----------

1536

1

Hz

=

f_clk

-----------

3072

0.5

=

An additional feature is for an arbitrary selection of LCD segments to blink. This applies to

the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. With the output bank selector, the displayed RAM banks are

exchanged with alternate RAM banks at the blink frequency. This mode can also be

specified by the blink-select command.

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD elements can blink by selectively changing the display RAM data at fixed time

intervals.

The entire display can blink at a frequency other than the nominal blink frequency. This

can be effectively performed by resetting and setting the display enable bit E at the

required rate using the mode-set command (see Table 11).

7.12 Command decoder

The command decoder identifies command bytes that arrive on the I²C-bus. The

commands available to the PCF8534A are defined in Table 10.

Table 10. Definition of commands

Command

Operation code

Reference

7

1

0

1

6

5

4

3

2

1

0

mode set

1

0

E

B

M[1:0]

Table 11

Table 12

Table 13

Table 14

Table 15

load data pointer

device select

bank select

blink select

P[6:0]

1

0

1

0

1

0

A[2:0]

0

I

O

AB

BF[1:0]

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Table 11. Mode-set command bit description

Bit

7 to 4

3

Symbol

Value

Description

-

1100

fixed value

E

display status

0^[1]

1

disabled (blank)^[2]

enable

2

B

LCD bias configuration^[3]

¹⁄₃bias

¹⁄₂bias

0^[1]

1

1 to 0 M[1:0]

LCD drive mode selection

static; one backplane

1:2 multiplex; two backplanes

1:3 multiplex; three backplanes

1:4 multiplex; four backplanes

01

10

11

00^[1]

[1] Default value.

[2] The possibility to disable the display allows implementation of blinking under external control.

[3] Not applicable for static drive mode.

Table 12. Load data pointer command bit description

See Section 7.10.1 on page 20.

Bit

Symbol

Value

Description

7

-

0

fixed value

6 to 0 P[6:0]

0000000^[1]to 7-bit binary value, 0 to 59; transferred to the

0111011

data pointer to define one of 60 display RAM

addresses

[1] Default value.

Table 13. Device select command bit description

See Section 7.10.2 on page 20.

Bit

Symbol

Value

Description

7 to 3

-

11100

fixed value

2 to 0 A[2:0]

000^[1]to 111

3-bit binary value, 0 to 7; transferred to the

subaddress counter to define one of eight

hardware subaddresses

[1] Default value.

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Table 14. Bank select command bit description

See Section 7.10.4 on page 22.

Bit

Symbol

Value

Description

Static

1:2 multiplex^[1]

7 to 2

1

-

I

111110

fixed value

input bank selection: storage of arriving

display data

0^[2]

1

RAM row 0

RAM row 2

RAM rows 0 and 1

RAM rows 2 and 3

0

O

output bank selection: retrieval of LCD display

data

0^[2]

1

RAM row 0

RAM row 2

RAM rows 0 and 1

RAM rows 2 and 3

[1] The bank select command has no effect in 1:3 or 1:4 multiplex drive modes.

[2] Default value.

Table 15. Blink select command bit description

Section 7.11 on page 22.

Bit

7 to 3

2

Symbol

Value

Description

-

11110

fixed value

AB

blink mode selection

normal blinking^[2]

alternate RAM bank blinking^[3]

0^[1]

1

1 to 0 BF[1:0]

blink frequency selection^[4]

00^[1]

01

off

1

10

2

11

3

[1] Default value.

[2] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.

[3] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.

[4] For the blink frequencies, see Table 9.

7.13 Display controller

The display controller executes the commands identified by the command decoder. It

contains the status registers of the PCF8534A and coordinates their effects. The display

controller is also responsible for loading display data into the display RAM in the correct

filling order.

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8. Characteristics of the I²C-bus

The I²C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta Line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 14).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 14. Bit transfer

8.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START

condition (S).

A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP

condition (P).

The START and STOP conditions are illustrated in Figure 15.

SDA

SCL

SDA

SCL

S

P

START condition

STOP condition

mbc622

Fig 15. Definition of START and STOP conditions

8.3 System configuration

A device generating a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message is the master; and the devices which are

controlled by the master are the slaves. The system configuration is shown in Figure 16.

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MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

SDA

SCL

mga807

Fig 16. System configuration

8.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge

cycle.

• A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte.

• A master receiver must generate an acknowledge after the reception of each byte that

has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I²C-bus is illustrated in Figure 17.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from

master

1

2

8

9

S

clock pulse for

acknowledgement

START

condition

mbc602

Fig 17. Acknowledgement of the I²C-bus

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8.5 I²C-bus controller

The PCF8534A acts as an I²C-bus slave receiver. It does not initiate I²C-bus transfers or

transmit data to an I²C-bus master receiver. The only data output from the PCF8534A are

the acknowledge signals of the selected devices. Device selection depends on the

I²C-bus slave address, on the transferred command data and on the hardware

subaddress.

In single device applications, the hardware subaddress inputs A0, A1, and A2 are

normally tied to V_SSwhich defines the hardware subaddress 0. In multiple device

applications A0, A1, and A2 are tied to V_SSor V_DDusing a binary coding scheme, so that

no two devices with a common I²C-bus slave address have the same hardware

subaddress.

8.6 Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

8.7 I²C-bus protocol

Two I²C-bus slave addresses (0111 000 and 0111 001) are used to address the

PCF8534A. The entire I²C-bus slave address byte is shown in Table 16.

Table 16. I²C slave address byte

Slave address

Bit

7

6

5

4

3

2

1

0

MSB

LSB

R/W

0

1

0

SA0

The PCF8534A is a write-only device and does not respond to a read access, therefore

bit 0 should always be logic 0. Bit 1 of the slave address byte, that a PCF8534A will

respond to, is defined by the level tied to its SA0 input (V_SSfor logic 0 and V_DDfor logic 1).

Having two reserved slave addresses allows the following on the same I²C-bus:

• Up to 16 PCF8534A for large LCD applications

• The use of two types of LCD multiplex drive

The I²C-bus protocol is shown in Figure 18. The sequence is initiated with a START

condition (S) from the I²C-bus master which is followed by one of the available PCF8534A

slave addresses. All PCF8534A with the same SA0 level acknowledge in parallel to the

slave address. All PCF8534A with the alternative SA0 level ignore the whole I²C-bus

transfer.

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R/W = 0

slave address

control byte

RAM/command byte

S

A

0

M

S

B

L

S

B

C

O

R

S

0

1

0

A

P

A

EXAMPLES

a) transmit two bytes of RAM data

S

0

1

0

A

0

A

0

1

0

RAM DATA

COMMAND

RAM DATA

A

P

A

b) transmit two command bytes

S

A

0

1

S

0

1

0

A

0

COMMAND

RAM DATA

A

P

c) transmit one command byte and two RAM date bytes

S

A

S

0

1

0

A

0

1

0

RAM DATA

A

P

mgl752

Fig 18. I²C-bus protocol

After acknowledgement, the control byte is sent defining if the next byte is a RAM or

command information. The control byte also defines if the next byte is a control byte or

further RAM or command data (see Figure 19 and Table 17). In this way it is possible to

configure the device and then fill the display RAM with little overhead.

MSB

LSB

7

6

5

4

3

2

1

0

CO RS

not relevant

mgl753

Fig 19. Control byte format

Table 17. Control byte description

Bit

Symbol Value

Description

7

CO

continue bit

last control byte

0

1

control bytes continue

register selection

command register

data register

6

RS

0

1

5 to 0

-

unused

The command bytes and control bytes are also acknowledged by all addressed

PCF8534A connected to the bus.

The display bytes are stored in the display RAM at the address specified by the data

pointer and the subaddress counter. Both data pointer and subaddress counter are

automatically updated.

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The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed

PCF8534A. After the last display byte, the I²C-bus master issues a STOP condition (P).

Alternatively a START may be issued to RESTART I²C-bus access.

9. Internal circuitry

V

DD

SA0

CLK

V

SS

DD

SCL

V

SS

DD

V

SS

OSC

V

SS

SDA

DD

SYNC

V

SS

DD

A0, A1, A2

V

LCD

V

SS

LCD

V

SS

BP0, BP1,

BP2, BP3

V

SS

LCD

S0 to S59

V

001aah615

SS

Fig 20. Device protection diagram

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10. Limiting values

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(V_LCD) is on while the IC supply voltage (V_DD) is off, or vice versa. This may cause unwanted

display artifacts. To avoid such artifacts, V_LCDand V_DDmust be applied or removed together.

Table 18. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

I_DD

Parameter

Conditions

Min

0.5

50

0.5

50

0.5

10

0.5

10

-

Max

+6.5

+50

+7.5

+50

+6.5

+10

+6.5

+7.5

+10

400

100

Unit

V

supply voltage

supply current

LCD supply voltage

LCD supply current

ground supply current

input voltage

mA

V

V_LCD

I_DD(LCD)

I_SS

mA

V

[1]

V_I

I_I

input current

mA

V

[1]

V_O

output voltage

[2]

V

[1][2]

I_O

output current

mA

mW

P_tot

P/out

total power dissipation

power dissipation per

output

-

[3]

[4]

[5]

[6]

V_ESD

electrostatic discharge

voltage

HBM

CDM

-

3000

1000

200

V

-

V

I_lu

latch-up current

-

mA

C

T_stg

T_amb

storage temperature

ambient temperature

65

40

+150

+85

operating device

[1] Pins SDA, SCL, CLK, SYNC, SA0, OSC, and A0 to A2.

[2] Pins S0 to S59 and BP0 to BP3.

[3] Pass level; Human Body Model (HBM), according to Ref. 5 “JESD22-A114”.

[4] Pass level; Charged-Device Model (CDM), according to Ref. 6 “JESD22-C101”.

[5] Pass level; latch-up testing according to Ref. 7 “JESD78” at maximum ambient temperature (T_amb(max)).

[6] According to the NXP store and transport requirements (see Ref. 9 “NX3-00092”) the devices have to be

stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. For long-term storage products

deviant conditions are described in that document.

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

11. Static characteristics

Table 19. Static characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 6.5 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Supplies

V_DD

supply voltage

1.8

2.5

-

5.5

6.5

20

V

V_LCD

I_DD

LCD supply voltage

supply current

-

V

[1]

f_clk= 1536 Hz

8

24

A

I_DD(LCD)

Logic

V_I

LCD supply current

-

60

input voltage

V_SS 0.5

V_DD+ 0.5 V

V_IL

LOW-level input voltage

on pins CLK, SYNC, OSC, A0 to A2

and SA0

V_SS

-

0.3V_DD

V

V_IH

HIGH-level input voltage

on pins CLK, SYNC, OSC, A0 to A2

and SA0

0.7V_DD

V_DD

V

V_POR

I_OL

power-on reset voltage

LOW-level output current

1.0

1

1.3

-

1.6

-

V

V_OL= 0.4 V; V_DD= 5 V; on pins CLK

and SYNC

mA

I_OH

I_L

HIGH-level output current

leakage current

V_OH= 4.6 V; V_DD= 5 V; on pin CLK

1

-

mA

V_I= V_DDor V_SS; on pins SA0, A0 to

A2 and CLK

+1

A

V_I= V_DD; on pin OSC

1

-

+1

7

A

[2]

C_I

input capacitance

-

pF

I²C-bus; pins SDA and SCL^[3]

V_I

input voltage

V_SS 0.5

-

5.5

V

V_IL

LOW-level input voltage

pin SCL

pin SDA

V_SS

0.3V_DD

V

V_SS

0.2V_DD

V

V_IH

I_OL

I_L

HIGH-level input voltage

LOW-level output current

leakage current

0.7V_DD

5.5

-

V

V_OL= 0.4 V; V_DD= 5 V; on pin SDA

V_I= V_DDor V_SS

3

mA

A

pF

1

-

+1

7

[2]

C_i

input capacitance

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

Table 19. Static characteristics …continued

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 6.5 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol Parameter

LCD outputs

Conditions

Min

Typ

Max

Unit

Output pins BP0, BP1, BP2 and BP3

[4]

[5]

V_BP

R_BP

voltage on pin BP

C_bpl= 35 nF

V_LCD= 5 V

100

-

+100

10

mV

resistance on pin BP

-

1.5

k

Output pins S0 to S59

[6]

[5]

V_S

R_S

voltage on pin S

resistance on pin S

C_sgm= 35 nF

V_LCD= 5 V

100

-

+100

13.5

mV

-

6.0

k

[1] LCD outputs are open circuit; inputs at V_SSor V_DD; external clock with 50 % duty factor; I²C-bus inactive.

[2] Not tested, design specification only.

[3] The I²C-bus interface of PCF8534A is 5 V tolerant.

[4]

C_bpl= backplane capacitance.

[5] Outputs measured individually and sequentially.

[6] C_sgm= segment capacitance.

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

12. Dynamic characteristics

Table 20. Dynamic characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 6.5 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

Clock

Internal: output pin CLK

Parameter

Conditions

Min

Typ

Max

Unit

[1]

f_osc

oscillator frequency

V_DD= 5 V

960

1536

3046

Hz

External: input pin CLK

f_clk(ext)

t_clk(H)

t_clk(L)

external clock frequency

797

130

1536

3046

Hz

s

HIGH-level clock time

LOW-level clock time

-

Synchronization: input pin SYNC

t_{PD(SYNC_N)}SYNC propagation delay

-

30

-

ns

t_{SYNC_NL}

Outputs: pins BP0 to BP3 and S0 to S59

t_PD(drv)driver propagation delay

SYNC LOW time

1

s

V_LCD= 5 V

-

30

s

I²C-bus: timing^[2]

Pin SCL

f_SCL

SCL frequency

-

400

kHz

s

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

1.3

0.6

-

t_HIGH

s

Pin SDA

t_SU;DAT

t_HD;DAT

data set-up time

data hold time

100

0

-

ns

Pins SCL and SDA

t_BUF

bus free time between a STOP and

1.3

-

s

START condition

t_SU;STO

t_HD;STA

t_SU;STA

set-up time for STOP condition

hold time (repeated) START condition

0.6

-

s

set-up time for a repeated START

condition

t_r

rise time of both SDA and SCL signals

fall time of both SDA and SCL signals

capacitive load for each bus line

spike pulse width

-

0.3

400

50

s

pF

ns

t_f

C_b

t_w(spike)

[1] Typical output (duty cycle  = 50 %).

[2] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V_ILand V_IHwith an

input voltage swing of V_SSto V_DD

.

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

1 / f

clk

t

clk(L)

clk(H)

0.7V

DD

CLK

0.3V

DD

0.7V

DD

SYNC

0.3V

t

PD(SYNC_N)

t

SYNC_NL

0.5 V

(V

BP0 to BP3,

and S0 to S59

= 5 V)

DD

0.5 V

t

PD(drv)

001aah618

Fig 21. Driver timing waveforms

SDA

t

f

BUF

LOW

SCL

SDA

t

HD;STA

t

SU;DAT

r

HD;DAT

t

HIGH

t

SU;STA

t

SU;STO

mga728

Fig 22. I²C-bus timing waveforms

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

13. Application information

13.1 Cascaded operation

Large display configurations of up to 16 PCF8534As can be recognized on the same

I²C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable

I²C-bus slave address (SA0).

Table 21. Addressing cascaded PCF8534A

Cluster

Bit SA0

Pin A2

Pin A1

Pin A0

Device

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

2

1

8

9

10

11

12

13

14

15

When cascaded PCF8534A are synchronized, they can share the backplane signals from

one of the devices in the cascade. Such an arrangement is cost-effective in large LCD

applications since the backplane outputs of only one device need to be through-plated to

the backplane electrodes of the display. The other PCF8534A of the cascade contribute

additional segment outputs, but their backplane outputs are left open-circuit

(see Figure 23).

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

V

LCD

DD

SDA

SCL

60 segment drives

SYNC

CLK

PCF8534A

(2)

BP0 to BP3

(open-circuit)

OSC

A0 A1 A2 SA0

V

SS

LCD PANEL

V

LCD

V

t

r

2C

DD

≤

R

b

V

LCD

DD

60 segment drives

SDA

SCL

HOST

MICRO-

PROCESSOR/

MICRO-

SYNC

4 backplanes

BP0 to BP3

PCF8534A

CONTROLLER

(1)

CLK

OSC

A0 A1 A2 SA0

V

SS

V

SS

013aaa513

(1) Is master (OSC connected to V_SS).

(2) Is slave (OSC connected to V_DD).

Fig 23. Cascaded PCF8534A configuration

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCF8534A. Synchronization is guaranteed after a power-on reset. The only time that

SYNC is likely to be needed is if synchronization is accidentally lost (for example, by noise

in adverse electrical environments or by defining a multiplex drive mode when PCF8534A

with different SA0 levels are cascaded).

SYNC is organized as an input/output pin. The output selection is realized as an

open-drain driver with an internal pull-up resistor. A PCF8534A asserts the SYNC line at

the onset of its last active backplane signal and monitors the SYNC line at all other times.

If synchronization in the cascade is lost, it is restored by the first PCF8534A to assert

SYNC. The timing relationship between the backplane waveforms and the SYNC signal

for the various drive modes of the PCF8534A are shown in Figure 24.

The contact resistance between the SYNC on each cascaded device must be controlled.

If the resistance is too high, the device is not able to synchronize properly; this is

applicable to chip-on-glass applications. The maximum SYNC contact resistance allowed

for the number of devices in cascade is given in Table 22.

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Product data sheet

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PCF8534A

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Universal LCD driver for low multiplex rates

Table 22. SYNC contact resistance

Number of devices

Maximum contact resistance

2

6000 

2200 

1200 

700 

3 to 5

6 to 10

11 to 16

The PCF8534A can always be cascaded with other devices of the same type or

conditionally with other devices of the same family. This allows optimal drive selection for

a given number of pixels to display. Figure 22 and Figure 24 show the timing of the

synchronization signals.

1

T

=

fr

f

fr

BP0

SYNC

(a) static drive mode.

BP0

(1/2 bias)

BP0

(1/3 bias)

SYNC

(b) 1:2 multiplex drive mode.

BP0

(1/3 bias)

SYNC

(c) 1:3 multiplex drive mode.

BP0

(1/3 bias)

SYNC

(d) 1:4 multiplex drive mode.

mgl755

Fig 24. Synchronization of the cascade for various PCF8534A drive modes

In a cascaded configuration, only one PCF8534A master must be used as clock source.

All other PCF8534A in the cascade must be configured as slave such that they receive

the clock from the master.

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

If an external clock source is used, all PCF8534A in the cascade must be configured such

as to receive the clock from that external source (pin OSC connected to V_DD). It must be

ensured that the clock tree is designed such that on all PCF8534A the clock propagation

delay from the clock source to all PCF8534A in the cascade is as equal as possible since

otherwise synchronization artifacts may occur.

In mixed cascading configurations, care has to be taken that the specifications of the

individual cascaded devices are met at all times.

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Product data sheet

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

14. Package outline

LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm

SOT315-1

y

X

A

60

41

Z

61

40

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

L

pin 1 index

80

21

detail X

1

20

Z

D

v

M

A

e

w M

b

p

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

p

v

w

y

Z

θ

1

2

3

p

E

D

E

max.

7^o

0^o

0.16 1.5

0.04 1.3

0.27 0.18 12.1 12.1

0.13 0.12 11.9 11.9

14.15 14.15

13.85 13.85

0.75

0.30

1.45 1.45

1.05 1.05

mm

1.6

0.25

0.5

1

0.2 0.15 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT315-1

136E15

MS-026

Fig 25. Package outline SOT315-1 (LQFP80)

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

15. Bare die outline

Wire bond die; 76 bonding pads; 2.91 x 2.62 x 0.38 mm

PCF8534AU

D

e

A

63

44

C1

C2

64

e

43

PC8534A-1⁽³⁾

x

E

0

76

y

1

24

3

F

4

23

X

0

0.5

1 mm

scale

P

3

4

DIMENSIONS (mm are the original dimensions)

(1)

(2)

(1)

(2)

UNIT

max

A

D

E

e

P

4

1

2

3

P

2

mm

nom 0.38 2.91 2.62

min

0.06 0.05 0.10 0.09

1

0.08

detail X

Notes

1. Pad size

2. Passivation opening

3. Marking code

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

PCF8534AU

08-08-06

Fig 26. PCF8534AU die outline

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

Table 23. Bonding pad locations

Symbol

Pad Coordinates^[1]

Description

X (m)

1384.4

978.7

829.3

714.3

584.3

454.3

324.3

194.3

64.3

Y (m)

SDA

SCL

CLK

V_DD

SYNC

OSC

A0

1

280

I²C-bus serial data input and output

I²C-bus serial clock input

2

760.5

945

3

external clock input and output

supply voltage

4

1238

841

5

cascade synchronization input and output

enable input for internal oscillator

subaddress counter input

6

7

A1

8

A2

9

SA0

V_SS

V_LCD

S0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

I²C-bus slave address input 0

ground

68.7

input of LCD supply voltage

LCD segment output

173.7

S1

253.7

S2

333.7

S3

413.7

S4

493.7

S5

573.7

S6

653.7

S7

733.7

S8

813.7

S9

893.7

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

S25

S26

S27

973.7

1384.4

761

681

601

521

441

361

281

201

121

41

39

119

301.6

381.6

461.6

541.6

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Universal LCD driver for low multiplex rates

Table 23. Bonding pad locations …continued

Symbol

Pad Coordinates^[1]

Description

X (m)

1384.4

896.5

Y (m)

S28

S29

S30

S31

S32

S33

S34

S35

S36

S37

S38

S39

S40

S41

S42

S43

S44

S45

S46

S47

S48

S49

S50

S51

S52

S53

S54

S55

S56

S57

S58

S59

BP0

BP1

BP2

BP3

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

621.6

701.6

781.6

1239.4

935

LCD segment output

816.5

736.5

576.5

496.5

416.5

336.5

256.5

176.5

96.5

16.5

63.5

143.5

223.5

303.5

463.5

543.5

623.5

703.5

783.5

1384.4

855

775

695

615

535

375

295

215

125

LCD backplane output

45

35

115

[1] All coordinates are referenced in m to the center of the die (see Figure 26).

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PCF8534A

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Universal LCD driver for low multiplex rates

REF

C1

C2

REF

F

001aai649

Fig 27. Alignment marks

Table 24. Alignment mark locations ^[1]

Symbol

X (m)

1387

1335

Y (m)

1190

C1

C2

F

1242

1345

1173

[1] All coordinates are referenced in m to the center of the die (see Figure 26).

16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent

standards.

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PCF8534A

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Universal LCD driver for low multiplex rates

17. Packing information

A

C

1.1

1.2

1.3

2.1

2.2

3.1

x.1

D

F

B

1.y

y

E

x

001aai625

Fig 28. Tray details for PCF8534AU/DA/1

PC8534A-1

001aai650

Fig 29. Tray alignment for PCF8534AU/DA/1

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PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

Table 25. Tray dimensions

Symbol

Description

Value

A

B

C

D

E

F

pocket pitch in x direction

pocket pitch in y direction

pocket width in x direction

pocket width in y direction

tray width in x direction

5.5 mm

4.9 mm

3.08 mm

2.79 mm

50.8 mm

8

tray width in y direction

N

M

number of pockets, x direction

number of pockets, y direction

9

18. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

18.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

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PCF8534A

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Universal LCD driver for low multiplex rates

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

18.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

18.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 30) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 26 and 27

Table 26. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 27. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 30.

PCF8534A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 25 July 2011

47 of 52

PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 30. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

19. Abbreviations

Table 28. Abbreviations

Acronym

CMOS

ESD

Description

Complementary Metal-Oxide Semiconductor

ElectroStatic Discharge

Human Body Model

HBM

IC

Integrated Circuit

LCD

Liquid Crystal Display

MM

Machine Model

RAM

Random Access Memory

PCF8534A

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Product data sheet

Rev. 6 — 25 July 2011

48 of 52

PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

20. References

[1] AN10365 — Surface mount reflow soldering description

[2] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[4] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for

Nonhermetic Solid-State Surface Mount Devices

[5] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[6] JESD22-C101 — Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[7] JESD78 — IC Latch-Up Test

[8] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[9] NX3-00092 — NXP store and transport requirements

[10] SNV-FA-01-02 — Marking Formats Integrated Circuits

[11] UM10204 — I²C-bus specification and user manual

21. Revision history

Table 29. Revision history

Document ID

PCF8534A v.6

Modifications:

Release date

20110725

Data sheet status

Change notice

Supersedes

Product data sheet

-

PCF8534A_5

• Added design-in and replacement part information

• Changed description of Table 17

• Added Section 7.10.3

PCF8534A_5

PCF8534A_4

PCF8534A_3

PCF8534A_2

PCF8534A_1

20090806

20090716

20081110

20080604

20080423

Product data sheet

-

PCF8534A_4

PCF8534A_3

PCF8534A_2

PCF8534A_1

-

PCF8534A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 25 July 2011

49 of 52

PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

22. Legal information

22.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

suitable for use in medical, military, aircraft, space or life support equipment,

22.2 Definitions

nor in applications where failure or malfunction of an NXP Semiconductors

product can reasonably be expected to result in personal injury, death or

severe property or environmental damage. NXP Semiconductors accepts no

liability for inclusion and/or use of NXP Semiconductors products in such

equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

22.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. The product is not designed, authorized or warranted to be

PCF8534A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 25 July 2011

50 of 52

PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

systems after third party sawing, handling, packing or assembly of the die. It

is the responsibility of the customer to test and qualify their application in

which the die is used.

All die sales are conditioned upon and subject to the customer entering into a

written die sale agreement with NXP Semiconductors through its legal

department.

Bare die — All die are tested on compliance with their related technical

specifications as stated in this data sheet up to the point of wafer sawing and

are handled in accordance with the NXP Semiconductors storage and

transportation conditions. If there are data sheet limits not guaranteed, these

will be separately indicated in the data sheet. There are no post-packing tests

performed on individual die or wafers.

22.4 Trademarks

NXP Semiconductors has no control of third party procedures in the sawing,

handling, packing or assembly of the die. Accordingly, NXP Semiconductors

assumes no liability for device functionality or performance of the die or

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

23. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PCF8534A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 25 July 2011

51 of 52

PCF8534A

NXP Semiconductors

Universal LCD driver for low multiplex rates

24. Contents

1

2

3

4

5

General description. . . . . . . . . . . . . . . . . . . . . . 1

12

Dynamic characteristics. . . . . . . . . . . . . . . . . 34

Application information . . . . . . . . . . . . . . . . . 36

Cascaded operation. . . . . . . . . . . . . . . . . . . . 36

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 40

Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 41

Handling information . . . . . . . . . . . . . . . . . . . 44

Packing information . . . . . . . . . . . . . . . . . . . . 45

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

13

13.1

14

15

16

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

17

18

Soldering of SMD packages. . . . . . . . . . . . . . 46

Introduction to soldering. . . . . . . . . . . . . . . . . 46

Wave and reflow soldering. . . . . . . . . . . . . . . 46

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 47

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 47

7

7.1

7.2

7.3

7.3.1

7.4

7.4.1

7.4.2

7.4.3

7.4.4

7.5

7.5.1

7.5.2

7.6

7.7

7.8

7.9

7.10

7.10.1

7.10.2

7.10.3

7.10.4

Functional description . . . . . . . . . . . . . . . . . . . 7

Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 8

LCD bias generator . . . . . . . . . . . . . . . . . . . . . 8

LCD voltage selector . . . . . . . . . . . . . . . . . . . . 9

Electro-optical performance . . . . . . . . . . . . . . 10

LCD drive mode waveforms . . . . . . . . . . . . . . 12

Static drive mode . . . . . . . . . . . . . . . . . . . . . . 12

1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 13

1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 15

1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 16

Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 17

External clock . . . . . . . . . . . . . . . . . . . . . . . . . 17

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Display register. . . . . . . . . . . . . . . . . . . . . . . . 17

Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 17

Backplane outputs . . . . . . . . . . . . . . . . . . . . . 18

Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 18

Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Subaddress counter . . . . . . . . . . . . . . . . . . . . 20

RAM writing in 1:3 multiplex drive mode. . . . . 21

Bank selector . . . . . . . . . . . . . . . . . . . . . . . . . 22

18.1

18.2

18.3

18.4

19

20

21

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 48

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Revision history . . . . . . . . . . . . . . . . . . . . . . . 49

22

Legal information . . . . . . . . . . . . . . . . . . . . . . 50

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 50

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 51

22.1

22.2

22.3

22.4

23

24

Contact information . . . . . . . . . . . . . . . . . . . . 51

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.10.4.1 Output bank selector . . . . . . . . . . . . . . . . . . . 22

7.10.4.2 Input bank selector . . . . . . . . . . . . . . . . . . . . . 22

7.11

7.12

7.13

Blinking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Command decoder. . . . . . . . . . . . . . . . . . . . . 23

Display controller . . . . . . . . . . . . . . . . . . . . . . 25

8

Characteristics of the I²C-bus . . . . . . . . . . . . 26

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

START and STOP conditions . . . . . . . . . . . . . 26

System configuration . . . . . . . . . . . . . . . . . . . 26

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 27

I²C-bus controller . . . . . . . . . . . . . . . . . . . . . . 28

Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 28

8.1

8.2

8.3

8.4

8.5

8.6

8.7

9

Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 30

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 31

Static characteristics. . . . . . . . . . . . . . . . . . . . 32

10

11

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 25 July 2011

Document identifier: PCF8534A


型号：	PCF8534AH/1,518
厂家：	NXP
描述：	IC LIQUID CRYSTAL DISPLAY DRIVER, PDSO80, 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80, Display Driver 驱动光电二极管接口集成电路
文件：	总52页 (文件大小：490K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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